1717def _check_cpu_topology (
1818 test_microvm , expected_cpu_count , expected_threads_per_core , expected_cpus_list
1919):
20- expected_cpu_topology = {
21- "CPU(s)" : str (expected_cpu_count ),
22- "On-line CPU(s) list" : expected_cpus_list ,
23- "Thread(s) per core" : str (expected_threads_per_core ),
24- "Core(s) per socket" : str (int (expected_cpu_count / expected_threads_per_core )),
25- "Socket(s)" : "1" ,
26- "NUMA node(s)" : "1" ,
27- }
20+ expected_lscpu_output = {}
21+ if PLATFORM == "x86_64" :
22+ expected_lscpu_output = {
23+ "CPU(s)" : str (expected_cpu_count ),
24+ "On-line CPU(s) list" : expected_cpus_list ,
25+ "Thread(s) per core" : str (expected_threads_per_core ),
26+ "Core(s) per socket" : str (
27+ int (expected_cpu_count / expected_threads_per_core )
28+ ),
29+ "Socket(s)" : "1" ,
30+ "NUMA node(s)" : "1" ,
31+ }
32+ else :
33+ expected_lscpu_output = {
34+ "CPU(s)" : str (expected_cpu_count ),
35+ "On-line CPU(s) list" : expected_cpus_list ,
36+ "Thread(s) per core" : "1" ,
37+ "Core(s) per cluster" : str (
38+ int (expected_cpu_count / expected_threads_per_core )
39+ ),
40+ "Cluster(s)" : "1" ,
41+ "NUMA node(s)" : "1" ,
42+ }
43+
44+ utils .check_guest_cpuid_output (
45+ test_microvm , "lscpu" , None , ":" , expected_lscpu_output
46+ )
47+
48+ if PLATFORM == "x86_64" :
49+ expected_hwloc_output = {
50+ "depth 0" : "1 Machine (type #0)" ,
51+ "depth 1" : "1 Package (type #1)" ,
52+ "depth 2" : "1 L3Cache (type #6)" ,
53+ "depth 3" : f"{ int (expected_cpu_count / expected_threads_per_core )} L2Cache (type #5)" ,
54+ "depth 4" : f"{ int (expected_cpu_count / expected_threads_per_core )} L1dCache (type #4)" ,
55+ "depth 5" : f"{ int (expected_cpu_count / expected_threads_per_core )} L1iCache (type #9)" ,
56+ "depth 6" : f"{ int (expected_cpu_count / expected_threads_per_core )} Core (type #2)" ,
57+ "depth 7" : f"{ expected_cpu_count } PU (type #3)" ,
58+ }
59+ else :
60+ expected_hwloc_output = {
61+ "depth 0" : "1 Machine (type #0)" ,
62+ "depth 1" : "1 Package (type #1)" ,
63+ "depth 2" : "1 L3Cache (type #6)" ,
64+ "depth 3" : f"{ expected_cpu_count } L2Cache (type #5)" ,
65+ "depth 4" : f"{ expected_cpu_count } L1dCache (type #4)" ,
66+ "depth 5" : f"{ expected_cpu_count } L1iCache (type #9)" ,
67+ "depth 6" : f"{ expected_cpu_count } Core (type #2)" ,
68+ "depth 7" : f"{ expected_cpu_count } PU (type #3)" ,
69+ }
2870
2971 utils .check_guest_cpuid_output (
30- test_microvm , "lscpu " , None , ":" , expected_cpu_topology
72+ test_microvm , "hwloc-info " , None , ":" , expected_hwloc_output
3173 )
3274
3375
@@ -148,15 +190,14 @@ def _check_cache_topology_arm(test_microvm, no_cpus, kernel_version_tpl):
148190 assert guest_slice == host_slice
149191
150192
151- @pytest .mark .skipif (
152- PLATFORM != "x86_64" , reason = "Firecracker supports CPU topology only on x86_64."
153- )
154193@pytest .mark .parametrize ("num_vcpus" , [1 , 2 , 16 ])
155- @pytest .mark .parametrize ("htt" , [True , False ])
194+ @pytest .mark .parametrize ("htt" , [True , False ], ids = [ "HTT_ON" , "HTT_OFF" ] )
156195def test_cpu_topology (uvm_plain_any , num_vcpus , htt ):
157196 """
158197 Check the CPU topology for a microvm with the specified config.
159198 """
199+ if htt and PLATFORM == "aarch64" :
200+ pytest .skip ("SMT is configurable only on x86." )
160201 vm = uvm_plain_any
161202 vm .spawn ()
162203 vm .basic_config (vcpu_count = num_vcpus , smt = htt )
@@ -169,7 +210,7 @@ def test_cpu_topology(uvm_plain_any, num_vcpus, htt):
169210
170211
171212@pytest .mark .parametrize ("num_vcpus" , [1 , 2 , 16 ])
172- @pytest .mark .parametrize ("htt" , [True , False ])
213+ @pytest .mark .parametrize ("htt" , [True , False ], ids = [ "HTT_ON" , "HTT_OFF" ] )
173214def test_cache_topology (uvm_plain_any , num_vcpus , htt ):
174215 """
175216 Check the cache topology for a microvm with the specified config.
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