@@ -30,7 +30,11 @@ e-mail : support@circuitsathome.com
3030/* SPI initialization */
3131template < typename SPI_CLK, typename SPI_MOSI, typename SPI_MISO, typename SPI_SS > class SPi {
3232public:
33- #if USING_SPI4TEENSY3
33+ #if SPI_HAS_TRANSACTION
34+ static void init () {
35+ SPI.begin (); // The SPI library with transaction will take care of setting up the pins - settings is set in beginTransaction()
36+ }
37+ #elif USING_SPI4TEENSY3
3438 static void init () {
3539 // spi4teensy3 inits everything for us, except /SS
3640 // CLK, MOSI and MISO are hard coded for now.
@@ -129,8 +133,17 @@ MAX3421e< SPI_SS, INTR >::MAX3421e() {
129133template < typename SPI_SS, typename INTR >
130134void MAX3421e< SPI_SS, INTR >::regWr(uint8_t reg, uint8_t data) {
131135 XMEM_ACQUIRE_SPI ();
136+ #if SPI_HAS_TRANSACTION
137+ SPI.beginTransaction (SPISettings (26000000 , MSBFIRST, SPI_MODE0)); // The MAX3421E can handle up to 26MHz, use MSB First and SPI mode 0
138+ #endif
132139 SPI_SS::Clear ();
133- #if USING_SPI4TEENSY3
140+
141+ #if SPI_HAS_TRANSACTION
142+ uint8_t c[2 ];
143+ c[0 ] = reg | 0x02 ;
144+ c[1 ] = data;
145+ SPI.transfer (c, 2 );
146+ #elif USING_SPI4TEENSY3
134147 uint8_t c[2 ];
135148 c[0 ] = reg | 0x02 ;
136149 c[1 ] = data;
@@ -144,7 +157,11 @@ void MAX3421e< SPI_SS, INTR >::regWr(uint8_t reg, uint8_t data) {
144157 SPDR = data;
145158 while (!(SPSR & (1 << SPIF)));
146159#endif
160+
147161 SPI_SS::Set ();
162+ #if SPI_HAS_TRANSACTION
163+ SPI.endTransaction ();
164+ #endif
148165 XMEM_RELEASE_SPI ();
149166 return ;
150167};
@@ -154,8 +171,16 @@ void MAX3421e< SPI_SS, INTR >::regWr(uint8_t reg, uint8_t data) {
154171template < typename SPI_SS, typename INTR >
155172uint8_t * MAX3421e< SPI_SS, INTR >::bytesWr(uint8_t reg, uint8_t nbytes, uint8_t * data_p) {
156173 XMEM_ACQUIRE_SPI ();
174+ #if SPI_HAS_TRANSACTION
175+ SPI.beginTransaction (SPISettings (26000000 , MSBFIRST, SPI_MODE0)); // The MAX3421E can handle up to 26MHz, use MSB First and SPI mode 0
176+ #endif
157177 SPI_SS::Clear ();
158- #if USING_SPI4TEENSY3
178+
179+ #if SPI_HAS_TRANSACTION
180+ SPI.transfer (reg | 0x02 );
181+ SPI.transfer (data_p, nbytes);
182+ data_p += nbytes;
183+ #elif USING_SPI4TEENSY3
159184 spi4teensy3::send (reg | 0x02 );
160185 spi4teensy3::send (data_p, nbytes);
161186 data_p += nbytes;
@@ -176,7 +201,11 @@ uint8_t* MAX3421e< SPI_SS, INTR >::bytesWr(uint8_t reg, uint8_t nbytes, uint8_t*
176201 }
177202 while (!(SPSR & (1 << SPIF)));
178203#endif
204+
179205 SPI_SS::Set ();
206+ #if SPI_HAS_TRANSACTION
207+ SPI.endTransaction ();
208+ #endif
180209 XMEM_RELEASE_SPI ();
181210 return ( data_p);
182211}
@@ -196,23 +225,31 @@ void MAX3421e< SPI_SS, INTR >::gpioWr(uint8_t data) {
196225template < typename SPI_SS, typename INTR >
197226uint8_t MAX3421e< SPI_SS, INTR >::regRd(uint8_t reg) {
198227 XMEM_ACQUIRE_SPI ();
228+ #if SPI_HAS_TRANSACTION
229+ SPI.beginTransaction (SPISettings (26000000 , MSBFIRST, SPI_MODE0)); // The MAX3421E can handle up to 26MHz, use MSB First and SPI mode 0
230+ #endif
199231 SPI_SS::Clear ();
200- #if USING_SPI4TEENSY3
201- spi4teensy3::send (reg);
202- uint8_t rv = spi4teensy3::receive ();
203- SPI_SS::Set ();
204- #elif defined(ARDUINO_SAM_DUE) && defined(__SAM3X8E__)
232+
233+ #if (defined(ARDUINO_SAM_DUE) && defined(__SAM3X8E__)) || SPI_HAS_TRANSACTION
205234 SPI.transfer (reg);
206- uint8_t rv = SPI.transfer (0 );
235+ uint8_t rv = SPI.transfer (0 ); // Send empty byte
236+ SPI_SS::Set ();
237+ #elif USING_SPI4TEENSY3
238+ spi4teensy3::send (reg);
239+ uint8_t rv = spi4teensy3::receive (); // Send empty byte
207240 SPI_SS::Set ();
208241#else
209242 SPDR = reg;
210243 while (!(SPSR & (1 << SPIF)));
211- SPDR = 0 ; // send empty byte
244+ SPDR = 0 ; // Send empty byte
212245 while (!(SPSR & (1 << SPIF)));
213246 SPI_SS::Set ();
214247 uint8_t rv = SPDR;
215248#endif
249+
250+ #if SPI_HAS_TRANSACTION
251+ SPI.endTransaction ();
252+ #endif
216253 XMEM_RELEASE_SPI ();
217254 return (rv);
218255}
@@ -222,8 +259,16 @@ uint8_t MAX3421e< SPI_SS, INTR >::regRd(uint8_t reg) {
222259template < typename SPI_SS, typename INTR >
223260uint8_t * MAX3421e< SPI_SS, INTR >::bytesRd(uint8_t reg, uint8_t nbytes, uint8_t * data_p) {
224261 XMEM_ACQUIRE_SPI ();
262+ #if SPI_HAS_TRANSACTION
263+ SPI.beginTransaction (SPISettings (26000000 , MSBFIRST, SPI_MODE0)); // The MAX3421E can handle up to 26MHz, use MSB First and SPI mode 0
264+ #endif
225265 SPI_SS::Clear ();
226- #if USING_SPI4TEENSY3
266+
267+ #if SPI_HAS_TRANSACTION
268+ SPI.transfer (reg);
269+ SPI.transfer (data_p, nbytes);
270+ data_p += nbytes;
271+ #elif USING_SPI4TEENSY3
227272 spi4teensy3::send (reg);
228273 spi4teensy3::receive (data_p, nbytes);
229274 data_p += nbytes;
@@ -253,7 +298,11 @@ uint8_t* MAX3421e< SPI_SS, INTR >::bytesRd(uint8_t reg, uint8_t nbytes, uint8_t*
253298 }
254299#endif
255300#endif
301+
256302 SPI_SS::Set ();
303+ #if SPI_HAS_TRANSACTION
304+ SPI.endTransaction ();
305+ #endif
257306 XMEM_RELEASE_SPI ();
258307 return ( data_p);
259308}
@@ -439,7 +488,7 @@ uint8_t MAX3421e< SPI_SS, INTR >::IntHandler() {
439488// template< typename SPI_SS, typename INTR >
440489// uint8_t MAX3421e< SPI_SS, INTR >::GpxHandler()
441490// {
442- // uint8_t GPINIRQ = regRd( rGPINIRQ ); //read GPIN IRQ register
491+ // uint8_t GPINIRQ = regRd( rGPINIRQ ); //read GPIN IRQ register
443492// // if( GPINIRQ & bmGPINIRQ7 ) { //vbus overload
444493// // vbusPwr( OFF ); //attempt powercycle
445494// // delay( 1000 );
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