Merge branch 'main' into quartus-gru

Author: vloncar

.github/PULL_REQUEST_TEMPLATE.md

@@ -30,7 +30,7 @@ Note: Please delete options that are not relevant.
 
 ## Checklist
 
-- [ ] I have read the [guidelines for contributing](https://github.com/fastmachinelearning/hls4ml/blob/master/CONTRIBUTING.md).
+- [ ] I have read the [guidelines for contributing](https://github.com/fastmachinelearning/hls4ml/blob/main/CONTRIBUTING.md).
 - [ ] I have commented my code, particularly in hard-to-understand areas.
 - [ ] I have made corresponding changes to the documentation.
 - [ ] My changes generate no new warnings.

.github/workflows/build-sphinx.yml

@@ -2,7 +2,7 @@ name: build-sphinx
 on:
   push:
     branches:    
-      - master
+      - main
 
 jobs:
   build:
@@ -30,4 +30,4 @@ jobs:
       with:
         branch: gh-pages
         directory: gh-pages
-        github_token: ${{ secrets.PERSONAL_TOKEN }}
+        github_token: ${{ secrets.PERSONAL_TOKEN }}

hls4ml/backends/quartus/quartus_backend.py

@@ -54,29 +54,32 @@ def _register_flows(self):
         ]
         quantization_flow = register_flow('quantization', quantization_passes, requires=[init_flow], backend=self.name)
 
+        optimization_passes = []
+        optimization_flow = register_flow('optimize', optimization_passes, requires=[init_flow], backend=self.name)
+
         templates = self._get_layer_templates()
-        template_flow = register_flow('apply_templates', templates, requires=[init_flow], backend=self.name)
+        template_flow = register_flow('apply_templates', self._get_layer_templates, requires=[init_flow], backend=self.name)
 
         writer_passes = [
             'make_stamp',
             'quartus:write_hls'
         ]
-        writer_flow_requirements = ['optimize', quartus_types_flow, template_flow]
-        self._writer_flow = register_flow('write', writer_passes, requires=writer_flow_requirements, backend=self.name)
+
+        self._writer_flow = register_flow('write', writer_passes, requires=['quartus:ip'], backend=self.name)
 
         all_passes = get_backend_passes(self.name)
 
         extras = [
             # Ideally this should be empty
-            opt_pass for opt_pass in all_passes if opt_pass not in initializers + quartus_types + templates + writer_passes
+            opt_pass for opt_pass in all_passes if opt_pass not in initializers + streaming_passes + quartus_types + quantization_passes + templates + optimization_passes + writer_passes
         ]
 
         if len(extras) > 0:
             extras_flow = register_flow('extras', extras, requires=[init_flow], backend=self.name)
         else:
             extras_flow = None
 
-        ip_flow_requirements = ['optimize', init_flow, streaming_flow, quantization_flow, quartus_types_flow, extras_flow, template_flow]
+        ip_flow_requirements = ['optimize', init_flow, streaming_flow, quantization_flow, optimization_flow, quartus_types_flow, extras_flow, template_flow]
         ip_flow_requirements = list(filter(None, ip_flow_requirements))
 
         self._default_flow = register_flow('ip', None, requires=ip_flow_requirements, backend=self.name)
@@ -97,35 +100,44 @@ def create_initial_config(self, part='Arria10', clock_period=5, io_type='io_para
 
         return config
 
-    def build(self, model, synth=True, fpgasynth=False):
+    def build(self, model, synth=True, fpgasynth=False, log_level=1, cont_if_large_area=False):
+
         """
         Builds the project using Intel HLS compiler.
 
-        Users should generally not call this function directly but instead use `ModelGraph.build()`.
-        This function assumes the model was written with a call to `ModelGraph.write()`
-
         Args:
             model (ModelGraph): The model to build
-            synth, optional: Whether to run synthesis
-            fpgasynth, optional:  Whether to run fpga synthesis
-
+            synth, optional: Whether to run HLS synthesis
+            fpgasynth, optional:  Whether to run FPGA synthesis (Quartus Compile)
+            log_level, optional: Logging level to be displayed during HLS synthesis (0, 1, 2)
+            cont_if_large_area: Instruct the HLS compiler to continue synthesis if the estimated resource usaga exceeds device resources
         Errors raise exceptions
         """
+
+        # Check software needed is present
         found = os.system('command -v i++ > /dev/null')
         if found != 0:
             raise Exception('Intel HLS installation not found. Make sure "i++" is on PATH.')
 
-        with chdir(model.config.get_output_dir()):
-            if synth:
-                os.system('make {}-fpga'.format(model.config.get_project_name()))
-                os.system('./{}-fpga'.format(model.config.get_project_name()))
-
-            if fpgasynth:
+        if fpgasynth:
+                if fpgasynth and not synth:
+                    raise Exception('HLS Synthesis needs to be run before FPGA synthesis')
                 found = os.system('command -v quartus_sh > /dev/null')
                 if found != 0:
                     raise Exception('Quartus installation not found. Make sure "quartus_sh" is on PATH.')
-                os.chdir(model.config.get_project_name() + '-fpga.prj/quartus')
-                os.system('quartus_sh --flow compile quartus_compile')
+
+        with chdir(model.config.get_output_dir()):
+            if synth:
+                quartus_compile = 'QUARTUS_COMPILE=--quartus-compile' if fpgasynth else ''
+                cont_synth = 'CONT_IF_LARGE_AREA=--dont-error-if-large-area-est' if cont_if_large_area else ''
+                log_1 = 'LOGGING_1=-v ' if log_level >= 1 else ''
+                log_2 = 'LOGGING_2=-v ' if log_level >= 2 else '' 
+                os.system(f'make {model.config.get_project_name()}-fpga {log_1} {log_2} {cont_synth} {quartus_compile}')
+                
+                # If running i++ through a container, such a singularity, this command will throw an exception, because the host OS doesn't have access to HLS simulation tools
+                # To avoid the exception, shell into the container (e.g. singularity shell ....) and then execute the following command manually
+                # This command simply tests the IP using a simulation tool and obtains the latency and initiation interval
+                os.system('./{}-fpga'.format(model.config.get_project_name()))
 
         return parse_quartus_report(model.config.get_output_dir())
 

hls4ml/backends/vivado/vivado_backend.py

@@ -56,8 +56,8 @@ def _register_flows(self):
         optimization_flow = register_flow('optimize', optimization_passes, requires=[init_flow], backend=self.name)
 
         vivado_types = [
-            'vivado:register_bram_weights',
             'vivado:transform_types',
+            'vivado:register_bram_weights',
             'vivado:generate_conv_streaming_instructions',
             'vivado:apply_resource_strategy',
         ]