@@ -106,13 +106,24 @@ void serial_printf(const char* fmt, ...)
106106#define MACONX_BANK 0x02
107107
108108#define MACON1 0x00
109+ #define MACSTAT1 0x01
109110#define MACON3 0x02
110111#define MACON4 0x03
111112#define MABBIPG 0x04
112113#define MAIPGL 0x06
113114#define MAIPGH 0x07
114115#define MAMXFLL 0x0a
115116#define MAMXFLH 0x0b
117+ #define MACON2 0x10
118+ #define MACSTAT2 0x11
119+ #define MICMD 0x12
120+ #define MIREGADR 0x14
121+ #define MIRDL 0x18
122+ #define MIRDH 0x19
123+
124+ /* MICMD Register Bit Definitions */
125+ #define MICMD_MIISCAN 0x02
126+ #define MICMD_MIIRD 0x01
116127
117128#define MACON1_TXPAUS 0x08
118129#define MACON1_RXPAUS 0x04
@@ -135,6 +146,9 @@ void serial_printf(const char* fmt, ...)
135146#define MISTAT 0x0a
136147#define EREVID 0x12
137148
149+ /* MISTAT Register Bit Definitions */
150+ #define MISTAT_BUSY 0x01
151+
138152#define EPKTCNT_BANK 0x01
139153#define ERXFCON 0x18
140154#define EPKTCNT 0x19
@@ -720,3 +734,26 @@ uint16_t ENC28J60::readFrameData(uint8_t* buffer, uint16_t framesize)
720734
721735 return _len;
722736}
737+
738+ uint16_t ENC28J60::phyread (uint8_t reg)
739+ {
740+ // ( https://github.com/JAndrassy/EthernetENC/tree/master/src/utility/enc28j60.h )
741+
742+ setregbank (MACONX_BANK);
743+ writereg (MIREGADR, reg);
744+ writereg (MICMD, MICMD_MIIRD);
745+ // wait until the PHY read completes
746+ while (readreg (MISTAT) & MISTAT_BUSY)
747+ {
748+ delayMicroseconds (15 );
749+ }
750+ writereg (MICMD, 0 );
751+ return (readreg (MIRDL) | readreg (MIRDH) << 8 );
752+ }
753+
754+ bool ENC28J60::isLinked ()
755+ {
756+ // ( https://github.com/JAndrassy/EthernetENC/tree/master/src/utility/enc28j60.h )
757+
758+ return !!(phyread (MACSTAT2) & 0x400 );
759+ }
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