diff --git a/data/header_map.yaml b/data/header_map.yaml index a85d2e904..22084088c 100644 --- a/data/header_map.yaml +++ b/data/header_map.yaml @@ -193,4 +193,5 @@ STM32G491xx: STM32G491xx STM32G4A1xx: STM32G4A1xx STM32GBK1CB: STM32GBK1CB STM32U5xx: STM32U5A5, STM32U5A9, STM32U535, STM32U545, STM32U575, STM32U585, STM32U595, STM32U599 +STM32U3xx: STM32U375, STM32U385 STM32WB0x: STM32WB05, STM32WB06, STM32WB07, STM32WB09 diff --git a/data/registers/dbgmcu_u3.yaml b/data/registers/dbgmcu_u3.yaml new file mode 100644 index 000000000..90a0715b8 --- /dev/null +++ b/data/registers/dbgmcu_u3.yaml @@ -0,0 +1,384 @@ +block/DBGMCU: + description: DBGMCU Address block. + items: + - name: IDCODE + byte_offset: 0 + access: Read + fieldset: IDCODE + - name: CR + description: DBGMCU configuration register. + byte_offset: 4 + fieldset: CR + - name: APB1LFZR + description: DBGMCU APB1L peripheral freeze register. + byte_offset: 8 + fieldset: APB1LFZR + - name: APB1HFZR + description: DBGMCU APB1H peripheral freeze register. + byte_offset: 12 + fieldset: APB1HFZR + - name: APB2FZR + description: DBGMCU APB2 peripheral freeze register. + byte_offset: 16 + fieldset: APB2FZR + - name: APB3FZR + description: DBGMCU APB3 peripheral freeze register. + byte_offset: 20 + fieldset: APB3FZR + - name: AHB1FZR + description: DBGMCU AHB1 peripheral freeze register. + byte_offset: 32 + fieldset: AHB1FZR + - name: DBGMCU_SR + description: DBGMCU status register. + byte_offset: 252 + access: Read + fieldset: DBGMCU_SR + - name: DBGMCU_DBG_AUTH_HOST + description: DBGMCU debug host authentication register. + byte_offset: 256 + access: Write + fieldset: DBGMCU_DBG_AUTH_HOST + - name: DBGMCU_DBG_AUTH_DEVICE + description: DBGMCU debug device authentication register. + byte_offset: 260 + access: Read + fieldset: DBGMCU_DBG_AUTH_DEVICE + - name: PIDR4 + description: DBGMCU CoreSight peripheral identity register 4. + byte_offset: 4048 + access: Read + fieldset: PIDR4 + - name: PIDR0 + description: DBGMCU CoreSight peripheral identity register 0. + byte_offset: 4064 + access: Read + fieldset: PIDR0 + - name: PIDR1 + description: DBGMCU CoreSight peripheral identity register 1. + byte_offset: 4068 + access: Read + fieldset: PIDR1 + - name: PIDR2 + description: DBGMCU CoreSight peripheral identity register 2. + byte_offset: 4072 + access: Read + fieldset: PIDR2 + - name: PIDR3 + description: DBGMCU CoreSight peripheral identity register 3. + byte_offset: 4076 + access: Read + fieldset: PIDR3 + - name: CIDR0 + description: DBGMCU CoreSight component identity register 0. + byte_offset: 4080 + access: Read + fieldset: CIDR0 + - name: CIDR1 + description: DBGMCU CoreSight component identity register 1. + byte_offset: 4084 + access: Read + fieldset: CIDR1 + - name: CIDR2 + description: DBGMCU CoreSight component identity register 2. + byte_offset: 4088 + access: Read + fieldset: CIDR2 + - name: CIDR3 + description: DBGMCU CoreSight component identity register 3. + byte_offset: 4092 + access: Read + fieldset: CIDR3 +fieldset/AHB1FZR: + description: DBGMCU AHB1 peripheral freeze register. + fields: + - name: DBG_GPDMA0_STOP + description: "None 0: normal operation. GPDMA channel 0 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 0 is frozen while CPU is in debug mode." + bit_offset: 0 + bit_size: 1 + - name: DBG_GPDMA1_STOP + description: "None 0: normal operation. GPDMA channel 1 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 1 is frozen while CPU is in debug mode." + bit_offset: 1 + bit_size: 1 + - name: DBG_GPDMA2_STOP + description: "None 0: normal operation. GPDMA channel 2 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 2 is frozen while CPU is in debug mode." + bit_offset: 2 + bit_size: 1 + - name: DBG_GPDMA3_STOP + description: "None 0: normal operation. GPDMA channel 3 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 3 is frozen while CPU is in debug mode." + bit_offset: 3 + bit_size: 1 + - name: DBG_GPDMA4_STOP + description: "None 0: normal operation. GPDMA channel 4 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 4 is frozen while CPU is in debug mode." + bit_offset: 4 + bit_size: 1 + - name: DBG_GPDMA5_STOP + description: "None 0: normal operation. GPDMA channel 5 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 5 is frozen while CPU is in debug mode." + bit_offset: 5 + bit_size: 1 + - name: DBG_GPDMA6_STOP + description: "None 0: normal operation. GPDMA channel 6 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 6 is frozen while CPU is in debug mode." + bit_offset: 6 + bit_size: 1 + - name: DBG_GPDMA7_STOP + description: "None 0: normal operation. GPDMA channel 7 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 7 is frozen while CPU is in debug mode." + bit_offset: 7 + bit_size: 1 + - name: DBG_GPDMA8_STOP + description: "None 0: normal operation. GPDMA channel 8 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 8 is frozen while CPU is in debug mode." + bit_offset: 8 + bit_size: 1 + - name: DBG_GPDMA9_STOP + description: "None 0: normal operation. GPDMA channel 9 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 9 is frozen while CPU is in debug mode." + bit_offset: 9 + bit_size: 1 + - name: DBG_GPDMA10_STOP + description: "None 0: normal operation. GPDMA channel 10 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 10 is frozen while CPU is in debug mode." + bit_offset: 10 + bit_size: 1 + - name: DBG_GPDMA11_STOP + description: "None 0: normal operation. GPDMA channel 11 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 11 is frozen while CPU is in debug mode." + bit_offset: 11 + bit_size: 1 +fieldset/APB1HFZR: + description: DBGMCU APB1H peripheral freeze register. + fields: + - name: DBG_LPTIM2_STOP + description: "None 0: normal operation. LPTIM2 continues to operate while CPU is in debug mode. 1: stop in debug. LPTIM2 is frozen while CPU is in debug mode." + bit_offset: 5 + bit_size: 1 +fieldset/APB1LFZR: + description: DBGMCU APB1L peripheral freeze register. + fields: + - name: DBG_TIM2_STOP + description: "None 0: normal operation. TIM2 continues to operate while CPU is in debug mode. 1: stop in debug. TIM2 is frozen while CPU is in debug mode." + bit_offset: 0 + bit_size: 1 + - name: DBG_TIM3_STOP + description: "None 0: normal operation. TIM3 continues to operate while CPU is in debug mode. 1: stop in debug. TIM3 is frozen while CPU is in debug mode." + bit_offset: 1 + bit_size: 1 + - name: DBG_TIM4_STOP + description: "None 0: normal operation. TIM4 continues to operate while CPU is in debug mode. 1: stop in debug. TIM4 is frozen while CPU is in debug mode." + bit_offset: 2 + bit_size: 1 + - name: DBG_TIM6_STOP + description: "None 0: normal operation. TIM6 continues to operate while CPU is in debug mode. 1: stop in debug. TIM6 is frozen while CPU is in debug mode." + bit_offset: 4 + bit_size: 1 + - name: DBG_TIM7_STOP + description: "None 0: normal operation. TIM7 continues to operate while CPU is in debug mode. 1: stop in debug. TIM7 is frozen while CPU is in debug mode." + bit_offset: 5 + bit_size: 1 + - name: DBG_WWDG_STOP + description: "None 0: normal operation. WWDG continues to operate while CPU is in debug mode. 1: stop in debug. WWDG is frozen while CPU is in debug mode." + bit_offset: 11 + bit_size: 1 + - name: DBG_IWDG_STOP + description: "None 0: normal operation. IWDG continues to operate while CPU is in debug mode. 1: stop in debug. IWDG is frozen while CPU is in debug mode." + bit_offset: 12 + bit_size: 1 + - name: DBG_I2C1_STOP + description: "None 0: normal operation. I2C1 SMBUS timeout continues to operate while CPU is in debug mode. 1: stop in debug. I2C1 SMBUS timeout is frozen while CPU is in debug mode." + bit_offset: 21 + bit_size: 1 + - name: DBG_I2C2_STOP + description: "None 0: normal operation. I2C2 SMBUS timeout continues to operate while CPU is in debug mode. 1: stop in debug. I2C2 SMBUS timeout is frozen while CPU is in debug mode." + bit_offset: 22 + bit_size: 1 + - name: DBG_I3C1_STOP + description: "None 0: normal operation. I3C1 timeout continues to operate while CPU is in debug mode. 1: stop in debug. I3C1 timeout is frozen while CPU is in debug mode." + bit_offset: 23 + bit_size: 1 + - name: DBG_RTC_STOP + description: "None 0: normal operation. RTC continues to operate while CPU is in debug mode. 1: stop in debug. RTC is frozen while CPU is in debug mode." + bit_offset: 30 + bit_size: 1 +fieldset/APB2FZR: + description: DBGMCU APB2 peripheral freeze register. + fields: + - name: DBG_TIM1_STOP + description: "None 0: normal operation. TIM1 continues to operate while CPU is in debug mode. 1: stop in debug. TIM1 is frozen while CPU is in debug mode." + bit_offset: 11 + bit_size: 1 + - name: DBG_TIM15_STOP + description: "None 0: normal operation. TIM15 continues to operate while CPU is in debug mode. 1: stop in debug. TIM15 is frozen while CPU is in debug mode." + bit_offset: 16 + bit_size: 1 + - name: DBG_TIM16_STOP + description: "None 0: normal operation. TIM16 continues to operate while CPU is in debug mode. 1: stop in debug. TIM16 is frozen while CPU is in debug mode." + bit_offset: 17 + bit_size: 1 + - name: DBG_TIM17_STOP + description: "None 0: normal operation. TIM17 continues to operate while CPU is in debug mode. 1: stop in debug. TIM17 is frozen while CPU is in debug mode." + bit_offset: 18 + bit_size: 1 + - name: DBG_I3C2_STOP + description: "None 0: normal operation. I3C2 timeout continues to operate while CPU is in debug mode. 1: stop in debug. I3C2 timeout is frozen while CPU is in debug mode." + bit_offset: 27 + bit_size: 1 +fieldset/APB3FZR: + description: DBGMCU APB3 peripheral freeze register. + fields: + - name: DBG_I2C3_STOP + description: "None 0: normal operation. I2C3 continues to operate while CPU is in debug mode. 1: stop in debug. I2C3 is frozen while CPU is in debug mode." + bit_offset: 10 + bit_size: 1 + - name: DBG_LPTIM1_STOP + description: "None 0: normal operation. LPTIM1 continues to operate while CPU is in debug mode. 1: stop in debug. LPTIM1 is frozen while CPU is in debug mode." + bit_offset: 17 + bit_size: 1 + - name: DBG_LPTIM3_STOP + description: "None 0: normal operation. LPTIM3 continues to operate while CPU is in debug mode. 1: stop in debug. LPTIM3 is frozen while CPU is in debug mode." + bit_offset: 18 + bit_size: 1 + - name: DBG_LPTIM4_STOP + description: "None 0: normal operation. LPTIM4 continues to operate while CPU is in debug mode. 1: stop in debug. LPTIM4 is frozen while CPU is in debug mode." + bit_offset: 19 + bit_size: 1 +fieldset/CIDR0: + description: DBGMCU CoreSight component identity register 0. + fields: + - name: PREAMBLE + description: "None 0x0D: common identification value." + bit_offset: 0 + bit_size: 8 +fieldset/CIDR1: + description: DBGMCU CoreSight component identity register 1. + fields: + - name: PREAMBLE + description: "None 0x0: common identification value." + bit_offset: 0 + bit_size: 4 + - name: CLASS + description: "None 0xF: Non-CoreSight component." + bit_offset: 4 + bit_size: 4 +fieldset/CIDR2: + description: DBGMCU CoreSight component identity register 2. + fields: + - name: PREAMBLE + description: "None 0x05: common identification value." + bit_offset: 0 + bit_size: 8 +fieldset/CIDR3: + description: DBGMCU CoreSight component identity register 3. + fields: + - name: PREAMBLE + description: "None 0xB1: common identification value." + bit_offset: 0 + bit_size: 8 +fieldset/CR: + description: DBGMCU configuration register. + fields: + - name: DBG_STOP + description: "All clocks are disabled automatically in Stop mode. All active clocks and oscillators continue to run during Stop mode, allowing full debug capability. On exit from Stop mode, the clock settings are set to the Stop mode exit state. 0: normal operation 1: automatic clock stop disabled." + bit_offset: 1 + bit_size: 1 + - name: DBG_STANDBY + description: "All clocks are disabled and the core powered down automatically in Standby mode. All active clocks and oscillators continue to run during Standby mode, and the core supply is maintained, allowing full debug capability. On exit from Standby mode, a system reset is performed. 0: normal operation 1: automatic clock stop/power down disabled." + bit_offset: 2 + bit_size: 1 + - name: TRACE_IOEN + description: "None 0: disabled-trace pins not assigned 1: enabled-trace pins assigned according to the value of TRACE_MODE field." + bit_offset: 4 + bit_size: 1 + - name: TRACE_EN + description: "This bit enables the trace port clock, TRACECK. 0: disabled 1: enabled." + bit_offset: 5 + bit_size: 1 + - name: TRACE_MODE + description: "None 0x0: trace pins assigned for asynchronous mode (TRACESWO) 0x1: trace pins assigned for synchronous mode with a port width of 1 (TRACECK, TRACED0) 0x2: trace pins assigned for synchronous mode with a port width of 2 ((TRACECK, TRACED0-1) 0x3: trace pins assigned for synchronous mode with a port width of 4 ((TRACECK, TRACED0-3)." + bit_offset: 6 + bit_size: 2 +fieldset/DBGMCU_DBG_AUTH_DEVICE: + description: DBGMCU debug device authentication register. + fields: + - name: AUTH_ID + description: Device specific ID used for RDP regression. + bit_offset: 0 + bit_size: 32 +fieldset/DBGMCU_DBG_AUTH_HOST: + description: DBGMCU debug host authentication register. + fields: + - name: AUTH_KEY + description: The device specific 64-bit authentication key (OEM key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory. + bit_offset: 0 + bit_size: 32 +fieldset/IDCODE: + description: DBGMCU identity code register. + fields: + - name: DEV_ID + description: "None 0x454: STM32U375/385." + bit_offset: 0 + bit_size: 12 + - name: REV_ID + description: "None 0x0001: revision A." + bit_offset: 16 + bit_size: 16 +fieldset/PIDR0: + description: DBGMCU CoreSight peripheral identity register 0. + fields: + - name: PARTNUM + description: "None 0x00: DBGMCU part number." + bit_offset: 0 + bit_size: 8 +fieldset/PIDR1: + description: DBGMCU CoreSight peripheral identity register 1. + fields: + - name: PARTNUM + description: "None 0x0: DBGMCU part number." + bit_offset: 0 + bit_size: 4 + - name: JEP106ID + description: "None 0x0: STMicroelectronics JEDEC code." + bit_offset: 4 + bit_size: 4 +fieldset/PIDR2: + description: DBGMCU CoreSight peripheral identity register 2. + fields: + - name: JEP106ID + description: "None 0x2: STMicroelectronics JEDEC code." + bit_offset: 0 + bit_size: 3 + - name: JEDEC + description: "None 0x1: designer identification specified by JEDEC." + bit_offset: 3 + bit_size: 1 + - name: REVISION + description: "None 0x0: r0p0." + bit_offset: 4 + bit_size: 4 +fieldset/PIDR3: + description: DBGMCU CoreSight peripheral identity register 3. + fields: + - name: CMOD + description: "None 0x0: no customer modifications." + bit_offset: 0 + bit_size: 4 + - name: REVAND + description: "None 0x0: no metal fix." + bit_offset: 4 + bit_size: 4 +fieldset/PIDR4: + description: DBGMCU CoreSight peripheral identity register 4. + fields: + - name: JEP106CON + description: "None 0x0: STMicroelectronics JEDEC code." + bit_offset: 0 + bit_size: 4 + - name: SIZE + description: "None 0x0: The register file occupies a single 4-Kbyte region." + bit_offset: 4 + bit_size: 4 +fieldset/DBGMCU_SR: + description: DBGMCU status register. + fields: + - name: AP_PRESENT + description: "Bit n=0: APn absent Bit n=1: APn present." + bit_offset: 0 + bit_size: 16 + - name: AP_ENABLED + description: "Bit n=0: APn locked Bit n=1: APn enabled." + bit_offset: 16 + bit_size: 16 diff --git a/data/registers/exti_u3.yaml b/data/registers/exti_u3.yaml new file mode 100644 index 000000000..f99931de8 --- /dev/null +++ b/data/registers/exti_u3.yaml @@ -0,0 +1,196 @@ +block/EXTI: + description: EXTI address block description. + items: + - name: RTSR1 + description: EXTI rising trigger selection register. + byte_offset: 0 + fieldset: RTSR1 + - name: FTSR1 + description: EXTI falling trigger selection register. + byte_offset: 4 + fieldset: FTSR1 + - name: SWIER1 + description: EXTI software interrupt event register. + byte_offset: 8 + fieldset: SWIER1 + - name: RPR1 + description: EXTI rising edge pending register. + byte_offset: 12 + fieldset: RPR1 + - name: FPR1 + description: EXTI falling edge pending register. + byte_offset: 16 + fieldset: FPR1 + - name: SECCFGR1 + description: EXTI security configuration register. + byte_offset: 20 + fieldset: SECCFGR1 + - name: PRIVCFGR1 + description: EXTI privilege configuration register. + byte_offset: 24 + fieldset: PRIVCFGR1 + - name: EXTICR1 + description: EXTI external interrupt selection register. + byte_offset: 96 + fieldset: EXTICR1 + - name: EXTICR2 + description: EXTI external interrupt selection register. + byte_offset: 100 + fieldset: EXTICR2 + - name: EXTICR3 + description: EXTI external interrupt selection register. + byte_offset: 104 + fieldset: EXTICR3 + - name: EXTICR4 + description: EXTI external interrupt selection register. + byte_offset: 108 + fieldset: EXTICR4 + - name: LOCKR + description: EXTI lock register. + byte_offset: 112 + fieldset: LOCKR + - name: IMR1 + description: EXTI CPU wake-up with interrupt mask register. + byte_offset: 128 + fieldset: IMR1 + - name: EMR1 + description: EXTI CPU wake-up with event mask register. + byte_offset: 132 + fieldset: EMR1 +fieldset/EMR1: + description: EXTI CPU wake-up with event mask register. + fields: + - name: EM + description: CPU wake-up with event generation mask on event input i. + bit_offset: 0 + bit_size: 1 + array: + len: 23 + stride: 1 +fieldset/EXTICR1: + description: EXTI external interrupt selection register. + fields: + - name: EXTI + description: None. + bit_offset: 0 + bit_size: 8 + array: + len: 4 + stride: 8 +fieldset/EXTICR2: + description: EXTI external interrupt selection register. + fields: + - name: EXTI + description: None. + bit_offset: 0 + bit_size: 8 + array: + len: 4 + stride: 8 +fieldset/EXTICR3: + description: EXTI external interrupt selection register. + fields: + - name: EXTI + description: None. + bit_offset: 0 + bit_size: 8 + array: + len: 4 + stride: 8 +fieldset/EXTICR4: + description: EXTI external interrupt selection register. + fields: + - name: EXTI + description: None. + bit_offset: 0 + bit_size: 8 + array: + len: 4 + stride: 8 +fieldset/FPR1: + description: EXTI falling edge pending register. + fields: + - name: FPIF + description: configurable event inputs i falling edge pending bit. + bit_offset: 0 + bit_size: 1 + array: + len: 23 + stride: 1 +fieldset/FTSR1: + description: EXTI falling trigger selection register. + fields: + - name: FT + description: Falling trigger event configuration bit of configurable event input i. + bit_offset: 0 + bit_size: 1 + array: + len: 23 + stride: 1 +fieldset/IMR1: + description: EXTI CPU wake-up with interrupt mask register. + fields: + - name: IM + description: CPU wake-up with interrupt mask on event input i. + bit_offset: 0 + bit_size: 1 + array: + len: 23 + stride: 1 +fieldset/LOCKR: + description: EXTI lock register. + fields: + - name: LOCK + description: Global security and privilege configuration registers (SECCFGR and PRIVCFGR) lock. + bit_offset: 0 + bit_size: 1 +fieldset/PRIVCFGR1: + description: EXTI privilege configuration register. + fields: + - name: PRIV + description: Security enable on event input i. + bit_offset: 0 + bit_size: 1 + array: + len: 23 + stride: 1 +fieldset/RPR1: + description: EXTI rising edge pending register. + fields: + - name: RPIF + description: Configurable event input i rising edge pending bit. + bit_offset: 0 + bit_size: 1 + array: + len: 23 + stride: 1 +fieldset/RTSR1: + description: EXTI rising trigger selection register. + fields: + - name: RT + description: Rising trigger event configuration bit of configurable event input i. + bit_offset: 0 + bit_size: 1 + array: + len: 23 + stride: 1 +fieldset/SECCFGR1: + description: EXTI security configuration register. + fields: + - name: SEC + description: Security enable on event input i. + bit_offset: 0 + bit_size: 1 + array: + len: 23 + stride: 1 +fieldset/SWIER1: + description: EXTI software interrupt event register. + fields: + - name: SWI + description: Software interrupt on event i. + bit_offset: 0 + bit_size: 1 + array: + len: 23 + stride: 1 diff --git a/data/registers/flash_u3.yaml b/data/registers/flash_u3.yaml new file mode 100644 index 000000000..2098169d8 --- /dev/null +++ b/data/registers/flash_u3.yaml @@ -0,0 +1,3047 @@ +block/FLASH: + description: FLASH address block description. + items: + - name: ACR + description: FLASH access control register. + byte_offset: 0 + fieldset: ACR + - name: KEYR + description: FLASH nonsecure key register. + byte_offset: 8 + access: Write + fieldset: KEYR + - name: SKEYR + description: FLASH secure key register. + byte_offset: 12 + access: Write + fieldset: SKEYR + - name: OPTKEYR + description: FLASH option key register. + byte_offset: 16 + access: Write + fieldset: OPTKEYR + - name: PDKEY1R + description: FLASH bank 1 power-down key register. + byte_offset: 24 + access: Write + fieldset: PDKEY1R + - name: PDKEY2R + description: FLASH bank 2 power-down key register. + byte_offset: 28 + access: Write + fieldset: PDKEY2R + - name: SR + description: FLASH nonsecure status register. + byte_offset: 32 + fieldset: SR + - name: SSR + description: FLASH secure status register. + byte_offset: 36 + fieldset: SSR + - name: CR + description: FLASH nonsecure control register. + byte_offset: 40 + fieldset: CR + - name: SCR + description: FLASH secure control register. + byte_offset: 44 + fieldset: SCR + - name: ECCCORR + description: FLASH ECC register. + byte_offset: 48 + fieldset: ECCCORR + - name: ECCDETR + description: FLASH ECC detection register. + byte_offset: 52 + fieldset: ECCDETR + - name: OPSR + description: FLASH operation status register. + byte_offset: 56 + access: Read + fieldset: OPSR + - name: OPTR + description: FLASH option register. + byte_offset: 64 + fieldset: OPTR + - name: BOOT0R + description: FLASH nonsecure boot address 0 register. + byte_offset: 68 + fieldset: BOOT0R + - name: BOOT1R + description: FLASH nonsecure boot address 1 register. + byte_offset: 72 + fieldset: BOOT1R + - name: SBOOT0R + description: FLASH secure boot address 0 register. + byte_offset: 76 + fieldset: SBOOT0R + - name: SECWM1R1 + description: FLASH secure watermark1 register 1. + byte_offset: 80 + fieldset: SECWM1R1 + - name: SECWM1R2 + description: FLASH secure watermark1 register 2. + byte_offset: 84 + fieldset: SECWM1R2 + - name: WRP1AR + description: FLASH WRP1 area A address register. + byte_offset: 88 + fieldset: WRP1AR + - name: WRP1BR + description: FLASH WRP1 area B address register. + byte_offset: 92 + fieldset: WRP1BR + - name: SECWM2R1 + description: FLASH secure watermark2 register 1. + byte_offset: 96 + fieldset: SECWM2R1 + - name: SECWM2R2 + description: FLASH secure watermark2 register 2. + byte_offset: 100 + fieldset: SECWM2R2 + - name: WRP2AR + description: FLASH WPR2 area A address register. + byte_offset: 104 + fieldset: WRP2AR + - name: WRP2BR + description: FLASH WPR2 area B address register. + byte_offset: 108 + fieldset: WRP2BR + - name: SECBB1R1 + description: FLASH secure block based bank 1 register 1. + byte_offset: 128 + fieldset: SECBB1R1 + - name: SECBB1R2 + description: FLASH secure block based bank 1 register 2. + byte_offset: 132 + fieldset: SECBB1R2 + - name: SECBB1R3 + description: FLASH secure block based bank 1 register 3. + byte_offset: 136 + fieldset: SECBB1R3 + - name: SECBB1R4 + description: FLASH secure block based bank 1 register 4. + byte_offset: 140 + fieldset: SECBB1R4 + - name: SECBB2R1 + description: FLASH secure block based bank 2 register 1. + byte_offset: 160 + fieldset: SECBB2R1 + - name: SECBB2R2 + description: FLASH secure block based bank 2 register 2. + byte_offset: 164 + fieldset: SECBB2R2 + - name: SECBB2R3 + description: FLASH secure block based bank 2 register 3. + byte_offset: 168 + fieldset: SECBB2R3 + - name: SECBB2R4 + description: FLASH secure block based bank 2 register 4. + byte_offset: 172 + fieldset: SECBB2R4 + - name: SECHDPCR + description: FLASH secure HDP control register. + byte_offset: 192 + fieldset: SECHDPCR + - name: PRIVCFGR + description: FLASH privilege configuration register. + byte_offset: 196 + fieldset: PRIVCFGR + - name: SECHDPExTR + description: FLASH HDP extension register. + byte_offset: 200 + fieldset: SECHDPExTR + - name: PRIVBB1R1 + description: FLASH privilege block-based bank 1 register 1. + byte_offset: 208 + fieldset: PRIVBB1R1 + - name: PRIVBB1R2 + description: FLASH privilege block-based bank 1 register 2. + byte_offset: 212 + fieldset: PRIVBB1R2 + - name: PRIVBB1R3 + description: FLASH privilege block-based bank 1 register 3. + byte_offset: 216 + fieldset: PRIVBB1R3 + - name: PRIVBB1R4 + description: FLASH privilege block-based bank 1 register 4. + byte_offset: 220 + fieldset: PRIVBB1R4 + - name: PRIVBB2R1 + description: FLASH privilege block based bank 2 register 1. + byte_offset: 240 + fieldset: PRIVBB2R1 + - name: PRIVBB2R2 + description: FLASH privilege block based bank 2 register 2. + byte_offset: 244 + fieldset: PRIVBB2R2 + - name: PRIVBB2R3 + description: FLASH privilege block based bank 2 register 3. + byte_offset: 248 + fieldset: PRIVBB2R3 + - name: PRIVBB2R4 + description: FLASH privilege block based bank 2 register 4. + byte_offset: 252 + fieldset: PRIVBB2R4 + - name: OEM1KEYR1 + description: FLASH OEM1 key register 1. + byte_offset: 272 + access: Write + fieldset: OEM1KEYR1 + - name: OEM1KEYR2 + description: FLASH OEM1 key register 2. + byte_offset: 276 + access: Write + fieldset: OEM1KEYR2 + - name: OEM1KEYR3 + description: FLASH OEM1 key register 3. + byte_offset: 280 + access: Write + fieldset: OEM1KEYR3 + - name: OEM1KEYR4 + description: FLASH OEM1 key register 4. + byte_offset: 284 + access: Write + fieldset: OEM1KEYR4 + - name: OEM2KEYR1 + description: FLASH OEM2 key register 1. + byte_offset: 288 + access: Write + fieldset: OEM2KEYR1 + - name: OEM2KEYR2 + description: FLASH OEM2 key register 2. + byte_offset: 292 + access: Write + fieldset: OEM2KEYR2 + - name: OEM2KEYR3 + description: FLASH OEM2 key register 3. + byte_offset: 296 + access: Write + fieldset: OEM2KEYR3 + - name: OEM2KEYR4 + description: FLASH OEM2 key register 4. + byte_offset: 300 + access: Write + fieldset: OEM2KEYR4 + - name: OEMKEYSR + description: FLASH OEM key status register. + byte_offset: 304 + access: Read + fieldset: OEMKEYSR +fieldset/ACR: + description: FLASH access control register. + fields: + - name: LATENCY + description: Latency. + bit_offset: 0 + bit_size: 4 + - name: PRFTEN + description: Prefetch enable. + bit_offset: 8 + bit_size: 1 + - name: LPM + description: Low-power read mode. + bit_offset: 11 + bit_size: 1 + - name: PDREQ1 + description: Bank 1 power-down mode request. + bit_offset: 12 + bit_size: 1 + - name: PDREQ2 + description: Bank 2 power-down mode request. + bit_offset: 13 + bit_size: 1 + - name: SLEEP_PD + description: Flash memory power-down mode during Sleep mode. + bit_offset: 14 + bit_size: 1 +fieldset/BOOT0R: + description: FLASH nonsecure boot address 0 register. + fields: + - name: ADD + description: Nonsecure boot base address 0. + bit_offset: 7 + bit_size: 25 +fieldset/BOOT1R: + description: FLASH nonsecure boot address 1 register. + fields: + - name: ADD + description: nonsecure boot address 1. + bit_offset: 7 + bit_size: 25 +fieldset/CR: + description: FLASH nonsecure control register. + fields: + - name: PG + description: Nonsecure programming. + bit_offset: 0 + bit_size: 1 + - name: PER + description: Nonsecure page erase. + bit_offset: 1 + bit_size: 1 + - name: MER1 + description: Nonsecure bank 1 mass erase. + bit_offset: 2 + bit_size: 1 + - name: PNB + description: Nonsecure page number selection. + bit_offset: 3 + bit_size: 7 + - name: BKER + description: Nonsecure bank selection for page erase. + bit_offset: 11 + bit_size: 1 + - name: BWR + description: Nonsecure burst write programming mode. + bit_offset: 14 + bit_size: 1 + - name: MER2 + description: Nonsecure bank 2 mass erase. + bit_offset: 15 + bit_size: 1 + - name: STRT + description: Nonsecure start. + bit_offset: 16 + bit_size: 1 + - name: OPTSTRT + description: Option modification start. + bit_offset: 17 + bit_size: 1 + - name: EOPIE + description: Nonsecure end of operation interrupt enable. + bit_offset: 24 + bit_size: 1 + - name: ERRIE + description: Nonsecure error interrupt enable. + bit_offset: 25 + bit_size: 1 + - name: OBL_LAUNCH + description: Option-byte loading forced. + bit_offset: 27 + bit_size: 1 + - name: OPTLOCK + description: Option lock. + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: Nonsecure lock. + bit_offset: 31 + bit_size: 1 +fieldset/ECCCORR: + description: FLASH ECC register. + fields: + - name: ADDR_ECC + description: ECC fail address. + bit_offset: 0 + bit_size: 19 + - name: BK_ECC + description: ECC fail bank. + bit_offset: 21 + bit_size: 1 + - name: SYSF_ECC + description: System flash memory ECC fail. + bit_offset: 22 + bit_size: 1 + - name: ECCIE + description: ECC correction interrupt enable. + bit_offset: 24 + bit_size: 1 + - name: ECCC + description: ECC correction. + bit_offset: 30 + bit_size: 1 +fieldset/ECCDETR: + description: FLASH ECC detection register. + fields: + - name: ADDR_ECC + description: ECC fail address. + bit_offset: 0 + bit_size: 19 + - name: BK_ECC + description: ECC fail bank. + bit_offset: 21 + bit_size: 1 + - name: SYSF_ECC + description: System flash memory ECC fail. + bit_offset: 22 + bit_size: 1 + - name: ECCD + description: ECC detection. + bit_offset: 31 + bit_size: 1 +fieldset/KEYR: + description: FLASH nonsecure key register. + fields: + - name: KEY + description: Flash memory nonsecure key. + bit_offset: 0 + bit_size: 32 +fieldset/OEM1KEYR1: + description: FLASH OEM1 key register 1. + fields: + - name: OEM1KEY + description: OEM1[31:0] bytes key. + bit_offset: 0 + bit_size: 32 +fieldset/OEM1KEYR2: + description: FLASH OEM1 key register 2. + fields: + - name: OEM1KEY + description: OEM1[63:32] bytes key. + bit_offset: 0 + bit_size: 32 +fieldset/OEM1KEYR3: + description: FLASH OEM1 key register 3. + fields: + - name: OEM1KEY + description: OEM1[95:64] bytes key. + bit_offset: 0 + bit_size: 32 +fieldset/OEM1KEYR4: + description: FLASH OEM1 key register 4. + fields: + - name: OEM1KEY + description: OEM1[127:96] bytes key. + bit_offset: 0 + bit_size: 32 +fieldset/OEM2KEYR1: + description: FLASH OEM2 key register 1. + fields: + - name: OEM2KEY + description: OEM2[31:0] bytes key. + bit_offset: 0 + bit_size: 32 +fieldset/OEM2KEYR2: + description: FLASH OEM2 key register 2. + fields: + - name: OEM2KEY + description: OEM2[63:32] bytes key. + bit_offset: 0 + bit_size: 32 +fieldset/OEM2KEYR3: + description: FLASH OEM2 key register 3. + fields: + - name: OEM2KEY + description: OEM2[95:64] bytes key. + bit_offset: 0 + bit_size: 32 +fieldset/OEM2KEYR4: + description: FLASH OEM2 key register 4. + fields: + - name: OEM2KEY + description: OEM2[127:96] bytes key. + bit_offset: 0 + bit_size: 32 +fieldset/OEMKEYSR: + description: FLASH OEM key status register. + fields: + - name: OEM1KEYCRC + description: 8-bit OEMKEY1 CRC. + bit_offset: 0 + bit_size: 8 + - name: OEM2KEYCRC + description: 8-bit OEM2KEY CRC. + bit_offset: 16 + bit_size: 8 +fieldset/OPSR: + description: FLASH operation status register. + fields: + - name: ADDR_OP + description: Interrupted operation address. + bit_offset: 0 + bit_size: 19 + - name: BK_OP + description: Interrupted operation bank. + bit_offset: 21 + bit_size: 1 + - name: SYSF_OP + description: Operation in system flash memory interrupted. + bit_offset: 22 + bit_size: 1 + - name: CODE_OP + description: Flash memory operation code. + bit_offset: 29 + bit_size: 3 + enum: CODE_OP +fieldset/OPTKEYR: + description: FLASH option key register. + fields: + - name: KEY + description: Option-byte key. + bit_offset: 0 + bit_size: 32 +fieldset/OPTR: + description: FLASH option register. + fields: + - name: RDP + description: Readout protection level. + bit_offset: 0 + bit_size: 8 + enum: RDP + - name: BOR_LEV + description: BOR reset level. + bit_offset: 8 + bit_size: 3 + enum: BOR_LEV + - name: BDRST_POR + description: Backup domain reset with power-on reset. + bit_offset: 11 + bit_size: 1 + - name: NRST_STOP + description: Reset generation in Stop mode. + bit_offset: 12 + bit_size: 1 + - name: NRST_STDBY + description: Reset generation in Standby mode. + bit_offset: 13 + bit_size: 1 + - name: NRST_SHDW + description: Reset generation in Shutdown mode. + bit_offset: 14 + bit_size: 1 + - name: SRAM1_RST + description: SRAM1 erase upon system reset. + bit_offset: 15 + bit_size: 1 + - name: IWDG_SW + description: Independent watchdog selection. + bit_offset: 16 + bit_size: 1 + - name: IWDG_STOP + description: Independent watchdog counter freeze in Stop mode. + bit_offset: 17 + bit_size: 1 + - name: IWDG_STDBY + description: Independent watchdog counter freeze in Standby mode. + bit_offset: 18 + bit_size: 1 + - name: WWDG_SW + description: Window watchdog selection. + bit_offset: 19 + bit_size: 1 + - name: SWAP_BANK + description: Swap banks. + bit_offset: 20 + bit_size: 1 + - name: DUALBANK + description: Dual-bank on 512-Kbyte flash memory devices. + bit_offset: 21 + bit_size: 1 + - name: SRAM2_PE + description: SRAM2 parity check enable. + bit_offset: 24 + bit_size: 1 + - name: SRAM2_RST + description: SRAM2 erase when system reset. + bit_offset: 25 + bit_size: 1 + - name: NSWBOOT0 + description: Software BOOT0. + bit_offset: 26 + bit_size: 1 + - name: NBOOT0 + description: NBOOT0 option bit. + bit_offset: 27 + bit_size: 1 + - name: IO_VDD_HSLV + description: High-speed I/O at low Vless thansub>DD less than/sub>voltage configuration bit. + bit_offset: 29 + bit_size: 1 + - name: IO_VDDIO2_HSLV + description: High-speed I/O at low Vless thansub>DDIO2less than/sub> voltage configuration bit. + bit_offset: 30 + bit_size: 1 + - name: TZEN + description: Global TrustZone security enable. + bit_offset: 31 + bit_size: 1 +fieldset/PDKEY1R: + description: FLASH bank 1 power-down key register. + fields: + - name: KEY1 + description: Bank 1 power-down key. + bit_offset: 0 + bit_size: 32 +fieldset/PDKEY2R: + description: FLASH bank 2 power-down key register. + fields: + - name: KEY2 + description: Bank 2 power-down key. + bit_offset: 0 + bit_size: 32 +fieldset/PRIVBB1R1: + description: FLASH privilege block-based bank 1 register 1. + fields: + - name: PRIV0 + description: Page privileged/unprivileged attribution. + bit_offset: 0 + bit_size: 1 + - name: PRIV1 + description: Page privileged/unprivileged attribution. + bit_offset: 1 + bit_size: 1 + - name: PRIV2 + description: Page privileged/unprivileged attribution. + bit_offset: 2 + bit_size: 1 + - name: PRIV3 + description: Page privileged/unprivileged attribution. + bit_offset: 3 + bit_size: 1 + - name: PRIV4 + description: Page privileged/unprivileged attribution. + bit_offset: 4 + bit_size: 1 + - name: PRIV5 + description: Page privileged/unprivileged attribution. + bit_offset: 5 + bit_size: 1 + - name: PRIV6 + description: Page privileged/unprivileged attribution. + bit_offset: 6 + bit_size: 1 + - name: PRIV7 + description: Page privileged/unprivileged attribution. + bit_offset: 7 + bit_size: 1 + - name: PRIV8 + description: Page privileged/unprivileged attribution. + bit_offset: 8 + bit_size: 1 + - name: PRIV9 + description: Page privileged/unprivileged attribution. + bit_offset: 9 + bit_size: 1 + - name: PRIV10 + description: Page privileged/unprivileged attribution. + bit_offset: 10 + bit_size: 1 + - name: PRIV11 + description: Page privileged/unprivileged attribution. + bit_offset: 11 + bit_size: 1 + - name: PRIV12 + description: Page privileged/unprivileged attribution. + bit_offset: 12 + bit_size: 1 + - name: PRIV13 + description: Page privileged/unprivileged attribution. + bit_offset: 13 + bit_size: 1 + - name: PRIV14 + description: Page privileged/unprivileged attribution. + bit_offset: 14 + bit_size: 1 + - name: PRIV15 + description: Page privileged/unprivileged attribution. + bit_offset: 15 + bit_size: 1 + - name: PRIV16 + description: Page privileged/unprivileged attribution. + bit_offset: 16 + bit_size: 1 + - name: PRIV17 + description: Page privileged/unprivileged attribution. + bit_offset: 17 + bit_size: 1 + - name: PRIV18 + description: Page privileged/unprivileged attribution. + bit_offset: 18 + bit_size: 1 + - name: PRIV19 + description: Page privileged/unprivileged attribution. + bit_offset: 19 + bit_size: 1 + - name: PRIV20 + description: Page privileged/unprivileged attribution. + bit_offset: 20 + bit_size: 1 + - name: PRIV21 + description: Page privileged/unprivileged attribution. + bit_offset: 21 + bit_size: 1 + - name: PRIV22 + description: Page privileged/unprivileged attribution. + bit_offset: 22 + bit_size: 1 + - name: PRIV23 + description: Page privileged/unprivileged attribution. + bit_offset: 23 + bit_size: 1 + - name: PRIV24 + description: Page privileged/unprivileged attribution. + bit_offset: 24 + bit_size: 1 + - name: PRIV25 + description: Page privileged/unprivileged attribution. + bit_offset: 25 + bit_size: 1 + - name: PRIV26 + description: Page privileged/unprivileged attribution. + bit_offset: 26 + bit_size: 1 + - name: PRIV27 + description: Page privileged/unprivileged attribution. + bit_offset: 27 + bit_size: 1 + - name: PRIV28 + description: Page privileged/unprivileged attribution. + bit_offset: 28 + bit_size: 1 + - name: PRIV29 + description: Page privileged/unprivileged attribution. + bit_offset: 29 + bit_size: 1 + - name: PRIV30 + description: Page privileged/unprivileged attribution. + bit_offset: 30 + bit_size: 1 + - name: PRIV31 + description: Page privileged/unprivileged attribution. + bit_offset: 31 + bit_size: 1 +fieldset/PRIVBB1R2: + description: FLASH privilege block-based bank 1 register 2. + fields: + - name: PRIV0 + description: Page privileged/unprivileged attribution. + bit_offset: 0 + bit_size: 1 + - name: PRIV1 + description: Page privileged/unprivileged attribution. + bit_offset: 1 + bit_size: 1 + - name: PRIV2 + description: Page privileged/unprivileged attribution. + bit_offset: 2 + bit_size: 1 + - name: PRIV3 + description: Page privileged/unprivileged attribution. + bit_offset: 3 + bit_size: 1 + - name: PRIV4 + description: Page privileged/unprivileged attribution. + bit_offset: 4 + bit_size: 1 + - name: PRIV5 + description: Page privileged/unprivileged attribution. + bit_offset: 5 + bit_size: 1 + - name: PRIV6 + description: Page privileged/unprivileged attribution. + bit_offset: 6 + bit_size: 1 + - name: PRIV7 + description: Page privileged/unprivileged attribution. + bit_offset: 7 + bit_size: 1 + - name: PRIV8 + description: Page privileged/unprivileged attribution. + bit_offset: 8 + bit_size: 1 + - name: PRIV9 + description: Page privileged/unprivileged attribution. + bit_offset: 9 + bit_size: 1 + - name: PRIV10 + description: Page privileged/unprivileged attribution. + bit_offset: 10 + bit_size: 1 + - name: PRIV11 + description: Page privileged/unprivileged attribution. + bit_offset: 11 + bit_size: 1 + - name: PRIV12 + description: Page privileged/unprivileged attribution. + bit_offset: 12 + bit_size: 1 + - name: PRIV13 + description: Page privileged/unprivileged attribution. + bit_offset: 13 + bit_size: 1 + - name: PRIV14 + description: Page privileged/unprivileged attribution. + bit_offset: 14 + bit_size: 1 + - name: PRIV15 + description: Page privileged/unprivileged attribution. + bit_offset: 15 + bit_size: 1 + - name: PRIV16 + description: Page privileged/unprivileged attribution. + bit_offset: 16 + bit_size: 1 + - name: PRIV17 + description: Page privileged/unprivileged attribution. + bit_offset: 17 + bit_size: 1 + - name: PRIV18 + description: Page privileged/unprivileged attribution. + bit_offset: 18 + bit_size: 1 + - name: PRIV19 + description: Page privileged/unprivileged attribution. + bit_offset: 19 + bit_size: 1 + - name: PRIV20 + description: Page privileged/unprivileged attribution. + bit_offset: 20 + bit_size: 1 + - name: PRIV21 + description: Page privileged/unprivileged attribution. + bit_offset: 21 + bit_size: 1 + - name: PRIV22 + description: Page privileged/unprivileged attribution. + bit_offset: 22 + bit_size: 1 + - name: PRIV23 + description: Page privileged/unprivileged attribution. + bit_offset: 23 + bit_size: 1 + - name: PRIV24 + description: Page privileged/unprivileged attribution. + bit_offset: 24 + bit_size: 1 + - name: PRIV25 + description: Page privileged/unprivileged attribution. + bit_offset: 25 + bit_size: 1 + - name: PRIV26 + description: Page privileged/unprivileged attribution. + bit_offset: 26 + bit_size: 1 + - name: PRIV27 + description: Page privileged/unprivileged attribution. + bit_offset: 27 + bit_size: 1 + - name: PRIV28 + description: Page privileged/unprivileged attribution. + bit_offset: 28 + bit_size: 1 + - name: PRIV29 + description: Page privileged/unprivileged attribution. + bit_offset: 29 + bit_size: 1 + - name: PRIV30 + description: Page privileged/unprivileged attribution. + bit_offset: 30 + bit_size: 1 + - name: PRIV31 + description: Page privileged/unprivileged attribution. + bit_offset: 31 + bit_size: 1 +fieldset/PRIVBB1R3: + description: FLASH privilege block-based bank 1 register 3. + fields: + - name: PRIV0 + description: Page privileged/unprivileged attribution. + bit_offset: 0 + bit_size: 1 + - name: PRIV1 + description: Page privileged/unprivileged attribution. + bit_offset: 1 + bit_size: 1 + - name: PRIV2 + description: Page privileged/unprivileged attribution. + bit_offset: 2 + bit_size: 1 + - name: PRIV3 + description: Page privileged/unprivileged attribution. + bit_offset: 3 + bit_size: 1 + - name: PRIV4 + description: Page privileged/unprivileged attribution. + bit_offset: 4 + bit_size: 1 + - name: PRIV5 + description: Page privileged/unprivileged attribution. + bit_offset: 5 + bit_size: 1 + - name: PRIV6 + description: Page privileged/unprivileged attribution. + bit_offset: 6 + bit_size: 1 + - name: PRIV7 + description: Page privileged/unprivileged attribution. + bit_offset: 7 + bit_size: 1 + - name: PRIV8 + description: Page privileged/unprivileged attribution. + bit_offset: 8 + bit_size: 1 + - name: PRIV9 + description: Page privileged/unprivileged attribution. + bit_offset: 9 + bit_size: 1 + - name: PRIV10 + description: Page privileged/unprivileged attribution. + bit_offset: 10 + bit_size: 1 + - name: PRIV11 + description: Page privileged/unprivileged attribution. + bit_offset: 11 + bit_size: 1 + - name: PRIV12 + description: Page privileged/unprivileged attribution. + bit_offset: 12 + bit_size: 1 + - name: PRIV13 + description: Page privileged/unprivileged attribution. + bit_offset: 13 + bit_size: 1 + - name: PRIV14 + description: Page privileged/unprivileged attribution. + bit_offset: 14 + bit_size: 1 + - name: PRIV15 + description: Page privileged/unprivileged attribution. + bit_offset: 15 + bit_size: 1 + - name: PRIV16 + description: Page privileged/unprivileged attribution. + bit_offset: 16 + bit_size: 1 + - name: PRIV17 + description: Page privileged/unprivileged attribution. + bit_offset: 17 + bit_size: 1 + - name: PRIV18 + description: Page privileged/unprivileged attribution. + bit_offset: 18 + bit_size: 1 + - name: PRIV19 + description: Page privileged/unprivileged attribution. + bit_offset: 19 + bit_size: 1 + - name: PRIV20 + description: Page privileged/unprivileged attribution. + bit_offset: 20 + bit_size: 1 + - name: PRIV21 + description: Page privileged/unprivileged attribution. + bit_offset: 21 + bit_size: 1 + - name: PRIV22 + description: Page privileged/unprivileged attribution. + bit_offset: 22 + bit_size: 1 + - name: PRIV23 + description: Page privileged/unprivileged attribution. + bit_offset: 23 + bit_size: 1 + - name: PRIV24 + description: Page privileged/unprivileged attribution. + bit_offset: 24 + bit_size: 1 + - name: PRIV25 + description: Page privileged/unprivileged attribution. + bit_offset: 25 + bit_size: 1 + - name: PRIV26 + description: Page privileged/unprivileged attribution. + bit_offset: 26 + bit_size: 1 + - name: PRIV27 + description: Page privileged/unprivileged attribution. + bit_offset: 27 + bit_size: 1 + - name: PRIV28 + description: Page privileged/unprivileged attribution. + bit_offset: 28 + bit_size: 1 + - name: PRIV29 + description: Page privileged/unprivileged attribution. + bit_offset: 29 + bit_size: 1 + - name: PRIV30 + description: Page privileged/unprivileged attribution. + bit_offset: 30 + bit_size: 1 + - name: PRIV31 + description: Page privileged/unprivileged attribution. + bit_offset: 31 + bit_size: 1 +fieldset/PRIVBB1R4: + description: FLASH privilege block-based bank 1 register 4. + fields: + - name: PRIV0 + description: Page privileged/unprivileged attribution. + bit_offset: 0 + bit_size: 1 + - name: PRIV1 + description: Page privileged/unprivileged attribution. + bit_offset: 1 + bit_size: 1 + + - name: PRIV2 + description: Page privileged/unprivileged attribution. + bit_offset: 2 + bit_size: 1 + + - name: PRIV3 + description: Page privileged/unprivileged attribution. + bit_offset: 3 + bit_size: 1 + + - name: PRIV4 + description: Page privileged/unprivileged attribution. + bit_offset: 4 + bit_size: 1 + + - name: PRIV5 + description: Page privileged/unprivileged attribution. + bit_offset: 5 + bit_size: 1 + + - name: PRIV6 + description: Page privileged/unprivileged attribution. + bit_offset: 6 + bit_size: 1 + + - name: PRIV7 + description: Page privileged/unprivileged attribution. + bit_offset: 7 + bit_size: 1 + + - name: PRIV8 + description: Page privileged/unprivileged attribution. + bit_offset: 8 + bit_size: 1 + + - name: PRIV9 + description: Page privileged/unprivileged attribution. + bit_offset: 9 + bit_size: 1 + + - name: PRIV10 + description: Page privileged/unprivileged attribution. + bit_offset: 10 + bit_size: 1 + + - name: PRIV11 + description: Page privileged/unprivileged attribution. + bit_offset: 11 + bit_size: 1 + + - name: PRIV12 + description: Page privileged/unprivileged attribution. + bit_offset: 12 + bit_size: 1 + + - name: PRIV13 + description: Page privileged/unprivileged attribution. + bit_offset: 13 + bit_size: 1 + - name: PRIV14 + description: Page privileged/unprivileged attribution. + bit_offset: 14 + bit_size: 1 + - name: PRIV15 + description: Page privileged/unprivileged attribution. + bit_offset: 15 + bit_size: 1 + - name: PRIV16 + description: Page privileged/unprivileged attribution. + bit_offset: 16 + bit_size: 1 + - name: PRIV17 + description: Page privileged/unprivileged attribution. + bit_offset: 17 + bit_size: 1 + - name: PRIV18 + description: Page privileged/unprivileged attribution. + bit_offset: 18 + bit_size: 1 + - name: PRIV19 + description: Page privileged/unprivileged attribution. + bit_offset: 19 + bit_size: 1 + - name: PRIV20 + description: Page privileged/unprivileged attribution. + bit_offset: 20 + bit_size: 1 + - name: PRIV21 + description: Page privileged/unprivileged attribution. + bit_offset: 21 + bit_size: 1 + - name: PRIV22 + description: Page privileged/unprivileged attribution. + bit_offset: 22 + bit_size: 1 + - name: PRIV23 + description: Page privileged/unprivileged attribution. + bit_offset: 23 + bit_size: 1 + - name: PRIV24 + description: Page privileged/unprivileged attribution. + bit_offset: 24 + bit_size: 1 + - name: PRIV25 + description: Page privileged/unprivileged attribution. + bit_offset: 25 + bit_size: 1 + - name: PRIV26 + description: Page privileged/unprivileged attribution. + bit_offset: 26 + bit_size: 1 + - name: PRIV27 + description: Page privileged/unprivileged attribution. + bit_offset: 27 + bit_size: 1 + - name: PRIV28 + description: Page privileged/unprivileged attribution. + bit_offset: 28 + bit_size: 1 + - name: PRIV29 + description: Page privileged/unprivileged attribution. + bit_offset: 29 + bit_size: 1 + - name: PRIV30 + description: Page privileged/unprivileged attribution. + bit_offset: 30 + bit_size: 1 + - name: PRIV31 + description: Page privileged/unprivileged attribution. + bit_offset: 31 + bit_size: 1 + +fieldset/PRIVBB2R1: + description: FLASH privilege block based bank 2 register 1. + fields: + - name: PRIV0 + description: Page privileged/unprivileged attribution. + bit_offset: 0 + bit_size: 1 + - name: PRIV1 + description: Page privileged/unprivileged attribution. + bit_offset: 1 + bit_size: 1 + - name: PRIV2 + description: Page privileged/unprivileged attribution. + bit_offset: 2 + bit_size: 1 + - name: PRIV3 + description: Page privileged/unprivileged attribution. + bit_offset: 3 + bit_size: 1 + - name: PRIV4 + description: Page privileged/unprivileged attribution. + bit_offset: 4 + bit_size: 1 + - name: PRIV5 + description: Page privileged/unprivileged attribution. + bit_offset: 5 + bit_size: 1 + - name: PRIV6 + description: Page privileged/unprivileged attribution. + bit_offset: 6 + bit_size: 1 + - name: PRIV7 + description: Page privileged/unprivileged attribution. + bit_offset: 7 + bit_size: 1 + - name: PRIV8 + description: Page privileged/unprivileged attribution. + bit_offset: 8 + bit_size: 1 + - name: PRIV9 + description: Page privileged/unprivileged attribution. + bit_offset: 9 + bit_size: 1 + - name: PRIV10 + description: Page privileged/unprivileged attribution. + bit_offset: 10 + bit_size: 1 + - name: PRIV11 + description: Page privileged/unprivileged attribution. + bit_offset: 11 + bit_size: 1 + - name: PRIV12 + description: Page privileged/unprivileged attribution. + bit_offset: 12 + bit_size: 1 + - name: PRIV13 + description: Page privileged/unprivileged attribution. + bit_offset: 13 + bit_size: 1 + - name: PRIV14 + description: Page privileged/unprivileged attribution. + bit_offset: 14 + bit_size: 1 + - name: PRIV15 + description: Page privileged/unprivileged attribution. + bit_offset: 15 + bit_size: 1 + - name: PRIV16 + description: Page privileged/unprivileged attribution. + bit_offset: 16 + bit_size: 1 + - name: PRIV17 + description: Page privileged/unprivileged attribution. + bit_offset: 17 + bit_size: 1 + - name: PRIV18 + description: Page privileged/unprivileged attribution. + bit_offset: 18 + bit_size: 1 + - name: PRIV19 + description: Page privileged/unprivileged attribution. + bit_offset: 19 + bit_size: 1 + - name: PRIV20 + description: Page privileged/unprivileged attribution. + bit_offset: 20 + bit_size: 1 + - name: PRIV21 + description: Page privileged/unprivileged attribution. + bit_offset: 21 + bit_size: 1 + - name: PRIV22 + description: Page privileged/unprivileged attribution. + bit_offset: 22 + bit_size: 1 + - name: PRIV23 + description: Page privileged/unprivileged attribution. + bit_offset: 23 + bit_size: 1 + - name: PRIV24 + description: Page privileged/unprivileged attribution. + bit_offset: 24 + bit_size: 1 + - name: PRIV25 + description: Page privileged/unprivileged attribution. + bit_offset: 25 + bit_size: 1 + - name: PRIV26 + description: Page privileged/unprivileged attribution. + bit_offset: 26 + bit_size: 1 + - name: PRIV27 + description: Page privileged/unprivileged attribution. + bit_offset: 27 + bit_size: 1 + - name: PRIV28 + description: Page privileged/unprivileged attribution. + bit_offset: 28 + bit_size: 1 + - name: PRIV29 + description: Page privileged/unprivileged attribution. + bit_offset: 29 + bit_size: 1 + - name: PRIV30 + description: Page privileged/unprivileged attribution. + bit_offset: 30 + bit_size: 1 + - name: PRIV31 + description: Page privileged/unprivileged attribution. + bit_offset: 31 + bit_size: 1 +fieldset/PRIVBB2R2: + description: FLASH privilege block based bank 2 register 2. + fields: + - name: PRIV0 + description: Page privileged/unprivileged attribution. + bit_offset: 0 + bit_size: 1 + - name: PRIV1 + description: Page privileged/unprivileged attribution. + bit_offset: 1 + bit_size: 1 + - name: PRIV2 + description: Page privileged/unprivileged attribution. + bit_offset: 2 + bit_size: 1 + - name: PRIV3 + description: Page privileged/unprivileged attribution. + bit_offset: 3 + bit_size: 1 + - name: PRIV4 + description: Page privileged/unprivileged attribution. + bit_offset: 4 + bit_size: 1 + - name: PRIV5 + description: Page privileged/unprivileged attribution. + bit_offset: 5 + bit_size: 1 + - name: PRIV6 + description: Page privileged/unprivileged attribution. + bit_offset: 6 + bit_size: 1 + - name: PRIV7 + description: Page privileged/unprivileged attribution. + bit_offset: 7 + bit_size: 1 + - name: PRIV8 + description: Page privileged/unprivileged attribution. + bit_offset: 8 + bit_size: 1 + - name: PRIV9 + description: Page privileged/unprivileged attribution. + bit_offset: 9 + bit_size: 1 + - name: PRIV10 + description: Page privileged/unprivileged attribution. + bit_offset: 10 + bit_size: 1 + - name: PRIV11 + description: Page privileged/unprivileged attribution. + bit_offset: 11 + bit_size: 1 + - name: PRIV12 + description: Page privileged/unprivileged attribution. + bit_offset: 12 + bit_size: 1 + - name: PRIV13 + description: Page privileged/unprivileged attribution. + bit_offset: 13 + bit_size: 1 + - name: PRIV14 + description: Page privileged/unprivileged attribution. + bit_offset: 14 + bit_size: 1 + - name: PRIV15 + description: Page privileged/unprivileged attribution. + bit_offset: 15 + bit_size: 1 + - name: PRIV16 + description: Page privileged/unprivileged attribution. + bit_offset: 16 + bit_size: 1 + - name: PRIV17 + description: Page privileged/unprivileged attribution. + bit_offset: 17 + bit_size: 1 + - name: PRIV18 + description: Page privileged/unprivileged attribution. + bit_offset: 18 + bit_size: 1 + - name: PRIV19 + description: Page privileged/unprivileged attribution. + bit_offset: 19 + bit_size: 1 + - name: PRIV20 + description: Page privileged/unprivileged attribution. + bit_offset: 20 + bit_size: 1 + - name: PRIV21 + description: Page privileged/unprivileged attribution. + bit_offset: 21 + bit_size: 1 + - name: PRIV22 + description: Page privileged/unprivileged attribution. + bit_offset: 22 + bit_size: 1 + - name: PRIV23 + description: Page privileged/unprivileged attribution. + bit_offset: 23 + bit_size: 1 + - name: PRIV24 + description: Page privileged/unprivileged attribution. + bit_offset: 24 + bit_size: 1 + - name: PRIV25 + description: Page privileged/unprivileged attribution. + bit_offset: 25 + bit_size: 1 + - name: PRIV26 + description: Page privileged/unprivileged attribution. + bit_offset: 26 + bit_size: 1 + - name: PRIV27 + description: Page privileged/unprivileged attribution. + bit_offset: 27 + bit_size: 1 + - name: PRIV28 + description: Page privileged/unprivileged attribution. + bit_offset: 28 + bit_size: 1 + - name: PRIV29 + description: Page privileged/unprivileged attribution. + bit_offset: 29 + bit_size: 1 + - name: PRIV30 + description: Page privileged/unprivileged attribution. + bit_offset: 30 + bit_size: 1 + - name: PRIV31 + description: Page privileged/unprivileged attribution. + bit_offset: 31 + bit_size: 1 +fieldset/PRIVBB2R3: + description: FLASH privilege block based bank 2 register 3. + fields: + - name: PRIV0 + description: Page privileged/unprivileged attribution. + bit_offset: 0 + bit_size: 1 + - name: PRIV1 + description: Page privileged/unprivileged attribution. + bit_offset: 1 + bit_size: 1 + - name: PRIV2 + description: Page privileged/unprivileged attribution. + bit_offset: 2 + bit_size: 1 + - name: PRIV3 + description: Page privileged/unprivileged attribution. + bit_offset: 3 + bit_size: 1 + - name: PRIV4 + description: Page privileged/unprivileged attribution. + bit_offset: 4 + bit_size: 1 + - name: PRIV5 + description: Page privileged/unprivileged attribution. + bit_offset: 5 + bit_size: 1 + - name: PRIV6 + description: Page privileged/unprivileged attribution. + bit_offset: 6 + bit_size: 1 + - name: PRIV7 + description: Page privileged/unprivileged attribution. + bit_offset: 7 + bit_size: 1 + - name: PRIV8 + description: Page privileged/unprivileged attribution. + bit_offset: 8 + bit_size: 1 + - name: PRIV9 + description: Page privileged/unprivileged attribution. + bit_offset: 9 + bit_size: 1 + - name: PRIV10 + description: Page privileged/unprivileged attribution. + bit_offset: 10 + bit_size: 1 + - name: PRIV11 + description: Page privileged/unprivileged attribution. + bit_offset: 11 + bit_size: 1 + - name: PRIV12 + description: Page privileged/unprivileged attribution. + bit_offset: 12 + bit_size: 1 + - name: PRIV13 + description: Page privileged/unprivileged attribution. + bit_offset: 13 + bit_size: 1 + - name: PRIV14 + description: Page privileged/unprivileged attribution. + bit_offset: 14 + bit_size: 1 + - name: PRIV15 + description: Page privileged/unprivileged attribution. + bit_offset: 15 + bit_size: 1 + - name: PRIV16 + description: Page privileged/unprivileged attribution. + bit_offset: 16 + bit_size: 1 + - name: PRIV17 + description: Page privileged/unprivileged attribution. + bit_offset: 17 + bit_size: 1 + - name: PRIV18 + description: Page privileged/unprivileged attribution. + bit_offset: 18 + bit_size: 1 + - name: PRIV19 + description: Page privileged/unprivileged attribution. + bit_offset: 19 + bit_size: 1 + - name: PRIV20 + description: Page privileged/unprivileged attribution. + bit_offset: 20 + bit_size: 1 + - name: PRIV21 + description: Page privileged/unprivileged attribution. + bit_offset: 21 + bit_size: 1 + - name: PRIV22 + description: Page privileged/unprivileged attribution. + bit_offset: 22 + bit_size: 1 + - name: PRIV23 + description: Page privileged/unprivileged attribution. + bit_offset: 23 + bit_size: 1 + - name: PRIV24 + description: Page privileged/unprivileged attribution. + bit_offset: 24 + bit_size: 1 + - name: PRIV25 + description: Page privileged/unprivileged attribution. + bit_offset: 25 + bit_size: 1 + - name: PRIV26 + description: Page privileged/unprivileged attribution. + bit_offset: 26 + bit_size: 1 + - name: PRIV27 + description: Page privileged/unprivileged attribution. + bit_offset: 27 + bit_size: 1 + - name: PRIV28 + description: Page privileged/unprivileged attribution. + bit_offset: 28 + bit_size: 1 + - name: PRIV29 + description: Page privileged/unprivileged attribution. + bit_offset: 29 + bit_size: 1 + - name: PRIV30 + description: Page privileged/unprivileged attribution. + bit_offset: 30 + bit_size: 1 + - name: PRIV31 + description: Page privileged/unprivileged attribution. + bit_offset: 31 + bit_size: 1 +fieldset/PRIVBB2R4: + description: FLASH privilege block based bank 2 register 4. + fields: + - name: PRIV0 + description: Page privileged/unprivileged attribution. + bit_offset: 0 + bit_size: 1 + - name: PRIV1 + description: Page privileged/unprivileged attribution. + bit_offset: 1 + bit_size: 1 + - name: PRIV2 + description: Page privileged/unprivileged attribution. + bit_offset: 2 + bit_size: 1 + - name: PRIV3 + description: Page privileged/unprivileged attribution. + bit_offset: 3 + bit_size: 1 + - name: PRIV4 + description: Page privileged/unprivileged attribution. + bit_offset: 4 + bit_size: 1 + - name: PRIV5 + description: Page privileged/unprivileged attribution. + bit_offset: 5 + bit_size: 1 + - name: PRIV6 + description: Page privileged/unprivileged attribution. + bit_offset: 6 + bit_size: 1 + - name: PRIV7 + description: Page privileged/unprivileged attribution. + bit_offset: 7 + bit_size: 1 + - name: PRIV8 + description: Page privileged/unprivileged attribution. + bit_offset: 8 + bit_size: 1 + - name: PRIV9 + description: Page privileged/unprivileged attribution. + bit_offset: 9 + bit_size: 1 + - name: PRIV10 + description: Page privileged/unprivileged attribution. + bit_offset: 10 + bit_size: 1 + - name: PRIV11 + description: Page privileged/unprivileged attribution. + bit_offset: 11 + bit_size: 1 + - name: PRIV12 + description: Page privileged/unprivileged attribution. + bit_offset: 12 + bit_size: 1 + - name: PRIV13 + description: Page privileged/unprivileged attribution. + bit_offset: 13 + bit_size: 1 + - name: PRIV14 + description: Page privileged/unprivileged attribution. + bit_offset: 14 + bit_size: 1 + - name: PRIV15 + description: Page privileged/unprivileged attribution. + bit_offset: 15 + bit_size: 1 + - name: PRIV16 + description: Page privileged/unprivileged attribution. + bit_offset: 16 + bit_size: 1 + - name: PRIV17 + description: Page privileged/unprivileged attribution. + bit_offset: 17 + bit_size: 1 + - name: PRIV18 + description: Page privileged/unprivileged attribution. + bit_offset: 18 + bit_size: 1 + - name: PRIV19 + description: Page privileged/unprivileged attribution. + bit_offset: 19 + bit_size: 1 + - name: PRIV20 + description: Page privileged/unprivileged attribution. + bit_offset: 20 + bit_size: 1 + - name: PRIV21 + description: Page privileged/unprivileged attribution. + bit_offset: 21 + bit_size: 1 + - name: PRIV22 + description: Page privileged/unprivileged attribution. + bit_offset: 22 + bit_size: 1 + - name: PRIV23 + description: Page privileged/unprivileged attribution. + bit_offset: 23 + bit_size: 1 + - name: PRIV24 + description: Page privileged/unprivileged attribution. + bit_offset: 24 + bit_size: 1 + - name: PRIV25 + description: Page privileged/unprivileged attribution. + bit_offset: 25 + bit_size: 1 + - name: PRIV26 + description: Page privileged/unprivileged attribution. + bit_offset: 26 + bit_size: 1 + - name: PRIV27 + description: Page privileged/unprivileged attribution. + bit_offset: 27 + bit_size: 1 + - name: PRIV28 + description: Page privileged/unprivileged attribution. + bit_offset: 28 + bit_size: 1 + - name: PRIV29 + description: Page privileged/unprivileged attribution. + bit_offset: 29 + bit_size: 1 + - name: PRIV30 + description: Page privileged/unprivileged attribution. + bit_offset: 30 + bit_size: 1 + - name: PRIV31 + description: Page privileged/unprivileged attribution. + bit_offset: 31 + bit_size: 1 +fieldset/PRIVCFGR: + description: FLASH privilege configuration register. + fields: + - name: SPRIV + description: Privileged protection for secure registers. + bit_offset: 0 + bit_size: 1 + - name: PRIV + description: Privileged protection for nonsecure registers. + bit_offset: 1 + bit_size: 1 +fieldset/SBOOT0R: + description: FLASH secure boot address 0 register. + fields: + - name: BOOT_LOCK + description: Boot lock. + bit_offset: 0 + bit_size: 1 + - name: ADD + description: Secure boot base address 0. + bit_offset: 7 + bit_size: 25 +fieldset/SCR: + description: FLASH secure control register. + fields: + - name: PG + description: Secure programming. + bit_offset: 0 + bit_size: 1 + - name: PER + description: Secure page erase. + bit_offset: 1 + bit_size: 1 + - name: MER1 + description: Secure bank 1 mass erase. + bit_offset: 2 + bit_size: 1 + - name: PNB + description: Secure page number selection. + bit_offset: 3 + bit_size: 7 + - name: BKER + description: Secure bank selection for page erase. + bit_offset: 11 + bit_size: 1 + - name: BWR + description: Secure burst write programming mode. + bit_offset: 14 + bit_size: 1 + - name: MER2 + description: Secure bank 2 mass erase. + bit_offset: 15 + bit_size: 1 + - name: STRT + description: Secure start. + bit_offset: 16 + bit_size: 1 + - name: EOPIE + description: Secure end of operation interrupt enable. + bit_offset: 24 + bit_size: 1 + - name: ERRIE + description: Secure error interrupt enable. + bit_offset: 25 + bit_size: 1 + - name: INV + description: Flash memory security state invert. + bit_offset: 29 + bit_size: 1 + - name: LOCK + description: Secure lock. + bit_offset: 31 + bit_size: 1 +fieldset/SECBB1R1: + description: FLASH secure block based bank 1 register 1. + fields: + - name: SEC0 + description: Page secure/nonsecure attribution. + bit_offset: 0 + bit_size: 1 + - name: SEC1 + description: Page secure/nonsecure attribution. + bit_offset: 1 + bit_size: 1 + - name: SEC2 + description: Page secure/nonsecure attribution. + bit_offset: 2 + bit_size: 1 + - name: SEC3 + description: Page secure/nonsecure attribution. + bit_offset: 3 + bit_size: 1 + - name: SEC4 + description: Page secure/nonsecure attribution. + bit_offset: 4 + bit_size: 1 + - name: SEC5 + description: Page secure/nonsecure attribution. + bit_offset: 5 + bit_size: 1 + - name: SEC6 + description: Page secure/nonsecure attribution. + bit_offset: 6 + bit_size: 1 + - name: SEC7 + description: Page secure/nonsecure attribution. + bit_offset: 7 + bit_size: 1 + - name: SEC8 + description: Page secure/nonsecure attribution. + bit_offset: 8 + bit_size: 1 + - name: SEC9 + description: Page secure/nonsecure attribution. + bit_offset: 9 + bit_size: 1 + - name: SEC10 + description: Page secure/nonsecure attribution. + bit_offset: 10 + bit_size: 1 + - name: SEC11 + description: Page secure/nonsecure attribution. + bit_offset: 11 + bit_size: 1 + - name: SEC12 + description: Page secure/nonsecure attribution. + bit_offset: 12 + bit_size: 1 + - name: SEC13 + description: Page secure/nonsecure attribution. + bit_offset: 13 + bit_size: 1 + - name: SEC14 + description: Page secure/nonsecure attribution. + bit_offset: 14 + bit_size: 1 + - name: SEC15 + description: Page secure/nonsecure attribution. + bit_offset: 15 + bit_size: 1 + - name: SEC16 + description: Page secure/nonsecure attribution. + bit_offset: 16 + bit_size: 1 + - name: SEC17 + description: Page secure/nonsecure attribution. + bit_offset: 17 + bit_size: 1 + - name: SEC18 + description: Page secure/nonsecure attribution. + bit_offset: 18 + bit_size: 1 + - name: SEC19 + description: Page secure/nonsecure attribution. + bit_offset: 19 + bit_size: 1 + - name: SEC20 + description: Page secure/nonsecure attribution. + bit_offset: 20 + bit_size: 1 + - name: SEC21 + description: Page secure/nonsecure attribution. + bit_offset: 21 + bit_size: 1 + - name: SEC22 + description: Page secure/nonsecure attribution. + bit_offset: 22 + bit_size: 1 + - name: SEC23 + description: Page secure/nonsecure attribution. + bit_offset: 23 + bit_size: 1 + - name: SEC24 + description: Page secure/nonsecure attribution. + bit_offset: 24 + bit_size: 1 + - name: SEC25 + description: Page secure/nonsecure attribution. + bit_offset: 25 + bit_size: 1 + - name: SEC26 + description: Page secure/nonsecure attribution. + bit_offset: 26 + bit_size: 1 + - name: SEC27 + description: Page secure/nonsecure attribution. + bit_offset: 27 + bit_size: 1 + - name: SEC28 + description: Page secure/nonsecure attribution. + bit_offset: 28 + bit_size: 1 + - name: SEC29 + description: Page secure/nonsecure attribution. + bit_offset: 29 + bit_size: 1 + - name: SEC30 + description: Page secure/nonsecure attribution. + bit_offset: 30 + bit_size: 1 + - name: SEC31 + description: Page secure/nonsecure attribution. + bit_offset: 31 + bit_size: 1 +fieldset/SECBB1R2: + description: FLASH secure block based bank 1 register 2. + fields: + - name: SEC0 + description: Page secure/nonsecure attribution. + bit_offset: 0 + bit_size: 1 + - name: SEC1 + description: Page secure/nonsecure attribution. + bit_offset: 1 + bit_size: 1 + - name: SEC2 + description: Page secure/nonsecure attribution. + bit_offset: 2 + bit_size: 1 + - name: SEC3 + description: Page secure/nonsecure attribution. + bit_offset: 3 + bit_size: 1 + - name: SEC4 + description: Page secure/nonsecure attribution. + bit_offset: 4 + bit_size: 1 + - name: SEC5 + description: Page secure/nonsecure attribution. + bit_offset: 5 + bit_size: 1 + - name: SEC6 + description: Page secure/nonsecure attribution. + bit_offset: 6 + bit_size: 1 + - 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name: SEC18 + description: Page secure/nonsecure attribution. + bit_offset: 18 + bit_size: 1 + - name: SEC19 + description: Page secure/nonsecure attribution. + bit_offset: 19 + bit_size: 1 + - name: SEC20 + description: Page secure/nonsecure attribution. + bit_offset: 20 + bit_size: 1 + - name: SEC21 + description: Page secure/nonsecure attribution. + bit_offset: 21 + bit_size: 1 + - name: SEC22 + description: Page secure/nonsecure attribution. + bit_offset: 22 + bit_size: 1 + - name: SEC23 + description: Page secure/nonsecure attribution. + bit_offset: 23 + bit_size: 1 + - name: SEC24 + description: Page secure/nonsecure attribution. + bit_offset: 24 + bit_size: 1 + - name: SEC25 + description: Page secure/nonsecure attribution. + bit_offset: 25 + bit_size: 1 + - name: SEC26 + description: Page secure/nonsecure attribution. + bit_offset: 26 + bit_size: 1 + - name: SEC27 + description: Page secure/nonsecure attribution. + bit_offset: 27 + bit_size: 1 + - name: SEC28 + description: Page secure/nonsecure attribution. + bit_offset: 28 + bit_size: 1 + - name: SEC29 + description: Page secure/nonsecure attribution. + bit_offset: 29 + bit_size: 1 + - name: SEC30 + description: Page secure/nonsecure attribution. + bit_offset: 30 + bit_size: 1 + - name: SEC31 + description: Page secure/nonsecure attribution. + bit_offset: 31 + bit_size: 1 +fieldset/SECBB1R3: + description: FLASH secure block based bank 1 register 3. + fields: + - name: SEC0 + description: Page secure/nonsecure attribution. + bit_offset: 0 + bit_size: 1 + - name: SEC1 + description: Page secure/nonsecure attribution. + bit_offset: 1 + bit_size: 1 + - name: SEC2 + description: Page secure/nonsecure attribution. + bit_offset: 2 + bit_size: 1 + - name: SEC3 + description: Page secure/nonsecure attribution. + bit_offset: 3 + bit_size: 1 + - name: SEC4 + description: Page secure/nonsecure attribution. + bit_offset: 4 + bit_size: 1 + - name: SEC5 + description: Page secure/nonsecure attribution. + bit_offset: 5 + bit_size: 1 + - name: SEC6 + description: Page secure/nonsecure attribution. + bit_offset: 6 + bit_size: 1 + - name: SEC7 + description: Page secure/nonsecure attribution. + bit_offset: 7 + bit_size: 1 + - name: SEC8 + description: Page secure/nonsecure attribution. + bit_offset: 8 + bit_size: 1 + - name: SEC9 + description: Page secure/nonsecure attribution. + bit_offset: 9 + bit_size: 1 + - name: SEC10 + description: Page secure/nonsecure attribution. + bit_offset: 10 + bit_size: 1 + - name: SEC11 + description: Page secure/nonsecure attribution. + bit_offset: 11 + bit_size: 1 + - name: SEC12 + description: Page secure/nonsecure attribution. + bit_offset: 12 + bit_size: 1 + - name: SEC13 + description: Page secure/nonsecure attribution. + bit_offset: 13 + bit_size: 1 + - name: SEC14 + description: Page secure/nonsecure attribution. + bit_offset: 14 + bit_size: 1 + - name: SEC15 + description: Page secure/nonsecure attribution. + bit_offset: 15 + bit_size: 1 + - name: SEC16 + description: Page secure/nonsecure attribution. + bit_offset: 16 + bit_size: 1 + - name: SEC17 + description: Page secure/nonsecure attribution. + bit_offset: 17 + bit_size: 1 + - name: SEC18 + description: Page secure/nonsecure attribution. + bit_offset: 18 + bit_size: 1 + - name: SEC19 + description: Page secure/nonsecure attribution. + bit_offset: 19 + bit_size: 1 + - name: SEC20 + description: Page secure/nonsecure attribution. + bit_offset: 20 + bit_size: 1 + - name: SEC21 + description: Page secure/nonsecure attribution. + bit_offset: 21 + bit_size: 1 + - name: SEC22 + description: Page secure/nonsecure attribution. + bit_offset: 22 + bit_size: 1 + - name: SEC23 + description: Page secure/nonsecure attribution. + bit_offset: 23 + bit_size: 1 + - name: SEC24 + description: Page secure/nonsecure attribution. + bit_offset: 24 + bit_size: 1 + - name: SEC25 + description: Page secure/nonsecure attribution. + bit_offset: 25 + bit_size: 1 + - name: SEC26 + description: Page secure/nonsecure attribution. + bit_offset: 26 + bit_size: 1 + - name: SEC27 + description: Page secure/nonsecure attribution. + bit_offset: 27 + bit_size: 1 + - name: SEC28 + description: Page secure/nonsecure attribution. + bit_offset: 28 + bit_size: 1 + - name: SEC29 + description: Page secure/nonsecure attribution. + bit_offset: 29 + bit_size: 1 + - name: SEC30 + description: Page secure/nonsecure attribution. + bit_offset: 30 + bit_size: 1 + - name: SEC31 + description: Page secure/nonsecure attribution. + bit_offset: 31 + bit_size: 1 +fieldset/SECBB1R4: + description: FLASH secure block based bank 1 register 4. + fields: + - name: SEC0 + description: Page secure/nonsecure attribution. + bit_offset: 0 + bit_size: 1 + - name: SEC1 + description: Page secure/nonsecure attribution. + bit_offset: 1 + bit_size: 1 + - name: SEC2 + description: Page secure/nonsecure attribution. + bit_offset: 2 + bit_size: 1 + - name: SEC3 + description: Page secure/nonsecure attribution. + bit_offset: 3 + bit_size: 1 + - name: SEC4 + description: Page secure/nonsecure attribution. + bit_offset: 4 + bit_size: 1 + - name: SEC5 + description: Page secure/nonsecure attribution. + bit_offset: 5 + bit_size: 1 + - name: SEC6 + description: Page secure/nonsecure attribution. + bit_offset: 6 + bit_size: 1 + - name: SEC7 + description: Page secure/nonsecure attribution. + bit_offset: 7 + bit_size: 1 + - name: SEC8 + description: Page secure/nonsecure attribution. + bit_offset: 8 + bit_size: 1 + - name: SEC9 + description: Page secure/nonsecure attribution. + bit_offset: 9 + bit_size: 1 + - name: SEC10 + description: Page secure/nonsecure attribution. + bit_offset: 10 + bit_size: 1 + - name: SEC11 + description: Page secure/nonsecure attribution. + bit_offset: 11 + bit_size: 1 + - name: SEC12 + description: Page secure/nonsecure attribution. + bit_offset: 12 + bit_size: 1 + - name: SEC13 + description: Page secure/nonsecure attribution. + bit_offset: 13 + bit_size: 1 + - name: SEC14 + description: Page secure/nonsecure attribution. + bit_offset: 14 + bit_size: 1 + - name: SEC15 + description: Page secure/nonsecure attribution. + bit_offset: 15 + bit_size: 1 + - name: SEC16 + description: Page secure/nonsecure attribution. + bit_offset: 16 + bit_size: 1 + - name: SEC17 + description: Page secure/nonsecure attribution. + bit_offset: 17 + bit_size: 1 + - name: SEC18 + description: Page secure/nonsecure attribution. + bit_offset: 18 + bit_size: 1 + - name: SEC19 + description: Page secure/nonsecure attribution. + bit_offset: 19 + bit_size: 1 + - name: SEC20 + description: Page secure/nonsecure attribution. + bit_offset: 20 + bit_size: 1 + - name: SEC21 + description: Page secure/nonsecure attribution. + bit_offset: 21 + bit_size: 1 + - name: SEC22 + description: Page secure/nonsecure attribution. + bit_offset: 22 + bit_size: 1 + - name: SEC23 + description: Page secure/nonsecure attribution. + bit_offset: 23 + bit_size: 1 + - name: SEC24 + description: Page secure/nonsecure attribution. + bit_offset: 24 + bit_size: 1 + - name: SEC25 + description: Page secure/nonsecure attribution. + bit_offset: 25 + bit_size: 1 + - name: SEC26 + description: Page secure/nonsecure attribution. + bit_offset: 26 + bit_size: 1 + - name: SEC27 + description: Page secure/nonsecure attribution. + bit_offset: 27 + bit_size: 1 + - name: SEC28 + description: Page secure/nonsecure attribution. + bit_offset: 28 + bit_size: 1 + - name: SEC29 + description: Page secure/nonsecure attribution. + bit_offset: 29 + bit_size: 1 + - name: SEC30 + description: Page secure/nonsecure attribution. + bit_offset: 30 + bit_size: 1 + - name: SEC31 + description: Page secure/nonsecure attribution. + bit_offset: 31 + bit_size: 1 +fieldset/SECBB2R1: + description: FLASH secure block based bank 2 register 1. + fields: + - name: SEC0 + description: Page secure/nonsecure attribution. + bit_offset: 0 + bit_size: 1 + - name: SEC1 + description: Page secure/nonsecure attribution. + bit_offset: 1 + bit_size: 1 + - name: SEC2 + description: Page secure/nonsecure attribution. + bit_offset: 2 + bit_size: 1 + - name: SEC3 + description: Page secure/nonsecure attribution. + bit_offset: 3 + bit_size: 1 + - name: SEC4 + description: Page secure/nonsecure attribution. + bit_offset: 4 + bit_size: 1 + - name: SEC5 + description: Page secure/nonsecure attribution. + bit_offset: 5 + bit_size: 1 + - name: SEC6 + description: Page secure/nonsecure attribution. + bit_offset: 6 + bit_size: 1 + - name: SEC7 + description: Page secure/nonsecure attribution. + bit_offset: 7 + bit_size: 1 + - name: SEC8 + description: Page secure/nonsecure attribution. + bit_offset: 8 + bit_size: 1 + - name: SEC9 + description: Page secure/nonsecure attribution. + bit_offset: 9 + bit_size: 1 + - name: SEC10 + description: Page secure/nonsecure attribution. + bit_offset: 10 + bit_size: 1 + - name: SEC11 + description: Page secure/nonsecure attribution. + bit_offset: 11 + bit_size: 1 + - name: SEC12 + description: Page secure/nonsecure attribution. + bit_offset: 12 + bit_size: 1 + - name: SEC13 + description: Page secure/nonsecure attribution. + bit_offset: 13 + bit_size: 1 + - name: SEC14 + description: Page secure/nonsecure attribution. + bit_offset: 14 + bit_size: 1 + - name: SEC15 + description: Page secure/nonsecure attribution. + bit_offset: 15 + bit_size: 1 + - name: SEC16 + description: Page secure/nonsecure attribution. + bit_offset: 16 + bit_size: 1 + - name: SEC17 + description: Page secure/nonsecure attribution. + bit_offset: 17 + bit_size: 1 + - name: SEC18 + description: Page secure/nonsecure attribution. + bit_offset: 18 + bit_size: 1 + - name: SEC19 + description: Page secure/nonsecure attribution. + bit_offset: 19 + bit_size: 1 + - name: SEC20 + description: Page secure/nonsecure attribution. + bit_offset: 20 + bit_size: 1 + - name: SEC21 + description: Page secure/nonsecure attribution. + bit_offset: 21 + bit_size: 1 + - name: SEC22 + description: Page secure/nonsecure attribution. + bit_offset: 22 + bit_size: 1 + - name: SEC23 + description: Page secure/nonsecure attribution. + bit_offset: 23 + bit_size: 1 + - name: SEC24 + description: Page secure/nonsecure attribution. + bit_offset: 24 + bit_size: 1 + - name: SEC25 + description: Page secure/nonsecure attribution. + bit_offset: 25 + bit_size: 1 + - name: SEC26 + description: Page secure/nonsecure attribution. + bit_offset: 26 + bit_size: 1 + - name: SEC27 + description: Page secure/nonsecure attribution. + bit_offset: 27 + bit_size: 1 + - name: SEC28 + description: Page secure/nonsecure attribution. + bit_offset: 28 + bit_size: 1 + - name: SEC29 + description: Page secure/nonsecure attribution. + bit_offset: 29 + bit_size: 1 + - name: SEC30 + description: Page secure/nonsecure attribution. + bit_offset: 30 + bit_size: 1 + - name: SEC31 + description: Page secure/nonsecure attribution. + bit_offset: 31 + bit_size: 1 +fieldset/SECBB2R2: + description: FLASH secure block based bank 2 register 2. + fields: + - name: SEC0 + description: Page secure/nonsecure attribution. + bit_offset: 0 + bit_size: 1 + - name: SEC1 + description: Page secure/nonsecure attribution. + bit_offset: 1 + bit_size: 1 + - name: SEC2 + description: Page secure/nonsecure attribution. + bit_offset: 2 + bit_size: 1 + - name: SEC3 + description: Page secure/nonsecure attribution. + bit_offset: 3 + bit_size: 1 + - name: SEC4 + description: Page secure/nonsecure attribution. + bit_offset: 4 + bit_size: 1 + - name: SEC5 + description: Page secure/nonsecure attribution. + bit_offset: 5 + bit_size: 1 + - name: SEC6 + description: Page secure/nonsecure attribution. + bit_offset: 6 + bit_size: 1 + - name: SEC7 + description: Page secure/nonsecure attribution. + bit_offset: 7 + bit_size: 1 + - name: SEC8 + description: Page secure/nonsecure attribution. + bit_offset: 8 + bit_size: 1 + - name: SEC9 + description: Page secure/nonsecure attribution. + bit_offset: 9 + bit_size: 1 + - name: SEC10 + description: Page secure/nonsecure attribution. + bit_offset: 10 + bit_size: 1 + - name: SEC11 + description: Page secure/nonsecure attribution. + bit_offset: 11 + bit_size: 1 + - name: SEC12 + description: Page secure/nonsecure attribution. + bit_offset: 12 + bit_size: 1 + - name: SEC13 + description: Page secure/nonsecure attribution. + bit_offset: 13 + bit_size: 1 + - name: SEC14 + description: Page secure/nonsecure attribution. + bit_offset: 14 + bit_size: 1 + - name: SEC15 + description: Page secure/nonsecure attribution. + bit_offset: 15 + bit_size: 1 + - name: SEC16 + description: Page secure/nonsecure attribution. + bit_offset: 16 + bit_size: 1 + - name: SEC17 + description: Page secure/nonsecure attribution. + bit_offset: 17 + bit_size: 1 + - name: SEC18 + description: Page secure/nonsecure attribution. + bit_offset: 18 + bit_size: 1 + - name: SEC19 + description: Page secure/nonsecure attribution. + bit_offset: 19 + bit_size: 1 + - name: SEC20 + description: Page secure/nonsecure attribution. + bit_offset: 20 + bit_size: 1 + - name: SEC21 + description: Page secure/nonsecure attribution. + bit_offset: 21 + bit_size: 1 + - name: SEC22 + description: Page secure/nonsecure attribution. + bit_offset: 22 + bit_size: 1 + - name: SEC23 + description: Page secure/nonsecure attribution. + bit_offset: 23 + bit_size: 1 + - name: SEC24 + description: Page secure/nonsecure attribution. + bit_offset: 24 + bit_size: 1 + - name: SEC25 + description: Page secure/nonsecure attribution. + bit_offset: 25 + bit_size: 1 + - name: SEC26 + description: Page secure/nonsecure attribution. + bit_offset: 26 + bit_size: 1 + - name: SEC27 + description: Page secure/nonsecure attribution. + bit_offset: 27 + bit_size: 1 + - name: SEC28 + description: Page secure/nonsecure attribution. + bit_offset: 28 + bit_size: 1 + - name: SEC29 + description: Page secure/nonsecure attribution. + bit_offset: 29 + bit_size: 1 + - name: SEC30 + description: Page secure/nonsecure attribution. + bit_offset: 30 + bit_size: 1 + - name: SEC31 + description: Page secure/nonsecure attribution. + bit_offset: 31 + bit_size: 1 +fieldset/SECBB2R3: + description: FLASH secure block based bank 2 register 3. + fields: + - name: SEC0 + description: Page secure/nonsecure attribution. + bit_offset: 0 + bit_size: 1 + - name: SEC1 + description: Page secure/nonsecure attribution. + bit_offset: 1 + bit_size: 1 + - name: SEC2 + description: Page secure/nonsecure attribution. + bit_offset: 2 + bit_size: 1 + - name: SEC3 + description: Page secure/nonsecure attribution. + bit_offset: 3 + bit_size: 1 + - name: SEC4 + description: Page secure/nonsecure attribution. + bit_offset: 4 + bit_size: 1 + - name: SEC5 + description: Page secure/nonsecure attribution. + bit_offset: 5 + bit_size: 1 + - name: SEC6 + description: Page secure/nonsecure attribution. + bit_offset: 6 + bit_size: 1 + - name: SEC7 + description: Page secure/nonsecure attribution. + bit_offset: 7 + bit_size: 1 + - name: SEC8 + description: Page secure/nonsecure attribution. + bit_offset: 8 + bit_size: 1 + - name: SEC9 + description: Page secure/nonsecure attribution. + bit_offset: 9 + bit_size: 1 + - name: SEC10 + description: Page secure/nonsecure attribution. + bit_offset: 10 + bit_size: 1 + - name: SEC11 + description: Page secure/nonsecure attribution. + bit_offset: 11 + bit_size: 1 + - name: SEC12 + description: Page secure/nonsecure attribution. + bit_offset: 12 + bit_size: 1 + - name: SEC13 + description: Page secure/nonsecure attribution. + bit_offset: 13 + bit_size: 1 + - name: SEC14 + description: Page secure/nonsecure attribution. + bit_offset: 14 + bit_size: 1 + - name: SEC15 + description: Page secure/nonsecure attribution. + bit_offset: 15 + bit_size: 1 + - name: SEC16 + description: Page secure/nonsecure attribution. + bit_offset: 16 + bit_size: 1 + - name: SEC17 + description: Page secure/nonsecure attribution. + bit_offset: 17 + bit_size: 1 + - name: SEC18 + description: Page secure/nonsecure attribution. + bit_offset: 18 + bit_size: 1 + - name: SEC19 + description: Page secure/nonsecure attribution. + bit_offset: 19 + bit_size: 1 + - name: SEC20 + description: Page secure/nonsecure attribution. + bit_offset: 20 + bit_size: 1 + - name: SEC21 + description: Page secure/nonsecure attribution. + bit_offset: 21 + bit_size: 1 + - name: SEC22 + description: Page secure/nonsecure attribution. + bit_offset: 22 + bit_size: 1 + - name: SEC23 + description: Page secure/nonsecure attribution. + bit_offset: 23 + bit_size: 1 + - name: SEC24 + description: Page secure/nonsecure attribution. + bit_offset: 24 + bit_size: 1 + - name: SEC25 + description: Page secure/nonsecure attribution. + bit_offset: 25 + bit_size: 1 + - name: SEC26 + description: Page secure/nonsecure attribution. + bit_offset: 26 + bit_size: 1 + - name: SEC27 + description: Page secure/nonsecure attribution. + bit_offset: 27 + bit_size: 1 + - name: SEC28 + description: Page secure/nonsecure attribution. + bit_offset: 28 + bit_size: 1 + - name: SEC29 + description: Page secure/nonsecure attribution. + bit_offset: 29 + bit_size: 1 + - name: SEC30 + description: Page secure/nonsecure attribution. + bit_offset: 30 + bit_size: 1 + - name: SEC31 + description: Page secure/nonsecure attribution. + bit_offset: 31 + bit_size: 1 +fieldset/SECBB2R4: + description: FLASH secure block based bank 2 register 4. + fields: + - name: SEC0 + description: Page secure/nonsecure attribution. + bit_offset: 0 + bit_size: 1 + - name: SEC1 + description: Page secure/nonsecure attribution. + bit_offset: 1 + bit_size: 1 + - name: SEC2 + description: Page secure/nonsecure attribution. + bit_offset: 2 + bit_size: 1 + - name: SEC3 + description: Page secure/nonsecure attribution. + bit_offset: 3 + bit_size: 1 + - name: SEC4 + description: Page secure/nonsecure attribution. + bit_offset: 4 + bit_size: 1 + - name: SEC5 + description: Page secure/nonsecure attribution. + bit_offset: 5 + bit_size: 1 + - name: SEC6 + description: Page secure/nonsecure attribution. + bit_offset: 6 + bit_size: 1 + - name: SEC7 + description: Page secure/nonsecure attribution. + bit_offset: 7 + bit_size: 1 + - name: SEC8 + description: Page secure/nonsecure attribution. + bit_offset: 8 + bit_size: 1 + - name: SEC9 + description: Page secure/nonsecure attribution. + bit_offset: 9 + bit_size: 1 + - name: SEC10 + description: Page secure/nonsecure attribution. + bit_offset: 10 + bit_size: 1 + - name: SEC11 + description: Page secure/nonsecure attribution. + bit_offset: 11 + bit_size: 1 + - name: SEC12 + description: Page secure/nonsecure attribution. + bit_offset: 12 + bit_size: 1 + - name: SEC13 + description: Page secure/nonsecure attribution. + bit_offset: 13 + bit_size: 1 + - name: SEC14 + description: Page secure/nonsecure attribution. + bit_offset: 14 + bit_size: 1 + - name: SEC15 + description: Page secure/nonsecure attribution. + bit_offset: 15 + bit_size: 1 + - name: SEC16 + description: Page secure/nonsecure attribution. + bit_offset: 16 + bit_size: 1 + - name: SEC17 + description: Page secure/nonsecure attribution. + bit_offset: 17 + bit_size: 1 + - name: SEC18 + description: Page secure/nonsecure attribution. + bit_offset: 18 + bit_size: 1 + - name: SEC19 + description: Page secure/nonsecure attribution. + bit_offset: 19 + bit_size: 1 + - name: SEC20 + description: Page secure/nonsecure attribution. + bit_offset: 20 + bit_size: 1 + - name: SEC21 + description: Page secure/nonsecure attribution. + bit_offset: 21 + bit_size: 1 + - name: SEC22 + description: Page secure/nonsecure attribution. + bit_offset: 22 + bit_size: 1 + - name: SEC23 + description: Page secure/nonsecure attribution. + bit_offset: 23 + bit_size: 1 + - name: SEC24 + description: Page secure/nonsecure attribution. + bit_offset: 24 + bit_size: 1 + - name: SEC25 + description: Page secure/nonsecure attribution. + bit_offset: 25 + bit_size: 1 + - name: SEC26 + description: Page secure/nonsecure attribution. + bit_offset: 26 + bit_size: 1 + - name: SEC27 + description: Page secure/nonsecure attribution. + bit_offset: 27 + bit_size: 1 + - name: SEC28 + description: Page secure/nonsecure attribution. + bit_offset: 28 + bit_size: 1 + - name: SEC29 + description: Page secure/nonsecure attribution. + bit_offset: 29 + bit_size: 1 + - name: SEC30 + description: Page secure/nonsecure attribution. + bit_offset: 30 + bit_size: 1 + - name: SEC31 + description: Page secure/nonsecure attribution. + bit_offset: 31 + bit_size: 1 +fieldset/SECHDPCR: + description: FLASH secure HDP control register. + fields: + - name: HDP1_ACCDIS + description: HDP1 area access disable. + bit_offset: 0 + bit_size: 8 + - name: HDP2_ACCDIS + description: HDP2 area access disable. + bit_offset: 8 + bit_size: 8 + - name: HDP1ExT_ACCDIS + description: HDP1 extension area access disable. + bit_offset: 16 + bit_size: 8 + - name: HDP2ExT_ACCDIS + description: HDP2 extension area access disable. + bit_offset: 24 + bit_size: 8 +fieldset/SECHDPExTR: + description: FLASH HDP extension register. + fields: + - name: HDP1_ExT + description: HDP area extension in 4-Kbyte pages in bank 1. + bit_offset: 0 + bit_size: 8 + - name: HDP2_ExT + description: HDP area extension in 4-Kbyte pages in bank 2. + bit_offset: 16 + bit_size: 8 +fieldset/SECWM1R1: + description: FLASH secure watermark1 register 1. + fields: + - name: SECWM1_STRT + description: Start page of first secure area. + bit_offset: 0 + bit_size: 7 + - name: SECWM1_END + description: End page of first secure area. + bit_offset: 16 + bit_size: 7 +fieldset/SECWM1R2: + description: FLASH secure watermark1 register 2. + fields: + - name: HDP1_END + description: End page of first hide protection area. + bit_offset: 16 + bit_size: 7 + - name: HDP1EN + description: Hide protection first area enable. + bit_offset: 24 + bit_size: 8 +fieldset/SECWM2R1: + description: FLASH secure watermark2 register 1. + fields: + - name: SECWM2_STRT + description: Start page of second secure area. + bit_offset: 0 + bit_size: 7 + - name: SECWM2_END + description: End page of second secure area. + bit_offset: 16 + bit_size: 7 +fieldset/SECWM2R2: + description: FLASH secure watermark2 register 2. + fields: + - name: HDP2_END + description: End page of hide protection second area. + bit_offset: 16 + bit_size: 7 + - name: HDP2EN + description: Hide protection second area enable. + bit_offset: 24 + bit_size: 8 +fieldset/SKEYR: + description: FLASH secure key register. + fields: + - name: KEY + description: Flash memory secure key. + bit_offset: 0 + bit_size: 32 +fieldset/SR: + description: FLASH nonsecure status register. + fields: + - name: EOP + description: Nonsecure end of operation. + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: Nonsecure operation error. + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: Nonsecure programming error. + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: Nonsecure write protection error. + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: Nonsecure programming alignment error. + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: Nonsecure size error. + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: Nonsecure programming sequence error. + bit_offset: 7 + bit_size: 1 + - name: OPTWERR + description: Option write error. + bit_offset: 13 + bit_size: 1 + - name: BSY + description: Nonsecure busy. + bit_offset: 16 + bit_size: 1 + - name: WDW + description: Nonsecure wait data to write. + bit_offset: 17 + bit_size: 1 + - name: OEM1LOCK + description: OEM1 lock. + bit_offset: 18 + bit_size: 1 + - name: OEM2LOCK + description: OEM2 lock. + bit_offset: 19 + bit_size: 1 + - name: PD1 + description: Bank 1 in power-down mode. + bit_offset: 20 + bit_size: 1 + - name: PD2 + description: Bank 2 in power-down mode. + bit_offset: 21 + bit_size: 1 +fieldset/SSR: + description: FLASH secure status register. + fields: + - name: EOP + description: Secure end of operation. + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: Secure operation error. + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: Secure programming error. + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: Secure write protection error. + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: Secure programming alignment error. + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: Secure size error. + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: Secure programming sequence error. + bit_offset: 7 + bit_size: 1 + - name: BSY + description: Secure busy. + bit_offset: 16 + bit_size: 1 + - name: WDW + description: Secure wait data to write. + bit_offset: 17 + bit_size: 1 +fieldset/WRP1AR: + description: FLASH WRP1 area A address register. + fields: + - name: STRT + description: Bank 1 WPR first area A start page. + bit_offset: 0 + bit_size: 7 + - name: END + description: Bank 1 WPR first area A end page. + bit_offset: 16 + bit_size: 7 + - name: UNLOCK + description: Bank 1 WPR first area A unlock. + bit_offset: 31 + bit_size: 1 +fieldset/WRP1BR: + description: FLASH WRP1 area B address register. + fields: + - name: STRT + description: Bank 1 WRP second area B start page. + bit_offset: 0 + bit_size: 7 + - name: END + description: Bank 1 WRP second area B end page. + bit_offset: 16 + bit_size: 7 + - name: UNLOCK + description: Bank 1 WPR second area B unlock. + bit_offset: 31 + bit_size: 1 +fieldset/WRP2AR: + description: FLASH WPR2 area A address register. + fields: + - name: STRT + description: Bank 2 WPR first area A start page. + bit_offset: 0 + bit_size: 7 + - name: END + description: Bank 2 WPR first area A end page. + bit_offset: 16 + bit_size: 7 + - name: UNLOCK + description: Bank 2 WPR first area A unlock. + bit_offset: 31 + bit_size: 1 +fieldset/WRP2BR: + description: FLASH WPR2 area B address register. + fields: + - name: STRT + description: Bank 2 WPR second area B start page. + bit_offset: 0 + bit_size: 7 + - name: END + description: Bank 2 WPR second area B end page. + bit_offset: 16 + bit_size: 7 + - name: UNLOCK + description: Bank 2 WPR second area B unlock. + bit_offset: 31 + bit_size: 1 +enum/BOR_LEV: + bit_size: 3 + variants: + - name: Level0 + description: BOR level 0 (reset level threshold around 1. + value: 0 + - name: Level1 + description: BOR level 1 (reset level threshold around 2. + value: 1 + - name: Level2 + description: BOR level 2 (reset level threshold around 2. + value: 2 + - name: Level3 + description: BOR level 3 (reset level threshold around 2. + value: 3 + - name: Level4 + description: BOR level 4 (reset level threshold around 2. + value: 4 +enum/CODE_OP: + bit_size: 3 + variants: + - name: NoFlashInt + description: No flash operation interrupted by previous reset. + value: 0 + - name: SingleWrInt + description: Single write operation interrupted. + value: 1 + - name: BurstWrInt + description: Burst write operation interrupted. + value: 2 + - name: PgEraseInt + description: Page erase operation interrupted. + value: 3 + - name: BankEraseInt + description: Bank erase operation interrupted. + value: 4 + - name: MassEraseInt + description: Mass erase operation interrupted. + value: 5 + - name: OptChangeInt + description: Option change operation interrupted. + value: 6 +enum/RDP: + bit_size: 8 + variants: + - name: Level0 + description: Level 0. + value: 85 + - name: Level0ROProtActive + description: Level 0 (readout protection not active). + value: 170 + - name: Level2 + description: Level 2 (chip readout protection active). + value: 204 diff --git a/data/registers/pwr_u3.yaml b/data/registers/pwr_u3.yaml new file mode 100644 index 000000000..15365dfdd --- /dev/null +++ b/data/registers/pwr_u3.yaml @@ -0,0 +1,1678 @@ +block/PWR: + description: PWR Address block. + items: + - name: CR1 + description: PWR control register 1. + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: PWR control register 2. + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: PWR control register 3. + byte_offset: 8 + fieldset: CR3 + - name: VOSR + description: PWR voltage scaling register. + byte_offset: 12 + fieldset: VOSR + - name: SVMCR + description: PWR supply voltage monitoring control register. + byte_offset: 16 + fieldset: SVMCR + - name: WUCR1 + description: PWR wakeup control register 1. + byte_offset: 20 + fieldset: WUCR1 + - name: WUCR2 + description: PWR wakeup control register 2. + byte_offset: 24 + fieldset: WUCR2 + - name: WUCR3 + description: PWR wakeup control register 3. + byte_offset: 28 + fieldset: WUCR3 + - name: BDCR + description: PWR Backup domain control register. + byte_offset: 36 + fieldset: BDCR + - name: DBPCR + description: PWR disable Backup domain register. + byte_offset: 40 + fieldset: DBPCR + - name: SECCFGR + description: PWR security configuration register. + byte_offset: 48 + fieldset: SECCFGR + - name: PRIVCFGR + description: PWR privilege control register. + byte_offset: 52 + fieldset: PRIVCFGR + - name: SR + description: PWR status register. + byte_offset: 56 + fieldset: SR + - name: SVMSR + description: PWR supply voltage monitoring status register. + byte_offset: 60 + fieldset: SVMSR + - name: WUSR + description: PWR wakeup status register. + byte_offset: 68 + fieldset: WUSR + - name: WUSCR + description: PWR wakeup status clear register. + byte_offset: 72 + fieldset: WUSCR + - name: APCR + description: PWR apply pull configuration register. + byte_offset: 76 + fieldset: APCR + - name: PUCRA + description: PWR port A pull-up control register. + byte_offset: 80 + fieldset: PUCRA + - name: PDCRA + description: PWR port A pull-down control register. + byte_offset: 84 + fieldset: PDCRA + - name: PUCRB + description: PWR port B pull-up control register. + byte_offset: 88 + fieldset: PUCRB + - name: PDCRB + description: PWR port B pull-down control register. + byte_offset: 92 + fieldset: PDCRB + - name: PUCRC + description: PWR port C pull-up control register. + byte_offset: 96 + fieldset: PUCRC + - name: PDCRC + description: PWR port C pull-down control register. + byte_offset: 100 + fieldset: PDCRC + - name: PUCRD + description: PWR port D pull-up control register. + byte_offset: 104 + fieldset: PUCRD + - name: PDCRD + description: PWR port D pull-down control register. + byte_offset: 108 + fieldset: PDCRD + - name: PUCRE + description: PWR port E pull-up control register. + byte_offset: 112 + fieldset: PUCRE + - name: PDCRE + description: PWR port E pull-down control register. + byte_offset: 116 + fieldset: PDCRE + - name: PUCRG + description: PWR port G pull-up control register. + byte_offset: 128 + fieldset: PUCRG + - name: PDCRG + description: PWR port G pull-down control register. + byte_offset: 132 + fieldset: PDCRG + - name: PUCRH + description: PWR port H pull-up control register. + byte_offset: 136 + fieldset: PUCRH + - name: PDCRH + description: PWR port H pull-down control register. + byte_offset: 140 + fieldset: PDCRH + - name: I3CPUCR1 + description: PWR I3C pull-up control register 1. + byte_offset: 176 + fieldset: I3CPUCR1 + - name: I3CPUCR2 + description: PWR I3C pull-up control register 2. + byte_offset: 180 + fieldset: I3CPUCR2 +fieldset/APCR: + description: PWR apply pull configuration register. + fields: + - name: APC + description: When this bit is set, the I/O pull-up and pull-down configurations defined in PUCRx and PDCRx are applied. When this bit is cleared, PUCRx and PDCRx are not applied to the I/Os. + bit_offset: 0 + bit_size: 1 +fieldset/BDCR: + description: PWR Backup domain control register. + fields: + - name: VBE + description: "None 0: VBAT battery charging disabled 1: VBAT battery charging enabled." + bit_offset: 0 + bit_size: 1 + - name: VBRS + description: "None 0: Charge VBAT through a 5 k ohm resistor 1: Charge VBAT through a 1.5 k ohm resistor." + bit_offset: 1 + bit_size: 1 + enum: VBRS +fieldset/CR1: + description: PWR control register 1. + fields: + - name: LPMS + description: "These bits select the low-power mode entered when the CPU enters the Deepsleep mode. 000: Stop 0 mode 001: Stop 1 mode 010: Stop 2 mode 011: Stop 3 mode 100-101: Standby mode 110-111: Shutdown mode." + bit_offset: 0 + bit_size: 3 + enum: LPMS + - name: RRSB1 + description: "This bit is used to keep the SRAM2 page 1 content in Standby mode. The SRAM2 page 1 corresponds to the first 8 Kbytes of the SRAM2 (from SRAM2 base address to SRAM2 base address + 0x1FFF). 0: SRAM2 page1 content not retained in Standby mode 1: SRAM2 page1 content retained in Standby mode Note: This bit has no effect in Shutdown mode." + bit_offset: 4 + bit_size: 1 + - name: RRSB2 + description: "This bit is used to keep the SRAM2 page 2 content in Standby mode. The SRAM2 page 2 corresponds to the 24 Kbytes of the SRAM2 (from SRAM2 base address + 0x2000 to SRAM2 base address + 0x7FFF). 0: SRAM2 page2 content not retained in Standby mode 1: SRAM2 page2 content retained in Standby mode Note: This bit has no effect in Shutdown mode." + bit_offset: 5 + bit_size: 1 + - name: RRSB3 + description: "This bit is used to keep the SRAM2 page 3 content in Standby mode. The SRAM2 page 3 corresponds to the last 32 Kbytes of the SRAM2 (from SRAM2 base address + 0x8000 to SRAM2 base address + 0xFFFF). 0: SRAM2 page3 content not retained in Standby mode 1: SRAM2 page3 content retained in Standby mode Note: This bit has no effect in Shutdown mode." + bit_offset: 6 + bit_size: 1 + - name: ULPMEN + description: "This bit is used to reduce the consumption by configuring the BOR in discontinuous mode. This bit has effect only when the BOR level 0 is selected and when the device is in Standby mode. This bit must be set to reach the lowest power consumption in Standby mode. 0: BOR level 0 operating in continuous (normal) mode in Standby mode 1: BOR level 0 operating in discontinuous (ultra-low power) mode in Standby mode." + bit_offset: 7 + bit_size: 1 + - name: SRAM1PD + description: "This bit is used to reduce the consumption by powering off the SRAM1. 0: SRAM1 powered on 1: SRAM1 powered off Note: When this bit is cleared to 0, wait for more than 1.6us before accessing the SRAM." + bit_offset: 8 + bit_size: 1 + enum: SRAMPD + - name: SRAM2PD + description: "This bit is used to reduce the consumption by powering off the SRAM2. 0: SRAM2 powered on 1: SRAM2 powered off Note: When this bit is cleared to 0, wait for more than 1.6us before accessing the SRAM." + bit_offset: 9 + bit_size: 1 + enum: SRAMPD +fieldset/CR2: + description: PWR control register 2. + fields: + - name: SRAM1PDS1 + description: "None 0: SRAM1 page 1 content retained in Stop modes 1: SRAM1 page 1 content lost in Stop modes Note: Page 1 to 2 size is 16 kBytes. Page 3 to 7 size is 32 kBytes." + bit_offset: 0 + bit_size: 1 + enum: PDS + - name: SRAM1PDS2 + description: "None 0: SRAM1 page 2 content retained in Stop modes 1: SRAM1 page 2 content lost in Stop modes Note: Page 1 to 2 size is 16 kBytes. Page 3 to 7 size is 32 kBytes." + bit_offset: 1 + bit_size: 1 + enum: PDS + - name: SRAM1PDS3 + description: "None 0: SRAM1 page 3 content retained in Stop modes 1: SRAM1 page 3 content lost in Stop modes Note: Page 1 to 2 size is 16 kBytes. Page 3 to 7 size is 32 kBytes." + bit_offset: 2 + bit_size: 1 + enum: PDS + - name: SRAM1PDS4 + description: "None 0: SRAM1 page 4 content retained in Stop modes 1: SRAM1 page 4 content lost in Stop modes Note: Page 1 to 2 size is 16 kBytes. Page 3 to 7 size is 32 kBytes." + bit_offset: 3 + bit_size: 1 + enum: PDS + - name: SRAM1PDS5 + description: "None 0: SRAM1 page 5 content retained in Stop modes 1: SRAM1 page 5 content lost in Stop modes Note: Page 1 to 2 size is 16 kBytes. Page 3 to 7 size is 32 kBytes." + bit_offset: 4 + bit_size: 1 + enum: PDS + - name: SRAM1PDS6 + description: "None 0: SRAM1 page 6 content retained in Stop modes 1: SRAM1 page 6 content lost in Stop modes Note: Page 1 to 2 size is 16 kBytes. Page 3 to 7 size is 32 kBytes." + bit_offset: 5 + bit_size: 1 + enum: PDS + - name: SRAM1PDS7 + description: "None 0: SRAM1 page 7 content retained in Stop modes 1: SRAM1 page 7 content lost in Stop modes Note: Page 1 to 2 size is 16 kBytes. Page 3 to 7 size is 32 kBytes." + bit_offset: 6 + bit_size: 1 + enum: PDS + - name: SRAM2PDS1 + description: "None 0: SRAM2 page 1 content retained in Stop modes 1: SRAM2 page 1 content lost in Stop modes." + bit_offset: 16 + bit_size: 1 + enum: PDS + - name: SRAM2PDS2 + description: "None 0: SRAM2 page 2 content retained in Stop modes 1: SRAM2 page 2 content lost in Stop modes." + bit_offset: 17 + bit_size: 1 + enum: PDS + - name: SRAM2PDS3 + description: "None 0: SRAM2 page 3 content retained in Stop modes 1: SRAM2 page 3 content lost in Stop modes." + bit_offset: 18 + bit_size: 1 + enum: PDS + - name: ICRAMPDS + description: "None 0: ICACHE SRAM content retained in Stop modes 1: ICACHE SRAM content lost in Stop modes." + bit_offset: 25 + bit_size: 1 + enum: PDS + - name: PRAMPDS + description: "None 0: FDCAN and USB peripherals SRAM content retained in Stop modes 1: FDCAN and USB peripherals SRAM content lost in Stop modes." + bit_offset: 26 + bit_size: 1 + enum: PDS + - name: PKARAMPDS + description: "None 0: PKA SRAM content retained in Stop modes 1: PKA SRAM content lost in Stop modes." + bit_offset: 27 + bit_size: 1 + enum: PDS + - name: SRAMFWU + description: "This bit is used to obtain the best trade-off between low-power consumption and wakeup time. SRAMs wakeup time increases the wakeup time when exiting Stop 0 and 1 modes, and also increases the GPDMA1 access time to SRAMs during Stop modes. 0: SRAMs enters low-power mode in Stop 0 and Stop 1 modes (source biasing for lower-power consumption). 1: SRAMs remains in normal mode in Stop 0 and Stop 1 modes (higher consumption but no SRAM wakeup time). Note: in case one or several SRAMs are configured to be in power-down in Stop mode, setting SRAMFWU bit has no effect." + bit_offset: 28 + bit_size: 1 + enum: SRAMFWU + - name: FLASHFWU + description: "This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption. 0: Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower-power consumption). 1: Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wakeup time)." + bit_offset: 29 + bit_size: 1 + enum: FLASHFWU +fieldset/CR3: + description: PWR control register 3. + fields: + - name: REGSEL + description: "None 0: LDO selected 1: SMPS selected Note: REGSEL is reserved and must be kept at reset value in packages without SMPS." + bit_offset: 1 + bit_size: 1 + enum: REGSEL + - name: FSTEN + description: "None 0: LDO/SMPS fast startup disabled (limited inrush current) 1: LDO/SMPS fast startup enabled." + bit_offset: 2 + bit_size: 1 +fieldset/DBPCR: + description: PWR disable Backup domain register. + fields: + - name: DBP + description: "In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers. 0: Write access to Backup domain disabled 1: Write access to Backup domain enabled." + bit_offset: 0 + bit_size: 1 +fieldset/I3CPUCR1: + description: PWR I3C pull-up control register 1. + fields: + - name: PA1_I3CPU + description: When set, the bit activates the I3C pull-up on PA1. + bit_offset: 0 + bit_size: 1 + - name: PA6_I3CPU + description: When set, the bit activates the I3C pull-up on PA6. + bit_offset: 1 + bit_size: 1 + - name: PA7_I3CPU + description: When set, the bit activates the I3C pull-up on PA7. + bit_offset: 2 + bit_size: 1 + - name: PB2_I3CPU + description: When set, the bit activates the I3C pull-up on PB2. + bit_offset: 4 + bit_size: 1 + - name: PB6_I3CPU + description: When set, the bit activates the I3C pull-up on PB6. + bit_offset: 5 + bit_size: 1 + - name: PB8_I3CPU + description: When set, the bit activates the I3C pull-up on PB8. + bit_offset: 6 + bit_size: 1 + - name: PB9_I3CPU + description: When set, the bit activates the I3C pull-up on PB9. + bit_offset: 7 + bit_size: 1 + - name: PB10_I3CPU + description: When set, the bit activates the I3C pull-up on PB10. + bit_offset: 8 + bit_size: 1 + - name: PB12_I3CPU + description: When set, the bit activates the I3C pull-up on PB12. + bit_offset: 9 + bit_size: 1 + - name: PB13_I3CPU + description: When set, the bit activates the I3C pull-up on PB13. + bit_offset: 10 + bit_size: 1 + - name: PB14_I3CPU + description: When set, the bit activates the I3C pull-up on PB14. + bit_offset: 11 + bit_size: 1 +fieldset/I3CPUCR2: + description: PWR I3C pull-up control register 2. + fields: + - name: PC0_I3CPU + description: When set, the bit activates the I3C pull-up on PC0. + bit_offset: 0 + bit_size: 1 + - name: PC1_I3CPU + description: When set, the bit activates the I3C pull-up on PC1. + bit_offset: 1 + bit_size: 1 + - name: PD12_I3CPU + description: When set, the bit activates the I3C pull-up on PD12. + bit_offset: 3 + bit_size: 1 + - name: PD13_I3CPU + description: When set, the bit activates the I3C pull-up on PD13. + bit_offset: 4 + bit_size: 1 + - name: PG7_I3CPU + description: When set, the bit activates the I3C pull-up on PG7. + bit_offset: 6 + bit_size: 1 + - name: PG8_I3CPU + description: When set, the bit activates the I3C pull-up on PG8. + bit_offset: 7 + bit_size: 1 + - name: PG13_I3CPU + description: When set, the bit activates the I3C pull-up on PG13. + bit_offset: 8 + bit_size: 1 + - name: PG14_I3CPU + description: When set, the bit activates the I3C pull-up on PG14. + bit_offset: 9 + bit_size: 1 + - name: PH3_I3CPU + description: When set, the bit activates the I3C pull-up on PH3. + bit_offset: 11 + bit_size: 1 +fieldset/PDCRA: + description: PWR port A pull-down control register. + fields: + - name: PD0 + description: "When set, each bit activates the pull-down on PA0 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: "When set, each bit activates the pull-down on PA1 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 1 + bit_size: 1 + - name: PD2 + description: "When set, each bit activates the pull-down on PA2 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 2 + bit_size: 1 + - name: PD3 + description: "When set, each bit activates the pull-down on PA3 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 3 + bit_size: 1 + - name: PD4 + description: "When set, each bit activates the pull-down on PA4 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 4 + bit_size: 1 + - name: PD5 + description: "When set, each bit activates the pull-down on PA5 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 5 + bit_size: 1 + - name: PD6 + description: "When set, each bit activates the pull-down on PA6 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 6 + bit_size: 1 + - name: PD7 + description: "When set, each bit activates the pull-down on PA7 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 7 + bit_size: 1 + - name: PD8 + description: "When set, each bit activates the pull-down on PA8 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 8 + bit_size: 1 + - name: PD9 + description: "When set, each bit activates the pull-down on PA9 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 9 + bit_size: 1 + - name: PD10 + description: "When set, each bit activates the pull-down on PA10 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 10 + bit_size: 1 + - name: PD11 + description: "When set, each bit activates the pull-down on PA11 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 11 + bit_size: 1 + - name: PD12 + description: "When set, each bit activates the pull-down on PA12 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 12 + bit_size: 1 + - name: PD14 + description: "When set, each bit activates the pull-down on PA14 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 14 + bit_size: 1 +fieldset/PDCRB: + description: PWR port B pull-down control register. + fields: + - name: PD0 + description: "When set, each bit activates the pull-down on PB0 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: "When set, each bit activates the pull-down on PB1 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 1 + bit_size: 1 + - name: PD2 + description: "When set, each bit activates the pull-down on PB2 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 2 + bit_size: 1 + - name: PD3 + description: "When set, each bit activates the pull-down on PB3 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 3 + bit_size: 1 + - name: PD5 + description: "When set, each bit activates the pull-down on PB5 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 5 + bit_size: 1 + - name: PD6 + description: "When set, each bit activates the pull-down on PB6 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 6 + bit_size: 1 + - name: PD7 + description: "When set, each bit activates the pull-down on PB7 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 7 + bit_size: 1 + - name: PD8 + description: "When set, each bit activates the pull-down on PB8 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 8 + bit_size: 1 + - name: PD9 + description: "When set, each bit activates the pull-down on PB9 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 9 + bit_size: 1 + - name: PD10 + description: "When set, each bit activates the pull-down on PB10 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 10 + bit_size: 1 + - name: PD11 + description: "When set, each bit activates the pull-down on PB11 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 11 + bit_size: 1 + - name: PD12 + description: "When set, each bit activates the pull-down on PB12 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 12 + bit_size: 1 + - name: PD13 + description: "When set, each bit activates the pull-down on PB13 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 13 + bit_size: 1 + - name: PD14 + description: "When set, each bit activates the pull-down on PB14 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 14 + bit_size: 1 + - name: PD15 + description: "When set, each bit activates the pull-down on PB15 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 15 + bit_size: 1 +fieldset/PDCRC: + description: PWR port C pull-down control register. + fields: + - name: PD0 + description: "When set, each bit activates the pull-down on PC0 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: "When set, each bit activates the pull-down on PC1 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 1 + bit_size: 1 + - name: PD2 + description: "When set, each bit activates the pull-down on PC2 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 2 + bit_size: 1 + - name: PD3 + description: "When set, each bit activates the pull-down on PC3 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 3 + bit_size: 1 + - name: PD4 + description: "When set, each bit activates the pull-down on PC4 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 4 + bit_size: 1 + - name: PD5 + description: "When set, each bit activates the pull-down on PC5 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 5 + bit_size: 1 + - name: PD6 + description: "When set, each bit activates the pull-down on PC6 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 6 + bit_size: 1 + - name: PD7 + description: "When set, each bit activates the pull-down on PC7 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 7 + bit_size: 1 + - name: PD8 + description: "When set, each bit activates the pull-down on PC8 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 8 + bit_size: 1 + - name: PD9 + description: "When set, each bit activates the pull-down on PC9 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 9 + bit_size: 1 + - name: PD10 + description: "When set, each bit activates the pull-down on PC10 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 10 + bit_size: 1 + - name: PD11 + description: "When set, each bit activates the pull-down on PC11 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 11 + bit_size: 1 + - name: PD12 + description: "When set, each bit activates the pull-down on PC12 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 12 + bit_size: 1 + - name: PD13 + description: "When set, each bit activates the pull-down on PC13 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 13 + bit_size: 1 + - name: PD14 + description: "When set, each bit activates the pull-down on PC14 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 14 + bit_size: 1 + - name: PD15 + description: "When set, each bit activates the pull-down on PC15 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 15 + bit_size: 1 +fieldset/PDCRD: + description: PWR port D pull-down control register. + fields: + - name: PD0 + description: "When set, each bit activates the pull-down on PD0 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: "When set, each bit activates the pull-down on PD1 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 1 + bit_size: 1 + - name: PD2 + description: "When set, each bit activates the pull-down on PD2 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 2 + bit_size: 1 + - name: PD3 + description: "When set, each bit activates the pull-down on PD3 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 3 + bit_size: 1 + - name: PD4 + description: "When set, each bit activates the pull-down on PD4 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 4 + bit_size: 1 + - name: PD5 + description: "When set, each bit activates the pull-down on PD5 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 5 + bit_size: 1 + - name: PD6 + description: "When set, each bit activates the pull-down on PD6 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 6 + bit_size: 1 + - name: PD7 + description: "When set, each bit activates the pull-down on PD7 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 7 + bit_size: 1 + - name: PD8 + description: "When set, each bit activates the pull-down on PD8 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 8 + bit_size: 1 + - name: PD9 + description: "When set, each bit activates the pull-down on PD9 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 9 + bit_size: 1 + - name: PD10 + description: "When set, each bit activates the pull-down on PD10 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 10 + bit_size: 1 + - name: PD11 + description: "When set, each bit activates the pull-down on PD11 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 11 + bit_size: 1 + - name: PD12 + description: "When set, each bit activates the pull-down on PD12 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 12 + bit_size: 1 + - name: PD13 + description: "When set, each bit activates the pull-down on PD13 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 13 + bit_size: 1 + - name: PD14 + description: "When set, each bit activates the pull-down on PD14 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 14 + bit_size: 1 + - name: PD15 + description: "When set, each bit activates the pull-down on PD15 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 15 + bit_size: 1 +fieldset/PDCRE: + description: PWR port E pull-down control register. + fields: + - name: PD0 + description: "When set, each bit activates the pull-down on PE0 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: "When set, each bit activates the pull-down on PE1 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 1 + bit_size: 1 + - name: PD2 + description: "When set, each bit activates the pull-down on PE2 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 2 + bit_size: 1 + - name: PD3 + description: "When set, each bit activates the pull-down on PE3 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 3 + bit_size: 1 + - name: PD4 + description: "When set, each bit activates the pull-down on PE4 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 4 + bit_size: 1 + - name: PD5 + description: "When set, each bit activates the pull-down on PE5 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 5 + bit_size: 1 + - name: PD6 + description: "When set, each bit activates the pull-down on PE6 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 6 + bit_size: 1 + - name: PD7 + description: "When set, each bit activates the pull-down on PE7 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 7 + bit_size: 1 + - name: PD8 + description: "When set, each bit activates the pull-down on PE8 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 8 + bit_size: 1 + - name: PD9 + description: "When set, each bit activates the pull-down on PE9 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 9 + bit_size: 1 + - name: PD10 + description: "When set, each bit activates the pull-down on PE10 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 10 + bit_size: 1 + - name: PD11 + description: "When set, each bit activates the pull-down on PE11 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 11 + bit_size: 1 + - name: PD12 + description: "When set, each bit activates the pull-down on PE12 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 12 + bit_size: 1 + - name: PD13 + description: "When set, each bit activates the pull-down on PE13 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 13 + bit_size: 1 + - name: PD14 + description: "When set, each bit activates the pull-down on PE14 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 14 + bit_size: 1 + - name: PD15 + description: "When set, each bit activates the pull-down on PE15 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 15 + bit_size: 1 +fieldset/PDCRG: + description: PWR port G pull-down control register. + fields: + - name: PD2 + description: "When set, each bit activates the pull-down on PG2 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 2 + bit_size: 1 + - name: PD3 + description: "When set, each bit activates the pull-down on PG3 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 3 + bit_size: 1 + - name: PD4 + description: "When set, each bit activates the pull-down on PG4 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 4 + bit_size: 1 + - name: PD5 + description: "When set, each bit activates the pull-down on PG5 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 5 + bit_size: 1 + - name: PD6 + description: "When set, each bit activates the pull-down on PG6 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 6 + bit_size: 1 + - name: PD7 + description: "When set, each bit activates the pull-down on PG7 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 7 + bit_size: 1 + - name: PD8 + description: "When set, each bit activates the pull-down on PG8 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 8 + bit_size: 1 + - name: PD9 + description: "When set, each bit activates the pull-down on PG9 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 9 + bit_size: 1 + - name: PD10 + description: "When set, each bit activates the pull-down on PG10 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 10 + bit_size: 1 + - name: PD11 + description: "When set, each bit activates the pull-down on PG11 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 11 + bit_size: 1 + - name: PD12 + description: "When set, each bit activates the pull-down on PG12 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 12 + bit_size: 1 + - name: PD13 + description: "When set, each bit activates the pull-down on PG13 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 13 + bit_size: 1 + - name: PD14 + description: "When set, each bit activates the pull-down on PG14 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 14 + bit_size: 1 + - name: PD15 + description: "When set, each bit activates the pull-down on PG15 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 15 + bit_size: 1 +fieldset/PDCRH: + description: PWR port H pull-down control register. + fields: + - name: PD0 + description: "When set, each bit activates the pull-down on PH0 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: "When set, each bit activates the pull-down on PH1 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 1 + bit_size: 1 + - name: PD3 + description: "When set, each bit activates the pull-down on PH3 when the APC bit is set in APCR. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 3 + bit_size: 1 +fieldset/PRIVCFGR: + description: PWR privilege control register. + fields: + - name: SPRIV + description: "This bit is set and reset by software. It can be written only by a secure privileged access. 0: Read and write to PWR secure functions can be done by privileged or unprivileged access. 1: Read and write to PWR secure functions can be done by privileged access only." + bit_offset: 0 + bit_size: 1 + - name: NSPRIV + description: "This bit is set and reset by software. It can be written only by privileged access, secure or non-secure. 0: Read and write to PWR non-secure functions can be done by privileged or unprivileged access. 1: Read and write to PWR non-secure functions can be done by privileged access only." + bit_offset: 1 + bit_size: 1 +fieldset/PUCRA: + description: PWR port A pull-up control register. + fields: + - name: PU0 + description: "When set, each bit activates the pull-up on PA0 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD0 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: "When set, each bit activates the pull-up on PA1 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD1 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 1 + bit_size: 1 + - name: PU2 + description: "When set, each bit activates the pull-up on PA2 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD2 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 2 + bit_size: 1 + - name: PU3 + description: "When set, each bit activates the pull-up on PA3 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD3 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 3 + bit_size: 1 + - name: PU4 + description: "When set, each bit activates the pull-up on PA4 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD4 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 4 + bit_size: 1 + - name: PU5 + description: "When set, each bit activates the pull-up on PA5 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD5 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 5 + bit_size: 1 + - name: PU6 + description: "When set, each bit activates the pull-up on PA6 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD6 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 6 + bit_size: 1 + - name: PU7 + description: "When set, each bit activates the pull-up on PA7 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD7 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 7 + bit_size: 1 + - name: PU8 + description: "When set, each bit activates the pull-up on PA8 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD8 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 8 + bit_size: 1 + - name: PU9 + description: "When set, each bit activates the pull-up on PA9 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD9 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 9 + bit_size: 1 + - name: PU10 + description: "When set, each bit activates the pull-up on PA10 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD10 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 10 + bit_size: 1 + - name: PU11 + description: "When set, each bit activates the pull-up on PA11 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD11 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 11 + bit_size: 1 + - name: PU12 + description: "When set, each bit activates the pull-up on PA12 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD12 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 12 + bit_size: 1 + - name: PU13 + description: "When set, each bit activates the pull-up on PA13 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD13 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 13 + bit_size: 1 + - name: PU15 + description: "When set, each bit activates the pull-up on PA15 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD15 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 15 + bit_size: 1 +fieldset/PUCRB: + description: PWR port B pull-up control register. + fields: + - name: PU0 + description: "When set, each bit activates the pull-up on PB0 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD0 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: "When set, each bit activates the pull-up on PB1 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD1 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 1 + bit_size: 1 + - name: PU2 + description: "When set, each bit activates the pull-up on PB2 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD2 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 2 + bit_size: 1 + - name: PU3 + description: "When set, each bit activates the pull-up on PB3 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD3 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 3 + bit_size: 1 + - name: PU4 + description: "When set, each bit activates the pull-up on PB4 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD4 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 4 + bit_size: 1 + - name: PU5 + description: "When set, each bit activates the pull-up on PB5 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD5 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 5 + bit_size: 1 + - name: PU6 + description: "When set, each bit activates the pull-up on PB6 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD6 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 6 + bit_size: 1 + - name: PU7 + description: "When set, each bit activates the pull-up on PB7 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD7 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 7 + bit_size: 1 + - name: PU8 + description: "When set, each bit activates the pull-up on PB8 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD8 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 8 + bit_size: 1 + - name: PU9 + description: "When set, each bit activates the pull-up on PB9 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD9 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 9 + bit_size: 1 + - name: PU10 + description: "When set, each bit activates the pull-up on PB10 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD10 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 10 + bit_size: 1 + - name: PU11 + description: "When set, each bit activates the pull-up on PB11 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD11 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 11 + bit_size: 1 + - name: PU12 + description: "When set, each bit activates the pull-up on PB12 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD12 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 12 + bit_size: 1 + - name: PU13 + description: "When set, each bit activates the pull-up on PB13 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD13 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 13 + bit_size: 1 + - name: PU14 + description: "When set, each bit activates the pull-up on PB14 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD14 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 14 + bit_size: 1 + - name: PU15 + description: "When set, each bit activates the pull-up on PB15 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD15 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 15 + bit_size: 1 +fieldset/PUCRC: + description: PWR port C pull-up control register. + fields: + - name: PU0 + description: "When set, each bit activates the pull-up on PC0 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD0 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: "When set, each bit activates the pull-up on PC1 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD1 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 1 + bit_size: 1 + - name: PU2 + description: "When set, each bit activates the pull-up on PC2 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD2 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 2 + bit_size: 1 + - name: PU3 + description: "When set, each bit activates the pull-up on PC3 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD3 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 3 + bit_size: 1 + - name: PU4 + description: "When set, each bit activates the pull-up on PC4 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD4 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 4 + bit_size: 1 + - name: PU5 + description: "When set, each bit activates the pull-up on PC5 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD5 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 5 + bit_size: 1 + - name: PU6 + description: "When set, each bit activates the pull-up on PC6 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD6 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 6 + bit_size: 1 + - name: PU7 + description: "When set, each bit activates the pull-up on PC7 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD7 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 7 + bit_size: 1 + - name: PU8 + description: "When set, each bit activates the pull-up on PC8 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD8 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 8 + bit_size: 1 + - name: PU9 + description: "When set, each bit activates the pull-up on PC9 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD9 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 9 + bit_size: 1 + - name: PU10 + description: "When set, each bit activates the pull-up on PC10 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD10 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 10 + bit_size: 1 + - name: PU11 + description: "When set, each bit activates the pull-up on PC11 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD11 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 11 + bit_size: 1 + - name: PU12 + description: "When set, each bit activates the pull-up on PC12 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD12 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 12 + bit_size: 1 + - name: PU13 + description: "When set, each bit activates the pull-up on PC13 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD13 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 13 + bit_size: 1 + - name: PU14 + description: "When set, each bit activates the pull-up on PC14 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD14 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 14 + bit_size: 1 + - name: PU15 + description: "When set, each bit activates the pull-up on PC15 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD15 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 15 + bit_size: 1 +fieldset/PUCRD: + description: PWR port D pull-up control register. + fields: + - name: PU0 + description: "When set, each bit activates the pull-up on PD0 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD0 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: "When set, each bit activates the pull-up on PD1 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD1 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 1 + bit_size: 1 + - name: PU2 + description: "When set, each bit activates the pull-up on PD2 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD2 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 2 + bit_size: 1 + - name: PU3 + description: "When set, each bit activates the pull-up on PD3 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD3 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 3 + bit_size: 1 + - name: PU4 + description: "When set, each bit activates the pull-up on PD4 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD4 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 4 + bit_size: 1 + - name: PU5 + description: "When set, each bit activates the pull-up on PD5 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD5 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 5 + bit_size: 1 + - name: PU6 + description: "When set, each bit activates the pull-up on PD6 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD6 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 6 + bit_size: 1 + - name: PU7 + description: "When set, each bit activates the pull-up on PD7 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD7 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 7 + bit_size: 1 + - name: PU8 + description: "When set, each bit activates the pull-up on PD8 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD8 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 8 + bit_size: 1 + - name: PU9 + description: "When set, each bit activates the pull-up on PD9 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD9 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 9 + bit_size: 1 + - name: PU10 + description: "When set, each bit activates the pull-up on PD10 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD10 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 10 + bit_size: 1 + - name: PU11 + description: "When set, each bit activates the pull-up on PD11 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD11 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 11 + bit_size: 1 + - name: PU12 + description: "When set, each bit activates the pull-up on PD12 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD12 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 12 + bit_size: 1 + - name: PU13 + description: "When set, each bit activates the pull-up on PD13 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD13 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 13 + bit_size: 1 + - name: PU14 + description: "When set, each bit activates the pull-up on PD14 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD14 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 14 + bit_size: 1 + - name: PU15 + description: "When set, each bit activates the pull-up on PD15 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD15 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 15 + bit_size: 1 +fieldset/PUCRE: + description: PWR port E pull-up control register. + fields: + - name: PU0 + description: "When set, each bit activates the pull-up on PE0 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD0 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: "When set, each bit activates the pull-up on PE1 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD1 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 1 + bit_size: 1 + - name: PU2 + description: "When set, each bit activates the pull-up on PE2 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD2 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 2 + bit_size: 1 + - name: PU3 + description: "When set, each bit activates the pull-up on PE3 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD3 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 3 + bit_size: 1 + - name: PU4 + description: "When set, each bit activates the pull-up on PE4 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD4 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 4 + bit_size: 1 + - name: PU5 + description: "When set, each bit activates the pull-up on PE5 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD5 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 5 + bit_size: 1 + - name: PU6 + description: "When set, each bit activates the pull-up on PE6 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD6 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 6 + bit_size: 1 + - name: PU7 + description: "When set, each bit activates the pull-up on PE7 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD7 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 7 + bit_size: 1 + - name: PU8 + description: "When set, each bit activates the pull-up on PE8 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD8 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 8 + bit_size: 1 + - name: PU9 + description: "When set, each bit activates the pull-up on PE9 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD9 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 9 + bit_size: 1 + - name: PU10 + description: "When set, each bit activates the pull-up on PE10 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD10 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 10 + bit_size: 1 + - name: PU11 + description: "When set, each bit activates the pull-up on PE11 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD11 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 11 + bit_size: 1 + - name: PU12 + description: "When set, each bit activates the pull-up on PE12 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD12 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 12 + bit_size: 1 + - name: PU13 + description: "When set, each bit activates the pull-up on PE13 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD13 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 13 + bit_size: 1 + - name: PU14 + description: "When set, each bit activates the pull-up on PE14 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD14 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 14 + bit_size: 1 + - name: PU15 + description: "When set, each bit activates the pull-up on PE15 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD15 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 15 + bit_size: 1 +fieldset/PUCRG: + description: PWR port G pull-up control register. + fields: + - name: PU2 + description: "When set, each bit activates the pull-up on PG2 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD2 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 2 + bit_size: 1 + - name: PU3 + description: "When set, each bit activates the pull-up on PG3 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD3 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 3 + bit_size: 1 + - name: PU4 + description: "When set, each bit activates the pull-up on PG4 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD4 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 4 + bit_size: 1 + - name: PU5 + description: "When set, each bit activates the pull-up on PG5 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD5 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 5 + bit_size: 1 + - name: PU6 + description: "When set, each bit activates the pull-up on PG6 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD6 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 6 + bit_size: 1 + - name: PU7 + description: "When set, each bit activates the pull-up on PG7 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD7 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 7 + bit_size: 1 + - name: PU8 + description: "When set, each bit activates the pull-up on PG8 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD8 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 8 + bit_size: 1 + - name: PU9 + description: "When set, each bit activates the pull-up on PG9 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD9 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 9 + bit_size: 1 + - name: PU10 + description: "When set, each bit activates the pull-up on PG10 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD10 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 10 + bit_size: 1 + - name: PU11 + description: "When set, each bit activates the pull-up on PG11 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD11 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 11 + bit_size: 1 + - name: PU12 + description: "When set, each bit activates the pull-up on PG12 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD12 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 12 + bit_size: 1 + - name: PU13 + description: "When set, each bit activates the pull-up on PG13 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD13 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 13 + bit_size: 1 + - name: PU14 + description: "When set, each bit activates the pull-up on PG14 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD14 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 14 + bit_size: 1 + - name: PU15 + description: "When set, each bit activates the pull-up on PG15 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD15 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 15 + bit_size: 1 +fieldset/PUCRH: + description: PWR port H pull-up control register. + fields: + - name: PU0 + description: "When set, each bit activates the pull-up on PH0 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD0 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: "When set, each bit activates the pull-up on PH1 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD1 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 1 + bit_size: 1 + - name: PU3 + description: "When set, each bit activates the pull-up on PH3 when the APC bit is set in APCR. The pull-up is not activated if the corresponding PD3 bit is also set. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package." + bit_offset: 3 + bit_size: 1 +fieldset/SECCFGR: + description: PWR security configuration register. + fields: + - name: WUP1SEC + description: "None 0: Bits related to the WKUP1 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written with secure or non-secure access. 1: Bits related to the WKUP1 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written only with secure access." + bit_offset: 0 + bit_size: 1 + - name: WUP2SEC + description: "None 0: Bits related to the WKUP2 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written with secure or non-secure access. 1: Bits related to the WKUP2 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written only with secure access." + bit_offset: 1 + bit_size: 1 + - name: WUP3SEC + description: "None 0: Bits related to the WKUP3 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written with secure or non-secure access. 1: Bits related to the WKUP3 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written only with secure access." + bit_offset: 2 + bit_size: 1 + - name: WUP4SEC + description: "None 0: Bits related to the WKUP4 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written with secure or non-secure access. 1: Bits related to the WKUP4 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written only with secure access." + bit_offset: 3 + bit_size: 1 + - name: WUP5SEC + description: "None 0: Bits related to the WKUP5 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written with secure or non-secure access. 1: Bits related to the WKUP5 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written only with secure access." + bit_offset: 4 + bit_size: 1 + - name: WUP6SEC + description: "None 0: Bits related to the WKUP6 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written with secure or non-secure access. 1: Bits related to the WKUP6 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written only with secure access." + bit_offset: 5 + bit_size: 1 + - name: WUP7SEC + description: "None 0: Bits related to the WKUP7 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written with secure or non-secure access. 1: Bits related to the WKUP7 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written only with secure access." + bit_offset: 6 + bit_size: 1 + - name: WUP8SEC + description: "None 0: Bits related to the WKUP8 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written with secure or non-secure access. 1: Bits related to the WKUP8 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written only with secure access." + bit_offset: 7 + bit_size: 1 + - name: WUP9SEC + description: "None 0: Bits related to the WKUP9 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written with secure or non-secure access. 1: Bits related to the WKUP9 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written only with secure access." + bit_offset: 8 + bit_size: 1 + - name: WUP10SEC + description: "None 0: Bits related to the WKUP10 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written with secure or non-secure access. 1: Bits related to the WKUP10 line in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written only with secure access." + bit_offset: 9 + bit_size: 1 + - name: LPMSEC + description: "None 0: CR1, CR2 and CSSF in the SR can be read and written with secure or non-secure access. 1: CR1, CR2, and CSSF in the SR can be read and written only with secure access." + bit_offset: 12 + bit_size: 1 + - name: VDMSEC + description: "None 0: SVMCR and CR3 can be read and written with secure or non-secure access. 1: SVMCR and CR3 can be read and written only with secure access." + bit_offset: 13 + bit_size: 1 + - name: VBSEC + description: "None 0: BDCR and DBPR can be read and written with secure or non-secure access. 1: BDCR and DBPR can be read and written only with secure access." + bit_offset: 14 + bit_size: 1 + - name: APCSEC + description: "None 0: APCR can be read and written with secure or non-secure access. 1: APCR can be read and written only with secure access." + bit_offset: 15 + bit_size: 1 +fieldset/SR: + description: PWR status register. + fields: + - name: CSSF + description: This bit is protected against non-secure access when LPMSEC=1 in SECCFGR. This bit is protected against unprivileged access when LPMSEC=1 and SPRIV=1 in PRIVCFGR, or when LPMSEC=0 and NSPRIV=1. Writing 1 to this bit clears the STOPF and SBF flags. + bit_offset: 0 + bit_size: 1 + - name: STOPF + description: "This bit is set by hardware when the device enters a Stop mode, and is cleared by software by writing 1 to the CSSF bit. 0: The device did not enter any Stop mode. 1: The device entered a Stop mode." + bit_offset: 1 + bit_size: 1 + - name: SBF + description: "This bit is set by hardware when the device enters the Standby mode, and is cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset. 0: The device did not enter Standby mode. 1: The device entered Standby mode." + bit_offset: 2 + bit_size: 1 +fieldset/SVMCR: + description: PWR supply voltage monitoring control register. + fields: + - name: PVDE + description: "None 0: PVD disabled 1: PVD enabled." + bit_offset: 4 + bit_size: 1 + - name: PVDLS + description: "These bits select the voltage threshold detected by the PVD: 000: VPVD0 around 2.0V 001: VPVD1 around 2.2V 010: VPVD2 around 2.4V 011: VPVD3 around 2.5V 100: VPVD4 around 2.6V 101: VPVD5 around 2.8V 110: VPVD6 around 2.9V 111: External input analog voltage PVD_IN (compared internally to VREFINT)." + bit_offset: 5 + bit_size: 3 + enum: PVDLS + - name: UVMEN + description: "None 0: VDDUSB voltage monitor disabled 1: VDDUSB voltage monitor enabled." + bit_offset: 24 + bit_size: 1 + - name: IO2VMEN + description: "None 0: VDDIO2 voltage monitor disabled 1: VDDIO2 voltage monitor enabled." + bit_offset: 25 + bit_size: 1 + - name: AVM1EN + description: "None 0: VDDA voltage monitor 1 disabled 1: VDDA voltage monitor 1 enabled." + bit_offset: 26 + bit_size: 1 + - name: AVM2EN + description: "None 0: VDDA voltage monitor 2 disabled 1: VDDA voltage monitor 2 enabled." + bit_offset: 27 + bit_size: 1 + - name: USV + description: "This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USB peripheral. If VDDUSB is not always present in the application, the VDDUSB voltage monitor can be used to determine whether this supply is ready or not. 0: VDDUSB not present: logical and electrical isolation is applied to ignore this supply. 1: VDDUSB valid." + bit_offset: 28 + bit_size: 1 + - name: IO2SV + description: "This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose. Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the application, the VDDIO2 voltage monitor can be used to determine whether this supply is ready or not. 0: VDDIO2 not present: logical and electrical isolation is applied to ignore this supply. 1: VDDIO2 valid." + bit_offset: 29 + bit_size: 1 + - name: ASV + description: "This bit is used to validate the VDDA supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the analog peripherals. If VDDA is not always present in the application, the VDDA voltage monitor can be used to determine whether this supply is ready or not. 0: VDDA not present: logical and electrical isolation is applied to ignore this supply. 1: VDDA valid." + bit_offset: 30 + bit_size: 1 +fieldset/SVMSR: + description: PWR supply voltage monitoring status register. + fields: + - name: REGS + description: "None 0: LDO selected 1: SMPS selected." + bit_offset: 1 + bit_size: 1 + enum: REGSEL + - name: PVDO + description: "None 0: VDD is equal or above the PVD threshold selected by PVDLS[2:0]. 1: VDD is below the PVD threshold selected by PVDLS[2:0]." + bit_offset: 4 + bit_size: 1 + enum: PVDO + - name: VDDUSBRDY + description: "None 0: VDDUSB is below the threshold of the VDDUSB voltage monitor. 1: VDDUSB is equal or above the threshold of the VDDUSB voltage monitor." + bit_offset: 24 + bit_size: 1 + - name: VDDIO2RDY + description: "None 0: VDDIO2 is below the threshold of the VDDIO2 voltage monitor. 1: VDDIO2 is equal or above the threshold of the VDDIO2 voltage monitor." + bit_offset: 25 + bit_size: 1 + - name: VDDA1RDY + description: "None 0: VDDA is below the threshold of the VDDA voltage monitor 1 (around 1.6V). 1: VDDA is equal or above the threshold of the VDDA voltage monitor 1 (around 1.6V)." + bit_offset: 26 + bit_size: 1 + - name: VDDA2RDY + description: "None 0: VDDA is below the threshold of the VDDA voltage monitor 2 (around 1.8V). 1: VDDA is equal or above the threshold of the VDDA voltage monitor 2 (around 1.8V)." + bit_offset: 27 + bit_size: 1 +fieldset/VOSR: + description: PWR voltage scaling register. + fields: + - name: R1EN + description: "This field is protected against non-secure access when SYSCLKSEC=1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC=1 in RCC_SECCFGR and SPRIV=1 in PRIVCFGR, or when SYSCLKSEC=0 and NSPRIV=1. 0: Voltage scaling range 1 disabled 1: Voltage scaling range 1 enabled Note: R1EN and R2EN must be at opposite value. Any attempt to write R1EN and R2EN to same value is ignored. Modifying R1EN and R2EN is possible only when current range is ready (R1RDY=R1EN and R2RDY=R2EN)." + bit_offset: 0 + bit_size: 1 + - name: R2EN + description: "This field is protected against non-secure access when SYSCLKSEC=1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC=1 in RCC_SECCFGR and SPRIV=1 in PRIVCFGR, or when SYSCLKSEC=0 and NSPRIV=1. 0: Voltage scaling range 2 disabled 1: Voltage scaling range 2 enabled Note: R1EN and R2EN must be at opposite value. Any attempt to write R1EN and R2EN to same value is ignored. Modifying R1EN and R2EN is possible only when current range is ready (R1RDY=R1EN and R2RDY=R2EN)." + bit_offset: 1 + bit_size: 1 + - name: BOOSTEN + description: "This bit is protected against non-secure access when SYSCLKSEC=1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC=1 in RCC_SECCFGR and SPRIV=1 in PRIVCFGR, or when SYSCLKSEC=0 and NSPRIV=1. This bit must be set in Range 1, and before increasing the system clock frequency above 24 MHz in Range 2. The booster clock must be configured before setting this bit, and must not be disabled as long as the booster is enabled. 0: Booster disabled 1: Booster enabled." + bit_offset: 8 + bit_size: 1 + - name: R1RDY + description: "None 0: Range 1 not ready: voltage level less than VOS range 1 level 1: Range 1 ready: voltage level greater or equal VOS range 1 level Note: R1RDY and R2RDY cannot be set at the same time." + bit_offset: 16 + bit_size: 1 + - name: R2RDY + description: "None 0: Range 2 not ready: voltage level less than VOS range 2 level 1: Range 2 ready: voltage level greater or equal VOS range 2 level Note: R1RDY and R2RDY cannot be set at the same time." + bit_offset: 17 + bit_size: 1 + - name: BOOSTRDY + description: "This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 24 MHz only after this bit is set. Disabling the booster clock when the booster is ready is forbidden. 0: Power booster not ready 1: Power booster ready." + bit_offset: 24 + bit_size: 1 +fieldset/WUCR1: + description: PWR wakeup control register 1. + fields: + - name: WUPEN1 + description: "None 0: Wakeup line WKUP1 disabled 1: Wakeup line WKUP1 enabled." + bit_offset: 0 + bit_size: 1 + - name: WUPEN2 + description: "None 0: Wakeup line WKUP2 disabled 1: Wakeup line WKUP2 enabled." + bit_offset: 1 + bit_size: 1 + - name: WUPEN3 + description: "None 0: Wakeup line WKUP3 disabled 1: Wakeup line WKUP3 enabled." + bit_offset: 2 + bit_size: 1 + - name: WUPEN4 + description: "None 0: Wakeup line WKUP4 disabled 1: Wakeup line WKUP4 enabled." + bit_offset: 3 + bit_size: 1 + - name: WUPEN5 + description: "None 0: Wakeup line WKUP5 disabled 1: Wakeup line WKUP5 enabled." + bit_offset: 4 + bit_size: 1 + - name: WUPEN6 + description: "None 0: Wakeup line WKUP6 disabled 1: Wakeup line WKUP6 enabled." + bit_offset: 5 + bit_size: 1 + - name: WUPEN7 + description: "None 0: Wakeup line WKUP7 disabled 1: Wakeup line WKUP7 enabled." + bit_offset: 6 + bit_size: 1 + - name: WUPEN8 + description: "None 0: Wakeup line WKUP8 disabled 1: Wakeup line WKUP8 enabled." + bit_offset: 7 + bit_size: 1 + - name: WUPEN9 + description: "None 0: Wakeup line WKUP9 disabled 1: Wakeup line WKUP9 enabled." + bit_offset: 8 + bit_size: 1 + - name: WUPEN10 + description: "None 0: Wakeup line WKUP10 disabled 1: Wakeup line WKUP10 enabled." + bit_offset: 9 + bit_size: 1 +fieldset/WUCR2: + description: PWR wakeup control register 2. + fields: + - name: WUPP + description: "This bit must be configured when WUPEN1 = 0. It has no effect when WUSEL1 = 11. 0: Detection on high level (rising edge) 1: Detection on low level (falling edge)." + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 + enum: WUPP +fieldset/WUCR3: + description: PWR wakeup control register 3. + fields: + - name: WUSEL1 + description: "This field must be configured when WUPEN1 = 0. 00: WKUP1_0 01: WKUP1_1 10: WKUP1_2 11: WKUP1_3." + bit_offset: 0 + bit_size: 2 + enum: WUSEL + - name: WUSEL2 + description: "This field must be configured when WUPEN2 = 0. 00: WKUP2_0 01: WKUP2_1 10: WKUP2_2 11: WKUP2_3." + bit_offset: 2 + bit_size: 2 + enum: WUSEL + - name: WUSEL3 + description: "This field must be configured when WUPEN3 = 0. 00: WKUP3_0 01: WKUP3_1 10: WKUP3_2 11: WKUP3_3." + bit_offset: 4 + bit_size: 2 + enum: WUSEL + - name: WUSEL4 + description: "This field must be configured when WUPEN4 = 0. 00: WKUP4_0 01: WKUP4_1 10: WKUP4_2 11: WKUP4_3." + bit_offset: 6 + bit_size: 2 + enum: WUSEL + - name: WUSEL5 + description: "This field must be configured when WUPEN5 = 0. 00: WKUP5_0 01: WKUP5_1 10: WKUP5_2 11: WKUP5_3." + bit_offset: 8 + bit_size: 2 + enum: WUSEL + - name: WUSEL6 + description: "This field must be configured when WUPEN6 = 0. 00: WKUP6_0 01: WKUP6_1 10: WKUP6_2 11: WKUP6_3." + bit_offset: 10 + bit_size: 2 + enum: WUSEL + - name: WUSEL7 + description: "This field must be configured when WUPEN7 = 0. 00: WKUP7_0 01: WKUP7_1 10: WKUP7_2 11: WKUP7_3." + bit_offset: 12 + bit_size: 2 + enum: WUSEL + - name: WUSEL8 + description: "This field must be configured when WUPEN8 = 0. 00: WKUP8_0 01: WKUP8_1 10: WKUP8_2 11: WKUP8_3." + bit_offset: 14 + bit_size: 2 + enum: WUSEL +fieldset/WUSCR: + description: PWR wakeup status clear register. + fields: + - name: CWUF1 + description: Writing 1 to this bit clears the WUF1 flag in WUSR. + bit_offset: 0 + bit_size: 1 + - name: CWUF2 + description: Writing 1 to this bit clears the WUF2 flag in WUSR. + bit_offset: 1 + bit_size: 1 + - name: CWUF3 + description: Writing 1 to this bit clears the WUF3 flag in WUSR. + bit_offset: 2 + bit_size: 1 + - name: CWUF4 + description: Writing 1 to this bit clears the WUF4 flag in WUSR. + bit_offset: 3 + bit_size: 1 + - name: CWUF5 + description: Writing 1 to this bit clears the WUF5 flag in WUSR. + bit_offset: 4 + bit_size: 1 + - name: CWUF6 + description: Writing 1 to this bit clears the WUF6 flag in WUSR. + bit_offset: 5 + bit_size: 1 + - name: CWUF7 + description: Writing 1 to this bit clears the WUF7 flag in WUSR. + bit_offset: 6 + bit_size: 1 + - name: CWUF8 + description: Writing 1 to this bit clears the WUF8 flag in WUSR. + bit_offset: 7 + bit_size: 1 + - name: CWUF9 + description: Writing 1 to this bit clears the WUF9 flag in WUSR. + bit_offset: 8 + bit_size: 1 + - name: CWUF10 + description: Writing 1 to this bit clears the WUF10 flag in WUSR. + bit_offset: 9 + bit_size: 1 +fieldset/WUSR: + description: PWR wakeup status register. + fields: + - name: WUF1 + description: This bit is set when a wakeup event is detected on WKUP1 line. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR when WUSEL different 11, or by hardware when WUPEN1=0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared. + bit_offset: 0 + bit_size: 1 + - name: WUF2 + description: This bit is set when a wakeup event is detected on WKUP2 line. This bit is cleared by writing 1 in the CWUF2 bit of WUSCR when WUSEL different 11, or by hardware when WUPEN2=0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared. + bit_offset: 1 + bit_size: 1 + - name: WUF3 + description: This bit is set when a wakeup event is detected on WKUP3 line. This bit is cleared by writing 1 in the CWUF3 bit of WUSCR when WUSEL different 11, or by hardware when WUPEN3=0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared. + bit_offset: 2 + bit_size: 1 + - name: WUF4 + description: This bit is set when a wakeup event is detected on WKUP4 line. This bit is cleared by writing 1 in the CWUF4 bit of WUSCR when WUSEL different 11, or by hardware when WUPEN4=0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared. + bit_offset: 3 + bit_size: 1 + - name: WUF5 + description: This bit is set when a wakeup event is detected on WKUP5 line. This bit is cleared by writing 1 in the CWUF5 bit of WUSCR when WUSEL different 11, or by hardware when WUPEN5=0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared. + bit_offset: 4 + bit_size: 1 + - name: WUF6 + description: This bit is set when a wakeup event is detected on WKUP6 line. This bit is cleared by writing 1 in the CWUF6 bit of WUSCR when WUSEL different 11, or by hardware when WUPEN6=0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared. + bit_offset: 5 + bit_size: 1 + - name: WUF7 + description: This bit is set when a wakeup event is detected on WKUP7 line. This bit is cleared by writing 1 in the CWUF7 bit of WUSCR when WUSEL different 11, or by hardware when WUPEN7=0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared. + bit_offset: 6 + bit_size: 1 + - name: WUF8 + description: This bit is set when a wakeup event is detected on WKUP8 line. This bit is cleared by writing 1 in the CWUF8 bit of WUSCR when WUSEL different 11, or by hardware when WUPEN8=0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared. + bit_offset: 7 + bit_size: 1 + - name: WUF9 + description: This bit is set when a wakeup event is detected on WKUP9 line. This bit is cleared by writing 1 in the CWUF9 bit of WUSCR when WUSEL different 11, or by hardware when WUPEN9=0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared. + bit_offset: 8 + bit_size: 1 + - name: WUF10 + description: This bit is set when a wakeup event is detected on WKUP10 line. This bit is cleared by writing 1 in the CWUF10 bit of WUSCR when WUSEL different 11, or by hardware when WUPEN10=0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared. + bit_offset: 9 + bit_size: 1 +enum/LPMS: + bit_size: 3 + variants: + - name: Stop0 + description: Stop 0 mode. + value: 0 + - name: Stop1 + description: Stop 1 mode. + value: 1 + - name: Stop2 + description: Stop 2 mode. + value: 2 + - name: Stop3 + description: Stop 3 mode. + value: 3 + - name: Stop4 + description: Standby mode. + value: 4 + - name: Stop5 + description: Standby mode. + value: 5 + - name: Stop6 + description: Shutdown mode. + value: 6 + - name: Stop7 + description: Shutdown mode. + value: 7 +enum/PVDLS: + bit_size: 3 + variants: + - name: v20 + description: VPVD0 around 2.0V. + value: 0 + - name: v22 + description: VPVD1 around 2.2V. + value: 1 + - name: v24 + description: VPVD2 around 2.4V. + value: 2 + - name: v25 + description: VPVD3 around 2.5V. + value: 3 + - name: v26 + description: VPVD4 around 2.6V. + value: 4 + - name: v28 + description: VPVD5 around 2.8V. + value: 5 + - name: v29 + description: VPVD6 around 2.9V. + value: 6 + - name: pvd_in + description: External input analog voltage PVD_IN (compared internally to VREFINT). + value: 7 +enum/PVDO: + bit_size: 1 + variants: + - name: AboveOrEqual + description: VDD is equal or above the PVD threshold selected by PVDLS[2:0]. + value: 0 + - name: Below + description: VDD is below the PVD threshold selected by PVDLS[2:0]. + value: 1 +enum/REGSEL: + bit_size: 1 + variants: + - name: LDO + description: LDO selected. + value: 0 + - name: SMPS + description: SMPS selected. + value: 1 +enum/SRAMPD: + bit_size: 1 + variants: + - name: PoweredOn + description: SRAM1 powered on. + value: 0 + - name: PoweredOff + description: SRAM1 powered off. + value: 1 +enum/PDS: + bit_size: 1 + variants: + - name: Retained + description: Contents retained in Stop modes. + value: 0 + - name: Lost + description: Content lost in Stop modes. + value: 1 +enum/FLASHFWU: + bit_size: 1 + variants: + - name: LowPower + description: Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower-power consumption). + value: 0 + - name: Normal + description: Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wakeup time). + value: 1 +enum/SRAMFWU: + bit_size: 1 + variants: + - name: LowPower + description: SRAMs enters low-power mode in Stop 0 and Stop 1 modes (source biasing for lower-power consumption). + value: 0 + - name: Normal + description: SRAMs remains in normal mode in Stop 0 and Stop 1 modes (higher consumption but no SRAM wakeup time). + value: 1 +enum/VBRS: + bit_size: 1 + variants: + - name: Charge_5k + description: Charge VBAT through a 5 k ohm resistor. + value: 0 + - name: Charge_1_5k + description: Charge VBAT through a 1.5 k ohm resistor. + value: 1 +enum/WUPP: + bit_size: 1 + variants: + - name: High + description: Detection on high level (rising edge). + value: 0 + - name: Low + description: Detection on low level (falling edge). + value: 1 +enum/WUSEL: + bit_size: 2 + variants: + - name: WKUPx_0 + description: WKUPx_0. + value: 0 + - name: WKUPx_1 + description: WKUPx_1. + value: 1 + - name: WKUPx_2 + description: WKUPx_2. + value: 2 + - name: WKUPx_3 + description: WKUPx_3. + value: 3 diff --git a/data/registers/rcc_u3.yaml b/data/registers/rcc_u3.yaml new file mode 100644 index 000000000..9210859ee --- /dev/null +++ b/data/registers/rcc_u3.yaml @@ -0,0 +1,2600 @@ +block/RCC: + description: Reset and clock control. + items: + - byte_offset: 0 + description: RCC clock control register. + fieldset: CR + name: CR + - byte_offset: 8 + description: RCC internal clock source calibration register 1. + fieldset: ICSCR1 + name: ICSCR1 + - byte_offset: 12 + description: RCC internal clock source calibration register 2. + fieldset: ICSCR2 + name: ICSCR2 + - byte_offset: 16 + description: RCC internal clock source calibration register 3. + fieldset: ICSCR3 + name: ICSCR3 + - access: Read + byte_offset: 20 + description: RCC clock recovery RC register. + fieldset: CRRCR + name: CRRCR + - byte_offset: 28 + description: RCC clock configuration register 1. + fieldset: CFGR1 + name: CFGR1 + - byte_offset: 32 + description: RCC clock configuration register 2. + fieldset: CFGR2 + name: CFGR2 + - byte_offset: 36 + description: RCC clock configuration register 3. + fieldset: CFGR3 + name: CFGR3 + - byte_offset: 40 + description: RCC clock configuration register 4. + fieldset: CFGR4 + name: CFGR4 + - byte_offset: 80 + description: RCC clock interrupt enable register. + fieldset: CIER + name: CIER + - access: Read + byte_offset: 84 + description: RCC clock interrupt flag register. + fieldset: CIFR + name: CIFR + - access: Write + byte_offset: 88 + description: RCC clock interrupt clear register. + fieldset: CICR + name: CICR + - byte_offset: 96 + description: RCC AHB1 peripheral reset register 1. + fieldset: AHB1RSTR1 + name: AHB1RSTR1 + - byte_offset: 100 + description: RCC AHB2 peripheral reset register 1. + fieldset: AHB2RSTR1 + name: AHB2RSTR1 + - byte_offset: 104 + description: RCC AHB2 peripheral reset register 2. + fieldset: AHB2RSTR2 + name: AHB2RSTR2 + - byte_offset: 116 + description: RCC APB1 peripheral reset register 1. + fieldset: APB1RSTR1 + name: APB1RSTR1 + - byte_offset: 120 + description: RCC APB1 peripheral reset register 2. + fieldset: APB1RSTR2 + name: APB1RSTR2 + - byte_offset: 124 + description: RCC APB2 peripheral reset register. + fieldset: APB2RSTR + name: APB2RSTR + - byte_offset: 128 + description: RCC APB3 peripheral reset register. + fieldset: APB3RSTR + name: APB3RSTR + - byte_offset: 136 + description: RCC AHB1 peripheral clock enable register 1. + fieldset: AHB1ENR1 + name: AHB1ENR1 + - byte_offset: 140 + description: RCC AHB2 peripheral clock enable register 1. + fieldset: AHB2ENR1 + name: AHB2ENR1 + - byte_offset: 144 + description: RCC AHB2 peripheral clock enable register 2. + fieldset: AHB2ENR2 + name: AHB2ENR2 + - byte_offset: 148 + description: RCC AHB1 peripheral clock enable register 2. + fieldset: AHB1ENR2 + name: AHB1ENR2 + - byte_offset: 156 + description: RCC APB1 peripheral clock enable register 1. + fieldset: APB1ENR1 + name: APB1ENR1 + - byte_offset: 160 + description: RCC APB1 peripheral clock enable register 2. + fieldset: APB1ENR2 + name: APB1ENR2 + - byte_offset: 164 + description: RCC APB2 peripheral clock enable register. + fieldset: APB2ENR + name: APB2ENR + - byte_offset: 168 + description: RCC APB3 peripheral clock enable register. + fieldset: APB3ENR + name: APB3ENR + - byte_offset: 176 + description: RCC AHB1 peripheral clock enable in Sleep mode register. + fieldset: AHB1SLPENR1 + name: AHB1SLPENR1 + - byte_offset: 180 + description: RCC AHB2 peripheral clock enable in Sleep mode register 1. + fieldset: AHB2SLPENR1 + name: AHB2SLPENR1 + - byte_offset: 184 + description: RCC AHB2 peripheral clock enable in Sleep mode register 2. + fieldset: AHB2SLPENR2 + name: AHB2SLPENR2 + - byte_offset: 188 + description: RCC AHB1 peripheral clock enable in Sleep mode register 2. + fieldset: AHB1SLPENR2 + name: AHB1SLPENR2 + - byte_offset: 196 + description: RCC APB1 peripheral clock enable in Sleep mode register 1. + fieldset: APB1SLPENR1 + name: APB1SLPENR1 + - byte_offset: 200 + description: RCC APB1 peripheral clock enable in Sleep mode register 2. + fieldset: APB1SLPENR2 + name: APB1SLPENR2 + - byte_offset: 204 + description: RCC APB2 peripheral clock enable in Sleep mode register. + fieldset: APB2SLPENR + name: APB2SLPENR + - byte_offset: 208 + description: RCC APB3 peripheral clock enable in Sleep mode register. + fieldset: APB3SLPENR + name: APB3SLPENR + - byte_offset: 216 + description: RCC AHB1 peripheral clock enable in Stop mode register. + fieldset: AHB1STPENR1 + name: AHB1STPENR1 + - byte_offset: 220 + description: RCC AHB2 peripheral clock enable in Stop mode register 1. + fieldset: AHB2STPENR1 + name: AHB2STPENR1 + - byte_offset: 236 + description: RCC APB1 peripheral clock enable in Stop mode register 1. + fieldset: APB1STPENR1 + name: APB1STPENR1 + - byte_offset: 240 + description: RCC APB1 peripheral clock enable in Stop mode register 2. + fieldset: APB1STPENR2 + name: APB1STPENR2 + - byte_offset: 244 + description: RCC APB2 peripheral clock enable in Stop mode register. + fieldset: APB2STPENR + name: APB2STPENR + - byte_offset: 248 + description: RCC APB3 peripheral clock enable in Stop mode register. + fieldset: APB3STPENR + name: APB3STPENR + - byte_offset: 256 + description: RCC peripheral independent clock configuration register 1. + fieldset: CCIPR1 + name: CCIPR1 + - byte_offset: 260 + description: RCC peripheral independent clock configuration register 2. + fieldset: CCIPR2 + name: CCIPR2 + - byte_offset: 264 + description: RCC peripheral independent clock configuration register 3. + fieldset: CCIPR3 + name: CCIPR3 + - byte_offset: 272 + description: RCC backup domain control register. + fieldset: BDCR + name: BDCR + - byte_offset: 276 + description: RCC control/status register. + fieldset: CSR + name: CSR + - byte_offset: 304 + description: RCC secure configuration register. + fieldset: SECCFGR + name: SECCFGR + - byte_offset: 308 + description: RCC privilege configuration register. + fieldset: PRIVCFGR + name: PRIVCFGR +enum/ADCDACPRE: + bit_size: 4 + variants: + - description: adcdac_iclk. + name: Div1 + value: 0 + - description: adcdac_iclk/2. + name: Div2 + value: 1 + - description: adcdac_iclk/4. + name: Div4 + value: 8 + - description: adcdac_iclk/8. + name: Div8 + value: 9 + - description: adcdac_iclk/16. + name: Div16 + value: 10 + - description: adcdac_iclk/32. + name: Div32 + value: 11 + - description: adcdac_iclk/64. + name: Div64 + value: 12 + - description: adcdac_iclk/128. + name: Div128 + value: 13 + - description: adcdac_iclk/256. + name: Div256 + value: 14 + - description: adcdac_iclk/512. + name: Div512 + value: 15 +enum/ADCDACSEL: + bit_size: 2 + variants: + - description: HCLK selected. + name: HCLK1 + value: 0 + - description: HSE selected. + name: HSE + value: 1 + - description: MSIK selected. + name: MSIK + value: 2 +enum/ADFSEL: + bit_size: 2 + variants: + - description: HCLK. + name: HCLK1 + value: 0 + - description: Input pin AUDIOCLK selected. + name: AUDIOCLK + value: 1 + - description: MSIK clock selected. + name: MSIK + value: 2 + - description: SAI1 kernel clock selected. + name: SAI1 + value: 3 +enum/BOOSTDIV: + bit_size: 4 + variants: + - description: Divided by 1 (bypass). + name: Div1 + value: 0 + - description: Divided by 2. + name: Div2 + value: 1 + - description: Divided by 4. + name: Div4 + value: 2 + - description: Divided by 6. + name: Div6 + value: 3 + - description: Divided by 8. + name: Div8 + value: 4 + - description: Divided by 10. + name: Div10 + value: 5 + - description: Divided by 12. + name: Div12 + value: 6 + - description: Divided by 14. + name: Div14 + value: 7 + - description: Divided by 16. + name: Div16 + value: 8 +enum/BOOSTSEL: + bit_size: 2 + variants: + - description: No clock. + name: DISABLE + value: 0 + - description: MSIS selected as EPOD booster clock source. + name: MSIS + value: 1 + - description: HSI16 selected as EPOD booster clock source. + name: HSI16 + value: 2 + - description: HSE selected as EPOD booster clock source. + name: HSE + value: 3 +enum/DACSHSEL: + bit_size: 1 + variants: + - description: LSE selected. + name: LSE + value: 0 + - description: LSI selected. + name: LSI + value: 1 +enum/FDCANSEL: + bit_size: 1 + variants: + - description: SYSCLK selected. + name: SYS + value: 0 + - description: MSIK selected. + name: MSIK + value: 1 +enum/HPRE: + bit_size: 4 + variants: + - description: HCLK = SYSCLK not divided. + name: Div1 + value: 0 + - description: HCLK = SYSCLK divided by 2. + name: Div2 + value: 8 + - description: HCLK = SYSCLK divided by 4. + name: Div4 + value: 9 + - description: HCLK = SYSCLK divided by 8. + name: Div8 + value: 10 + - description: HCLK = SYSCLK divided by 16. + name: Div16 + value: 11 + - description: HCLK = SYSCLK divided by 64. + name: Div64 + value: 12 + - description: HCLK = SYSCLK divided by 128. + name: Div128 + value: 13 + - description: HCLK = SYSCLK divided by 256. + name: Div256 + value: 14 + - description: HCLK = SYSCLK divided by 512. + name: Div512 + value: 15 +enum/HSEEXT: + bit_size: 1 + variants: + - description: External HSE clock analog mode. + name: ANALOG + value: 0 + - description: External HSE clock digital mode (through I/O Schmitt trigger). + name: DIGITAL + value: 1 +enum/ICLKSEL: + bit_size: 2 + variants: + - description: HSI48 selected. + name: HSI48 + value: 0 + - description: MSIK selected. + name: MSIK + value: 1 + - description: HSE selected. + name: HSE + value: 2 + - description: SYSCLK selected. + name: SYS + value: 3 +enum/I2CSEL: + bit_size: 1 + variants: + - description: PCLK1 selected. + name: PCLK1 + value: 0 + - description: MSIK selected. + name: MSIK + value: 1 +enum/I2C3SEL: + bit_size: 1 + variants: + - description: PCLK1 selected. + name: PCLK3 + value: 0 + - description: MSIK selected. + name: MSIK + value: 1 +enum/I3CSEL: + bit_size: 1 + variants: + - description: PCLK1 selected. + name: PCLK1 + value: 0 + - description: MSIK selected. + name: MSIK + value: 1 +enum/I3C2SEL: + bit_size: 1 + variants: + - description: PCLK2 selected. + name: PCLK2 + value: 0 + - description: MSIK selected. + name: MSIK + value: 1 +enum/LPTIMSEL: + bit_size: 2 + variants: + - description: MSIK clock selected. + name: MSIK + value: 0 + - description: LSI selected. + name: LSI + value: 1 + - description: HSI16 selected. + name: HSI + value: 2 + - description: LSE selected. + name: LSE + value: 3 +enum/LPUARTSEL: + bit_size: 2 + variants: + - description: PCLK3 selected. + name: PCLK3 + value: 0 + - description: HSI16 selected. + name: HSI + value: 1 + - description: LSE selected. + name: LSE + value: 2 + - description: MSIK selected. + name: MSIK + value: 3 +enum/LSCOSEL: + bit_size: 1 + variants: + - description: LSI selected. + name: LSI + value: 0 + - description: LSE selected. + name: LSE + value: 1 +enum/LSEDRV: + bit_size: 2 + variants: + - description: Low driving capability + name: Low + value: 0 + - description: Medium-low driving capability + name: MediumLow + value: 1 + - description: Medium-high driving capability + name: MediumHigh + value: 2 + - description: High driving capability + name: High + value: 3 +enum/LSIPREDIV: + bit_size: 1 + variants: + - description: LSI not divided. + name: Div1 + value: 0 + - description: LSI divided by 128. + name: Div128 + value: 1 +enum/MCO2SEL: + bit_size: 4 + variants: + - description: MCO2 output disabled, no clock on MCO2. + name: DISABLE + value: 0 + - description: SYSCLK system clock selected. + name: SYS + value: 1 + - description: MSIS clock selected. + name: MSIS + value: 2 + - description: HSI16 clock selected. + name: HSI16 + value: 3 + - description: "HSE clock selected 0101: LSI clock selected." + name: HSE + value: 4 + - description: LSE clock selected. + name: LSE + value: 6 + - description: HSI48 clock selected. + name: HSI48 + value: 7 + - description: MSIK clock selected. + name: MSIK + value: 8 +enum/MCOPRE: + bit_size: 3 + variants: + - description: MCO2 divided by 1. + name: Div1 + value: 0 + - description: MCO2 divided by 2. + name: Div2 + value: 1 + - description: MCO2 divided by 4. + name: Div4 + value: 2 + - description: MCO2 divided by 8. + name: Div8 + value: 3 + - description: MCO2 divided by 16. + name: Div16 + value: 4 + - description: MCO2 divided by 32. + name: Div32 + value: 5 + - description: MCO2 divided by 64. + name: Div64 + value: 6 + - description: MCO2 divided by 128. + name: Div128 + value: 7 +enum/MCOSEL: + bit_size: 4 + variants: + - description: MCO output disabled, no clock on MCO. + name: DISABLE + value: 0 + - description: SYSCLK system clock selected. + name: SYS + value: 1 + - description: MSIS clock selected. + name: MSIS + value: 2 + - description: HSI16 clock selected. + name: HSI16 + value: 3 + - description: HSE clock selected. + name: HSE + value: 4 + - description: LSI clock selected. + name: LSI + value: 5 + - description: LSE clock selected. + name: LSE + value: 6 + - description: HSI48 clock selected. + name: HSI48 + value: 7 + - description: MSIK clock selected. + name: MSIK + value: 8 +enum/MSIBIAS: + bit_size: 1 + variants: + - description: MSI bias continuous mode (clock accuracy fast settling time). + name: CONTINUOUS + value: 0 + - description: + MSI bias sampling mode when the device is in Stop 1 or Stop 2 mode, + or when the regulator is in range 2. + name: SAMPLING + value: 1 +enum/MSIHSINDIV: + bit_size: 1 + variants: + - description: + HSE (16 MHz) is used as MSI input clock when PLL mode with high-speed + clock is selected. + name: Div1 + value: 0 + - description: + HSE (32 MHz)/2 is used as MSI input clock when PLL mode with high-speed + clock is selected. + name: Div2 + value: 1 +enum/MSIKDIV: + bit_size: 2 + variants: + - description: MSIRC0/1 is selected for MSIK (range 0 around 96 MHz). + name: Div1 + value: 0 + - description: MSIRC0/2 is selected for MSIK (range 1 around 48 MHz). + name: Div2 + value: 1 + - description: MSIRC0/4 is selected for MSIK (range 2 around 24 MHz). + name: Div4 + value: 2 + - description: MSIRC0/8 is selected for MSIK (range 3 around 12 MHz). + name: Div8 + value: 3 +enum/MSIKDIVS: + bit_size: 2 + variants: + - description: Range 5 around 12 MHz (reset value). + name: RANGE5_12MHZ + value: 1 + - description: Range 6 around 6 MHz. + name: RANGE6_6MHZ + value: 2 + - description: Range 7 around 3 MHz. + name: RANGE7_3MHZ + value: 3 +enum/MSIKSEL: + bit_size: 1 + variants: + - description: MSIRC0 (96 MHz) is selected as source to generate MSIK. + name: MSIRC0_96MHZ + value: 0 + - description: MSIRC1 (24 MHz) is selected as source to generate MSIK. + name: MSIRC1_24MHZ + value: 1 +enum/MSIPLLSEL: + bit_size: 1 + variants: + - description: LSE is used as MSIRC0 input clock when PLL mode is selected. + name: LSE + value: 0 + - description: HSE or HSE/2 is used as MSIRC0 input clock when PLL mode is selected. + name: HSE + value: 1 +enum/MSIRGSEL: + bit_size: 1 + variants: + - description: MSIS/MSIK ranges provided by MSISDIVS[1:0] and MSIKDIVS[1:0] in RCC_CSR. + name: RCC_CSR + value: 0 + - description: MSIS/MSIK ranges provided by MSISDIV[1:0] and MSIKDIV[1:0] in RCC_ICSCR1. + name: RCC_ICSCR1 + value: 1 +enum/MSISDIV: + bit_size: 2 + variants: + - description: MSIRC0/1 is selected for MSIS (range 0 around 96 MHz). + name: Div1 + value: 0 + - description: MSIRC0/2 is selected for MSIS (range 1 around 48 MHz). + name: Div2 + value: 1 + - description: MSIRC0/4 is selected for MSIS (range 2 around 24 MHz). + name: Div4 + value: 2 + - description: MSIRC0/8 is selected for MSIS (range 3 around 12 MHz). + name: Div8 + value: 3 +enum/MSISDIVS: + bit_size: 2 + variants: + - description: Range 5 around 12 MHz (reset value). + name: RANGE5_12MHZ + value: 1 + - description: Range 6 around 6 MHz. + name: RANGE6_6MHZ + value: 2 + - description: Range 7 around 3 MHz. + name: RANGE7_3MHZ + value: 3 +enum/MSISSEL: + bit_size: 1 + variants: + - description: MSIRC0 (96 MHz) is selected as source to generate MSIS. + name: MSIRC0_96MHZ + value: 0 + - description: MSIRC1 (24 MHz) is selected as source to generate MSIS. + name: MSIRC1_24MHZ + value: 1 +enum/OCTOSPISEL: + bit_size: 1 + variants: + - description: SYSCLK selected. + name: SYS + value: 0 + - description: MSIK selected. + name: MSIK + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - description: PCLK1 = HCLK not divided. + name: Div1 + value: 0 + - description: PCLK1 = HCLK divided by 2. + name: Div2 + value: 4 + - description: PCLK1 = HCLK divided by 4. + name: Div4 + value: 5 + - description: PCLK1 = HCLK divided by 8. + name: Div8 + value: 6 + - description: PCLK1 = HCLK divided by 16. + name: Div16 + value: 7 +enum/SECURITY: + bit_size: 1 + variants: + - description: Nonsecure. + name: NON_SECURE + value: 0 + - description: Secure. + name: SECURE + value: 1 +enum/RNGSEL: + bit_size: 1 + variants: + - description: HSI48 selected. + name: HSI48 + value: 0 + - description: MSIK selected. + name: MSIK + value: 1 +enum/RTCSEL: + bit_size: 2 + variants: + - description: No clock selected. + name: DISABLE + value: 0 + - description: LSE selected. + name: LSE + value: 1 + - description: LSI selected. + name: LSI + value: 2 + - description: HSE/32 selected. + name: HSE + value: 3 +enum/SAISEL: + bit_size: 2 + variants: + - description: MSIK selected. + name: MSIK + value: 0 + - description: input pin AUDIOCLK selected. + name: AUDIOCLK + value: 1 + - description: HSE clock selected. + name: HSE + value: 2 +enum/SPISEL: + bit_size: 1 + variants: + - description: PCLK2 selected. + name: PCLK2 + value: 0 + - description: MSIK selected. + name: MSIK + value: 1 +enum/SPI2SEL: + bit_size: 1 + variants: + - description: PCLK1 selected. + name: PCLK1 + value: 0 + - description: MSIK selected. + name: MSIK + value: 1 +enum/SPI3SEL: + bit_size: 1 + variants: + - description: PCLK1 selected. + name: PCLK1 + value: 0 + - description: MSIK selected. + name: MSIK + value: 1 +enum/STOPWUCK: + bit_size: 1 + variants: + - description: + MSIS oscillator selected as wake-up from stop clock and CSS backup + clock. + name: MSIS + value: 0 + - description: + HSI16 oscillator selected as wake-up from stop clock and CSS backup + clock. + name: HSI16 + value: 1 +enum/SW: + bit_size: 2 + variants: + - description: MSIS selected as system clock. + name: MSIS + value: 0 + - description: HSI16 selected as system clock. + name: HSI16 + value: 1 + - description: HSE selected as system clock. + name: HSE + value: 2 +enum/SWS: + bit_size: 2 + variants: + - description: MSIS oscillator used as system clock. + name: MSIS + value: 0 + - description: HSI16 oscillator used as system clock. + name: HSI16 + value: 1 + - description: HSE used as system clock. + name: HSE + value: 2 +enum/SYSTICKSEL: + bit_size: 2 + variants: + - description: HCLK/8 selected. + name: HCLK1_DIV_8 + value: 0 + - description: LSI selected. + name: LSI + value: 1 + - description: LSE selected. + name: LSE + value: 2 +enum/TIMICSEL: + bit_size: 3 + variants: + - description: HSI, MSIK and MSIS dividers disabled. + name: DISABLE + value: 0 + - description: + HSI/256, MSIS/1024 and MSIS/4 are generated and can be selected by + TIM16, TIM17, and LPTIM2 as internal input capture. + name: HSI256_MSIS1024_MSIS4 + value: 4 + - description: + HSI/256, MSIS/1024 and MSIK/4 are generated and can be selected by + TIM16, TIM17, and LPTIM2 as internal input capture. + name: HSI256_MSIS1024_MSIK4 + value: 5 + - description: + HSI/256, MSIK/1024 and MSIS/4 are generated and can be selected by + TIM16, TIM17, and LPTIM2 as internal input capture. + name: HSI256_MSIK1024_MSIS4 + value: 6 + - description: + HSI/256, MSIK/1024 and MSIK/4 are generated and can be selected by + TIM16, TIM17, and LPTIM2 as internal input capture. + name: HSI256_MSIK1024_MSIK4 + value: 7 +enum/UARTSEL: + bit_size: 1 + variants: + - description: PCLK1 selected. + name: PCLK1 + value: 0 + - description: HSI16 selected. + name: HSI + value: 1 +enum/USARTSEL: + bit_size: 1 + variants: + - description: PCLK2 selected. + name: PCLK2 + value: 0 + - description: HSI16 selected. + name: HSI + value: 1 +enum/USART3SEL: + bit_size: 1 + variants: + - description: PCLK1 selected. + name: PCLK1 + value: 0 + - description: HSI16 selected. + name: HSI + value: 1 +fieldset/AHB1ENR1: + description: RCC AHB1 peripheral clock enable register 1. + fields: + - bit_offset: 0 + bit_size: 1 + description: GPDMA1 clock enable. + name: GPDMA1EN + - bit_offset: 3 + bit_size: 1 + description: ADF1 clock enable. + name: ADF1EN + - bit_offset: 8 + bit_size: 1 + description: FLASH clock enable. + name: FLASHEN + - bit_offset: 12 + bit_size: 1 + description: CRC clock enable. + name: CRCEN + - bit_offset: 16 + bit_size: 1 + description: Touch sensing controller clock enable. + name: TSCEN + - bit_offset: 17 + bit_size: 1 + description: RAMCFG clock enable. + name: RAMCFGEN + - bit_offset: 24 + bit_size: 1 + description: GTZC1 clock enable. + name: GTZC1EN + - bit_offset: 31 + bit_size: 1 + description: SRAM1 clock enable. + name: SRAM1EN +fieldset/AHB1ENR2: + description: RCC AHB1 peripheral clock enable register 2. + fields: + - bit_offset: 2 + bit_size: 1 + description: PWR clock enable. + name: PWREN +fieldset/AHB1RSTR1: + description: RCC AHB1 peripheral reset register 1. + fields: + - bit_offset: 0 + bit_size: 1 + description: GPDMA1 reset. + name: GPDMA1RST + - bit_offset: 3 + bit_size: 1 + description: ADF1 reset. + name: ADF1RST + - bit_offset: 12 + bit_size: 1 + description: CRC reset. + name: CRCRST + - bit_offset: 16 + bit_size: 1 + description: TSC reset. + name: TSCRST + - bit_offset: 17 + bit_size: 1 + description: RAMCFG reset. + name: RAMCFGRST +fieldset/AHB1SLPENR1: + description: RCC AHB1 peripheral clock enable in Sleep mode register. + fields: + - bit_offset: 0 + bit_size: 1 + description: GPDMA1 clock enable during Sleep mode. + name: GPDMA1SLPEN + - bit_offset: 3 + bit_size: 1 + description: ADF1 clock enable during Sleep mode. + name: ADF1SLPEN + - bit_offset: 8 + bit_size: 1 + description: FLASH clock enable during Sleep mode. + name: FLASHSLPEN + - bit_offset: 12 + bit_size: 1 + description: CRC clock enable during Sleep mode. + name: CRCSLPEN + - bit_offset: 16 + bit_size: 1 + description: TSC clock enable during Sleep mode. + name: TSCSLPEN + - bit_offset: 17 + bit_size: 1 + description: RAMCFG clock enable during Sleep mode. + name: RAMCFGSLPEN + - bit_offset: 24 + bit_size: 1 + description: GTZC1 clock enable during Sleep mode. + name: GTZC1SLPEN + - bit_offset: 29 + bit_size: 1 + description: ICACHE clock enable during Sleep mode. + name: ICACHESLPEN + - bit_offset: 31 + bit_size: 1 + description: SRAM1 clock enable during Sleep mode. + name: SRAM1SLPEN +fieldset/AHB1SLPENR2: + description: RCC AHB1 peripheral clock enable in Sleep mode register 2. + fields: + - bit_offset: 2 + bit_size: 1 + description: PWR clock enable during Sleep mode. + name: PWRSLPEN +fieldset/AHB1STPENR1: + description: RCC AHB1 peripheral clock enable in Stop mode register. + fields: + - bit_offset: 0 + bit_size: 1 + description: GPDMA1 clock enable during Stop mode. + name: GPDMA1STPEN + - bit_offset: 3 + bit_size: 1 + description: ADF1 clock enable during Stop mode. + name: ADF1STPEN + - bit_offset: 8 + bit_size: 1 + description: FLASH clock enable during Stop mode. + name: FLASHSTPEN + - bit_offset: 17 + bit_size: 1 + description: RAMCFG clock enable during Stop mode. + name: RAMCFGSTPEN + - bit_offset: 24 + bit_size: 1 + description: GTZC1 clock enable during Stop mode. + name: GTZC1STPEN + - bit_offset: 31 + bit_size: 1 + description: SRAM1 clock enable during Stop mode. + name: SRAM1STPEN +fieldset/AHB2ENR1: + description: RCC AHB2 peripheral clock enable register 1. + fields: + - bit_offset: 0 + bit_size: 1 + description: I/O port i clock enable (i = E to A). + name: GPIOAEN + - bit_offset: 1 + bit_size: 1 + description: I/O port i clock enable (i = E to A). + name: GPIOBEN + - bit_offset: 2 + bit_size: 1 + description: I/O port i clock enable (i = E to A). + name: GPIOCEN + - bit_offset: 3 + bit_size: 1 + description: I/O port i clock enable (i = E to A). + name: GPIODEN + - bit_offset: 4 + bit_size: 1 + description: I/O port i clock enable (i = E to A). + name: GPIOEEN + - bit_offset: 6 + bit_size: 1 + description: I/O port i clock enable (i = H to G). + name: GPIOGEN + - bit_offset: 7 + bit_size: 1 + description: I/O port i clock enable (i = H to G). + name: GPIOHEN + - bit_offset: 10 + bit_size: 1 + description: ADC12 clock enable. + name: ADC12EN + - bit_offset: 11 + bit_size: 1 + description: DAC1 clock enable. + name: DAC1EN + - bit_offset: 16 + bit_size: 1 + description: AES clock enable. + name: AESEN + - bit_offset: 17 + bit_size: 1 + description: HASH clock enable. + name: HASHEN + - bit_offset: 18 + bit_size: 1 + description: RNG clock enable. + name: RNGEN + - bit_offset: 19 + bit_size: 1 + description: PKA clock enable. + name: PKAEN + - bit_offset: 20 + bit_size: 1 + description: SAES clock enable. + name: SAESEN + - bit_offset: 21 + bit_size: 1 + description: CCB clock enable. + name: CCBEN + - bit_offset: 27 + bit_size: 1 + description: SDMMC1 clock enable. + name: SDMMC1EN + - bit_offset: 30 + bit_size: 1 + description: SRAM2 clock enable. + name: SRAM2EN +fieldset/AHB2ENR2: + description: RCC AHB2 peripheral clock enable register 2. + fields: + - bit_offset: 4 + bit_size: 1 + description: OCTOSPI1 clock enable. + name: OCTOSPI1EN +fieldset/AHB2RSTR1: + description: RCC AHB2 peripheral reset register 1. + fields: + - bit_offset: 0 + bit_size: 1 + description: I/O port i reset (i = E to A). + name: GPIOARST + - bit_offset: 1 + bit_size: 1 + description: I/O port i reset (i = E to A). + name: GPIOBRST + - bit_offset: 2 + bit_size: 1 + description: I/O port i reset (i = E to A). + name: GPIOCRST + - bit_offset: 3 + bit_size: 1 + description: I/O port i reset (i = E to A). + name: GPIODRST + - bit_offset: 4 + bit_size: 1 + description: I/O port i reset (i = E to A). + name: GPIOERST + - bit_offset: 6 + bit_size: 1 + description: I/O port i reset (i = H to G). + name: GPIOGRST + - bit_offset: 7 + bit_size: 1 + description: I/O port i reset (i = H to G). + name: GPIOHRST + - bit_offset: 10 + bit_size: 1 + description: ADC12 reset. + name: ADC12RST + - bit_offset: 11 + bit_size: 1 + description: DAC1 reset. + name: DAC1RST + - bit_offset: 16 + bit_size: 1 + description: AES hardware accelerator reset. + name: AESRST + - bit_offset: 17 + bit_size: 1 + description: HASH reset. + name: HASHRST + - bit_offset: 18 + bit_size: 1 + description: Random number generator reset. + name: RNGRST + - bit_offset: 19 + bit_size: 1 + description: PKA reset. + name: PKARST + - bit_offset: 20 + bit_size: 1 + description: SAES hardware accelerator reset. + name: SAESRST + - bit_offset: 21 + bit_size: 1 + description: CCB reset. + name: CCBRST + - bit_offset: 27 + bit_size: 1 + description: SDMMC1 reset. + name: SDMMC1RST +fieldset/AHB2RSTR2: + description: RCC AHB2 peripheral reset register 2. + fields: + - bit_offset: 4 + bit_size: 1 + description: OCTOSPI1 reset. + name: OCTOSPI1RST +fieldset/AHB2SLPENR1: + description: RCC AHB2 peripheral clock enable in Sleep mode register 1. + fields: + - bit_offset: 0 + bit_size: 1 + description: I/O port i clock enable during Sleep mode (i = E to A). + name: GPIOASLPEN + - bit_offset: 1 + bit_size: 1 + description: I/O port i clock enable during Sleep mode (i = E to A). + name: GPIOBSLPEN + - bit_offset: 2 + bit_size: 1 + description: I/O port i clock enable during Sleep mode (i = E to A). + name: GPIOCSLPEN + - bit_offset: 3 + bit_size: 1 + description: I/O port i clock enable during Sleep mode (i = E to A). + name: GPIODSLPEN + - bit_offset: 4 + bit_size: 1 + description: I/O port i clock enable during Sleep mode (i = E to A). + name: GPIOESLPEN + - bit_offset: 6 + bit_size: 1 + description: I/O port i clock enable during Sleep mode (i = H to G). + name: GPIOGSLPEN + - bit_offset: 7 + bit_size: 1 + description: I/O port i clock enable during Sleep mode (i = H to G). + name: GPIOHSLPEN + - bit_offset: 10 + bit_size: 1 + description: ADC12 clock enable during Sleep mode. + name: ADC12SLPEN + - bit_offset: 11 + bit_size: 1 + description: DAC1 clock enable during Sleep mode. + name: DAC1SLPEN + - bit_offset: 16 + bit_size: 1 + description: AES clock enable during Sleep mode. + name: AESSLPEN + - bit_offset: 17 + bit_size: 1 + description: HASH clock enable during Sleep mode. + name: HASHSLPEN + - bit_offset: 18 + bit_size: 1 + description: RNG clock enable during Sleep mode. + name: RNGSLPEN + - bit_offset: 19 + bit_size: 1 + description: PKA clock enable during Sleep mode. + name: PKASLPEN + - bit_offset: 20 + bit_size: 1 + description: SAES accelerator clock enable during Sleep mode. + name: SAESSLPEN + - bit_offset: 21 + bit_size: 1 + description: CCB accelerator clock enable during Sleep mode. + name: CCBSLPEN + - bit_offset: 27 + bit_size: 1 + description: SDMMC1 clock enable during Sleep mode. + name: SDMMC1SLPEN + - bit_offset: 30 + bit_size: 1 + description: SRAM2 clock enable during Sleep mode. + name: SRAM2SLPEN +fieldset/AHB2SLPENR2: + description: RCC AHB2 peripheral clock enable in Sleep mode register 2. + fields: + - bit_offset: 4 + bit_size: 1 + description: OCTOSPI1 clock enable during Sleep mode. + name: OCTOSPI1SLPEN +fieldset/AHB2STPENR1: + description: RCC AHB2 peripheral clock enable in Stop mode register 1. + fields: + - bit_offset: 0 + bit_size: 1 + description: I/O port i clock enable during Stop mode (i = E to A). + name: GPIOASTPEN + - bit_offset: 1 + bit_size: 1 + description: I/O port i clock enable during Stop mode (i = E to A). + name: GPIOBSTPEN + - bit_offset: 2 + bit_size: 1 + description: I/O port i clock enable during Stop mode (i = E to A). + name: GPIOCSTPEN + - bit_offset: 3 + bit_size: 1 + description: I/O port i clock enable during Stop mode (i = E to A). + name: GPIODSTPEN + - bit_offset: 4 + bit_size: 1 + description: I/O port i clock enable during Stop mode (i = E to A). + name: GPIOESTPEN + - bit_offset: 6 + bit_size: 1 + description: I/O port i clock enable during Stop mode (i = H to G). + name: GPIOGSTPEN + - bit_offset: 7 + bit_size: 1 + description: I/O port i clock enable during Stop mode (i = H to G). + name: GPIOHSTPEN + - bit_offset: 11 + bit_size: 1 + description: DAC1 clock enable during Stop mode. + name: DAC1STPEN + - bit_offset: 30 + bit_size: 1 + description: SRAM2 clock enable during Stop mode. + name: SRAM2STPEN +fieldset/APB1ENR1: + description: RCC APB1 peripheral clock enable register 1. + fields: + - bit_offset: 0 + bit_size: 1 + description: TIMj clock enable. + name: TIM2EN + - bit_offset: 1 + bit_size: 1 + description: TIMj clock enable. + name: TIM3EN + - bit_offset: 2 + bit_size: 1 + description: TIMj clock enable. + name: TIM4EN + - bit_offset: 4 + bit_size: 1 + description: TIMj clock enable. + name: TIM6EN + - bit_offset: 5 + bit_size: 1 + description: TIMj clock enable. + name: TIM7EN + - bit_offset: 8 + bit_size: 1 + description: SPI3 clock enable. + name: SPI3EN + - bit_offset: 11 + bit_size: 1 + description: WWDG clock enable. + name: WWDGEN + - bit_offset: 14 + bit_size: 1 + description: SPI2 clock enable. + name: SPI2EN + - bit_offset: 18 + bit_size: 1 + description: USART3 clock enable. + name: USART3EN + - bit_offset: 19 + bit_size: 1 + description: UART4 clock enable. + name: UART4EN + - bit_offset: 20 + bit_size: 1 + description: UART5 clock enable. + name: UART5EN + - bit_offset: 21 + bit_size: 1 + description: I2C1 clock enable. + name: I2C1EN + - bit_offset: 22 + bit_size: 1 + description: I2C2 clock enable. + name: I2C2EN + - bit_offset: 23 + bit_size: 1 + description: I3C1 clock enable. + name: I3C1EN + - bit_offset: 24 + bit_size: 1 + description: CRS clock enable. + name: CRSEN + - bit_offset: 28 + bit_size: 1 + description: OPAMP clock enable. + name: OPAMPEN + - bit_offset: 29 + bit_size: 1 + description: VREFBUF clock enable. + name: VREFEN + - bit_offset: 30 + bit_size: 1 + description: RTC and TAMP APB clock enable. + name: RTCAPBEN +fieldset/APB1ENR2: + description: RCC APB1 peripheral clock enable register 2. + fields: + - bit_offset: 5 + bit_size: 1 + description: LPTIM2 clock enable. + name: LPTIM2EN + - bit_offset: 9 + bit_size: 1 + description: FDCAN1 clock enable. + name: FDCAN1EN +fieldset/APB1RSTR1: + description: RCC APB1 peripheral reset register 1. + fields: + - bit_offset: 0 + bit_size: 1 + description: TIMj reset. + name: TIM2RST + - bit_offset: 1 + bit_size: 1 + description: TIMj reset. + name: TIM3RST + - bit_offset: 2 + bit_size: 1 + description: TIMj reset. + name: TIM4RST + - bit_offset: 4 + bit_size: 1 + description: TIMj reset. + name: TIM6RST + - bit_offset: 5 + bit_size: 1 + description: TIMj reset. + name: TIM7RST + - bit_offset: 8 + bit_size: 1 + description: SPI3 reset. + name: SPI3RST + - bit_offset: 14 + bit_size: 1 + description: SPI2 reset. + name: SPI2RST + - bit_offset: 18 + bit_size: 1 + description: USART3 reset. + name: USART3RST + - bit_offset: 19 + bit_size: 1 + description: UART4 reset. + name: UART4RST + - bit_offset: 20 + bit_size: 1 + description: UART5 reset. + name: UART5RST + - bit_offset: 21 + bit_size: 1 + description: I2C1 reset. + name: I2C1RST + - bit_offset: 22 + bit_size: 1 + description: I2C2 reset. + name: I2C2RST + - bit_offset: 23 + bit_size: 1 + description: I3C1 reset. + name: I3C1RST + - bit_offset: 24 + bit_size: 1 + description: CRS reset. + name: CRSRST + - bit_offset: 28 + bit_size: 1 + description: OPAMP reset. + name: OPAMPRST + - bit_offset: 29 + bit_size: 1 + description: VREFBUF reset. + name: VREFRST +fieldset/APB1RSTR2: + description: RCC APB1 peripheral reset register 2. + fields: + - bit_offset: 5 + bit_size: 1 + description: LPTIM2 reset. + name: LPTIM2RST + - bit_offset: 9 + bit_size: 1 + description: FDCAN1 reset. + name: FDCAN1RST +fieldset/APB1SLPENR1: + description: RCC APB1 peripheral clock enable in Sleep mode register 1. + fields: + - bit_offset: 0 + bit_size: 1 + description: TIMj clock enable during Sleep mode. + name: TIM2SLPEN + - bit_offset: 1 + bit_size: 1 + description: TIMj clock enable during Sleep mode. + name: TIM3SLPEN + - bit_offset: 2 + bit_size: 1 + description: TIMj clock enable during Sleep mode. + name: TIM4SLPEN + - bit_offset: 4 + bit_size: 1 + description: TIMj clock enable during Sleep mode. + name: TIM6SLPEN + - bit_offset: 5 + bit_size: 1 + description: TIMj clock enable during Sleep mode. + name: TIM7SLPEN + - bit_offset: 8 + bit_size: 1 + description: SPI3 clock enable during Sleep mode. + name: SPI3SLPEN + - bit_offset: 11 + bit_size: 1 + description: WWDG clock enable during Sleep mode. + name: WWDGSLPEN + - bit_offset: 14 + bit_size: 1 + description: SPI2 clock enable during Sleep mode. + name: SPI2SLPEN + - bit_offset: 18 + bit_size: 1 + description: USART3 clock enable during Sleep mode. + name: USART3SLPEN + - bit_offset: 19 + bit_size: 1 + description: UART4 clock enable during Sleep mode. + name: UART4SLPEN + - bit_offset: 20 + bit_size: 1 + description: UART5 clock enable during Sleep mode. + name: UART5SLPEN + - bit_offset: 21 + bit_size: 1 + description: I2C1 clock enable during Sleep mode. + name: I2C1SLPEN + - bit_offset: 22 + bit_size: 1 + description: I2C2 clock enable during Sleep mode. + name: I2C2SLPEN + - bit_offset: 23 + bit_size: 1 + description: I3C1 clock enable during Sleep mode. + name: I3C1SLPEN + - bit_offset: 24 + bit_size: 1 + description: CRS clock enable during Sleep mode. + name: CRSSLPEN + - bit_offset: 28 + bit_size: 1 + description: OPAMP clock enable during Sleep mode. + name: OPAMPSLPEN + - bit_offset: 29 + bit_size: 1 + description: VREFBUF clock enable during Sleep mode. + name: VREFSLPEN + - bit_offset: 30 + bit_size: 1 + description: RTC and TAMP APB clock enable during Sleep mode. + name: RTCAPBSLPEN +fieldset/APB1SLPENR2: + description: RCC APB1 peripheral clock enable in Sleep mode register 2. + fields: + - bit_offset: 5 + bit_size: 1 + description: LPTIM2 clock enable during Sleep mode. + name: LPTIM2SLPEN + - bit_offset: 9 + bit_size: 1 + description: FDCAN1 clock enable during Sleep mode. + name: FDCAN1SLPEN +fieldset/APB1STPENR1: + description: RCC APB1 peripheral clock enable in Stop mode register 1. + fields: + - bit_offset: 8 + bit_size: 1 + description: SPI3 clock enable during Stop mode. + name: SPI3STPEN + - bit_offset: 14 + bit_size: 1 + description: SPI2 clock enable during Stop mode. + name: SPI2STPEN + - bit_offset: 18 + bit_size: 1 + description: USART3 clock enable during Stop mode. + name: USART3STPEN + - bit_offset: 19 + bit_size: 1 + description: UART4 clock enable during Stop mode. + name: UART4STPEN + - bit_offset: 20 + bit_size: 1 + description: UART5 clock enable during Stop mode. + name: UART5STPEN + - bit_offset: 21 + bit_size: 1 + description: I2C1 clock enable during Stop mode. + name: I2C1STPEN + - bit_offset: 22 + bit_size: 1 + description: I2C2 clock enable during Stop mode. + name: I2C2STPEN + - bit_offset: 23 + bit_size: 1 + description: I3C1 clock enable during Stop mode. + name: I3C1STPEN + - bit_offset: 28 + bit_size: 1 + description: OPAMP clock enable during Stop mode. + name: OPAMPSTPEN + - bit_offset: 29 + bit_size: 1 + description: VREFBUF clock enable during Stop mode. + name: VREFSTPEN + - bit_offset: 30 + bit_size: 1 + description: RTC and TAMP APB clock enable during Stop mode. + name: RTCAPBSTPEN +fieldset/APB1STPENR2: + description: RCC APB1 peripheral clock enable in Stop mode register 2. + fields: + - bit_offset: 5 + bit_size: 1 + description: LPTIM2 clock enable during Stop mode. + name: LPTIM2STPEN +fieldset/APB2ENR: + description: RCC APB2 peripheral clock enable register. + fields: + - bit_offset: 11 + bit_size: 1 + description: TIM1 clock enable. + name: TIM1EN + - bit_offset: 12 + bit_size: 1 + description: SPI1 clock enable. + name: SPI1EN + - bit_offset: 14 + bit_size: 1 + description: USART1clock enable. + name: USART1EN + - bit_offset: 16 + bit_size: 1 + description: TIMi clock enable. + name: TIM15EN + - bit_offset: 17 + bit_size: 1 + description: TIMi clock enable. + name: TIM16EN + - bit_offset: 18 + bit_size: 1 + description: TIMi clock enable. + name: TIM17EN + - bit_offset: 21 + bit_size: 1 + description: SAI1 clock enable. + name: SAI1EN + - bit_offset: 24 + bit_size: 1 + description: USB1 clock enable. + name: USB1EN + - bit_offset: 27 + bit_size: 1 + description: I3C2 clock enable. + name: I3C2EN +fieldset/APB2RSTR: + description: RCC APB2 peripheral reset register. + fields: + - bit_offset: 11 + bit_size: 1 + description: TIM1 reset. + name: TIM1RST + - bit_offset: 12 + bit_size: 1 + description: SPI1 reset. + name: SPI1RST + - bit_offset: 14 + bit_size: 1 + description: USART1 reset. + name: USART1RST + - bit_offset: 16 + bit_size: 1 + description: TIMi reset. + name: TIM15RST + - bit_offset: 17 + bit_size: 1 + description: TIMi reset. + name: TIM16RST + - bit_offset: 18 + bit_size: 1 + description: TIMi reset. + name: TIM17RST + - bit_offset: 21 + bit_size: 1 + description: SAI1 reset. + name: SAI1RST + - bit_offset: 24 + bit_size: 1 + description: USB1 reset. + name: USB1RST + - bit_offset: 27 + bit_size: 1 + description: I3C2 reset. + name: I3C2RST +fieldset/APB2SLPENR: + description: RCC APB2 peripheral clock enable in Sleep mode register. + fields: + - bit_offset: 11 + bit_size: 1 + description: TIM1 clock enable during Sleep mode. + name: TIM1SLPEN + - bit_offset: 12 + bit_size: 1 + description: SPI1 clock enable during Sleep mode. + name: SPI1SLPEN + - bit_offset: 14 + bit_size: 1 + description: USART1clock enable during Sleep mode. + name: USART1SLPEN + - bit_offset: 16 + bit_size: 1 + description: TIMi clock enable during Sleep mode. + name: TIM15SLPEN + - bit_offset: 17 + bit_size: 1 + description: TIMi clock enable during Sleep mode. + name: TIM16SLPEN + - bit_offset: 18 + bit_size: 1 + description: TIMi clock enable during Sleep mode. + name: TIM17SLPEN + - bit_offset: 21 + bit_size: 1 + description: SAI1 clock enable during Sleep mode. + name: SAI1SLPEN + - bit_offset: 24 + bit_size: 1 + description: USB1 clock enable during Sleep mode. + name: USB1SLPEN + - bit_offset: 27 + bit_size: 1 + description: I3C2 clock enable during Sleep mode. + name: I3C2SLPEN +fieldset/APB2STPENR: + description: RCC APB2 peripheral clock enable in Stop mode register. + fields: + - bit_offset: 12 + bit_size: 1 + description: SPI1 clock enable during Stop mode. + name: SPI1STPEN + - bit_offset: 14 + bit_size: 1 + description: USART1clock enable during Stop mode. + name: USART1STPEN + - bit_offset: 24 + bit_size: 1 + description: USB1 clock enable during Stop mode. + name: USB1STPEN + - bit_offset: 27 + bit_size: 1 + description: I3C2 clock enable during Stop mode. + name: I3C2STPEN +fieldset/APB3ENR: + description: RCC APB3 peripheral clock enable register. + fields: + - bit_offset: 1 + bit_size: 1 + description: SYSCFG clock enable. + name: SYSCFGEN + - bit_offset: 6 + bit_size: 1 + description: LPUART1 clock enable. + name: LPUART1EN + - bit_offset: 7 + bit_size: 1 + description: I2C3 clock enable. + name: I2C3EN + - bit_offset: 11 + bit_size: 1 + description: LPTIM1 clock enable. + name: LPTIM1EN + - bit_offset: 12 + bit_size: 1 + description: LPTIMi clock enable. + name: LPTIM3EN + - bit_offset: 13 + bit_size: 1 + description: LPTIMi clock enable. + name: LPTIM4EN + - bit_offset: 15 + bit_size: 1 + description: COMP clock enable. + name: COMPEN +fieldset/APB3RSTR: + description: RCC APB3 peripheral reset register. + fields: + - bit_offset: 1 + bit_size: 1 + description: SYSCFG reset. + name: SYSCFGRST + - bit_offset: 6 + bit_size: 1 + description: LPUART1 reset. + name: LPUART1RST + - bit_offset: 7 + bit_size: 1 + description: I2C3 reset. + name: I2C3RST + - bit_offset: 11 + bit_size: 1 + description: LPTIM1 reset. + name: LPTIM1RST + - bit_offset: 12 + bit_size: 1 + description: LPTIMi reset. + name: LPTIM3RST + - bit_offset: 13 + bit_size: 1 + description: LPTIMi reset. + name: LPTIM4RST + - bit_offset: 15 + bit_size: 1 + description: COMP reset. + name: COMPRST +fieldset/APB3SLPENR: + description: RCC APB3 peripheral clock enable in Sleep mode register. + fields: + - bit_offset: 1 + bit_size: 1 + description: SYSCFG clock enable during Sleep mode. + name: SYSCFGSLPEN + - bit_offset: 6 + bit_size: 1 + description: LPUART1 clock enable during Sleep mode. + name: LPUART1SLPEN + - bit_offset: 7 + bit_size: 1 + description: I2C3 clock enable during Sleep mode. + name: I2C3SLPEN + - bit_offset: 11 + bit_size: 1 + description: LPTIM1clock enable during Sleep mode. + name: LPTIM1SLPEN + - bit_offset: 12 + bit_size: 1 + description: LPTIMi clock enable during Sleep mode. + name: LPTIM3SLPEN + - bit_offset: 13 + bit_size: 1 + description: LPTIMi clock enable during Sleep mode. + name: LPTIM4SLPEN + - bit_offset: 15 + bit_size: 1 + description: COMP clock enable during Sleep mode. + name: COMPSLPEN +fieldset/APB3STPENR: + description: RCC APB3 peripheral clock enable in Stop mode register. + fields: + - bit_offset: 6 + bit_size: 1 + description: LPUART1 clock enable during Stop mode. + name: LPUART1STPEN + - bit_offset: 7 + bit_size: 1 + description: I2C3 clock enable during Stop mode. + name: I2C3STPEN + - bit_offset: 11 + bit_size: 1 + description: LPTIM1clock enable during Stop mode. + name: LPTIM1STPEN + - bit_offset: 12 + bit_size: 1 + description: LPTIMi clock enable during Stop mode. + name: LPTIM3STPEN + - bit_offset: 13 + bit_size: 1 + description: LPTIMi clock enable during Stop mode. + name: LPTIM4STPEN + - bit_offset: 15 + bit_size: 1 + description: COMP clock enable during Stop mode. + name: COMPSTPEN +fieldset/BDCR: + description: RCC backup domain control register. + fields: + - bit_offset: 0 + bit_size: 1 + description: LSE oscillator enable. + name: LSEON + - bit_offset: 1 + bit_size: 1 + description: LSE oscillator ready. + name: LSERDY + - bit_offset: 2 + bit_size: 1 + description: LSE oscillator bypass. + name: LSEBYP + - bit_offset: 3 + bit_size: 2 + description: LSE oscillator drive capability. + enum: LSEDRV + name: LSEDRV + - bit_offset: 5 + bit_size: 1 + description: CSS on LSE enable. + name: LSECSSON + - bit_offset: 6 + bit_size: 1 + description: CSS on LSE failure detection. + name: LSECSSD + - bit_offset: 7 + bit_size: 1 + description: LSE system clock (LSESYS) enable. + name: LSESYSEN + - bit_offset: 8 + bit_size: 2 + description: RTC and TAMP clock source selection. + enum: RTCSEL + name: RTCSEL + - bit_offset: 11 + bit_size: 1 + description: LSE system clock (LSESYS) ready. + name: LSESYSRDY + - bit_offset: 12 + bit_size: 1 + description: LSE clock glitch filter enable. + name: LSEGFON + - bit_offset: 15 + bit_size: 1 + description: RTC and TAMP clock enable. + name: RTCEN + - bit_offset: 16 + bit_size: 1 + description: Backup domain software reset. + name: BDRST + - bit_offset: 24 + bit_size: 1 + description: Low-speed clock output (LSCO) enable. + name: LSCOEN + - bit_offset: 25 + bit_size: 1 + description: Low-speed clock output selection. + enum: LSCOSEL + name: LSCOSEL +fieldset/CCIPR1: + description: RCC peripheral independent clock configuration register 1. + fields: + - bit_offset: 0 + bit_size: 1 + description: USART1 kernel clock source selection. + enum: USARTSEL + name: USART1SEL + - bit_offset: 2 + bit_size: 1 + description: USART3 kernel clock source selection. + enum: USART3SEL + name: USART3SEL + - bit_offset: 4 + bit_size: 1 + description: UART4 kernel clock source selection. + enum: UARTSEL + name: UART4SEL + - bit_offset: 6 + bit_size: 1 + description: UART5 kernel clock source selection. + enum: UARTSEL + name: UART5SEL + - bit_offset: 8 + bit_size: 1 + description: I3C1 kernel clock source selection. + enum: I3CSEL + name: I3C1SEL + - bit_offset: 10 + bit_size: 1 + description: I2C1 kernel clock source selection. + enum: I2CSEL + name: I2C1SEL + - bit_offset: 12 + bit_size: 1 + description: I2C2 kernel clock source selection. + enum: I2CSEL + name: I2C2SEL + - bit_offset: 14 + bit_size: 1 + description: I3C2 kernel clock source selection. + enum: I3C2SEL + name: I3C2SEL + - bit_offset: 16 + bit_size: 1 + description: SPI2 kernel clock source selection. + enum: SPI2SEL + name: SPI2SEL + - bit_offset: 18 + bit_size: 2 + description: Low-power timer 2 kernel clock source selection. + enum: LPTIMSEL + name: LPTIM2SEL + - bit_offset: 20 + bit_size: 1 + description: SPI1 kernel clock source selection. + enum: SPISEL + name: SPI1SEL + - bit_offset: 22 + bit_size: 2 + description: SysTick clock source selection. + enum: SYSTICKSEL + name: SYSTICKSEL + - bit_offset: 24 + bit_size: 1 + description: FDCAN1 kernel clock source selection. + enum: FDCANSEL + name: FDCAN1SEL + - bit_offset: 26 + bit_size: 2 + description: Intermediate clock source selection. + enum: ICLKSEL + name: ICLKSEL + - bit_offset: 28 + bit_size: 1 + description: USB1 kernel clock prescaler selection. + name: USB1SEL + - bit_offset: 29 + bit_size: 3 + description: Clock sources for TIM16,TIM17, and LPTIM2 internal input capture. + enum: TIMICSEL + name: TIMICSEL +fieldset/CCIPR2: + description: RCC peripheral independent clock configuration register 2. + fields: + - bit_offset: 0 + bit_size: 2 + description: ADF1 kernel clock source selection. + enum: ADFSEL + name: ADF1SEL + - bit_offset: 3 + bit_size: 1 + description: SPI3 kernel clock source selection. + enum: SPI3SEL + name: SPI3SEL + - bit_offset: 5 + bit_size: 2 + description: SAI1 kernel clock source selection. + enum: SAISEL + name: SAI1SEL + - bit_offset: 11 + bit_size: 1 + description: RNG kernel clock source selection. + enum: RNGSEL + name: RNGSEL + - bit_offset: 12 + bit_size: 4 + description: ADC12 and DAC1 kernel clock prescaler. + enum: ADCDACPRE + name: ADCDACPRE + - bit_offset: 16 + bit_size: 2 + description: ADC12 and DAC1 intermediate kernel clock source selection. + enum: ADCDACSEL + name: ADCDACSEL + - bit_offset: 19 + bit_size: 1 + description: DAC1 sample and hold clock source selection. + enum: DACSHSEL + name: DAC1SHSEL + - bit_offset: 20 + bit_size: 1 + description: OCTOSPI1 kernel clock source selection. + enum: OCTOSPISEL + name: OCTOSPISEL +fieldset/CCIPR3: + description: RCC peripheral independent clock configuration register 3. + fields: + - bit_offset: 0 + bit_size: 2 + description: LPUART1 kernel clock source selection. + enum: LPUARTSEL + name: LPUART1SEL + - bit_offset: 6 + bit_size: 1 + description: I2C3 kernel clock source selection. + enum: I2C3SEL + name: I2C3SEL + - bit_offset: 8 + bit_size: 2 + description: LPTIM3 and LPTIM4 kernel clock source selection. + enum: LPTIMSEL + name: LPTIM34SEL + - bit_offset: 10 + bit_size: 2 + description: LPTIM1 kernel clock source selection. + enum: LPTIMSEL + name: LPTIM1SEL +fieldset/CFGR1: + description: RCC clock configuration register 1. + fields: + - bit_offset: 0 + bit_size: 2 + description: System clock switch. + enum: SW + name: SW + - bit_offset: 2 + bit_size: 2 + description: System clock switch status. + enum: SWS + name: SWS + - bit_offset: 4 + bit_size: 1 + description: Wake-up from Stop and CSS backup clock selection. + enum: STOPWUCK + name: STOPWUCK + - bit_offset: 5 + bit_size: 1 + description: Wake-up from Stop kernel clock automatic enable selection. + name: STOPKERWUCK + - bit_offset: 16 + bit_size: 4 + description: Microcontroller clock output 2. + enum: MCO2SEL + name: MCO2SEL + - bit_offset: 20 + bit_size: 3 + description: Microcontroller clock output 2 prescaler. + enum: MCOPRE + name: MCO2PRE + - bit_offset: 24 + bit_size: 4 + description: Microcontroller clock output. + enum: MCOSEL + name: MCOSEL + - bit_offset: 28 + bit_size: 3 + description: Microcontroller clock output prescaler. + enum: MCOPRE + name: MCOPRE +fieldset/CFGR2: + description: RCC clock configuration register 2. + fields: + - bit_offset: 0 + bit_size: 4 + description: AHB prescaler. + enum: HPRE + name: HPRE + - bit_offset: 4 + bit_size: 3 + description: APB1 prescaler. + enum: PPRE + name: PPRE1 + - bit_offset: 8 + bit_size: 3 + description: APB2 prescaler. + enum: PPRE + name: PPRE2 +fieldset/CFGR3: + description: RCC clock configuration register 3. + fields: + - bit_offset: 4 + bit_size: 3 + description: APB3 prescaler. + enum: PPRE + name: PPRE3 +fieldset/CFGR4: + description: RCC clock configuration register 4. + fields: + - bit_offset: 0 + bit_size: 2 + description: EPOD booster input clock source selection. + enum: BOOSTSEL + name: BOOSTSEL + - bit_offset: 12 + bit_size: 4 + description: EPOD booster input clock prescaler. + enum: BOOSTDIV + name: BOOSTDIV +fieldset/CICR: + description: RCC clock interrupt clear register. + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI ready interrupt clear. + name: LSIRDYC + - bit_offset: 1 + bit_size: 1 + description: LSE ready interrupt clear. + name: LSERDYC + - bit_offset: 2 + bit_size: 1 + description: MSIS ready interrupt clear. + name: MSISRDYC + - bit_offset: 3 + bit_size: 1 + description: HSI16 ready interrupt clear. + name: HSIRDYC + - bit_offset: 4 + bit_size: 1 + description: HSE ready interrupt clear. + name: HSERDYC + - bit_offset: 5 + bit_size: 1 + description: HSI48 ready interrupt clear. + name: HSI48RDYC + - bit_offset: 6 + bit_size: 1 + description: MSIRC1 PLL mode ready interrupt clear. + name: MSIPLL1RDYC + - bit_offset: 7 + bit_size: 1 + description: MSIRC0 PLL mode ready interrupt clear. + name: MSIPLL0RDYC + - bit_offset: 8 + bit_size: 1 + description: MSI PLL mode with LSE unlock interrupt clear. + name: MSIPLLUC + - bit_offset: 9 + bit_size: 1 + description: MSI PLL mode with HSE unlock interrupt clear. + name: MSIPLLHSUC + - bit_offset: 10 + bit_size: 1 + description: Clock security system interrupt clear. + name: CSSC + - bit_offset: 11 + bit_size: 1 + description: MSIK oscillator ready interrupt clear. + name: MSIKRDYC + - bit_offset: 12 + bit_size: 1 + description: LSE CSS interrupt clear. + name: LSECSSC +fieldset/CIER: + description: RCC clock interrupt enable register. + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI ready interrupt enable. + name: LSIRDYIE + - bit_offset: 1 + bit_size: 1 + description: LSE ready interrupt enable. + name: LSERDYIE + - bit_offset: 2 + bit_size: 1 + description: MSIS ready interrupt enable. + name: MSISRDYIE + - bit_offset: 3 + bit_size: 1 + description: HSI16 ready interrupt enable. + name: HSIRDYIE + - bit_offset: 4 + bit_size: 1 + description: HSE ready interrupt enable. + name: HSERDYIE + - bit_offset: 5 + bit_size: 1 + description: HSI48 ready interrupt enable. + name: HSI48RDYIE + - bit_offset: 6 + bit_size: 1 + description: MSIRC1 PLL mode ready interrupt enable. + name: MSIPLL1RDYIE + - bit_offset: 7 + bit_size: 1 + description: MSIRC0 PLL mode ready interrupt enable. + name: MSIPLL0RDYIE + - bit_offset: 8 + bit_size: 1 + description: MSI PLL mode with LSE unlock interrupt enable. + name: MSIPLLUIE + - bit_offset: 9 + bit_size: 1 + description: MSI PLL mode with HSE unlock interrupt enable. + name: MSIPLLHSUIE + - bit_offset: 11 + bit_size: 1 + description: MSIK ready interrupt enable. + name: MSIKRDYIE + - bit_offset: 12 + bit_size: 1 + description: LSE clock security system interrupt enable. + name: LSECSSIE +fieldset/CIFR: + description: RCC clock interrupt flag register. + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI ready interrupt flag. + name: LSIRDYF + - bit_offset: 1 + bit_size: 1 + description: LSE ready interrupt flag. + name: LSERDYF + - bit_offset: 2 + bit_size: 1 + description: MSIS ready interrupt flag. + name: MSISRDYF + - bit_offset: 3 + bit_size: 1 + description: HSI16 ready interrupt flag. + name: HSIRDYF + - bit_offset: 4 + bit_size: 1 + description: HSE ready interrupt flag. + name: HSERDYF + - bit_offset: 5 + bit_size: 1 + description: HSI48 ready interrupt flag. + name: HSI48RDYF + - bit_offset: 6 + bit_size: 1 + description: MSIRC1 PLL mode ready interrupt enable. + name: MSIPLL1RDYF + - bit_offset: 7 + bit_size: 1 + description: MSIRC0 PLL mode ready interrupt flag. + name: MSIPLL0RDYF + - bit_offset: 8 + bit_size: 1 + description: MSI PLL mode with LSE unlock interrupt flag. + name: MSIPLLUF + - bit_offset: 9 + bit_size: 1 + description: MSI PLL mode with HSE unlock interrupt flag. + name: MSIPLLHSUF + - bit_offset: 10 + bit_size: 1 + description: Clock security system interrupt flag. + name: CSSF + - bit_offset: 11 + bit_size: 1 + description: MSIK ready interrupt flag. + name: MSIKRDYF + - bit_offset: 12 + bit_size: 1 + description: LSE clock security system interrupt flag. + name: LSECSSF +fieldset/CR: + description: RCC clock control register. + fields: + - bit_offset: 0 + bit_size: 1 + description: MSIS clock enable. + name: MSISON + - bit_offset: 1 + bit_size: 1 + description: MSI enable for some peripheral kernels. + name: MSIKERON + - bit_offset: 2 + bit_size: 1 + description: MSIS clock ready flag. + name: MSISRDY + - bit_offset: 3 + bit_size: 1 + description: MSIK clock enable. + name: MSIKON + - bit_offset: 4 + bit_size: 1 + description: MSIK clock ready flag. + name: MSIKRDY + - bit_offset: 5 + bit_size: 1 + description: MSIRC1 PLL mode enable. + name: MSIPLL1EN + - bit_offset: 6 + bit_size: 1 + description: MSIRC0 PLL mode enable. + name: MSIPLL0EN + - bit_offset: 7 + bit_size: 1 + description: MSIRC1 PLL mode fast startup. + name: MSIPLL1FAST + - bit_offset: 8 + bit_size: 1 + description: MSIRC0 PLL mode fast startup. + name: MSIPLL0FAST + - bit_offset: 9 + bit_size: 1 + description: MSIRC1 PLL mode ready flag. + name: MSIPLL1RDY + - bit_offset: 10 + bit_size: 1 + description: MSIRC0 PLL mode ready flag. + name: MSIPLL0RDY + - bit_offset: 11 + bit_size: 1 + description: HSI16 clock enable. + name: HSION + - bit_offset: 12 + bit_size: 1 + description: HSI16 enable for some peripheral kernels. + name: HSIKERON + - bit_offset: 13 + bit_size: 1 + description: HSI16 clock ready flag. + name: HSIRDY + - bit_offset: 14 + bit_size: 1 + description: HSI48 clock enable. + name: HSI48ON + - bit_offset: 15 + bit_size: 1 + description: HSI48 clock ready flag. + name: HSI48RDY + - bit_offset: 16 + bit_size: 1 + description: HSE clock enable. + name: HSEON + - bit_offset: 17 + bit_size: 1 + description: HSE clock ready flag. + name: HSERDY + - bit_offset: 18 + bit_size: 1 + description: HSE crystal oscillator bypass. + name: HSEBYP + - bit_offset: 19 + bit_size: 1 + description: Clock security system enable. + name: HSECSSON + - bit_offset: 20 + bit_size: 1 + description: HSE external clock bypass mode. + enum: HSEEXT + name: HSEEXT +fieldset/CRRCR: + description: RCC clock recovery RC register. + fields: + - bit_offset: 0 + bit_size: 9 + description: HSI48 clock calibration. + name: HSI48CAL +fieldset/CSR: + description: RCC control/status register. + fields: + - name: LSION + description: LSI oscillator enable. + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: LSI oscillator ready. + bit_offset: 1 + bit_size: 1 + - name: LSIPREDIV + description: Low-speed clock divider configuration. + bit_offset: 2 + bit_size: 1 + enum: LSIPREDIV + - name: MSIKDIVS + description: MSIK oscillator division after Standby mode. + bit_offset: 8 + bit_size: 2 + enum: MSIKDIVS + - name: MSISDIVS + description: MSIS oscillator division after Standby mode. + bit_offset: 12 + bit_size: 2 + enum: MSISDIVS + - name: RMVF + description: Remove reset flag. + bit_offset: 23 + bit_size: 1 + - name: OBLRSTF + description: Option-byte loader reset flag. + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: NRST pin reset flag. + bit_offset: 26 + bit_size: 1 + - name: BORRSTF + description: BOR flag. + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag. + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent watchdog reset flag. + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag. + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag. + bit_offset: 31 + bit_size: 1 +fieldset/ICSCR1: + description: RCC internal clock source calibration register 1. + fields: + - name: MSICAL1 + description: MSIRC1 clock calibration for MSI ranges 4 to 7. + bit_offset: 0 + bit_size: 6 + - name: MSICAL0 + description: MSIRC0 clock calibration for MSI ranges 0 to 3. + bit_offset: 6 + bit_size: 6 + - name: MSIHSINDIV + description: MSIRCx (x = 0, 1) PLL mode HSE input division. + bit_offset: 19 + bit_size: 1 + enum: MSIHSINDIV + - name: MSIPLL1SEL + description: MSIRC1 PLL mode input clock selection. + bit_offset: 20 + bit_size: 1 + enum: MSIPLLSEL + - name: MSIPLL0SEL + description: MSIRC0 PLL mode input clock selection. + bit_offset: 21 + bit_size: 1 + enum: MSIPLLSEL + - name: MSIBIAS + description: MSI bias mode selection. + bit_offset: 22 + bit_size: 1 + enum: MSIBIAS + - name: MSIRGSEL + description: MSI clock range selection. + bit_offset: 23 + bit_size: 1 + enum: MSIRGSEL + - name: MSIPLL1N + description: MSIRC1 PLL mode with LSE multiplication factor. + bit_offset: 24 + bit_size: 2 + - name: MSIKDIV + description: MSIK oscillator division. + bit_offset: 26 + bit_size: 2 + enum: MSIKDIV + - name: MSIKSEL + description: MSIK clock source selection. + bit_offset: 28 + bit_size: 1 + enum: MSIKSEL + - name: MSISDIV + description: MSIS oscillator division. + bit_offset: 29 + bit_size: 2 + enum: MSISDIV + - name: MSISSEL + description: MSIS clock source selection. + bit_offset: 31 + bit_size: 1 + enum: MSISSEL +fieldset/ICSCR2: + description: RCC internal clock source calibration register 2. + fields: + - name: MSITRIM1 + description: MSIRC1 clock trimming for ranges 4 to 7. + bit_offset: 0 + bit_size: 6 + - name: MSITRIM0 + description: MSIRC0 clock trimming for ranges 0 to 3. + bit_offset: 6 + bit_size: 6 +fieldset/ICSCR3: + description: RCC internal clock source calibration register 3. + fields: + - name: HSICAL + description: HSI clock calibration. + bit_offset: 0 + bit_size: 12 + - name: HSITRIM + description: HSI clock trimming. + bit_offset: 16 + bit_size: 5 +fieldset/PRIVCFGR: + description: RCC privilege configuration register. + fields: + - name: SPRIV + description: RCC secure function privilege configuration. + bit_offset: 0 + bit_size: 1 + enum: SECURITY + - name: NSPRIV + description: RCC nonsecure function privilege configuration. + bit_offset: 1 + bit_size: 1 + enum: SECURITY +fieldset/SECCFGR: + description: RCC secure configuration register. + fields: + - name: HSISEC + description: HSI clock configuration and status bit security. + bit_offset: 0 + bit_size: 1 + enum: SECURITY + - name: HSESEC + description: HSE clock configuration, status bits, and HSE_CSS security. + bit_offset: 1 + bit_size: 1 + enum: SECURITY + - name: MSISEC + description: MSI clock configuration and status bit security. + bit_offset: 2 + bit_size: 1 + enum: SECURITY + - name: LSISEC + description: LSI clock configuration and status bit security. + bit_offset: 3 + bit_size: 1 + enum: SECURITY + - name: LSESEC + description: LSE clock configuration and status bit security. + bit_offset: 4 + bit_size: 1 + enum: SECURITY + - name: SYSCLKSEC + description: + SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration + security. + bit_offset: 5 + bit_size: 1 + enum: SECURITY + - name: PRESCSEC + description: AHBx/APBx prescaler configuration bit security. + bit_offset: 6 + bit_size: 1 + enum: SECURITY + - name: BOOSTSEC + description: EPOD booster configuration bit security. + bit_offset: 7 + bit_size: 1 + enum: SECURITY + - name: ICLKSEC + description: Intermediate clock source selection security. + bit_offset: 10 + bit_size: 1 + enum: SECURITY + - name: HSI48SEC + description: HSI48 clock configuration and status bit security. + bit_offset: 11 + bit_size: 1 + enum: SECURITY + - name: RMVFSEC + description: Remove reset flag security. + bit_offset: 12 + bit_size: 1 + enum: SECURITY diff --git a/data/registers/syscfg_u3.yaml b/data/registers/syscfg_u3.yaml new file mode 100644 index 000000000..e2f42a12a --- /dev/null +++ b/data/registers/syscfg_u3.yaml @@ -0,0 +1,251 @@ +block/SYSCFG: + description: SYSCFG address block description. + items: + - name: SECCFGR + description: SYSCFG secure configuration register. + byte_offset: 0 + fieldset: SECCFGR + - name: CFGR1 + description: SYSCFG configuration register 1. + byte_offset: 4 + fieldset: CFGR1 + - name: FPUIMR + description: SYSCFG FPU interrupt mask register. + byte_offset: 8 + fieldset: FPUIMR + - name: CNSLCKR + description: SYSCFG CPU nonsecure lock register. + byte_offset: 12 + fieldset: CNSLCKR + - name: CSLCKR + description: SYSCFG CPU secure lock register. + byte_offset: 16 + fieldset: CSLCKR + - name: CFGR2 + description: SYSCFG configuration register 2. + byte_offset: 20 + fieldset: CFGR2 + - name: CCCSR + description: SYSCFG compensation cell control/status register. + byte_offset: 28 + fieldset: CCCSR + - name: CCVR + description: SYSCFG compensation cell value register. + byte_offset: 32 + access: Read + fieldset: CCVR + - name: CCCR + description: SYSCFG compensation cell code register. + byte_offset: 36 + fieldset: CCCR + - name: RSSCMDR + description: SYSCFG RSS command register. + byte_offset: 44 + fieldset: RSSCMDR +fieldset/CCCR: + description: SYSCFG compensation cell code register. + fields: + - name: NCC1 + description: NMOS compensation code of the I/Os supplied by Vless thansub>DDless than/sub>. + bit_offset: 0 + bit_size: 4 + - name: PCC1 + description: PMOS compensation code of the I/Os supplied by Vless thansub>DDless than/sub>. + bit_offset: 4 + bit_size: 4 + - name: NCC2 + description: NMOS compensation code of the I/Os supplied by Vless thansub>DDIO2less than/sub>. + bit_offset: 8 + bit_size: 4 + - name: PCC2 + description: PMOS compensation code of the I/Os supplied by Vless thansub>DDIO2less than/sub>. + bit_offset: 12 + bit_size: 4 +fieldset/CCCSR: + description: SYSCFG compensation cell control/status register. + fields: + - name: EN1 + description: VDD I/O compensation cell enable. + bit_offset: 0 + bit_size: 1 + - name: CS1 + description: VDD I/O code selection. + bit_offset: 1 + bit_size: 1 + - name: EN2 + description: VDDIO2 I/O compensation cell enable. + bit_offset: 2 + bit_size: 1 + - name: CS2 + description: VDDIO2 I/O code selection. + bit_offset: 3 + bit_size: 1 + - name: RDY1 + description: VDD I/O compensation cell ready flag. + bit_offset: 8 + bit_size: 1 + - name: RDY2 + description: VDDIO2 I/O compensation cell ready flag. + bit_offset: 9 + bit_size: 1 +fieldset/CCVR: + description: SYSCFG compensation cell value register. + fields: + - name: NCV1 + description: NMOS compensation value of the I/Os supplied by Vless thansub>DDless than/sub>. + bit_offset: 0 + bit_size: 4 + - name: PCV1 + description: PMOS compensation value of the I/Os supplied by Vless thansub>DDless than/sub>. + bit_offset: 4 + bit_size: 4 + - name: NCV2 + description: NMOS compensation value of the I/Os supplied by Vless thansub>DDIO2less than/sub>. + bit_offset: 8 + bit_size: 4 + - name: PCV2 + description: PMOS compensation value of the I/Os supplied by Vless thansub>DDIO2less than/sub>. + bit_offset: 12 + bit_size: 4 +fieldset/CFGR1: + description: SYSCFG configuration register 1. + fields: + - name: IR_POL + description: IR output polarity selection. + bit_offset: 5 + bit_size: 1 + - name: IR_MOD + description: IR modulation envelope signal selection. + bit_offset: 6 + bit_size: 2 + enum: IR_MOD + - name: BOOSTEN + description: I/O analog switch voltage booster enable. + bit_offset: 8 + bit_size: 1 + - name: ANASWVDD + description: GPIO analog switch control voltage selection. + bit_offset: 9 + bit_size: 1 + - name: PB6_FMP + description: Fast-mode Plus driving capability activation on PBi. + bit_offset: 16 + bit_size: 1 + - name: PB7_FMP + description: Fast-mode Plus driving capability activation on PBi. + bit_offset: 17 + bit_size: 1 + - name: PB8_FMP + description: Fast-mode Plus driving capability activation on PBi. + bit_offset: 18 + bit_size: 1 + - name: PB9_FMP + description: Fast-mode Plus driving capability activation on PBi. + bit_offset: 19 + bit_size: 1 +fieldset/CFGR2: + description: SYSCFG configuration register 2. + fields: + - name: CLL + description: Cortex-M33 LOCKUP (HardFault) output enable. + bit_offset: 0 + bit_size: 1 + - name: SPL + description: SRAM2 parity bit. + bit_offset: 1 + bit_size: 1 + - name: PVDL + description: PVD lock enable bit. + bit_offset: 2 + bit_size: 1 + - name: ECCL + description: ECC lock. + bit_offset: 3 + bit_size: 1 +fieldset/CNSLCKR: + description: SYSCFG CPU nonsecure lock register. + fields: + - name: LOCKNSVTOR + description: VTOR_NS register lock. + bit_offset: 0 + bit_size: 1 + - name: LOCKNSMPU + description: Nonsecure MPU registers lock. + bit_offset: 1 + bit_size: 1 +fieldset/CSLCKR: + description: SYSCFG CPU secure lock register. + fields: + - name: LOCKSVTAIRCR + description: VTOR_S register and AIRCR register bits lock. + bit_offset: 0 + bit_size: 1 + - name: LOCKSMPU + description: Secure MPU registers lock. + bit_offset: 1 + bit_size: 1 + - name: LOCKSAU + description: SAU register lock. + bit_offset: 2 + bit_size: 1 +fieldset/FPUIMR: + description: SYSCFG FPU interrupt mask register. + fields: + - name: FPU_IOIE + description: Floating point unit interrupt enable bit-invalid operation. + bit_offset: 0 + bit_size: 1 + - name: FPU_DZIE + description: Floating point unit interrupt enable bit-divide-by-zero. + bit_offset: 1 + bit_size: 1 + - name: FPU_UFIE + description: Floating point unit interrupt enable bit-underflow. + bit_offset: 2 + bit_size: 1 + - name: FPU_OFIE + description: Floating point unit interrupt enable bit-overflow. + bit_offset: 3 + bit_size: 1 + - name: FPU_IDIE + description: Floating point unit interrupt enable bit-input denormal. + bit_offset: 4 + bit_size: 1 + - name: FPU_IxIE + description: Floating point unit interrupt enable bit-inexact. + bit_offset: 5 + bit_size: 1 +fieldset/RSSCMDR: + description: SYSCFG RSS command register. + fields: + - name: RSSCMD + description: RSS commands. + bit_offset: 0 + bit_size: 16 +fieldset/SECCFGR: + description: SYSCFG secure configuration register. + fields: + - name: SYSCFGSEC + description: Security of SYSCFG clock control, memory erase status, and compensation cell registers. + bit_offset: 0 + bit_size: 1 + - name: CLASSBSEC + description: Class B security. + bit_offset: 1 + bit_size: 1 + - name: FPUSEC + description: FPU security. + bit_offset: 3 + bit_size: 1 +enum/IR_MOD: + bit_size: 2 + variants: + - name: TIM16 + description: TIM16. + value: 0 + - name: USART1 + description: USART1. + value: 1 + - name: UART4 + description: UART4. + value: 2 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 50fbe411f..95c347ae2 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -89,6 +89,7 @@ fn chip_name_from_package_name(x: &str) -> String { (regex!("^(STM32L5....).x[PQ]$"), "$1"), (regex!("^(STM32L0....).xS$"), "$1"), (regex!("^(STM32H7....).x[QH]$"), "$1"), + (regex!("^(STM32U3....).x[QG]$"), "$1"), (regex!("^(STM32U5....).xQ$"), "$1"), (regex!("^(STM32H5....).xQ$"), "$1"), (regex!("^(STM32WB0....).x$"), "$1"), @@ -142,8 +143,6 @@ pub fn parse_groups() -> Result<(HashMap, Vec), anyhow: static NOPELIST: RegexSet = RegexSet::new(&[ // Not supported, not planned unless someone wants to do it. "STM32MP.*", - // TODO, PRs welcome :) - "STM32U3.*", // "STM32N6.*", "STM32G41[14].*", "STM32G4.*xZ", diff --git a/stm32-data-gen/src/interrupts.rs b/stm32-data-gen/src/interrupts.rs index 40cf80060..addebf029 100644 --- a/stm32-data-gen/src/interrupts.rs +++ b/stm32-data-gen/src/interrupts.rs @@ -95,6 +95,15 @@ impl ChipInterrupts { if chip_name.starts_with("STM32F100") { header_irqs.remove("DMA2_Channel4_5"); } + // STM32U3 changed the advanced timer IRQ BRK/TRG names + // to include multiple signal names. This change maps + // them back to the common names. + if let Some(num) = header_irqs.remove("TIM1_BRK_TERR_IERR") { + header_irqs.insert("TIM1_BRK".to_string(), num); + } + if let Some(num) = header_irqs.remove("TIM1_TRG_COM_DIR_IDX") { + header_irqs.insert("TIM1_TRG_COM".to_string(), num); + } core.interrupts = header_irqs .iter() .map(|(k, v)| stm32_data_serde::chip::core::Interrupt { @@ -149,7 +158,13 @@ impl ChipInterrupts { } // More typos - let name = name.replace("USAR11", "USART11"); + let name = name + .replace("USAR11", "USART11") + // STM32U3 introduced new naming for advanced timer IRQs + // that differ from the rest of the STM32 family. + // Map them back to the common names. + .replace("TIM1_BRK_TERR_IERR", "TIM1_BRK") + .replace("TIM1_TRG_COM_DIR_IDX", "TIM1_TRG_COM"); trace!(" name={name}"); // Skip interrupts that don't exist. @@ -454,7 +469,7 @@ fn match_peris(peris: &[String], name: &str) -> Vec { ("TEMP", &["TEMPSENS"]), ("DSI", &["DSIHOST"]), ("HRTIM1", &["HRTIM"]), - ("GTZC", &["GTZC_S"]), + ("GTZC", &["GTZC_S", "GTZC_NS"]), ("TZIC", &["GTZC_S"]), ]; @@ -586,7 +601,7 @@ static PICK_NVIC: RegexMap<&str> = RegexMap::new(&[ ("STM32WL5.*:cm4", "NVIC1"), ("STM32WL5.*:cm0p", "NVIC2"), // Exception 2: TrustZone: NVIC1 is Secure mode, NVIC2 is NonSecure mode. For now, we pick the NonSecure one. - ("STM32(L5|U5|H5[2367]|WBA5[245]|WBA6[2345]).*", "NVIC2"), + ("STM32(L5|U3|U5|H5[2367]|WBA5[245]|WBA6[2345]).*", "NVIC2"), // Exception 3: NVICs are split for "bootloader" and "application", not sure what that means? ("STM32H7[RS].*", "NVIC2"), // Exception 4: NVICS are split for bootloader NVIC, secure NVIC1 and non-secure NVIC2. diff --git a/stm32-data-gen/src/memory.rs b/stm32-data-gen/src/memory.rs index bd46e5cb9..6b1118e0e 100644 --- a/stm32-data-gen/src/memory.rs +++ b/stm32-data-gen/src/memory.rs @@ -362,6 +362,9 @@ static MEMS: RegexMap<&[&[Mem]]> = RegexMap::new(&[ ("STM32U0[78]3.8", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 40 }, OTP { 0x1fff6800 1 })]), ("STM32U0[78]3.B", &[mem!(BANK_1 { 0x08000000 128 }, SRAM { 0x20000000 40 }, OTP { 0x1fff6800 1 })]), ("STM32U0[78]3.C", &[mem!(BANK_1 { 0x08000000 256 }, SRAM { 0x20000000 40 }, OTP { 0x1fff6800 1 })]), + // U3 + ("STM32U3[78]..E", &[mem!(BANK_1 { 0x08000000 256 }, BANK_2 { 0x08010000 256 }, SRAM { 0x20000000 192 }, SRAM2 { 0x20030000 64 }, OTP { 0x0bfa0000 512 bytes })]), + ("STM32U3[78]..G", &[mem!(BANK_1 { 0x08000000 512 }, BANK_2 { 0x08010000 512 }, SRAM { 0x20000000 192 }, SRAM2 { 0x20030000 64 }, OTP { 0x0bfa0000 512 bytes })]), // U5 ("STM32U5[34]..B", &[mem!(BANK_1 { 0x08000000 64 }, BANK_2 { 0x08010000 64 }, SRAM { 0x20000000 192 }, SRAM2 { 0x20030000 64 }, OTP { 0x0bfa0000 512 bytes })]), ("STM32U5[34]..C", &[mem!(BANK_1 { 0x08000000 128 }, BANK_2 { 0x08020000 128 }, SRAM { 0x20000000 192 }, SRAM2 { 0x20030000 64 }, OTP { 0x0bfa0000 512 bytes })]), diff --git a/stm32-data-gen/src/perimap.rs b/stm32-data-gen/src/perimap.rs index b2e8706c6..c19e4a1fd 100644 --- a/stm32-data-gen/src/perimap.rs +++ b/stm32-data-gen/src/perimap.rs @@ -81,6 +81,7 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[ ("STM32H7.*:SPI:.*", ("spi", "v4_i2s", "SPI")), ("STM32H5.*:SPI:.*", ("spi", "v5_i2s", "SPI")), ("STM32N6.*:SPI:.*", ("spi", "v5", "SPI")), + ("STM32U3.*:SPI:.*", ("spi", "v6", "SPI")), ("STM32U5.*:SPI:.*", ("spi", "v6", "SPI")), ("STM32WB0.*:SPI:.*", ("spi", "v3_i2s", "SPI")), ("STM32WBA.*:SPI:.*", ("spi", "v6", "SPI")), @@ -174,6 +175,7 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[ ), ("STM32H7.*:SYSCFG:.*", ("syscfg", "h7", "SYSCFG")), ("STM32U0.*:SYSCFG:.*", ("syscfg", "u0", "SYSCFG")), + ("STM32U3.*:SYSCFG:.*", ("syscfg", "u3", "SYSCFG")), ("STM32U5.*:SYSCFG:.*", ("syscfg", "u5", "SYSCFG")), ("STM32WBA.*:SYSCFG:.*", ("syscfg", "wba", "SYSCFG")), ("STM32WB.*:SYSCFG:.*", ("syscfg", "wb", "SYSCFG")), @@ -248,8 +250,8 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[ ("STM32F373.*:USBRAM:.*", ("usbram", "16x2_512", "USBRAM")), ("STM32(F0|L[045]|G4|WB).*:USB:.*", ("usb", "v3", "USB")), ("STM32(F0|L[045]|G4|WB).*:USBRAM:.*", ("usbram", "16x2_1024", "USBRAM")), - ("STM32(C07|G0|H5|U5|U0).*:USB:.*", ("usb", "v4", "USB")), - ("STM32(C07|G0|H5|U5).*:USBRAM:.*", ("usbram", "32_2048", "USBRAM")), + ("STM32(C07|G0|H5|U[035]).*:USB:.*", ("usb", "v4", "USB")), + ("STM32(C07|G0|H5|U[53]).*:USBRAM:.*", ("usbram", "32_2048", "USBRAM")), ("STM32U0.*:USBRAM:.*", ("usbram", "32_1024", "USBRAM")), // # USB OTG (".*:USB_OTG_FS:otgfs1_.*", ("otg", "v1", "OTG")), @@ -291,6 +293,7 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[ ("STM32L4.*:RCC:.*", ("rcc", "l4", "RCC")), ("STM32L5.*:RCC:.*", ("rcc", "l5", "RCC")), ("STM32U0.*:RCC:.*", ("rcc", "u0", "RCC")), + ("STM32U3.*:RCC:.*", ("rcc", "u3", "RCC")), ("STM32U5.*:RCC:.*", ("rcc", "u5", "RCC")), ("STM32H50.*:RCC:.*", ("rcc", "h50", "RCC")), ("STM32H5.*:RCC:.*", ("rcc", "h5", "RCC")), @@ -307,6 +310,7 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[ ("STM32G0.*:EXTI:.*", ("exti", "g0", "EXTI")), ("STM32H7.*:EXTI:.*", ("exti", "h7", "EXTI")), ("STM32U0.*:EXTI:.*", ("exti", "u0", "EXTI")), + ("STM32U3.*:EXTI:.*", ("exti", "u3", "EXTI")), ("STM32U5.*:EXTI:.*", ("exti", "u5", "EXTI")), ("STM32WB.*:EXTI:.*", ("exti", "w", "EXTI")), ("STM32WL5.*:EXTI:.*", ("exti", "w", "EXTI")), @@ -323,6 +327,7 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[ ("STM32G0.*:CRS:.*", ("crs", "v1", "CRS")), ("STM32G4.*:CRS:.*", ("crs", "v1", "CRS")), ("STM32U5.*:CRS:.*", ("crs", "v1", "CRS")), + ("STM32U3.*:CRS:.*", ("crs", "v1", "CRS")), ("STM32U0.*:CRS:.*", ("crs", "v1", "CRS")), ("STM32H5.*:CRS:.*", ("crs", "v1", "CRS")), ("STM32H7.*:CRS:.*", ("crs", "v1", "CRS")), @@ -350,6 +355,7 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[ ("STM32L5.*:PWR:.*", ("pwr", "l5", "PWR")), ("STM32N6.*:PWR:.*", ("pwr", "n6", "PWR")), ("STM32U0.*:PWR:.*", ("pwr", "u0", "PWR")), + ("STM32U3.*:PWR:.*", ("pwr", "u3", "PWR")), ("STM32U5.*:PWR:.*", ("pwr", "u5", "PWR")), ("STM32WL.*:PWR:.*", ("pwr", "wl5", "PWR")), ("STM32WBA.*:PWR:.*", ("pwr", "wba", "PWR")), @@ -371,6 +377,7 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[ ("STM32L4.*:FLASH:.*", ("flash", "l4", "FLASH")), ("STM32L5.*:FLASH:.*", ("flash", "l5", "FLASH")), ("STM32U0.*:FLASH:.*", ("flash", "u0", "FLASH")), + ("STM32U3.*:FLASH:.*", ("flash", "u3", "FLASH")), ("STM32U5.*:FLASH:.*", ("flash", "u5", "FLASH")), ("STM32WB0.*:FLASH:.*", ("flash", "wb0", "FLASH")), ("STM32WBA.*:FLASH:.*", ("flash", "wba", "FLASH")), @@ -452,18 +459,21 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[ ("STM32L0.*:LPTIM.*:.*", ("lptim", "v1", "LPTIM")), // AN4013 Table 4: STM32Gx/Hx/Ux/Wx (and Cx) serials // timer_v2 for STM32Gx/Hx/Ux/Wx (and Cx) serials - ("STM32U5.*:TIM(3|4):.*", ("timer", "v2", "TIM_GP32")), - ("STM32(G4|H5|U0|U5|WBA).*:TIM(1|8|20):.*", ("timer", "v2", "TIM_ADV")), + ("STM32(U5|U3).*:TIM(3|4):.*", ("timer", "v2", "TIM_GP32")), + ("STM32(G4|H5|U0|U3|U5|WBA).*:TIM(1|8|20):.*", ("timer", "v2", "TIM_ADV")), ( - "STM32(G4|H5|U0|U5|WBA).*:TIM(2|5|23|24):.*", + "STM32(G4|H5|U0|U3|U5|WBA).*:TIM(2|5|23|24):.*", ("timer", "v2", "TIM_GP32"), ), - ("STM32(G4|H5|U0|U5|WBA).*:TIM(3|4):.*", ("timer", "v2", "TIM_GP16")), - ("STM32(G4|H5|U0|U5|WBA).*:TIM(6|7):.*", ("timer", "v2", "TIM_BASIC")), - ("STM32(G4|H5|U0|U5|WBA).*:TIM(13|14):.*", ("timer", "v2", "TIM_1CH")), - ("STM32(G4|H5|U0|U5|WBA).*:TIM12:.*", ("timer", "v2", "TIM_2CH")), - ("STM32(G4|H5|U0|U5|WBA).*:TIM15:.*", ("timer", "v2", "TIM_2CH_CMP")), - ("STM32(G4|H5|U0|U5|WBA).*:TIM(16|17):.*", ("timer", "v2", "TIM_1CH_CMP")), + ("STM32(G4|H5|U0|U3|U5|WBA).*:TIM(3|4):.*", ("timer", "v2", "TIM_GP16")), + ("STM32(G4|H5|U0|U3|U5|WBA).*:TIM(6|7):.*", ("timer", "v2", "TIM_BASIC")), + ("STM32(G4|H5|U0|U3|U5|WBA).*:TIM(13|14):.*", ("timer", "v2", "TIM_1CH")), + ("STM32(G4|H5|U0|U3|U5|WBA).*:TIM12:.*", ("timer", "v2", "TIM_2CH")), + ("STM32(G4|H5|U0|U3|U5|WBA).*:TIM15:.*", ("timer", "v2", "TIM_2CH_CMP")), + ( + "STM32(G4|H5|U0|U3|U5|WBA).*:TIM(16|17):.*", + ("timer", "v2", "TIM_1CH_CMP"), + ), ("STM32G4.*:HRTIM1:.*", ("hrtim", "v2", "HRTIM")), // timer_v1 for STM32Gx/Hx/Ux/Wx (and Cx) serials ( @@ -487,8 +497,8 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[ ("STM32(H7(R|S)|N6).*:TIM9:.*", ("timer", "v1", "TIM_2CH")), // LPTIM for STM32Gx/Hx/Ux/Wx (and Cx) serials ("STM32U0.*:LPTIM.*:.*", ("lptim", "v2b", "LPTIM")), - ("STM32(H5|U5|WBA).*:LPTIM[12356]:.*", ("lptim", "v2a", "LPTIM")), - ("STM32(H5|U5).*:LPTIM4:.*", ("lptim", "v2a", "LPTIM_BASIC")), + ("STM32(H5|U3|U5|WBA).*:LPTIM[12356]:.*", ("lptim", "v2a", "LPTIM")), + ("STM32(H5|U3|U5).*:LPTIM4:.*", ("lptim", "v2a", "LPTIM_BASIC")), ("STM32WL.*:LPTIM.*:.*", ("lptim", "v1c", "LPTIM")), ("STM32H7.*:LPTIM.*:.*", ("lptim", "v1b_h7", "LPTIM")), ("STM32G4.*:LPTIM.*:.*", ("lptim", "v1b_g4", "LPTIM")), @@ -513,6 +523,7 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[ ("STM32N6.*:DBGMCU:.*", ("dbgmcu", "n6", "DBGMCU")), ("STM32U5.*:DBGMCU:.*", ("dbgmcu", "u5", "DBGMCU")), ("STM32U0.*:DBGMCU:.*", ("dbgmcu", "u0", "DBGMCU")), + ("STM32U3.*:DBGMCU:.*", ("dbgmcu", "u3", "DBGMCU")), ("STM32WB0.*:DBGMCU:.*", ("dbgmcu", "wb0", "DBGMCU")), ("STM32WBA.*:DBGMCU:.*", ("dbgmcu", "wba", "DBGMCU")), ("STM32WB.*:DBGMCU:.*", ("dbgmcu", "wb", "DBGMCU")), @@ -563,8 +574,7 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[ ("STM32WB0.*:CRC:.*", ("crc", "v2", "CRC")), ("STM32W[BL].*:CRC:.*", ("crc", "v3", "CRC")), ("STM32C[0].*:CRC:.*", ("crc", "v3", "CRC")), - ("STM32U[0].*:CRC:.*", ("crc", "v3", "CRC")), - ("STM32U[5].*:CRC:.*", ("crc", "v3", "CRC")), + ("STM32U[035].*:CRC:.*", ("crc", "v3", "CRC")), (".*:LCD:lcdc1_v1.0.*", ("lcd", "v1", "LCD")), (".*:LCD:lcdc1_v1.2.*", ("lcd", "v2", "LCD")), (".*:LCD:lcdc1_v1.3.*", ("lcd", "v2", "LCD")), @@ -609,6 +619,7 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[ ("STM32L4.*:GFXMMU:.*", ("gfxmmu", "v1", "GFXMMU")), ("STM32U5.*:GFXMMU:.*", ("gfxmmu", "v2", "GFXMMU")), ("STM32U5.*:ICACHE:.*", ("icache", "v1_3crr", "ICACHE")), + ("STM32U3.*:ICACHE:.*", ("icache", "v1_3crr", "ICACHE")), ("STM32H50.*:ICACHE:.*", ("icache", "v1_0crr", "ICACHE")), ("STM32(L5|H5[67]|WBA).*:ICACHE:.*", ("icache", "v1_4crr", "ICACHE")), (".*:CORDIC:.*", ("cordic", "v1", "CORDIC")), diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs index f8a281ace..6d45a502a 100644 --- a/stm32-data-gen/src/rcc.rs +++ b/stm32-data-gen/src/rcc.rs @@ -356,6 +356,8 @@ impl ParsedRccs { const RCC_PERI_MUX_EXCEPTIONS: &[(&str, &str)] = &[ // These peripherals have a different mux name than the bus clock // Format: rcc_version, peripheral_name + ("u3", "ADC"), + ("u3", "DAC"), ("u5", "ADC"), ("n6", "I2C4"), ("n6", "SDMMC1"), // HCLK2 is corrext per Cube and Docs so no mux check diff --git a/stm32-metapac-gen/res/Cargo.toml b/stm32-metapac-gen/res/Cargo.toml index e53baa2ec..15251e787 100644 --- a/stm32-metapac-gen/res/Cargo.toml +++ b/stm32-metapac-gen/res/Cargo.toml @@ -39,6 +39,7 @@ flavors = [ { regex_feature = "stm32l4.*", target = "thumbv7em-none-eabi" }, { regex_feature = "stm32l5.*", target = "thumbv8m.main-none-eabihf" }, { regex_feature = "stm32u0.*", target = "thumbv6m-none-eabi" }, + { regex_feature = "stm32u3.*", target = "thumbv8m.main-none-eabihf" }, { regex_feature = "stm32u5.*", target = "thumbv8m.main-none-eabihf" }, { regex_feature = "stm32wb0.*", target = "thumbv6m-none-eabi" }, { regex_feature = "stm32wba.*", target = "thumbv8m.main-none-eabihf" }, @@ -55,11 +56,11 @@ defmt = { version = "0.3.0", optional = true } default = ["pac"] # Build the actual PAC. Set by default. -# If you just want the metadata, unset it with `default-features = false`. +# If you just want the metadata, unset it with `default-features = false`. pac = [] # Build the chip metadata. -# If set, a const `stm32_metapac::METADATA` will be exported, containing all the +# If set, a const `stm32_metapac::METADATA` will be exported, containing all the # metadata for the currently selected chip. metadata = []