@@ -48,32 +48,34 @@ defmodule Protobuf.Wire.Varint do
4848 @ max_bits 64
4949 @ mask64 bsl ( 1 , @ max_bits ) - 1
5050
51+ # generated: true is required here to silence compilation warnings in Elixir
52+ # 1.10 and 1.11. OK to remove once we support only 1.12+
5153 @ varints [
5254 {
5355 quote ( do: << 0 :: 1 , value :: 7 >> ) ,
5456 quote ( do: value )
5557 } ,
5658 {
5759 quote ( do: << 1 :: 1 , x0 :: 7 , 0 :: 1 , x1 :: 7 >> ) ,
58- quote ( do: x0 + bsl ( x1 , 7 ) )
60+ quote ( generated: true , do: x0 + bsl ( x1 , 7 ) )
5961 } ,
6062 {
6163 quote ( do: << 1 :: 1 , x0 :: 7 , 1 :: 1 , x1 :: 7 , 0 :: 1 , x2 :: 7 >> ) ,
62- quote ( do: x0 + bsl ( x1 , 7 ) + bsl ( x2 , 14 ) )
64+ quote ( generated: true , do: x0 + bsl ( x1 , 7 ) + bsl ( x2 , 14 ) )
6365 } ,
6466 {
6567 quote ( do: << 1 :: 1 , x0 :: 7 , 1 :: 1 , x1 :: 7 , 1 :: 1 , x2 :: 7 , 0 :: 1 , x3 :: 7 >> ) ,
66- quote ( do: x0 + bsl ( x1 , 7 ) + bsl ( x2 , 14 ) + bsl ( x3 , 21 ) )
68+ quote ( generated: true , do: x0 + bsl ( x1 , 7 ) + bsl ( x2 , 14 ) + bsl ( x3 , 21 ) )
6769 } ,
6870 {
6971 quote ( do: << 1 :: 1 , x0 :: 7 , 1 :: 1 , x1 :: 7 , 1 :: 1 , x2 :: 7 , 1 :: 1 , x3 :: 7 , 0 :: 1 , x4 :: 7 >> ) ,
70- quote ( do: x0 + bsl ( x1 , 7 ) + bsl ( x2 , 14 ) + bsl ( x3 , 21 ) + bsl ( x4 , 28 ) )
72+ quote ( generated: true , do: x0 + bsl ( x1 , 7 ) + bsl ( x2 , 14 ) + bsl ( x3 , 21 ) + bsl ( x4 , 28 ) )
7173 } ,
7274 {
7375 quote do
7476 << 1 :: 1 , x0 :: 7 , 1 :: 1 , x1 :: 7 , 1 :: 1 , x2 :: 7 , 1 :: 1 , x3 :: 7 , 1 :: 1 , x4 :: 7 , 0 :: 1 , x5 :: 7 >>
7577 end ,
76- quote do
78+ quote ( generated: true ) do
7779 x0 +
7880 bsl ( x1 , 7 ) +
7981 bsl ( x2 , 14 ) +
@@ -87,7 +89,7 @@ defmodule Protobuf.Wire.Varint do
8789 << 1 :: 1 , x0 :: 7 , 1 :: 1 , x1 :: 7 , 1 :: 1 , x2 :: 7 , 1 :: 1 , x3 :: 7 , 1 :: 1 , x4 :: 7 , 1 :: 1 , x5 :: 7 , 0 :: 1 ,
8890 x6 :: 7 >>
8991 end ,
90- quote do
92+ quote ( generated: true ) do
9193 x0 +
9294 bsl ( x1 , 7 ) +
9395 bsl ( x2 , 14 ) +
@@ -102,7 +104,7 @@ defmodule Protobuf.Wire.Varint do
102104 << 1 :: 1 , x0 :: 7 , 1 :: 1 , x1 :: 7 , 1 :: 1 , x2 :: 7 , 1 :: 1 , x3 :: 7 , 1 :: 1 , x4 :: 7 , 1 :: 1 , x5 :: 7 , 1 :: 1 ,
103105 x6 :: 7 , 0 :: 1 , x7 :: 7 >>
104106 end ,
105- quote do
107+ quote ( generated: true ) do
106108 x0 +
107109 bsl ( x1 , 7 ) +
108110 bsl ( x2 , 14 ) +
@@ -118,7 +120,7 @@ defmodule Protobuf.Wire.Varint do
118120 << 1 :: 1 , x0 :: 7 , 1 :: 1 , x1 :: 7 , 1 :: 1 , x2 :: 7 , 1 :: 1 , x3 :: 7 , 1 :: 1 , x4 :: 7 , 1 :: 1 , x5 :: 7 , 1 :: 1 ,
119121 x6 :: 7 , 1 :: 1 , x7 :: 7 , 0 :: 1 , x8 :: 7 >>
120122 end ,
121- quote do
123+ quote ( generated: true ) do
122124 x0 +
123125 bsl ( x1 , 7 ) +
124126 bsl ( x2 , 14 ) +
@@ -135,7 +137,7 @@ defmodule Protobuf.Wire.Varint do
135137 << 1 :: 1 , x0 :: 7 , 1 :: 1 , x1 :: 7 , 1 :: 1 , x2 :: 7 , 1 :: 1 , x3 :: 7 , 1 :: 1 , x4 :: 7 , 1 :: 1 , x5 :: 7 , 1 :: 1 ,
136138 x6 :: 7 , 1 :: 1 , x7 :: 7 , 1 :: 1 , x8 :: 7 , 0 :: 1 , x9 :: 7 >>
137139 end ,
138- quote do
140+ quote ( generated: true ) do
139141 band (
140142 x0 +
141143 bsl ( x1 , 7 ) +
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