DM: fix dac clock and first write bug

Author: deanm1278

cores/arduino/startup.c

@@ -30,6 +30,8 @@
 #define GENERIC_CLOCK_GENERATOR_48M_SYNC	GCLK_SYNCBUSY_GENCTRL1
 #define GENERIC_CLOCK_GENERATOR_100M	  (2u)
 #define GENERIC_CLOCK_GENERATOR_100M_SYNC	GCLK_SYNCBUSY_GENCTRL2
+#define GENERIC_CLOCK_GENERATOR_12M       (4u)
+#define GENERIC_CLOCK_GENERATOR_12M_SYNC   GCLK_SYNCBUSY_GENCTRL4
 
 //USE DPLL0 for 120MHZ
 #define MAIN_CLOCK_SOURCE				  GCLK_GENCTRL_SRC_DPLL0
@@ -204,6 +206,19 @@ void SystemInit( void )
 	{
 		/* Wait for synchronization */
 	}
+
+  //12MHZ CLOCK FOR DAC
+    GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_12M].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL_Val) |
+    GCLK_GENCTRL_IDC |
+    GCLK_GENCTRL_DIV(4) |
+    GCLK_GENCTRL_DIVSEL |
+    //GCLK_GENCTRL_OE |
+    GCLK_GENCTRL_GENEN;
+
+    while ( GCLK->SYNCBUSY.reg & GENERIC_CLOCK_GENERATOR_12M_SYNC)
+    {
+        /* Wait for synchronization */
+    }
 
   /*---------------------------------------------------------------------
   * Set up main clock

cores/arduino/wiring.c

@@ -131,7 +131,7 @@ void init( void )
 
 	analogReference( AR_DEFAULT ) ; // Analog Reference is AREF pin (3.3v)
 
-	GCLK->PCHCTRL[DAC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK1_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); //use clock generator 1 (48mhz)
+	GCLK->PCHCTRL[DAC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK4_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); //use clock generator 4 (12mhz)
 	while (GCLK->PCHCTRL[DAC_GCLK_ID].bit.CHEN == 0);
 
 	while ( DAC->SYNCBUSY.bit.SWRST == 1 ); // Wait for synchronization of registers between the clock domains

cores/arduino/wiring_analog.c

@@ -373,6 +373,22 @@ void analogWrite(uint32_t pin, uint32_t value)
 
 			while (DAC->SYNCBUSY.bit.ENABLE || DAC->SYNCBUSY.bit.SWRST);
 			DAC->CTRLA.bit.ENABLE = 1;     // enable DAC
+
+	        if(channel == 0){
+
+	            while ( !DAC->STATUS.bit.READY0 );
+
+	            while (DAC->SYNCBUSY.bit.DATA0);
+	            DAC->DATA[0].reg = value;
+	        }
+	        else if(channel == 1){
+	            while ( !DAC->STATUS.bit.READY1 );
+
+	            while (DAC->SYNCBUSY.bit.DATA1);
+	            DAC->DATA[1].reg = value;
+	        }
+
+            delay(10);
 		}
 
 		//ERROR!