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x86/mce: Break up __mcheck_cpu_apply_quirks()
JIRA: https://issues.redhat.com/browse/RHEL-118444 commit 51a12c2 Author: Tony Luck <tony.luck@intel.com> Date: Thu Dec 12 22:01:00 2024 +0800 x86/mce: Break up __mcheck_cpu_apply_quirks() Split each vendor specific part into its own helper function. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Sohil Mehta <sohil.mehta@intel.com> Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com> Tested-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Link: https://lore.kernel.org/r/20241212140103.66964-5-qiuxu.zhuo@intel.com Signed-off-by: David Arcari <darcari@redhat.com>
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‎arch/x86/kernel/cpu/mce/core.c‎

Lines changed: 92 additions & 76 deletions
Original file line numberDiff line numberDiff line change
@@ -1909,101 +1909,117 @@ static void __mcheck_cpu_check_banks(void)
19091909
}
19101910
}
19111911

1912-
/* Add per CPU specific workarounds here */
1913-
static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1912+
static void apply_quirks_amd(struct cpuinfo_x86 *c)
19141913
{
19151914
struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1916-
struct mca_config *cfg = &mca_cfg;
1917-
1918-
if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1919-
pr_info("unknown CPU type - not enabling MCE support\n");
1920-
return false;
1921-
}
19221915

19231916
/* This should be disabled by the BIOS, but isn't always */
1924-
if (c->x86_vendor == X86_VENDOR_AMD) {
1925-
if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
1926-
/*
1927-
* disable GART TBL walk error reporting, which
1928-
* trips off incorrectly with the IOMMU & 3ware
1929-
* & Cerberus:
1930-
*/
1931-
clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1932-
}
1933-
if (c->x86 < 0x11 && cfg->bootlog < 0) {
1934-
/*
1935-
* Lots of broken BIOS around that don't clear them
1936-
* by default and leave crap in there. Don't log:
1937-
*/
1938-
cfg->bootlog = 0;
1939-
}
1917+
if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
19401918
/*
1941-
* Various K7s with broken bank 0 around. Always disable
1942-
* by default.
1919+
* disable GART TBL walk error reporting, which
1920+
* trips off incorrectly with the IOMMU & 3ware
1921+
* & Cerberus:
19431922
*/
1944-
if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0)
1945-
mce_banks[0].ctl = 0;
1923+
clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1924+
}
19461925

1926+
if (c->x86 < 0x11 && mca_cfg.bootlog < 0) {
19471927
/*
1948-
* overflow_recov is supported for F15h Models 00h-0fh
1949-
* even though we don't have a CPUID bit for it.
1928+
* Lots of broken BIOS around that don't clear them
1929+
* by default and leave crap in there. Don't log:
19501930
*/
1951-
if (c->x86 == 0x15 && c->x86_model <= 0xf)
1952-
mce_flags.overflow_recov = 1;
1931+
mca_cfg.bootlog = 0;
1932+
}
19531933

1954-
if (c->x86 >= 0x17 && c->x86 <= 0x1A)
1955-
mce_flags.zen_ifu_quirk = 1;
1934+
/*
1935+
* Various K7s with broken bank 0 around. Always disable
1936+
* by default.
1937+
*/
1938+
if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0)
1939+
mce_banks[0].ctl = 0;
19561940

1957-
}
1941+
/*
1942+
* overflow_recov is supported for F15h Models 00h-0fh
1943+
* even though we don't have a CPUID bit for it.
1944+
*/
1945+
if (c->x86 == 0x15 && c->x86_model <= 0xf)
1946+
mce_flags.overflow_recov = 1;
19581947

1959-
if (c->x86_vendor == X86_VENDOR_INTEL) {
1960-
/*
1961-
* SDM documents that on family 6 bank 0 should not be written
1962-
* because it aliases to another special BIOS controlled
1963-
* register.
1964-
* But it's not aliased anymore on model 0x1a+
1965-
* Don't ignore bank 0 completely because there could be a
1966-
* valid event later, merely don't write CTL0.
1967-
*/
1948+
if (c->x86 >= 0x17 && c->x86 <= 0x1A)
1949+
mce_flags.zen_ifu_quirk = 1;
1950+
}
19681951

1969-
if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0)
1970-
mce_banks[0].init = false;
1952+
static void apply_quirks_intel(struct cpuinfo_x86 *c)
1953+
{
1954+
struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
19711955

1972-
/*
1973-
* All newer Intel systems support MCE broadcasting. Enable
1974-
* synchronization with a one second timeout.
1975-
*/
1976-
if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1977-
cfg->monarch_timeout < 0)
1978-
cfg->monarch_timeout = USEC_PER_SEC;
1956+
/*
1957+
* SDM documents that on family 6 bank 0 should not be written
1958+
* because it aliases to another special BIOS controlled
1959+
* register.
1960+
* But it's not aliased anymore on model 0x1a+
1961+
* Don't ignore bank 0 completely because there could be a
1962+
* valid event later, merely don't write CTL0.
1963+
*/
1964+
if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0)
1965+
mce_banks[0].init = false;
19791966

1980-
/*
1981-
* There are also broken BIOSes on some Pentium M and
1982-
* earlier systems:
1983-
*/
1984-
if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1985-
cfg->bootlog = 0;
1967+
/*
1968+
* All newer Intel systems support MCE broadcasting. Enable
1969+
* synchronization with a one second timeout.
1970+
*/
1971+
if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1972+
mca_cfg.monarch_timeout < 0)
1973+
mca_cfg.monarch_timeout = USEC_PER_SEC;
1974+
1975+
/*
1976+
* There are also broken BIOSes on some Pentium M and
1977+
* earlier systems:
1978+
*/
1979+
if (c->x86 == 6 && c->x86_model <= 13 && mca_cfg.bootlog < 0)
1980+
mca_cfg.bootlog = 0;
19861981

1987-
if (c->x86_vfm == INTEL_SANDYBRIDGE_X)
1988-
mce_flags.snb_ifu_quirk = 1;
1982+
if (c->x86_vfm == INTEL_SANDYBRIDGE_X)
1983+
mce_flags.snb_ifu_quirk = 1;
19891984

1990-
/*
1991-
* Skylake, Cascacde Lake and Cooper Lake require a quirk on
1992-
* rep movs.
1993-
*/
1994-
if (c->x86_vfm == INTEL_SKYLAKE_X)
1995-
mce_flags.skx_repmov_quirk = 1;
1985+
/*
1986+
* Skylake, Cascacde Lake and Cooper Lake require a quirk on
1987+
* rep movs.
1988+
*/
1989+
if (c->x86_vfm == INTEL_SKYLAKE_X)
1990+
mce_flags.skx_repmov_quirk = 1;
1991+
}
1992+
1993+
static void apply_quirks_zhaoxin(struct cpuinfo_x86 *c)
1994+
{
1995+
/*
1996+
* All newer Zhaoxin CPUs support MCE broadcasting. Enable
1997+
* synchronization with a one second timeout.
1998+
*/
1999+
if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
2000+
if (mca_cfg.monarch_timeout < 0)
2001+
mca_cfg.monarch_timeout = USEC_PER_SEC;
19962002
}
2003+
}
19972004

1998-
if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
1999-
/*
2000-
* All newer Zhaoxin CPUs support MCE broadcasting. Enable
2001-
* synchronization with a one second timeout.
2002-
*/
2003-
if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
2004-
if (cfg->monarch_timeout < 0)
2005-
cfg->monarch_timeout = USEC_PER_SEC;
2006-
}
2005+
/* Add per CPU specific workarounds here */
2006+
static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
2007+
{
2008+
struct mca_config *cfg = &mca_cfg;
2009+
2010+
switch (c->x86_vendor) {
2011+
case X86_VENDOR_UNKNOWN:
2012+
pr_info("unknown CPU type - not enabling MCE support\n");
2013+
return false;
2014+
case X86_VENDOR_AMD:
2015+
apply_quirks_amd(c);
2016+
break;
2017+
case X86_VENDOR_INTEL:
2018+
apply_quirks_intel(c);
2019+
break;
2020+
case X86_VENDOR_ZHAOXIN:
2021+
apply_quirks_zhaoxin(c);
2022+
break;
20072023
}
20082024

20092025
if (cfg->monarch_timeout < 0)

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