phy: ti: gmii-sel: Enable SGMII mode for J721E

JIRA: https://issues.redhat.com/browse/RHEL-44742

commit 2de2e49
Author: Siddharth Vadapalli <s-vadapalli@ti.com>
Date:   Thu Mar 9 12:05:14 2023 +0530

    phy: ti: gmii-sel: Enable SGMII mode for J721E

    TI's J721E SoC supports SGMII mode with the CPSW9G instance of the CPSW
    Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the
    corresponding extra_modes member.

    Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
    Reviewed-by: Roger Quadros <rogerq@kernel.org>
    Link: https://lore.kernel.org/r/20230309063514.398705-4-s-vadapalli@ti.com
    Signed-off-by: Vinod Koul <vkoul@kernel.org>

Signed-off-by: Andrew Halaney <ahalaney@redhat.com>

Author: ahalaney

drivers/phy/ti/phy-gmii-sel.c

@@ -230,7 +230,7 @@ static const
 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = {
 	.use_of_data = true,
 	.regfields = phy_gmii_sel_fields_am654,
-	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
+	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
 	.num_ports = 8,
 	.num_qsgmii_main_ports = 2,
 };