cxl/edac: Add CXL memory device ECS control feature

JIRA: https://issues.redhat.com/browse/RHEL-107284

commit 85fb6a1
Author: Shiju Jose <shiju.jose@huawei.com>
Date:   Wed May 21 13:47:42 2025 +0100

    cxl/edac: Add CXL memory device ECS control feature

    CXL spec 3.2 section 8.2.10.9.11.2 describes the DDR5 ECS (Error Check
    Scrub) control feature.
    The Error Check Scrub (ECS) is a feature defined in JEDEC DDR5 SDRAM
    Specification (JESD79-5) and allows the DRAM to internally read, correct
    single-bit errors, and write back corrected data bits to the DRAM array
    while providing transparency to error counts.

    The ECS control allows the requester to change the log entry type, the ECS
    threshold count (provided the request falls within the limits specified in
    DDR5 mode registers), switch between codeword mode and row count mode, and
    reset the ECS counter.

    Register with EDAC device driver, which retrieves the ECS attribute
    descriptors from the EDAC ECS and exposes the ECS control attributes to
    userspace via sysfs. For example, the ECS control for the memory media FRU0
    in CXL mem0 device is located at /sys/bus/edac/devices/cxl_mem0/ecs_fru0/

    Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
    Reviewed-by: Fan Ni <fan.ni@samsung.com>
    Reviewed-by: Dave Jiang <dave.jiang@intel.com>
    Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
    Reviewed-by: Alison Schofield <alison.schofield@intel.com>
    Acked-by: Dan Williams <dan.j.williams@intel.com>
    Link: https://patch.msgid.link/20250521124749.817-5-shiju.jose@huawei.com
    Signed-off-by: Dave Jiang <dave.jiang@intel.com>

Signed-off-by: John W. Linville <linville@redhat.com>

Author: John W. Linville

drivers/cxl/Kconfig

@@ -147,6 +147,23 @@ config CXL_EDAC_SCRUB
 	  (e.g. scrub rates for the patrol scrub feature).
 	  Otherwise say 'n'.
 
+config CXL_EDAC_ECS
+	bool "Enable CXL Error Check Scrub (Repair)"
+	depends on CXL_EDAC_MEM_FEATURES
+	depends on EDAC_ECS
+	help
+	  The CXL EDAC ECS control is optional and allows host to
+	  control the ECS feature configurations of CXL memory expander
+	  devices.
+
+	  When enabled 'cxl_mem' EDAC devices are published with memory
+	  ECS control attributes as described by
+	  Documentation/ABI/testing/sysfs-edac-ecs.
+
+	  Say 'y' if you have an expert need to change default settings
+	  of a memory ECS feature established by the platform/device.
+	  Otherwise say 'n'.
+
 config CXL_PORT
 	default CXL_BUS
 	tristate