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Marc Zyngier
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KVM: arm64: Allow sysreg ranges for FGT descriptors
Just like we allow sysreg ranges for Coarse Grained Trap descriptors, allow them for Fine Grain Traps as well. This comes with a warning that not all ranges are suitable for this particular definition of ranges. Signed-off-by: Marc Zyngier <maz@kernel.org>
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‎arch/arm64/kvm/emulate-nested.c‎

Lines changed: 42 additions & 81 deletions
Original file line numberDiff line numberDiff line change
@@ -622,6 +622,11 @@ struct encoding_to_trap_config {
622622
const unsigned int line;
623623
};
624624

625+
/*
626+
* WARNING: using ranges is a treacherous endeavour, as sysregs that
627+
* are part of an architectural range are not necessarily contiguous
628+
* in the [Op0,Op1,CRn,CRm,Ops] space. Tread carefully.
629+
*/
625630
#define SR_RANGE_TRAP(sr_start, sr_end, trap_id) \
626631
{ \
627632
.encoding = sr_start, \
@@ -1289,15 +1294,22 @@ enum fg_filter_id {
12891294

12901295
#define FGT(g, b, p) __FGT(g, b, p, __NO_FGF__)
12911296

1292-
#define SR_FGF(sr, g, b, p, f) \
1297+
/*
1298+
* See the warning next to SR_RANGE_TRAP(), and apply the same
1299+
* level of caution.
1300+
*/
1301+
#define SR_FGF_RANGE(sr, e, g, b, p, f) \
12931302
{ \
12941303
.encoding = sr, \
1295-
.end = sr, \
1304+
.end = e, \
12961305
.tc = __FGT(g, b, p, f), \
12971306
.line = __LINE__, \
12981307
}
12991308

1300-
#define SR_FGT(sr, g, b, p) SR_FGF(sr, g, b, p, __NO_FGF__)
1309+
#define SR_FGF(sr, g, b, p, f) SR_FGF_RANGE(sr, sr, g, b, p, f)
1310+
#define SR_FGT(sr, g, b, p) SR_FGF_RANGE(sr, sr, g, b, p, __NO_FGF__)
1311+
#define SR_FGT_RANGE(sr, end, g, b, p) \
1312+
SR_FGF_RANGE(sr, end, g, b, p, __NO_FGF__)
13011313

13021314
static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = {
13031315
/* HFGRTR_EL2, HFGWTR_EL2 */
@@ -1794,68 +1806,12 @@ static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = {
17941806
SR_FGT(SYS_PMCNTENSET_EL0, HDFGRTR, PMCNTEN, 1),
17951807
SR_FGT(SYS_PMCCNTR_EL0, HDFGRTR, PMCCNTR_EL0, 1),
17961808
SR_FGT(SYS_PMCCFILTR_EL0, HDFGRTR, PMCCFILTR_EL0, 1),
1797-
SR_FGT(SYS_PMEVTYPERn_EL0(0), HDFGRTR, PMEVTYPERn_EL0, 1),
1798-
SR_FGT(SYS_PMEVTYPERn_EL0(1), HDFGRTR, PMEVTYPERn_EL0, 1),
1799-
SR_FGT(SYS_PMEVTYPERn_EL0(2), HDFGRTR, PMEVTYPERn_EL0, 1),
1800-
SR_FGT(SYS_PMEVTYPERn_EL0(3), HDFGRTR, PMEVTYPERn_EL0, 1),
1801-
SR_FGT(SYS_PMEVTYPERn_EL0(4), HDFGRTR, PMEVTYPERn_EL0, 1),
1802-
SR_FGT(SYS_PMEVTYPERn_EL0(5), HDFGRTR, PMEVTYPERn_EL0, 1),
1803-
SR_FGT(SYS_PMEVTYPERn_EL0(6), HDFGRTR, PMEVTYPERn_EL0, 1),
1804-
SR_FGT(SYS_PMEVTYPERn_EL0(7), HDFGRTR, PMEVTYPERn_EL0, 1),
1805-
SR_FGT(SYS_PMEVTYPERn_EL0(8), HDFGRTR, PMEVTYPERn_EL0, 1),
1806-
SR_FGT(SYS_PMEVTYPERn_EL0(9), HDFGRTR, PMEVTYPERn_EL0, 1),
1807-
SR_FGT(SYS_PMEVTYPERn_EL0(10), HDFGRTR, PMEVTYPERn_EL0, 1),
1808-
SR_FGT(SYS_PMEVTYPERn_EL0(11), HDFGRTR, PMEVTYPERn_EL0, 1),
1809-
SR_FGT(SYS_PMEVTYPERn_EL0(12), HDFGRTR, PMEVTYPERn_EL0, 1),
1810-
SR_FGT(SYS_PMEVTYPERn_EL0(13), HDFGRTR, PMEVTYPERn_EL0, 1),
1811-
SR_FGT(SYS_PMEVTYPERn_EL0(14), HDFGRTR, PMEVTYPERn_EL0, 1),
1812-
SR_FGT(SYS_PMEVTYPERn_EL0(15), HDFGRTR, PMEVTYPERn_EL0, 1),
1813-
SR_FGT(SYS_PMEVTYPERn_EL0(16), HDFGRTR, PMEVTYPERn_EL0, 1),
1814-
SR_FGT(SYS_PMEVTYPERn_EL0(17), HDFGRTR, PMEVTYPERn_EL0, 1),
1815-
SR_FGT(SYS_PMEVTYPERn_EL0(18), HDFGRTR, PMEVTYPERn_EL0, 1),
1816-
SR_FGT(SYS_PMEVTYPERn_EL0(19), HDFGRTR, PMEVTYPERn_EL0, 1),
1817-
SR_FGT(SYS_PMEVTYPERn_EL0(20), HDFGRTR, PMEVTYPERn_EL0, 1),
1818-
SR_FGT(SYS_PMEVTYPERn_EL0(21), HDFGRTR, PMEVTYPERn_EL0, 1),
1819-
SR_FGT(SYS_PMEVTYPERn_EL0(22), HDFGRTR, PMEVTYPERn_EL0, 1),
1820-
SR_FGT(SYS_PMEVTYPERn_EL0(23), HDFGRTR, PMEVTYPERn_EL0, 1),
1821-
SR_FGT(SYS_PMEVTYPERn_EL0(24), HDFGRTR, PMEVTYPERn_EL0, 1),
1822-
SR_FGT(SYS_PMEVTYPERn_EL0(25), HDFGRTR, PMEVTYPERn_EL0, 1),
1823-
SR_FGT(SYS_PMEVTYPERn_EL0(26), HDFGRTR, PMEVTYPERn_EL0, 1),
1824-
SR_FGT(SYS_PMEVTYPERn_EL0(27), HDFGRTR, PMEVTYPERn_EL0, 1),
1825-
SR_FGT(SYS_PMEVTYPERn_EL0(28), HDFGRTR, PMEVTYPERn_EL0, 1),
1826-
SR_FGT(SYS_PMEVTYPERn_EL0(29), HDFGRTR, PMEVTYPERn_EL0, 1),
1827-
SR_FGT(SYS_PMEVTYPERn_EL0(30), HDFGRTR, PMEVTYPERn_EL0, 1),
1828-
SR_FGT(SYS_PMEVCNTRn_EL0(0), HDFGRTR, PMEVCNTRn_EL0, 1),
1829-
SR_FGT(SYS_PMEVCNTRn_EL0(1), HDFGRTR, PMEVCNTRn_EL0, 1),
1830-
SR_FGT(SYS_PMEVCNTRn_EL0(2), HDFGRTR, PMEVCNTRn_EL0, 1),
1831-
SR_FGT(SYS_PMEVCNTRn_EL0(3), HDFGRTR, PMEVCNTRn_EL0, 1),
1832-
SR_FGT(SYS_PMEVCNTRn_EL0(4), HDFGRTR, PMEVCNTRn_EL0, 1),
1833-
SR_FGT(SYS_PMEVCNTRn_EL0(5), HDFGRTR, PMEVCNTRn_EL0, 1),
1834-
SR_FGT(SYS_PMEVCNTRn_EL0(6), HDFGRTR, PMEVCNTRn_EL0, 1),
1835-
SR_FGT(SYS_PMEVCNTRn_EL0(7), HDFGRTR, PMEVCNTRn_EL0, 1),
1836-
SR_FGT(SYS_PMEVCNTRn_EL0(8), HDFGRTR, PMEVCNTRn_EL0, 1),
1837-
SR_FGT(SYS_PMEVCNTRn_EL0(9), HDFGRTR, PMEVCNTRn_EL0, 1),
1838-
SR_FGT(SYS_PMEVCNTRn_EL0(10), HDFGRTR, PMEVCNTRn_EL0, 1),
1839-
SR_FGT(SYS_PMEVCNTRn_EL0(11), HDFGRTR, PMEVCNTRn_EL0, 1),
1840-
SR_FGT(SYS_PMEVCNTRn_EL0(12), HDFGRTR, PMEVCNTRn_EL0, 1),
1841-
SR_FGT(SYS_PMEVCNTRn_EL0(13), HDFGRTR, PMEVCNTRn_EL0, 1),
1842-
SR_FGT(SYS_PMEVCNTRn_EL0(14), HDFGRTR, PMEVCNTRn_EL0, 1),
1843-
SR_FGT(SYS_PMEVCNTRn_EL0(15), HDFGRTR, PMEVCNTRn_EL0, 1),
1844-
SR_FGT(SYS_PMEVCNTRn_EL0(16), HDFGRTR, PMEVCNTRn_EL0, 1),
1845-
SR_FGT(SYS_PMEVCNTRn_EL0(17), HDFGRTR, PMEVCNTRn_EL0, 1),
1846-
SR_FGT(SYS_PMEVCNTRn_EL0(18), HDFGRTR, PMEVCNTRn_EL0, 1),
1847-
SR_FGT(SYS_PMEVCNTRn_EL0(19), HDFGRTR, PMEVCNTRn_EL0, 1),
1848-
SR_FGT(SYS_PMEVCNTRn_EL0(20), HDFGRTR, PMEVCNTRn_EL0, 1),
1849-
SR_FGT(SYS_PMEVCNTRn_EL0(21), HDFGRTR, PMEVCNTRn_EL0, 1),
1850-
SR_FGT(SYS_PMEVCNTRn_EL0(22), HDFGRTR, PMEVCNTRn_EL0, 1),
1851-
SR_FGT(SYS_PMEVCNTRn_EL0(23), HDFGRTR, PMEVCNTRn_EL0, 1),
1852-
SR_FGT(SYS_PMEVCNTRn_EL0(24), HDFGRTR, PMEVCNTRn_EL0, 1),
1853-
SR_FGT(SYS_PMEVCNTRn_EL0(25), HDFGRTR, PMEVCNTRn_EL0, 1),
1854-
SR_FGT(SYS_PMEVCNTRn_EL0(26), HDFGRTR, PMEVCNTRn_EL0, 1),
1855-
SR_FGT(SYS_PMEVCNTRn_EL0(27), HDFGRTR, PMEVCNTRn_EL0, 1),
1856-
SR_FGT(SYS_PMEVCNTRn_EL0(28), HDFGRTR, PMEVCNTRn_EL0, 1),
1857-
SR_FGT(SYS_PMEVCNTRn_EL0(29), HDFGRTR, PMEVCNTRn_EL0, 1),
1858-
SR_FGT(SYS_PMEVCNTRn_EL0(30), HDFGRTR, PMEVCNTRn_EL0, 1),
1809+
SR_FGT_RANGE(SYS_PMEVTYPERn_EL0(0),
1810+
SYS_PMEVTYPERn_EL0(30),
1811+
HDFGRTR, PMEVTYPERn_EL0, 1),
1812+
SR_FGT_RANGE(SYS_PMEVCNTRn_EL0(0),
1813+
SYS_PMEVCNTRn_EL0(30),
1814+
HDFGRTR, PMEVCNTRn_EL0, 1),
18591815
SR_FGT(SYS_OSDLR_EL1, HDFGRTR, OSDLR_EL1, 1),
18601816
SR_FGT(SYS_OSECCR_EL1, HDFGRTR, OSECCR_EL1, 1),
18611817
SR_FGT(SYS_OSLSR_EL1, HDFGRTR, OSLSR_EL1, 1),
@@ -2172,6 +2128,9 @@ static __init int check_all_fgt_masks(int ret)
21722128
return ret ?: err;
21732129
}
21742130

2131+
#define for_each_encoding_in(__x, __s, __e) \
2132+
for (u32 __x = __s; __x <= __e; __x = encoding_next(__x))
2133+
21752134
int __init populate_nv_trap_config(void)
21762135
{
21772136
int ret = 0;
@@ -2191,7 +2150,7 @@ int __init populate_nv_trap_config(void)
21912150
ret = -EINVAL;
21922151
}
21932152

2194-
for (u32 enc = cgt->encoding; enc <= cgt->end; enc = encoding_next(enc)) {
2153+
for_each_encoding_in(enc, cgt->encoding, cgt->end) {
21952154
prev = xa_store(&sr_forward_xa, enc,
21962155
xa_mk_value(cgt->tc.val), GFP_KERNEL);
21972156
if (prev && !xa_is_err(prev)) {
@@ -2226,25 +2185,27 @@ int __init populate_nv_trap_config(void)
22262185
print_nv_trap_error(fgt, "Invalid FGT", ret);
22272186
}
22282187

2229-
tc = get_trap_config(fgt->encoding);
2188+
for_each_encoding_in(enc, fgt->encoding, fgt->end) {
2189+
tc = get_trap_config(enc);
22302190

2231-
if (tc.fgt) {
2232-
ret = -EINVAL;
2233-
print_nv_trap_error(fgt, "Duplicate FGT", ret);
2234-
}
2191+
if (tc.fgt) {
2192+
ret = -EINVAL;
2193+
print_nv_trap_error(fgt, "Duplicate FGT", ret);
2194+
}
22352195

2236-
tc.val |= fgt->tc.val;
2237-
prev = xa_store(&sr_forward_xa, fgt->encoding,
2238-
xa_mk_value(tc.val), GFP_KERNEL);
2196+
tc.val |= fgt->tc.val;
2197+
prev = xa_store(&sr_forward_xa, enc,
2198+
xa_mk_value(tc.val), GFP_KERNEL);
22392199

2240-
if (xa_is_err(prev)) {
2241-
ret = xa_err(prev);
2242-
print_nv_trap_error(fgt, "Failed FGT insertion", ret);
2243-
}
2200+
if (xa_is_err(prev)) {
2201+
ret = xa_err(prev);
2202+
print_nv_trap_error(fgt, "Failed FGT insertion", ret);
2203+
}
22442204

2245-
if (!aggregate_fgt(tc)) {
2246-
ret = -EINVAL;
2247-
print_nv_trap_error(fgt, "FGT bit is reserved", ret);
2205+
if (!aggregate_fgt(tc)) {
2206+
ret = -EINVAL;
2207+
print_nv_trap_error(fgt, "FGT bit is reserved", ret);
2208+
}
22482209
}
22492210
}
22502211

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