tools arch x86: Sync the msr-index.h copy with the kernel sources

PlaidCat · PlaidCat · commit f1ac17191ca3 · 2025-11-12T10:07:51.000-05:00
jira LE-4694 Rebuild_History Non-Buildable kernel-6.12.0-55.43.1.el10_0 commit-author Arnaldo Carvalho de Melo <acme@redhat.com> commit 8122b04 Empty-Commit: Cherry-Pick Conflicts during history rebuild. Will be included in final tarball splat. Ref for failed cherry-pick at: ciq/ciq_backports/kernel-6.12.0-55.43.1.el10_0/8122b047.failed To pick up the changes from these csets: 3f3c8be Merge tag 'for-linus-5.5a-rc1-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip 4e3f77d ("xen/mcelog: add PPIN to record when available") db4d30f ("x86/bugs: Add ITLB_MULTIHIT bug infrastructure") 1b42f01 ("x86/speculation/taa: Add mitigation for TSX Async Abort") c2955f2 ("x86/msr: Add the IA32_TSX_CTRL MSR") These are the changes in tooling that this udpate ensues: $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > /tmp/before $ $ cp arch/x86/include/asm/msr-index.h tools/arch/x86/include/asm/msr-index.h $ $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > /tmp/after $ diff -u /tmp/before /tmp/after --- /tmp/before 2019-12-02 11:54:44.371035723 -0300 +++ /tmp/after 2019-12-02 11:55:31.847859784 -0300 @@ -48,6 +48,7 @@ [0x00000119] = "IA32_BBL_CR_CTL", [0x0000011e] = "IA32_BBL_CR_CTL3", [0x00000120] = "IDT_MCR_CTRL", + [0x00000122] = "IA32_TSX_CTRL", [0x00000140] = "MISC_FEATURES_ENABLES", [0x00000174] = "IA32_SYSENTER_CS", [0x00000175] = "IA32_SYSENTER_ESP", @@ -283,4 +284,6 @@ [0xc0010240 - x86_AMD_V_KVM_MSRs_offset] = "F15H_NB_PERF_CTL", [0xc0010241 - x86_AMD_V_KVM_MSRs_offset] = "F15H_NB_PERF_CTR", [0xc0010280 - x86_AMD_V_KVM_MSRs_offset] = "F15H_PTSC", + [0xc00102f0 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PPIN_CTL", + [0xc00102f1 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PPIN", }; $ CC /tmp/build/perf/trace/beauty/tracepoints/x86_msr.o LD /tmp/build/perf/trace/beauty/tracepoints/perf-in.o LD /tmp/build/perf/trace/beauty/perf-in.o LD /tmp/build/perf/perf-in.o Now it is possible to use these strings when setting up filters for the msr:* tracepoints, like: # perf trace -e msr:* --filter=msr==IA32_TSX_CTRL ^C[root@quaco ~]# If we use an invalid operator we can check what is the filter that is put in place: # perf trace -e msr:* --filter=msr=IA32_TSX_CTRL Failed to set filter "(msr=0x122) && (common_pid != 25976 && common_pid != 25860)" on event msr:read_msr with 22 (Invalid argument) One can as well use -v to see the tracepoints and its filters: # perf trace -v -e msr:* --filter=msr==IA32_TSX_CTRL Using CPUID GenuineIntel-6-8E-A New filter for msr:read_msr: (msr==0x122) && (common_pid != 26110 && common_pid != 25860) New filter for msr:write_msr: (msr==0x122) && (common_pid != 26110 && common_pid != 25860) New filter for msr:rdpmc: (msr==0x122) && (common_pid != 26110 && common_pid != 25860) mmap size 528384B ^C# Better than keep looking up those numbers, works with callchains as well, e.g. for something more common: # perf trace -e msr:*/max-stack=16/ --filter="msr==IA32_SPEC_CTRL" --max-events=2 0.000 SCTP timer/6158 msr:write_msr(msr: IA32_SPEC_CTRL, val: 6) do_trace_write_msr ([kernel.kallsyms]) do_trace_write_msr ([kernel.kallsyms]) __switch_to_xtra ([kernel.kallsyms]) __switch_to ([kernel.kallsyms]) __sched_text_start ([kernel.kallsyms]) schedule ([kernel.kallsyms]) schedule_hrtimeout_range_clock ([kernel.kallsyms]) poll_schedule_timeout.constprop.0 ([kernel.kallsyms]) do_select ([kernel.kallsyms]) core_sys_select ([kernel.kallsyms]) kern_select ([kernel.kallsyms]) __x64_sys_select ([kernel.kallsyms]) do_syscall_64 ([kernel.kallsyms]) entry_SYSCALL_64 ([kernel.kallsyms]) __select (/usr/lib64/libc-2.29.so) [0] ([unknown]) 0.024 :0/0 msr:write_msr(msr: IA32_SPEC_CTRL) do_trace_write_msr ([kernel.kallsyms]) do_trace_write_msr ([kernel.kallsyms]) __switch_to_xtra ([kernel.kallsyms]) __switch_to ([kernel.kallsyms]) __sched_text_start ([kernel.kallsyms]) schedule_idle ([kernel.kallsyms]) do_idle ([kernel.kallsyms]) cpu_startup_entry ([kernel.kallsyms]) start_secondary ([kernel.kallsyms]) [0x2000d4] ([kernel.kallsyms]) # Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Jan Beulich <jbeulich@suse.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Juergen Gross <jgross@suse.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vineela Tummalapalli <vineela.tummalapalli@intel.com> Link: https://lkml.kernel.org/n/tip-n1xd78fpd5lxn4q1brqi2jl6@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> (cherry picked from commit 8122b04) Signed-off-by: Jonathan Maple <jmaple@ciq.com> # Conflicts: # tools/arch/x86/include/asm/msr-index.h
diff --git a/ciq/ciq_backports/kernel-6.12.0-55.43.1.el10_0/8122b047.failed b/ciq/ciq_backports/kernel-6.12.0-55.43.1.el10_0/8122b047.failed
@@ -0,0 +1,233 @@
+tools arch x86: Sync the msr-index.h copy with the kernel sources
+
+jira LE-4694
+Rebuild_History Non-Buildable kernel-6.12.0-55.43.1.el10_0
+commit-author Arnaldo Carvalho de Melo <acme@redhat.com>
+commit 8122b047dd18ef6e7e1c564e28f3c7067c5a2d71
+Empty-Commit: Cherry-Pick Conflicts during history rebuild.
+Will be included in final tarball splat. Ref for failed cherry-pick at:
+ciq/ciq_backports/kernel-6.12.0-55.43.1.el10_0/8122b047.failed
+
+To pick up the changes from these csets:
+
+  3f3c8be973af Merge tag 'for-linus-5.5a-rc1-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip
+  4e3f77d8419b ("xen/mcelog: add PPIN to record when available")
+  db4d30fbb71b ("x86/bugs: Add ITLB_MULTIHIT bug infrastructure")
+  1b42f017415b ("x86/speculation/taa: Add mitigation for TSX Async Abort")
+  c2955f270a84 ("x86/msr: Add the IA32_TSX_CTRL MSR")
+
+These are the changes in tooling that this udpate ensues:
+
+  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > /tmp/before
+  $
+  $ cp arch/x86/include/asm/msr-index.h tools/arch/x86/include/asm/msr-index.h
+  $
+  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > /tmp/after
+  $ diff -u /tmp/before /tmp/after
+  --- /tmp/before	2019-12-02 11:54:44.371035723 -0300
+  +++ /tmp/after	2019-12-02 11:55:31.847859784 -0300
+  @@ -48,6 +48,7 @@
+   	[0x00000119] = "IA32_BBL_CR_CTL",
+   	[0x0000011e] = "IA32_BBL_CR_CTL3",
+   	[0x00000120] = "IDT_MCR_CTRL",
+  +	[0x00000122] = "IA32_TSX_CTRL",
+   	[0x00000140] = "MISC_FEATURES_ENABLES",
+   	[0x00000174] = "IA32_SYSENTER_CS",
+   	[0x00000175] = "IA32_SYSENTER_ESP",
+  @@ -283,4 +284,6 @@
+   	[0xc0010240 - x86_AMD_V_KVM_MSRs_offset] = "F15H_NB_PERF_CTL",
+   	[0xc0010241 - x86_AMD_V_KVM_MSRs_offset] = "F15H_NB_PERF_CTR",
+   	[0xc0010280 - x86_AMD_V_KVM_MSRs_offset] = "F15H_PTSC",
+  +	[0xc00102f0 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PPIN_CTL",
+  +	[0xc00102f1 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PPIN",
+   };
+  $
+
+  CC       /tmp/build/perf/trace/beauty/tracepoints/x86_msr.o
+  LD       /tmp/build/perf/trace/beauty/tracepoints/perf-in.o
+  LD       /tmp/build/perf/trace/beauty/perf-in.o
+  LD       /tmp/build/perf/perf-in.o
+
+Now it is possible to use these strings when setting up filters for the msr:*
+tracepoints, like:
+
+  # perf trace -e msr:* --filter=msr==IA32_TSX_CTRL
+  ^C[root@quaco ~]#
+
+If we use an invalid operator we can check what is the filter that is put in
+place:
+
+  # perf trace -e msr:* --filter=msr=IA32_TSX_CTRL
+  Failed to set filter "(msr=0x122) && (common_pid != 25976 && common_pid != 25860)" on event msr:read_msr with 22 (Invalid argument)
+
+One can as well use -v to see the tracepoints and its filters:
+
+  # perf trace -v -e msr:* --filter=msr==IA32_TSX_CTRL
+  Using CPUID GenuineIntel-6-8E-A
+  New filter for msr:read_msr: (msr==0x122) && (common_pid != 26110 && common_pid != 25860)
+  New filter for msr:write_msr: (msr==0x122) && (common_pid != 26110 && common_pid != 25860)
+  New filter for msr:rdpmc: (msr==0x122) && (common_pid != 26110 && common_pid != 25860)
+  mmap size 528384B
+  ^C#
+
+Better than keep looking up those numbers, works with callchains as
+well, e.g. for something more common:
+
+  # perf trace -e msr:*/max-stack=16/ --filter="msr==IA32_SPEC_CTRL" --max-events=2
+       0.000 SCTP timer/6158 msr:write_msr(msr: IA32_SPEC_CTRL, val: 6)
+                                         do_trace_write_msr ([kernel.kallsyms])
+                                         do_trace_write_msr ([kernel.kallsyms])
+                                         __switch_to_xtra ([kernel.kallsyms])
+                                         __switch_to ([kernel.kallsyms])
+                                         __sched_text_start ([kernel.kallsyms])
+                                         schedule ([kernel.kallsyms])
+                                         schedule_hrtimeout_range_clock ([kernel.kallsyms])
+                                         poll_schedule_timeout.constprop.0 ([kernel.kallsyms])
+                                         do_select ([kernel.kallsyms])
+                                         core_sys_select ([kernel.kallsyms])
+                                         kern_select ([kernel.kallsyms])
+                                         __x64_sys_select ([kernel.kallsyms])
+                                         do_syscall_64 ([kernel.kallsyms])
+                                         entry_SYSCALL_64 ([kernel.kallsyms])
+                                         __select (/usr/lib64/libc-2.29.so)
+                                         [0] ([unknown])
+       0.024 :0/0 msr:write_msr(msr: IA32_SPEC_CTRL)
+                                         do_trace_write_msr ([kernel.kallsyms])
+                                         do_trace_write_msr ([kernel.kallsyms])
+                                         __switch_to_xtra ([kernel.kallsyms])
+                                         __switch_to ([kernel.kallsyms])
+                                         __sched_text_start ([kernel.kallsyms])
+                                         schedule_idle ([kernel.kallsyms])
+                                         do_idle ([kernel.kallsyms])
+                                         cpu_startup_entry ([kernel.kallsyms])
+                                         start_secondary ([kernel.kallsyms])
+                                         [0x2000d4] ([kernel.kallsyms])
+  #
+
+	Cc: Adrian Hunter <adrian.hunter@intel.com>
+	Cc: Jan Beulich <jbeulich@suse.com>
+	Cc: Jiri Olsa <jolsa@kernel.org>
+	Cc: Juergen Gross <jgross@suse.com>
+	Cc: Namhyung Kim <namhyung@kernel.org>
+	Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
+	Cc: Thomas Gleixner <tglx@linutronix.de>
+	Cc: Vineela Tummalapalli <vineela.tummalapalli@intel.com>
+Link: https://lkml.kernel.org/n/tip-n1xd78fpd5lxn4q1brqi2jl6@git.kernel.org
+	Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
+(cherry picked from commit 8122b047dd18ef6e7e1c564e28f3c7067c5a2d71)
+	Signed-off-by: Jonathan Maple <jmaple@ciq.com>
+
+# Conflicts:
+#	tools/arch/x86/include/asm/msr-index.h
+diff --cc tools/arch/x86/include/asm/msr-index.h
+index 3ae84c3b8e6d,084e98da04a7..000000000000
+--- a/tools/arch/x86/include/asm/msr-index.h
++++ b/tools/arch/x86/include/asm/msr-index.h
+@@@ -149,66 -105,6 +149,69 @@@
+  						 * Not susceptible to
+  						 * TSX Async Abort (TAA) vulnerabilities.
+  						 */
+++<<<<<<< HEAD
+ +#define ARCH_CAP_SBDR_SSDP_NO		BIT(13)	/*
+ +						 * Not susceptible to SBDR and SSDP
+ +						 * variants of Processor MMIO stale data
+ +						 * vulnerabilities.
+ +						 */
+ +#define ARCH_CAP_FBSDP_NO		BIT(14)	/*
+ +						 * Not susceptible to FBSDP variant of
+ +						 * Processor MMIO stale data
+ +						 * vulnerabilities.
+ +						 */
+ +#define ARCH_CAP_PSDP_NO		BIT(15)	/*
+ +						 * Not susceptible to PSDP variant of
+ +						 * Processor MMIO stale data
+ +						 * vulnerabilities.
+ +						 */
+ +#define ARCH_CAP_FB_CLEAR		BIT(17)	/*
+ +						 * VERW clears CPU fill buffer
+ +						 * even on MDS_NO CPUs.
+ +						 */
+ +#define ARCH_CAP_FB_CLEAR_CTRL		BIT(18)	/*
+ +						 * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]
+ +						 * bit available to control VERW
+ +						 * behavior.
+ +						 */
+ +#define ARCH_CAP_RRSBA			BIT(19)	/*
+ +						 * Indicates RET may use predictors
+ +						 * other than the RSB. With eIBRS
+ +						 * enabled predictions in kernel mode
+ +						 * are restricted to targets in
+ +						 * kernel.
+ +						 */
+ +#define ARCH_CAP_BHI_NO			BIT(20)	/*
+ +						 * CPU is not affected by Branch
+ +						 * History Injection.
+ +						 */
+ +#define ARCH_CAP_XAPIC_DISABLE		BIT(21)	/*
+ +						 * IA32_XAPIC_DISABLE_STATUS MSR
+ +						 * supported
+ +						 */
+ +#define ARCH_CAP_PBRSB_NO		BIT(24)	/*
+ +						 * Not susceptible to Post-Barrier
+ +						 * Return Stack Buffer Predictions.
+ +						 */
+ +#define ARCH_CAP_GDS_CTRL		BIT(25)	/*
+ +						 * CPU is vulnerable to Gather
+ +						 * Data Sampling (GDS) and
+ +						 * has controls for mitigation.
+ +						 */
+ +#define ARCH_CAP_GDS_NO			BIT(26)	/*
+ +						 * CPU is not vulnerable to Gather
+ +						 * Data Sampling (GDS).
+ +						 */
+ +#define ARCH_CAP_RFDS_NO		BIT(27)	/*
+ +						 * Not susceptible to Register
+ +						 * File Data Sampling.
+ +						 */
+ +#define ARCH_CAP_RFDS_CLEAR		BIT(28)	/*
+ +						 * VERW clears CPU Register
+ +						 * File.
+ +						 */
+++=======
+++>>>>>>> 8122b047dd18 (tools arch x86: Sync the msr-index.h copy with the kernel sources)
+  
+  #define MSR_IA32_FLUSH_CMD		0x0000010b
+  #define L1D_FLUSH			BIT(0)	/*
+@@@ -223,13 -119,6 +226,16 @@@
+  #define TSX_CTRL_RTM_DISABLE		BIT(0)	/* Disable RTM feature */
+  #define TSX_CTRL_CPUID_CLEAR		BIT(1)	/* Disable TSX enumeration */
+  
+++<<<<<<< HEAD
+ +#define MSR_IA32_MCU_OPT_CTRL		0x00000123
+ +#define RNGDS_MITG_DIS			BIT(0)	/* SRBDS support */
+ +#define RTM_ALLOW			BIT(1)	/* TSX development mode */
+ +#define FB_CLEAR_DIS			BIT(3)	/* CPU Fill buffer clear disable */
+ +#define GDS_MITG_DIS			BIT(4)	/* Disable GDS mitigation */
+ +#define GDS_MITG_LOCKED			BIT(5)	/* GDS mitigation locked */
+ +
+++=======
+++>>>>>>> 8122b047dd18 (tools arch x86: Sync the msr-index.h copy with the kernel sources)
+  #define MSR_IA32_SYSENTER_CS		0x00000174
+  #define MSR_IA32_SYSENTER_ESP		0x00000175
+  #define MSR_IA32_SYSENTER_EIP		0x00000176
+@@@ -612,16 -411,8 +618,19 @@@
+  #define MSR_AMD64_OSVW_STATUS		0xc0010141
+  #define MSR_AMD_PPIN_CTL		0xc00102f0
+  #define MSR_AMD_PPIN			0xc00102f1
+++<<<<<<< HEAD
+ +#define MSR_AMD64_CPUID_FN_1		0xc0011004
+++=======
+++>>>>>>> 8122b047dd18 (tools arch x86: Sync the msr-index.h copy with the kernel sources)
+  #define MSR_AMD64_LS_CFG		0xc0011020
+  #define MSR_AMD64_DC_CFG		0xc0011022
+ +#define MSR_AMD64_TW_CFG		0xc0011023
+ +
+ +#define MSR_AMD64_DE_CFG		0xc0011029
+ +#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT	 1
+ +#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE	BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
+ +#define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9
+ +
+  #define MSR_AMD64_BU_CFG2		0xc001102a
+  #define MSR_AMD64_IBSFETCHCTL		0xc0011030
+  #define MSR_AMD64_IBSFETCHLINAD		0xc0011031
+* Unmerged path tools/arch/x86/include/asm/msr-index.h
