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ardbiesheuvelIngo Molnar
ardbiesheuvel
authored and
Ingo Molnar
committed
x86/boot: Move the LA57 trampoline to separate source file
To permit the EFI stub to call this code even when building the kernel without the legacy decompressor, move the trampoline out of the latter's startup code. This is part of an ongoing WIP effort on my part to make the existing, generic EFI zboot format work on x86 as well. No functional change intended. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20250313120324.1095968-2-ardb+git@google.com
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‎arch/x86/boot/compressed/Makefile‎

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Original file line numberDiff line numberDiff line change
@@ -98,6 +98,7 @@ ifdef CONFIG_X86_64
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vmlinux-objs-$(CONFIG_AMD_MEM_ENCRYPT) += $(obj)/mem_encrypt.o
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vmlinux-objs-y += $(obj)/pgtable_64.o
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vmlinux-objs-$(CONFIG_AMD_MEM_ENCRYPT) += $(obj)/sev.o
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vmlinux-objs-y += $(obj)/la57toggle.o
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endif
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vmlinux-objs-$(CONFIG_ACPI) += $(obj)/acpi.o

‎arch/x86/boot/compressed/head_64.S‎

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@@ -483,110 +483,7 @@ SYM_FUNC_START_LOCAL_NOALIGN(.Lrelocated)
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jmp *%rax
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SYM_FUNC_END(.Lrelocated)
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/*
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* This is the 32-bit trampoline that will be copied over to low memory. It
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* will be called using the ordinary 64-bit calling convention from code
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* running in 64-bit mode.
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*
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* Return address is at the top of the stack (might be above 4G).
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* The first argument (EDI) contains the address of the temporary PGD level
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* page table in 32-bit addressable memory which will be programmed into
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* register CR3.
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*/
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.section ".rodata", "a", @progbits
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SYM_CODE_START(trampoline_32bit_src)
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/*
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* Preserve callee save 64-bit registers on the stack: this is
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* necessary because the architecture does not guarantee that GPRs will
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* retain their full 64-bit values across a 32-bit mode switch.
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*/
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pushq %r15
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pushq %r14
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pushq %r13
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pushq %r12
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pushq %rbp
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pushq %rbx
509-
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/* Preserve top half of RSP in a legacy mode GPR to avoid truncation */
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movq %rsp, %rbx
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shrq $32, %rbx
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/* Switch to compatibility mode (CS.L = 0 CS.D = 1) via far return */
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pushq $__KERNEL32_CS
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leaq 0f(%rip), %rax
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pushq %rax
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lretq
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/*
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* The 32-bit code below will do a far jump back to long mode and end
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* up here after reconfiguring the number of paging levels. First, the
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* stack pointer needs to be restored to its full 64-bit value before
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* the callee save register contents can be popped from the stack.
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*/
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.Lret:
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shlq $32, %rbx
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orq %rbx, %rsp
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/* Restore the preserved 64-bit registers */
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popq %rbx
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popq %rbp
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popq %r12
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popq %r13
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popq %r14
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popq %r15
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retq
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.code32
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0:
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/* Disable paging */
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movl %cr0, %eax
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btrl $X86_CR0_PG_BIT, %eax
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movl %eax, %cr0
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/* Point CR3 to the trampoline's new top level page table */
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movl %edi, %cr3
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/* Set EFER.LME=1 as a precaution in case hypervsior pulls the rug */
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movl $MSR_EFER, %ecx
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rdmsr
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btsl $_EFER_LME, %eax
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/* Avoid writing EFER if no change was made (for TDX guest) */
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jc 1f
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wrmsr
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1:
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/* Toggle CR4.LA57 */
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movl %cr4, %eax
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btcl $X86_CR4_LA57_BIT, %eax
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movl %eax, %cr4
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/* Enable paging again. */
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movl %cr0, %eax
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btsl $X86_CR0_PG_BIT, %eax
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movl %eax, %cr0
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/*
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* Return to the 64-bit calling code using LJMP rather than LRET, to
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* avoid the need for a 32-bit addressable stack. The destination
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* address will be adjusted after the template code is copied into a
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* 32-bit addressable buffer.
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*/
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.Ljmp: ljmpl $__KERNEL_CS, $(.Lret - trampoline_32bit_src)
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SYM_CODE_END(trampoline_32bit_src)
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/*
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* This symbol is placed right after trampoline_32bit_src() so its address can
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* be used to infer the size of the trampoline code.
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*/
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SYM_DATA(trampoline_ljmp_imm_offset, .word .Ljmp + 1 - trampoline_32bit_src)
581-
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/*
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* The trampoline code has a size limit.
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* Make sure we fail to compile if the trampoline code grows
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* beyond TRAMPOLINE_32BIT_CODE_SIZE bytes.
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*/
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.org trampoline_32bit_src + TRAMPOLINE_32BIT_CODE_SIZE
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.text
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SYM_FUNC_START_LOCAL_NOALIGN(.Lno_longmode)
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/* This isn't an x86-64 CPU, so hang intentionally, we cannot continue */
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1:

‎arch/x86/boot/compressed/la57toggle.S‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,112 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/linkage.h>
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#include <asm/segment.h>
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#include <asm/boot.h>
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#include <asm/msr.h>
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#include <asm/processor-flags.h>
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#include "pgtable.h"
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/*
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* This is the 32-bit trampoline that will be copied over to low memory. It
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* will be called using the ordinary 64-bit calling convention from code
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* running in 64-bit mode.
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*
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* Return address is at the top of the stack (might be above 4G).
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* The first argument (EDI) contains the address of the temporary PGD level
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* page table in 32-bit addressable memory which will be programmed into
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* register CR3.
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*/
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.section ".rodata", "a", @progbits
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SYM_CODE_START(trampoline_32bit_src)
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/*
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* Preserve callee save 64-bit registers on the stack: this is
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* necessary because the architecture does not guarantee that GPRs will
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* retain their full 64-bit values across a 32-bit mode switch.
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*/
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pushq %r15
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pushq %r14
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pushq %r13
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pushq %r12
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pushq %rbp
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pushq %rbx
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/* Preserve top half of RSP in a legacy mode GPR to avoid truncation */
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movq %rsp, %rbx
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shrq $32, %rbx
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/* Switch to compatibility mode (CS.L = 0 CS.D = 1) via far return */
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pushq $__KERNEL32_CS
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leaq 0f(%rip), %rax
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pushq %rax
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lretq
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/*
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* The 32-bit code below will do a far jump back to long mode and end
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* up here after reconfiguring the number of paging levels. First, the
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* stack pointer needs to be restored to its full 64-bit value before
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* the callee save register contents can be popped from the stack.
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*/
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.Lret:
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shlq $32, %rbx
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orq %rbx, %rsp
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/* Restore the preserved 64-bit registers */
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popq %rbx
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popq %rbp
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popq %r12
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popq %r13
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popq %r14
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popq %r15
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retq
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.code32
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0:
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/* Disable paging */
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movl %cr0, %eax
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btrl $X86_CR0_PG_BIT, %eax
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movl %eax, %cr0
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71+
/* Point CR3 to the trampoline's new top level page table */
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movl %edi, %cr3
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74+
/* Set EFER.LME=1 as a precaution in case hypervsior pulls the rug */
75+
movl $MSR_EFER, %ecx
76+
rdmsr
77+
btsl $_EFER_LME, %eax
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/* Avoid writing EFER if no change was made (for TDX guest) */
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jc 1f
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wrmsr
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1:
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/* Toggle CR4.LA57 */
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movl %cr4, %eax
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btcl $X86_CR4_LA57_BIT, %eax
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movl %eax, %cr4
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/* Enable paging again. */
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movl %cr0, %eax
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btsl $X86_CR0_PG_BIT, %eax
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movl %eax, %cr0
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/*
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* Return to the 64-bit calling code using LJMP rather than LRET, to
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* avoid the need for a 32-bit addressable stack. The destination
95+
* address will be adjusted after the template code is copied into a
96+
* 32-bit addressable buffer.
97+
*/
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.Ljmp: ljmpl $__KERNEL_CS, $(.Lret - trampoline_32bit_src)
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SYM_CODE_END(trampoline_32bit_src)
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/*
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* This symbol is placed right after trampoline_32bit_src() so its address can
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* be used to infer the size of the trampoline code.
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*/
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SYM_DATA(trampoline_ljmp_imm_offset, .word .Ljmp + 1 - trampoline_32bit_src)
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107+
/*
108+
* The trampoline code has a size limit.
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* Make sure we fail to compile if the trampoline code grows
110+
* beyond TRAMPOLINE_32BIT_CODE_SIZE bytes.
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*/
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.org trampoline_32bit_src + TRAMPOLINE_32BIT_CODE_SIZE

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