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hkasivisgregkh
hkasivis
authored and
gregkh
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drm/amdkfd: Set per-process flags only once for gfx9/10/11/12
[ Upstream commit 61972cd ] Define set_cache_memory_policy() for these asics and move all static changes from update_qpd() which is called each time a queue is created to set_cache_memory_policy() which is called once during process initialization Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by: Amber Lin <Amber.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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-52
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4 files changed

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-52
lines changed

‎drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c‎

Lines changed: 24 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -31,10 +31,17 @@ static int update_qpd_v10(struct device_queue_manager *dqm,
3131
struct qcm_process_device *qpd);
3232
static void init_sdma_vm_v10(struct device_queue_manager *dqm, struct queue *q,
3333
struct qcm_process_device *qpd);
34+
static bool set_cache_memory_policy_v10(struct device_queue_manager *dqm,
35+
struct qcm_process_device *qpd,
36+
enum cache_policy default_policy,
37+
enum cache_policy alternate_policy,
38+
void __user *alternate_aperture_base,
39+
uint64_t alternate_aperture_size);
3440

3541
void device_queue_manager_init_v10(
3642
struct device_queue_manager_asic_ops *asic_ops)
3743
{
44+
asic_ops->set_cache_memory_policy = set_cache_memory_policy_v10;
3845
asic_ops->update_qpd = update_qpd_v10;
3946
asic_ops->init_sdma_vm = init_sdma_vm_v10;
4047
asic_ops->mqd_manager_init = mqd_manager_init_v10;
@@ -49,27 +56,27 @@ static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
4956
private_base;
5057
}
5158

52-
static int update_qpd_v10(struct device_queue_manager *dqm,
53-
struct qcm_process_device *qpd)
59+
static bool set_cache_memory_policy_v10(struct device_queue_manager *dqm,
60+
struct qcm_process_device *qpd,
61+
enum cache_policy default_policy,
62+
enum cache_policy alternate_policy,
63+
void __user *alternate_aperture_base,
64+
uint64_t alternate_aperture_size)
5465
{
55-
struct kfd_process_device *pdd;
56-
57-
pdd = qpd_to_pdd(qpd);
58-
59-
/* check if sh_mem_config register already configured */
60-
if (qpd->sh_mem_config == 0) {
61-
qpd->sh_mem_config =
62-
(SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
63-
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
64-
(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
65-
qpd->sh_mem_ape1_limit = 0;
66-
qpd->sh_mem_ape1_base = 0;
67-
}
68-
69-
qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
66+
qpd->sh_mem_config = (SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
67+
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
68+
(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
69+
qpd->sh_mem_ape1_limit = 0;
70+
qpd->sh_mem_ape1_base = 0;
71+
qpd->sh_mem_bases = compute_sh_mem_bases_64bit(qpd_to_pdd(qpd));
7072

7173
pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
74+
return true;
75+
}
7276

77+
static int update_qpd_v10(struct device_queue_manager *dqm,
78+
struct qcm_process_device *qpd)
79+
{
7380
return 0;
7481
}
7582

‎drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v11.c‎

Lines changed: 24 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -30,10 +30,17 @@ static int update_qpd_v11(struct device_queue_manager *dqm,
3030
struct qcm_process_device *qpd);
3131
static void init_sdma_vm_v11(struct device_queue_manager *dqm, struct queue *q,
3232
struct qcm_process_device *qpd);
33+
static bool set_cache_memory_policy_v11(struct device_queue_manager *dqm,
34+
struct qcm_process_device *qpd,
35+
enum cache_policy default_policy,
36+
enum cache_policy alternate_policy,
37+
void __user *alternate_aperture_base,
38+
uint64_t alternate_aperture_size);
3339

3440
void device_queue_manager_init_v11(
3541
struct device_queue_manager_asic_ops *asic_ops)
3642
{
43+
asic_ops->set_cache_memory_policy = set_cache_memory_policy_v11;
3744
asic_ops->update_qpd = update_qpd_v11;
3845
asic_ops->init_sdma_vm = init_sdma_vm_v11;
3946
asic_ops->mqd_manager_init = mqd_manager_init_v11;
@@ -48,28 +55,28 @@ static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
4855
private_base;
4956
}
5057

51-
static int update_qpd_v11(struct device_queue_manager *dqm,
52-
struct qcm_process_device *qpd)
58+
static bool set_cache_memory_policy_v11(struct device_queue_manager *dqm,
59+
struct qcm_process_device *qpd,
60+
enum cache_policy default_policy,
61+
enum cache_policy alternate_policy,
62+
void __user *alternate_aperture_base,
63+
uint64_t alternate_aperture_size)
5364
{
54-
struct kfd_process_device *pdd;
55-
56-
pdd = qpd_to_pdd(qpd);
57-
58-
/* check if sh_mem_config register already configured */
59-
if (qpd->sh_mem_config == 0) {
60-
qpd->sh_mem_config =
61-
(SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
62-
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
63-
(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
64-
65-
qpd->sh_mem_ape1_limit = 0;
66-
qpd->sh_mem_ape1_base = 0;
67-
}
65+
qpd->sh_mem_config = (SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
66+
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
67+
(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
6868

69-
qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
69+
qpd->sh_mem_ape1_limit = 0;
70+
qpd->sh_mem_ape1_base = 0;
71+
qpd->sh_mem_bases = compute_sh_mem_bases_64bit(qpd_to_pdd(qpd));
7072

7173
pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
74+
return true;
75+
}
7276

77+
static int update_qpd_v11(struct device_queue_manager *dqm,
78+
struct qcm_process_device *qpd)
79+
{
7380
return 0;
7481
}
7582

‎drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12.c‎

Lines changed: 24 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -30,10 +30,17 @@ static int update_qpd_v12(struct device_queue_manager *dqm,
3030
struct qcm_process_device *qpd);
3131
static void init_sdma_vm_v12(struct device_queue_manager *dqm, struct queue *q,
3232
struct qcm_process_device *qpd);
33+
static bool set_cache_memory_policy_v12(struct device_queue_manager *dqm,
34+
struct qcm_process_device *qpd,
35+
enum cache_policy default_policy,
36+
enum cache_policy alternate_policy,
37+
void __user *alternate_aperture_base,
38+
uint64_t alternate_aperture_size);
3339

3440
void device_queue_manager_init_v12(
3541
struct device_queue_manager_asic_ops *asic_ops)
3642
{
43+
asic_ops->set_cache_memory_policy = set_cache_memory_policy_v12;
3744
asic_ops->update_qpd = update_qpd_v12;
3845
asic_ops->init_sdma_vm = init_sdma_vm_v12;
3946
asic_ops->mqd_manager_init = mqd_manager_init_v12;
@@ -48,28 +55,28 @@ static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
4855
private_base;
4956
}
5057

51-
static int update_qpd_v12(struct device_queue_manager *dqm,
52-
struct qcm_process_device *qpd)
58+
static bool set_cache_memory_policy_v12(struct device_queue_manager *dqm,
59+
struct qcm_process_device *qpd,
60+
enum cache_policy default_policy,
61+
enum cache_policy alternate_policy,
62+
void __user *alternate_aperture_base,
63+
uint64_t alternate_aperture_size)
5364
{
54-
struct kfd_process_device *pdd;
55-
56-
pdd = qpd_to_pdd(qpd);
57-
58-
/* check if sh_mem_config register already configured */
59-
if (qpd->sh_mem_config == 0) {
60-
qpd->sh_mem_config =
61-
(SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
62-
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
63-
(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
64-
65-
qpd->sh_mem_ape1_limit = 0;
66-
qpd->sh_mem_ape1_base = 0;
67-
}
65+
qpd->sh_mem_config = (SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
66+
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
67+
(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
6868

69-
qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
69+
qpd->sh_mem_ape1_limit = 0;
70+
qpd->sh_mem_ape1_base = 0;
71+
qpd->sh_mem_bases = compute_sh_mem_bases_64bit(qpd_to_pdd(qpd));
7072

7173
pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
74+
return true;
75+
}
7276

77+
static int update_qpd_v12(struct device_queue_manager *dqm,
78+
struct qcm_process_device *qpd)
79+
{
7380
return 0;
7481
}
7582

‎drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c‎

Lines changed: 35 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,10 +30,17 @@ static int update_qpd_v9(struct device_queue_manager *dqm,
3030
struct qcm_process_device *qpd);
3131
static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q,
3232
struct qcm_process_device *qpd);
33+
static bool set_cache_memory_policy_v9(struct device_queue_manager *dqm,
34+
struct qcm_process_device *qpd,
35+
enum cache_policy default_policy,
36+
enum cache_policy alternate_policy,
37+
void __user *alternate_aperture_base,
38+
uint64_t alternate_aperture_size);
3339

3440
void device_queue_manager_init_v9(
3541
struct device_queue_manager_asic_ops *asic_ops)
3642
{
43+
asic_ops->set_cache_memory_policy = set_cache_memory_policy_v9;
3744
asic_ops->update_qpd = update_qpd_v9;
3845
asic_ops->init_sdma_vm = init_sdma_vm_v9;
3946
asic_ops->mqd_manager_init = mqd_manager_init_v9;
@@ -48,10 +55,37 @@ static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
4855
private_base;
4956
}
5057

58+
static bool set_cache_memory_policy_v9(struct device_queue_manager *dqm,
59+
struct qcm_process_device *qpd,
60+
enum cache_policy default_policy,
61+
enum cache_policy alternate_policy,
62+
void __user *alternate_aperture_base,
63+
uint64_t alternate_aperture_size)
64+
{
65+
qpd->sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
66+
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
67+
68+
if (dqm->dev->kfd->noretry)
69+
qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
70+
71+
if (KFD_GC_VERSION(dqm->dev->kfd) == IP_VERSION(9, 4, 3) ||
72+
KFD_GC_VERSION(dqm->dev->kfd) == IP_VERSION(9, 4, 4) ||
73+
KFD_GC_VERSION(dqm->dev->kfd) == IP_VERSION(9, 5, 0))
74+
qpd->sh_mem_config |= (1 << SH_MEM_CONFIG__F8_MODE__SHIFT);
75+
76+
qpd->sh_mem_ape1_limit = 0;
77+
qpd->sh_mem_ape1_base = 0;
78+
qpd->sh_mem_bases = compute_sh_mem_bases_64bit(qpd_to_pdd(qpd));
79+
80+
pr_debug("sh_mem_bases 0x%X sh_mem_config 0x%X\n", qpd->sh_mem_bases,
81+
qpd->sh_mem_config);
82+
return true;
83+
}
84+
5185
static int update_qpd_v9(struct device_queue_manager *dqm,
5286
struct qcm_process_device *qpd)
5387
{
54-
struct kfd_process_device *pdd;
88+
struct kfd_process_device *pdd = qpd_to_pdd(qpd);
5589

5690
pdd = qpd_to_pdd(qpd);
5791

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