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Merge: Expand arm SSBS table to match upstream + RHEL10
MR: https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-9/-/merge_requests/7226 # Merge Request Required Information ## Summary of Changes Expand arm64 SSBS tables to include more cores. ## Approved Development Ticket(s) https://issues.redhat.com/browse/RHEL-108306 <details><summary>RHEL9/Centos9 SSBS mitigations expand to include more cores</summary> Resolves: RHEL-108306 </details> JIRA: https://issues.redhat.com/browse/RHEL-108306 Signed-off-by: Jeremy Linton <jlinton@redhat.com> Approved-by: Charles Mirabile <cmirabil@redhat.com> Approved-by: Mark Salter <msalter@redhat.com> Approved-by: CKI KWF Bot <cki-ci-bot+kwf-gitlab-com@redhat.com> Merged-by: CKI GitLab Kmaint Pipeline Bot <26919896-cki-kmaint-pipeline-bot@users.noreply.gitlab.com>
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‎Documentation/arm64/silicon-errata.rst‎

Lines changed: 28 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -126,17 +126,27 @@ stable kernels.
126126
+----------------+-----------------+-----------------+-----------------------------+
127127
| ARM | Cortex-A76 | #1490853 | N/A |
128128
+----------------+-----------------+-----------------+-----------------------------+
129+
| ARM | Cortex-A76 | #3324349 | ARM64_ERRATUM_3194386 |
130+
+----------------+-----------------+-----------------+-----------------------------+
129131
| ARM | Cortex-A77 | #1491015 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
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+----------------+-----------------+-----------------+-----------------------------+
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<<<<<<< HEAD:Documentation/arm64/silicon-errata.rst
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| ARM | Cortex-A510 | #2051678 | ARM64_ERRATUM_2051678 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2077057 | ARM64_ERRATUM_2077057 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2441009 | ARM64_ERRATUM_2441009 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2658417 | ARM64_ERRATUM_2658417 |
143+
=======
144+
| ARM | Cortex-A77 | #3324348 | ARM64_ERRATUM_3194386 |
145+
+----------------+-----------------+-----------------+-----------------------------+
146+
| ARM | Cortex-A78 | #3324344 | ARM64_ERRATUM_3194386 |
147+
+----------------+-----------------+-----------------+-----------------------------+
148+
| ARM | Cortex-A78C | #3324346,3324347| ARM64_ERRATUM_3194386 |
149+
>>>>>>> adeec61a4723 (arm64: errata: Expand speculative SSBS workaround (again)):Documentation/arch/arm64/silicon-errata.rst
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
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+----------------+-----------------+-----------------+-----------------------------+
@@ -148,10 +158,18 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A715 | #2645198 | ARM64_ERRATUM_2645198 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A715 | #3456084 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
165+
| ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X1 | #1502854 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
169+
| ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 |
170+
+----------------+-----------------+-----------------+-----------------------------+
171+
| ARM | Cortex-X1C | #3324346 | ARM64_ERRATUM_3194386 |
172+
+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 |
@@ -172,6 +190,8 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 |
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+----------------+-----------------+-----------------+-----------------------------+
193+
| ARM | Neoverse-N1 | #3324349 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 |
@@ -180,12 +200,16 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N2 | #3324339 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N3 | #3456111 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
205+
| ARM | Neoverse-V1 | #1619801 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
207+
| ARM | Neoverse-V1 | #3324341 | ARM64_ERRATUM_3194386 |
208+
+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
187-
| ARM | Neoverse-V1 | #1619801 | N/A |
188-
+----------------+-----------------+-----------------+-----------------------------+
189213
| ARM | MMU-500 | #841119,826419 | ARM_SMMU_MMU_500_CPRE_ERRATA|
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| | | #562869,1047329 | |
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+----------------+-----------------+-----------------+-----------------------------+
@@ -282,3 +306,5 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| Microsoft | Azure Cobalt 100| #2253138 | ARM64_ERRATUM_2253138 |
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+----------------+-----------------+-----------------+-----------------------------+
309+
| Microsoft | Azure Cobalt 100| #3324339 | ARM64_ERRATUM_3194386 |
310+
+----------------+-----------------+-----------------+-----------------------------+

‎arch/arm64/Kconfig‎

Lines changed: 18 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1058,30 +1058,42 @@ config ARM64_ERRATUM_3117295
10581058
If unsure, say Y.
10591059

10601060
config ARM64_ERRATUM_3194386
1061-
bool "Cortex-{A720,X4,X925}/Neoverse-V3: workaround for MSR SSBS not self-synchronizing"
1061+
bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
10621062
default y
10631063
help
10641064
This option adds the workaround for the following errata:
10651065

1066+
* ARM Cortex-A76 erratum 3324349
1067+
* ARM Cortex-A77 erratum 3324348
1068+
* ARM Cortex-A78 erratum 3324344
1069+
* ARM Cortex-A78C erratum 3324346
1070+
* ARM Cortex-A78C erratum 3324347
10661071
* ARM Cortex-A710 erratam 3324338
1072+
* ARM Cortex-A715 errartum 3456084
10671073
* ARM Cortex-A720 erratum 3456091
1074+
* ARM Cortex-A725 erratum 3456106
1075+
* ARM Cortex-X1 erratum 3324344
1076+
* ARM Cortex-X1C erratum 3324346
10681077
* ARM Cortex-X2 erratum 3324338
10691078
* ARM Cortex-X3 erratum 3324335
10701079
* ARM Cortex-X4 erratum 3194386
10711080
* ARM Cortex-X925 erratum 3324334
1081+
* ARM Neoverse-N1 erratum 3324349
10721082
* ARM Neoverse N2 erratum 3324339
1083+
* ARM Neoverse-N3 erratum 3456111
1084+
* ARM Neoverse-V1 erratum 3324341
10731085
* ARM Neoverse V2 erratum 3324336
10741086
* ARM Neoverse-V3 erratum 3312417
10751087

10761088
On affected cores "MSR SSBS, #0" instructions may not affect
10771089
subsequent speculative instructions, which may permit unexepected
10781090
speculative store bypassing.
10791091

1080-
Work around this problem by placing a speculation barrier after
1081-
kernel changes to SSBS. The presence of the SSBS special-purpose
1082-
register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such
1083-
that userspace will use the PR_SPEC_STORE_BYPASS prctl to change
1084-
SSBS.
1092+
Work around this problem by placing a Speculation Barrier (SB) or
1093+
Instruction Synchronization Barrier (ISB) after kernel changes to
1094+
SSBS. The presence of the SSBS special-purpose register is hidden
1095+
from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace
1096+
will use the PR_SPEC_STORE_BYPASS prctl to change SSBS.
10851097

10861098
If unsure, say Y.
10871099

‎arch/arm64/include/asm/cputype.h‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -87,12 +87,15 @@
8787
#define ARM_CPU_PART_CORTEX_X2 0xD48
8888
#define ARM_CPU_PART_NEOVERSE_N2 0xD49
8989
#define ARM_CPU_PART_CORTEX_A78C 0xD4B
90+
#define ARM_CPU_PART_CORTEX_X1C 0xD4C
9091
#define ARM_CPU_PART_CORTEX_X3 0xD4E
9192
#define ARM_CPU_PART_NEOVERSE_V2 0xD4F
9293
#define ARM_CPU_PART_CORTEX_A720 0xD81
9394
#define ARM_CPU_PART_CORTEX_X4 0xD82
9495
#define ARM_CPU_PART_NEOVERSE_V3 0xD84
9596
#define ARM_CPU_PART_CORTEX_X925 0xD85
97+
#define ARM_CPU_PART_CORTEX_A725 0xD87
98+
#define ARM_CPU_PART_NEOVERSE_N3 0xD8E
9699

97100
#define APM_CPU_PART_XGENE 0x000
98101
#define APM_CPU_VAR_POTENZA 0x00
@@ -168,12 +171,15 @@
168171
#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
169172
#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
170173
#define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
174+
#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C)
171175
#define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3)
172176
#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
173177
#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)
174178
#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
175179
#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
176180
#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
181+
#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
182+
#define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
177183
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
178184
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
179185
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

‎arch/arm64/kernel/cpu_errata.c‎

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -434,15 +434,27 @@ static const struct midr_range erratum_spec_unpriv_load_list[] = {
434434

435435
#ifdef CONFIG_ARM64_ERRATUM_3194386
436436
static const struct midr_range erratum_spec_ssbs_list[] = {
437+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
438+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
439+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
440+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
437441
MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
442+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
438443
MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
444+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
445+
MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
446+
MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
439447
MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
440448
MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
441449
MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
442450
MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
451+
MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
452+
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
443453
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
444-
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
454+
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3),
455+
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
445456
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
457+
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
446458
{}
447459
};
448460
#endif

‎tools/arch/arm64/include/asm/cputype.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -94,6 +94,7 @@
9494
#define ARM_CPU_PART_NEOVERSE_V3 0xD84
9595
#define ARM_CPU_PART_CORTEX_X925 0xD85
9696
#define ARM_CPU_PART_CORTEX_A725 0xD87
97+
#define ARM_CPU_PART_NEOVERSE_N3 0xD8E
9798

9899
#define APM_CPU_PART_XGENE 0x000
99100
#define APM_CPU_VAR_POTENZA 0x00
@@ -176,6 +177,7 @@
176177
#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
177178
#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
178179
#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
180+
#define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
179181
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
180182
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
181183
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

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