Merge: Rebase kernel's PCI subsystem with content from v6.15

MR: https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-10/-/merge_requests/1388

```
    PCI updates from v6.15:
     "Enumeration:

       - Enable Configuration RRS SV, which makes device readiness visible,
         early instead of during child bus scanning (Bjorn Helgaas)

       - Log debug messages about reset methods being used (Bjorn Helgaas)

       - Add common pci-ep-bus.yaml schema for exporting several peripherals
         of a single PCI function via devicetree (Andrea della Porta)

       - Create DT nodes for PCI host bridges to enable loading device tree
         overlays to create platform devices for PCI devices that have
         several features that require multiple drivers (Herve Codina)

      Resource management:

       - Enlarge devres table[] to accommodate bridge windows, ROM, IOV
         BARs, etc., and validate BAR index in devres interfaces (Philipp
         Stanner)

       - Fix typo that repeatedly distributed resources to a bridge instead
         of iterating over subordinate bridges, which resulted in too little
         space to assign some BARs (Kai-Heng Feng)

       - Relax bridge window tail sizing for optional resources, e.g., IOV
         BARs, to avoid failures when removing and re-adding devices (Ilpo
         Järvinen)

       - Allow drivers to enable devices even if we haven't assigned
         optional IOV resources to them (Ilpo Järvinen)

       - Rework handling of optional resources (IOV BARs, ROMs) to reduce
         failures if we can't allocate them (Ilpo Järvinen)

       - Fix a NULL dereference in the SR-IOV VF creation error path (Shay
         Drory)

       - Fix s390 mmio_read/write syscalls, which didn't cause page faults
         in some cases, which broke vfio-pci lazy mapping on first access
         (Niklas Schnelle)

       - Add pdev->non_mappable_bars to replace CONFIG_VFIO_PCI_MMAP, which
         was disabled only for s390 (Niklas Schnelle)

       - Support mmap of PCI resources on s390 except for ISM devices
         (Niklas Schnelle)

      ASPM:

       - Delay pcie_link_state deallocation to avoid dangling pointers that
         cause invalid references during hot-unplug (Daniel Stodden)

      Power management:

       - Allow PCI bridges to go to D3Hot when suspending on all non-x86
         systems (Manivannan Sadhasivam)

      Bandwidth control:

       - Add set_pcie_speed.sh to TEST_PROGS to fix issue when executing the
         set_pcie_cooling_state.sh test case (Yi Lai)

       - Avoid a NULL pointer dereference when we run out of bus numbers to
         assign for a bridge secondary bus (Lukas Wunner)

      Hotplug:

       - Drop superfluous pci_hotplug_slot_list, try_module_get() calls, and
         NULL pointer checks (Lukas Wunner)

       - Drop shpchp module init/exit logging, replace shpchp dbg() with
         ctrl_dbg(), and remove unused dbg(), err(), info(), warn() wrappers
         (Ilpo Järvinen)

       - Drop 'shpchp_debug' module parameter in favor of standard dynamic
         debugging (Ilpo Järvinen)

       - Drop unused cpcihp .get_power(), .set_power() function pointers
         (Guilherme Giacomo Simoes)

       - Disable hotplug interrupts in portdrv only when pciehp is not
         enabled to avoid issuing two hotplug commands too close together
         (Feng Tang)

       - Skip pciehp 'device replaced' check if the device has been removed
         to address a deadlock when resuming after a device was removed
         during system sleep (Lukas Wunner)

       - Don't enable pciehp hotplug interupt when resuming in poll mode
         (Ilpo Järvinen)

      Virtualization:

       - Fix bugs in 'pci=config_acs=' kernel command line parameter (Tushar
         Dave)

      DOE:

       - Expose supported DOE features via sysfs (Alistair Francis)

       - Allow DOE support to be enabled even if CXL isn't enabled (Alistair
         Francis)

      Endpoint framework:

       - Convert PCI device data so pci-epf-test works correctly on
         big-endian endpoint systems (Niklas Cassel)

       - Add BAR_RESIZABLE type to endpoint framework and add DWC core
         support for EPF drivers to set BAR_RESIZABLE type and size (Niklas
         Cassel)

       - Fix pci-epf-test double free that causes an oops if the host
         reboots and PERST# deassertion restarts endpoint BAR allocation
         (Christian Bruel)

       - Fix endpoint BAR testing so tests can skip disabled BARs instead of
         reporting them as failures (Niklas Cassel)

       - Widen endpoint test BAR size variable to accommodate BARs larger
         than INT_MAX (Niklas Cassel)

       - Remove unused tools 'pci' build target left over after moving tests
         to tools/testing/selftests/pci_endpoint (Jianfeng Liu)

      Altera PCIe controller driver:

       - Add DT binding and driver support for Agilex family (P-Tile,
         F-Tile, R-Tile) (Matthew Gerlach and D M, Sharath Kumar)

      Broadcom STB PCIe controller driver:

       - Add BCM2712 MSI-X DT binding and interrupt controller drivers and
         add softdep on irq_bcm2712_mip driver to ensure that it is loaded
         first (Stanimir Varbanov)

       - Expand inbound window map to 64GB so it can accommodate BCM2712
         (Stanimir Varbanov)

       - Add BCM2712 support and DT updates (Stanimir Varbanov)

       - Apply link speed restriction before bringing link up, not after
         (Jim Quinlan)

       - Update Max Link Speed in Link Capabilities via the internal
         writable register, not the read-only config register (Jim Quinlan)

       - Handle regulator_bulk_get() error to avoid panic when we call
         regulator_bulk_free() later (Jim Quinlan)

       - Disable regulators only when removing the bus immediately below a
         Root Port because we don't support regulators deeper in the
         hierarchy (Jim Quinlan)

       - Make const read-only arrays static (Colin Ian King)

      Cadence PCIe endpoint driver:

       - Correct MSG TLP generation so endpoints can generate INTx messages
         (Hans Zhang)

      Freescale i.MX6 PCIe controller driver:

       - Identify the second controller on i.MX8MQ based on devicetree
         'linux,pci-domain' instead of DBI 'reg' address (Richard Zhu)

       - Remove imx_pcie_cpu_addr_fixup() since dwc core can now derive the
         ATU input address (using parent_bus_offset) from devicetree (Frank
         Li)

      Freescale Layerscape PCIe controller driver:

       - Drop deprecated 'num-ib-windows' and 'num-ob-windows' and
         unnecessary 'status' from example (Krzysztof Kozlowski)

       - Correct the syscon_regmap_lookup_by_phandle_args("fsl,pcie-scfg")
         arg_count to fix probe failure on LS1043A (Ioana Ciornei)

      HiSilicon STB PCIe controller driver:

       - Call phy_exit() to clean up if histb_pcie_probe() fails (Christophe
         JAILLET)

      Intel Gateway PCIe controller driver:

       - Remove intel_pcie_cpu_addr() since dwc core can now derive the ATU
         input address (using parent_bus_offset) from devicetree (Frank Li)

      Intel VMD host bridge driver:

       - Convert vmd_dev.cfg_lock from spinlock_t to raw_spinlock_t so
         pci_ops.read() will never sleep, even on PREEMPT_RT where
         spinlock_t becomes a sleepable lock, to avoid calling a sleeping
         function from invalid context (Ryo Takakura)

      MediaTek PCIe Gen3 controller driver:

       - Remove leftover mac_reset assert for Airoha EN7581 SoC (Lorenzo
         Bianconi)

       - Add EN7581 PBUS controller 'mediatek,pbus-csr' DT property and
         program host bridge memory aperture to this syscon node (Lorenzo
         Bianconi)

      Qualcomm PCIe controller driver:

       - Add qcom,pcie-ipq5332 binding (Varadarajan Narayanan)

       - Add qcom i.MX8QM and i.MX8QXP/DXP optional DMA interrupt (Alexander
         Stein)

       - Add optional dma-coherent DT property for Qualcomm SA8775P (Dmitry
         Baryshkov)

       - Make DT iommu property required for SA8775P and prohibited for
         SDX55 (Dmitry Baryshkov)

       - Add DT IOMMU and DMA-related properties for Qualcomm SM8450 (Dmitry
         Baryshkov)

       - Add endpoint DT properties for SAR2130P and enable endpoint mode in
         driver (Dmitry Baryshkov)

       - Describe endpoint BAR0 and BAR2 as 64-bit only and BAR1 and BAR3 as
         RESERVED (Manivannan Sadhasivam)

      Rockchip DesignWare PCIe controller driver:

       - Describe rk3568 and rk3588 BARs as Resizable, not Fixed (Niklas
         Cassel)

      Synopsys DesignWare PCIe controller driver:

       - Add debugfs-based Silicon Debug, Error Injection, Statistical
         Counter support for DWC (Shradha Todi)

       - Add debugfs property to expose LTSSM status of DWC PCIe link (Hans
         Zhang)

       - Add Rockchip support for DWC debugfs features (Niklas Cassel)

       - Add dw_pcie_parent_bus_offset() to look up the parent bus address
         of a specified 'reg' property and return the offset from the CPU
         physical address (Frank Li)

       - Use dw_pcie_parent_bus_offset() to derive CPU -> ATU addr offset
         via 'reg[config]' for host controllers and 'reg[addr_space]' for
         endpoint controllers (Frank Li)

       - Apply struct dw_pcie.parent_bus_offset in ATU users to remove use
         of .cpu_addr_fixup() when programming ATU (Frank Li)

      TI J721E PCIe driver:

       - Correct the 'link down' interrupt bit for J784S4 (Siddharth
         Vadapalli)

      TI Keystone PCIe controller driver:

       - Describe AM65x BARs 2 and 5 as Resizable (not Fixed) and reduce
         alignment requirement from 1MB to 64KB (Niklas Cassel)

      Xilinx Versal CPM PCIe controller driver:

       - Free IRQ domain in probe error path to avoid leaking it
         (Thippeswamy Havalige)

       - Add DT .compatible "xlnx,versal-cpm5nc-host" and driver support for
         Versal Net CPM5NC Root Port controller (Thippeswamy Havalige)

       - Add driver support for CPM5_HOST1 (Thippeswamy Havalige)

      Miscellaneous:

       - Convert fsl,mpc83xx-pcie binding to YAML (J. Neuschäfer)

       - Use for_each_available_child_of_node_scoped() to simplify apple,
         kirin, mediatek, mt7621, tegra drivers (Zhang Zekun)"

JIRA: https://issues.redhat.com/browse/RHEL-86521

Signed-off-by: Myron Stowe <mstowe@redhat.com>
```

Approved-by: John W. Linville <linville@redhat.com>
Approved-by: Brian Masney <bmasney@redhat.com>
Approved-by: CKI KWF Bot <cki-ci-bot+kwf-gitlab-com@redhat.com>

Merged-by: Scott Weaver <scweaver@redhat.com>

Author: swvrrh

Documentation/ABI/testing/sysfs-bus-pci

@@ -583,3 +583,32 @@ Description:
 		enclosure-specific indications "specific0" to "specific7",
 		hence the corresponding led class devices are unavailable if
 		the DSM interface is used.
+
+What:		/sys/bus/pci/devices/.../doe_features
+Date:		March 2025
+Contact:	Linux PCI developers <linux-pci@vger.kernel.org>
+Description:
+		This directory contains a list of the supported Data Object
+		Exchange (DOE) features. The features are the file name.
+		The contents of each file is the raw Vendor ID and data
+		object feature values.
+
+		The value comes from the device and specifies the vendor and
+		data object type supported. The lower (RHS of the colon) is
+		the data object type in hex. The upper (LHS of the colon)
+		is the vendor ID.
+
+		As all DOE devices must support the DOE discovery feature,
+		if DOE is supported you will at least see the doe_discovery
+		file, with this contents:
+
+		  # cat doe_features/doe_discovery
+		  0001:00
+
+		If the device supports other features you will see other
+		files as well. For example if CMA/SPDM and secure CMA/SPDM
+		are supported the doe_features directory will look like
+		this:
+
+		  # ls doe_features
+		  0001:01        0001:02        doe_discovery

Documentation/PCI/endpoint/pci-endpoint.rst

@@ -57,11 +57,10 @@ by the PCI controller driver.
    The PCI controller driver can then create a new EPC device by invoking
    devm_pci_epc_create()/pci_epc_create().
 
-* devm_pci_epc_destroy()/pci_epc_destroy()
+* pci_epc_destroy()
 
-   The PCI controller driver can destroy the EPC device created by either
-   devm_pci_epc_create() or pci_epc_create() using devm_pci_epc_destroy() or
-   pci_epc_destroy().
+   The PCI controller driver can destroy the EPC device created by
+   pci_epc_create() using pci_epc_destroy().
 
 * pci_epc_linkup()
 

Documentation/admin-guide/perf/dwc_pcie_pmu.rst

@@ -60,7 +60,7 @@ description of available events and configuration options in sysfs, see
 The "format" directory describes format of the config fields of the
 perf_event_attr structure. The "events" directory provides configuration
 templates for all documented events.  For example,
-"Rx_PCIe_TLP_Data_Payload" is an equivalent of "eventid=0x22,type=0x1".
+"rx_pcie_tlp_data_payload" is an equivalent of "eventid=0x21,type=0x0".
 
 The "perf list" command shall list the available events from sysfs, e.g.::
 
@@ -79,8 +79,8 @@ Example usage of counting PCIe RX TLP data payload (Units of bytes)::
 
 The average RX/TX bandwidth can be calculated using the following formula:
 
-    PCIe RX Bandwidth = Rx_PCIe_TLP_Data_Payload / Measure_Time_Window
-    PCIe TX Bandwidth = Tx_PCIe_TLP_Data_Payload / Measure_Time_Window
+    PCIe RX Bandwidth = rx_pcie_tlp_data_payload / Measure_Time_Window
+    PCIe TX Bandwidth = tx_pcie_tlp_data_payload / Measure_Time_Window
 
 Lane Event Usage
 -------------------------------

Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml

@@ -12,9 +12,19 @@ maintainers:
 
 properties:
   compatible:
+    description: Each family of socfpga has its own implementation of the
+      PCI controller. The altr,pcie-root-port-1.0 is used for the Cyclone5
+      family of chips. The Stratix10 family of chips is supported by the
+      altr,pcie-root-port-2.0. The Agilex family of chips has three,
+      non-register compatible, variants of PCIe Hard IP referred to as the
+      F-Tile, P-Tile, and R-Tile, depending on the specific chip instance.
+
     enum:
       - altr,pcie-root-port-1.0
       - altr,pcie-root-port-2.0
+      - altr,pcie-root-port-3.0-f-tile
+      - altr,pcie-root-port-3.0-p-tile
+      - altr,pcie-root-port-3.0-r-tile
 
   reg:
     items:

Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml

@@ -14,6 +14,7 @@ properties:
     items:
       - enum:
           - brcm,bcm2711-pcie # The Raspberry Pi 4
+          - brcm,bcm2712-pcie # Raspberry Pi 5
           - brcm,bcm4908-pcie
           - brcm,bcm7211-pcie # Broadcom STB version of RPi4
           - brcm,bcm7216-pcie # Broadcom 7216 Arm
@@ -102,7 +103,10 @@ properties:
 
   reset-names:
     minItems: 1
-    maxItems: 3
+    items:
+      - enum: [perst, rescal]
+      - const: bridge
+      - const: swinit
 
 required:
   - compatible

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml

@@ -47,12 +47,16 @@ properties:
     maxItems: 5
 
   interrupts:
+    minItems: 1
     items:
       - description: builtin MSI controller.
+      - description: builtin DMA controller.
 
   interrupt-names:
+    minItems: 1
     items:
       - const: msi
+      - const: dma
 
   reset-gpio:
     description: Should specify the GPIO for controlling the PCI bus device

Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml

@@ -94,9 +94,6 @@ examples:
         reg-names = "regs", "addr_space";
         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
         interrupt-names = "pme";
-        num-ib-windows = <6>;
-        num-ob-windows = <8>;
-        status = "disabled";
       };
     };
 ...

Documentation/devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml

@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/pci/fsl,mpc8xxx-pci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale MPC83xx PCI/PCI-X/PCIe controllers
+
+description:
+  Binding for the PCI/PCI-X/PCIe host bridges on MPC8xxx SoCs
+
+maintainers:
+  - J. Neuschäfer <j.neuschaefer@gmx.net>
+
+allOf:
+  - $ref: /schemas/pci/pci-host-bridge.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - fsl,mpc8314-pcie
+          - fsl,mpc8349-pci
+          - fsl,mpc8540-pci
+          - fsl,mpc8548-pcie
+          - fsl,mpc8641-pcie
+      - items:
+          - enum:
+              - fsl,mpc8308-pcie
+              - fsl,mpc8315-pcie
+              - fsl,mpc8377-pcie
+              - fsl,mpc8378-pcie
+          - const: fsl,mpc8314-pcie
+      - items:
+          - const: fsl,mpc8360-pci
+          - const: fsl,mpc8349-pci
+      - items:
+          - const: fsl,mpc8540-pcix
+          - const: fsl,mpc8540-pci
+
+  reg:
+    minItems: 1
+    items:
+      - description: internal registers
+      - description: config space access registers
+
+  clock-frequency: true
+
+  interrupts:
+    items:
+      - description: Consolidated PCI interrupt
+
+  fsl,pci-agent-force-enum:
+    type: boolean
+    description:
+      Typically any Freescale PCI-X bridge hardware strapped into Agent mode is
+      prevented from enumerating the bus. The PrPMC form-factor requires all
+      mezzanines to be PCI-X Agents, but one per system may still enumerate the
+      bus.
+
+      This property allows a PCI-X bridge to be used for bus enumeration
+      despite being strapped into Agent mode.
+
+required:
+  - reg
+  - compatible
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    pcie@e0009000 {
+        compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
+        reg = <0xe0009000 0x00001000>;
+        ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
+                  0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
+        #address-cells = <3>;
+        #size-cells = <2>;
+        #interrupt-cells = <1>;
+        device_type = "pci";
+        bus-range = <0 255>;
+        interrupt-map-mask = <0xf800 0 0 7>;
+        interrupt-map = <0 0 0 1 &ipic 1 IRQ_TYPE_LEVEL_LOW
+                         0 0 0 2 &ipic 1 IRQ_TYPE_LEVEL_LOW
+                         0 0 0 3 &ipic 1 IRQ_TYPE_LEVEL_LOW
+                         0 0 0 4 &ipic 1 IRQ_TYPE_LEVEL_LOW>;
+        clock-frequency = <0>;
+    };
+
+  - |
+    pci@ef008000 {
+        compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
+        reg = <0xef008000 0x1000>;
+        ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
+                  0x01000000 0 0x00000000 0xd0000000 0 0x01000000>;
+        #interrupt-cells = <1>;
+        #size-cells = <2>;
+        #address-cells = <3>;
+        device_type = "pci";
+        clock-frequency = <33333333>;
+        interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+        interrupt-map = </* IDSEL */
+                         0xe000 0 0 1 &mpic 2 1
+                         0xe000 0 0 2 &mpic 3 1>;
+        interrupts-extended = <&mpic 24 2>;
+        bus-range = <0 0>;
+        fsl,pci-agent-force-enum;
+    };
+
+...

Documentation/devicetree/bindings/pci/fsl,pci.txt

@@ -109,6 +109,17 @@ properties:
   power-domains:
     maxItems: 1
 
+  mediatek,pbus-csr:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle to pbus-csr syscon
+          - description: offset of pbus-csr base address register
+          - description: offset of pbus-csr base address mask register
+    description:
+      Phandle with two arguments to the syscon node used to detect if
+      a given address is accessible on PCIe controller.
+
   '#interrupt-cells':
     const: 1
 
@@ -168,6 +179,8 @@ allOf:
           minItems: 1
           maxItems: 2
 
+        mediatek,pbus-csr: false
+
   - if:
       properties:
         compatible:
@@ -197,6 +210,8 @@ allOf:
           minItems: 1
           maxItems: 2
 
+        mediatek,pbus-csr: false
+
   - if:
       properties:
         compatible:
@@ -224,6 +239,8 @@ allOf:
           minItems: 1
           maxItems: 2
 
+        mediatek,pbus-csr: false
+
   - if:
       properties:
         compatible: