cxl: core/region - ignore interleave granularity when ways=1

JIRA: https://issues.redhat.com/browse/RHEL-107880

commit ce32b0c
Author: Gregory Price <gourry@gourry.net>
Date:   Wed Apr 2 19:25:52 2025 -0400

    cxl: core/region - ignore interleave granularity when ways=1

    When validating decoder IW/IG when setting up regions, the granularity
    is irrelevant when iw=1 - all accesses will always route to the only
    target anyway - so all ig values are "correct". Loosen the requirement
    that `ig = (parent_iw * parent_ig)` when iw=1.

    On some Zen5 platforms, the platform BIOS specifies a 256-byte
    interleave granularity window for host bridges when there is only
    one target downstream.  This leads to Linux rejecting the configuration
    of a region with a x2 root with two x1 hostbridges.

    Decoder Programming:
       root - iw:2 ig:256
       hb1  - iw:1 ig:256  (Linux expects 512)
       hb2  - iw:1 ig:256  (Linux expects 512)
       ep1  - iw:2 ig:256
       ep2  - iw:2 ig:256

    This change allows all decoders downstream of a passthrough decoder to
    also be configured as passthrough (iw:1 ig:X), but still disallows
    downstream decoders from applying subsequent interleaves.

    e.g. in the above example if there was another decoder south of hb1
    attempting to interleave 2 endpoints - Linux would enforce hb1.ig=512
    because the southern decoder would have iw:2 and require ig=pig*piw.

    [DJ: Fixed up against 6.15-rc1]

    Signed-off-by: Gregory Price <gourry@gourry.net>
    Reviewed-by: Dave Jiang <dave.jiang@intel.com>
    Tested-by: Li Zhijian <lizhijian@fujitsu.com>
    Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
    Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
    Reviewed-by: Dan Williams <dan.j.williams@intel.com>
    Link: https://patch.msgid.link/20250402232552.999634-1-gourry@gourry.net
    Signed-off-by: Dave Jiang <dave.jiang@intel.com>

Conflicts:
- drivers/cxl/core/region.c: 1 hunk modified

Assisted-by: Patchpal AI
Signed-off-by: John W. Linville <linville@redhat.com>

Author: John W. Linville

drivers/cxl/core/region.c

@@ -1423,7 +1423,7 @@ static int cxl_port_setup_targets(struct cxl_port *port,
 
 	if (test_bit(CXL_REGION_F_AUTO, &cxlr->flags)) {
 		if (cxld->interleave_ways != iw ||
-		    cxld->interleave_granularity != ig ||
+		    (iw > 1 && cxld->interleave_granularity != ig) ||
 		    cxld->hpa_range.start != p->res->start ||
 		    cxld->hpa_range.end != p->res->end ||
 		    ((cxld->flags & CXL_DECODER_F_ENABLE) == 0)) {