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Chandrakanth Patil
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scsi: mpi3mr: Update MPI Headers to revision 35
JIRA: https://issues.redhat.com/browse/RHEL-80698 Update MPI Headers to revision 35 Co-developed-by: Prayas Patel <prayas.patel@broadcom.com> Signed-off-by: Prayas Patel <prayas.patel@broadcom.com> Signed-off-by: Ranjan Kumar <ranjan.kumar@broadcom.com> Link: https://lore.kernel.org/r/20250220142528.20837-2-ranjan.kumar@broadcom.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> (cherry picked from commit b928757) Signed-off-by: Chandrakanth Patil <chanpati@redhat.com>
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5 files changed

+62
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‎drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
#define MPI3_CONFIG_PAGETYPE_PCIE_SWITCH (0x31)
2020
#define MPI3_CONFIG_PAGETYPE_PCIE_LINK (0x33)
2121
#define MPI3_CONFIG_PAGEATTR_MASK (0xf0)
22+
#define MPI3_CONFIG_PAGEATTR_SHIFT (4)
2223
#define MPI3_CONFIG_PAGEATTR_READ_ONLY (0x00)
2324
#define MPI3_CONFIG_PAGEATTR_CHANGEABLE (0x10)
2425
#define MPI3_CONFIG_PAGEATTR_PERSISTENT (0x20)
@@ -29,10 +30,13 @@
2930
#define MPI3_CONFIG_ACTION_READ_PERSISTENT (0x04)
3031
#define MPI3_CONFIG_ACTION_WRITE_PERSISTENT (0x05)
3132
#define MPI3_DEVICE_PGAD_FORM_MASK (0xf0000000)
33+
#define MPI3_DEVICE_PGAD_FORM_SHIFT (28)
3234
#define MPI3_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
3335
#define MPI3_DEVICE_PGAD_FORM_HANDLE (0x20000000)
3436
#define MPI3_DEVICE_PGAD_HANDLE_MASK (0x0000ffff)
37+
#define MPI3_DEVICE_PGAD_HANDLE_SHIFT (0)
3538
#define MPI3_SAS_EXPAND_PGAD_FORM_MASK (0xf0000000)
39+
#define MPI3_SAS_EXPAND_PGAD_FORM_SHIFT (28)
3640
#define MPI3_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
3741
#define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x10000000)
3842
#define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE (0x20000000)

‎drivers/scsi/mpi3mr/mpi/mpi30_image.h‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,12 @@ struct mpi3_component_image_header {
6666
#define MPI3_IMAGE_HEADER_SIGNATURE1_SMM (0x204d4d53)
6767
#define MPI3_IMAGE_HEADER_SIGNATURE1_PSW (0x20575350)
6868
#define MPI3_IMAGE_HEADER_SIGNATURE2_VALUE (0x50584546)
69+
#define MPI3_IMAGE_HEADER_FLAGS_SIGNED_UEFI_MASK (0x00000300)
70+
#define MPI3_IMAGE_HEADER_FLAGS_SIGNED_UEFI_SHIFT (8)
71+
#define MPI3_IMAGE_HEADER_FLAGS_CERT_CHAIN_FORMAT_MASK (0x000000c0)
72+
#define MPI3_IMAGE_HEADER_FLAGS_CERT_CHAIN_FORMAT_SHIFT (6)
6973
#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_MASK (0x00000030)
74+
#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_SHIFT (4)
7075
#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_CDI (0x00000000)
7176
#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_DI (0x00000010)
7277
#define MPI3_IMAGE_HEADER_FLAGS_SIGNED_NVDATA (0x00000008)
@@ -214,11 +219,13 @@ struct mpi3_encrypted_hash_entry {
214219
#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_HASH_1_OF_2 (0x04)
215220
#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_HASH_2_OF_2 (0x05)
216221
#define MPI3_HASH_ALGORITHM_VERSION_MASK (0xe0)
222+
#define MPI3_HASH_ALGORITHM_VERSION_SHIFT (5)
217223
#define MPI3_HASH_ALGORITHM_VERSION_NONE (0x00)
218224
#define MPI3_HASH_ALGORITHM_VERSION_SHA1 (0x20)
219225
#define MPI3_HASH_ALGORITHM_VERSION_SHA2 (0x40)
220226
#define MPI3_HASH_ALGORITHM_VERSION_SHA3 (0x60)
221227
#define MPI3_HASH_ALGORITHM_SIZE_MASK (0x1f)
228+
#define MPI3_HASH_ALGORITHM_SIZE_SHIFT (0)
222229
#define MPI3_HASH_ALGORITHM_SIZE_UNUSED (0x00)
223230
#define MPI3_HASH_ALGORITHM_SIZE_SHA256 (0x01)
224231
#define MPI3_HASH_ALGORITHM_SIZE_SHA512 (0x02)
@@ -236,6 +243,7 @@ struct mpi3_encrypted_hash_entry {
236243
#define MPI3_ENCRYPTION_ALGORITHM_ML_DSA_65 (0x0c)
237244
#define MPI3_ENCRYPTION_ALGORITHM_ML_DSA_44 (0x0d)
238245
#define MPI3_ENCRYPTED_HASH_ENTRY_FLAGS_PAIRED_KEY_MASK (0x0f)
246+
#define MPI3_ENCRYPTED_HASH_ENTRY_FLAGS_PAIRED_KEY_SHIFT (0)
239247

240248
#ifndef MPI3_ENCRYPTED_HASH_ENTRY_MAX
241249
#define MPI3_ENCRYPTED_HASH_ENTRY_MAX (1)

‎drivers/scsi/mpi3mr/mpi/mpi30_init.h‎

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,23 +38,31 @@ struct mpi3_scsi_io_request {
3838
#define MPI3_SCSIIO_MSGFLAGS_METASGL_VALID (0x80)
3939
#define MPI3_SCSIIO_MSGFLAGS_DIVERT_TO_FIRMWARE (0x40)
4040
#define MPI3_SCSIIO_FLAGS_LARGE_CDB (0x60000000)
41+
#define MPI3_SCSIIO_FLAGS_LARGE_CDB_MASK (0x60000000)
42+
#define MPI3_SCSIIO_FLAGS_LARGE_CDB_SHIFT (29)
43+
#define MPI3_SCSIIO_FLAGS_IOC_USE_ONLY_27_MASK (0x18000000)
44+
#define MPI3_SCSIIO_FLAGS_IOC_USE_ONLY_27_SHIFT (27)
4145
#define MPI3_SCSIIO_FLAGS_CDB_16_OR_LESS (0x00000000)
4246
#define MPI3_SCSIIO_FLAGS_CDB_GREATER_THAN_16 (0x20000000)
4347
#define MPI3_SCSIIO_FLAGS_CDB_IN_SEPARATE_BUFFER (0x40000000)
4448
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_MASK (0x07000000)
49+
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_SHIFT (24)
50+
#define MPI3_SCSIIO_FLAGS_DATADIRECTION_MASK (0x000c0000)
51+
#define MPI3_SCSIIO_FLAGS_DATADIRECTION_SHIFT (18)
4552
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_SIMPLEQ (0x00000000)
4653
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_HEADOFQ (0x01000000)
4754
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_ORDEREDQ (0x02000000)
4855
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_ACAQ (0x04000000)
4956
#define MPI3_SCSIIO_FLAGS_CMDPRI_MASK (0x00f00000)
5057
#define MPI3_SCSIIO_FLAGS_CMDPRI_SHIFT (20)
51-
#define MPI3_SCSIIO_FLAGS_DATADIRECTION_MASK (0x000c0000)
5258
#define MPI3_SCSIIO_FLAGS_DATADIRECTION_NO_DATA_TRANSFER (0x00000000)
5359
#define MPI3_SCSIIO_FLAGS_DATADIRECTION_WRITE (0x00040000)
5460
#define MPI3_SCSIIO_FLAGS_DATADIRECTION_READ (0x00080000)
5561
#define MPI3_SCSIIO_FLAGS_DMAOPERATION_MASK (0x00030000)
62+
#define MPI3_SCSIIO_FLAGS_DMAOPERATION_SHIFT (16)
5663
#define MPI3_SCSIIO_FLAGS_DMAOPERATION_HOST_PI (0x00010000)
5764
#define MPI3_SCSIIO_FLAGS_DIVERT_REASON_MASK (0x000000f0)
65+
#define MPI3_SCSIIO_FLAGS_DIVERT_REASON_SHIFT (4)
5866
#define MPI3_SCSIIO_FLAGS_DIVERT_REASON_IO_THROTTLING (0x00000010)
5967
#define MPI3_SCSIIO_FLAGS_DIVERT_REASON_WRITE_SAME_TOO_LARGE (0x00000020)
6068
#define MPI3_SCSIIO_FLAGS_DIVERT_REASON_PROD_SPECIFIC (0x00000080)
@@ -99,6 +107,7 @@ struct mpi3_scsi_io_reply {
99107
#define MPI3_SCSI_STATUS_ACA_ACTIVE (0x30)
100108
#define MPI3_SCSI_STATUS_TASK_ABORTED (0x40)
101109
#define MPI3_SCSI_STATE_SENSE_MASK (0x03)
110+
#define MPI3_SCSI_STATE_SENSE_SHIFT (0)
102111
#define MPI3_SCSI_STATE_SENSE_VALID (0x00)
103112
#define MPI3_SCSI_STATE_SENSE_FAILED (0x01)
104113
#define MPI3_SCSI_STATE_SENSE_BUFF_Q_EMPTY (0x02)

‎drivers/scsi/mpi3mr/mpi/mpi30_ioc.h‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ struct mpi3_ioc_init_request {
3030
#define MPI3_IOCINIT_MSGFLAGS_WRITESAMEDIVERT_SUPPORTED (0x08)
3131
#define MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED (0x04)
3232
#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_MASK (0x03)
33+
#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SHIFT (0)
3334
#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_NOT_USED (0x00)
3435
#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SEPARATED (0x01)
3536
#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_INLINE (0x02)
@@ -40,6 +41,7 @@ struct mpi3_ioc_init_request {
4041
#define MPI3_WHOINIT_MANUFACTURER (0x04)
4142

4243
#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_MASK (0x00000003)
44+
#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_SHIFT (0)
4345
#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_NO_GUIDANCE (0x00000000)
4446
#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_NO_SPECIAL (0x00000001)
4547
#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_REPORT_AS_HDD (0x00000002)
@@ -111,9 +113,11 @@ struct mpi3_ioc_facts_data {
111113
__le32 diag_tty_size;
112114
};
113115
#define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_MASK (0x80000000)
116+
#define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_SHIFT (31)
114117
#define MPI3_IOCFACTS_CAPABILITY_SUPERVISOR_IOC (0x00000000)
115118
#define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_IOC (0x80000000)
116119
#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_MASK (0x00000600)
120+
#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_SHIFT (9)
117121
#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_FIXED_THRESHOLD (0x00000000)
118122
#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_OUTSTANDING_IO (0x00000200)
119123
#define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_SUPPORTED (0x00000100)
@@ -134,6 +138,7 @@ struct mpi3_ioc_facts_data {
134138
#define MPI3_IOCFACTS_EXCEPT_SAS_DISABLED (0x1000)
135139
#define MPI3_IOCFACTS_EXCEPT_SAFE_MODE (0x0800)
136140
#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_MASK (0x0700)
141+
#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_SHIFT (8)
137142
#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_NONE (0x0000)
138143
#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_MGMT (0x0100)
139144
#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_MGMT (0x0200)
@@ -149,6 +154,7 @@ struct mpi3_ioc_facts_data {
149154
#define MPI3_IOCFACTS_EXCEPT_BLOCKING_BOOT_EVENT (0x0004)
150155
#define MPI3_IOCFACTS_EXCEPT_SECURITY_SELFTEST_FAILURE (0x0002)
151156
#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x0001)
157+
#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SHIFT (0)
152158
#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_PRIMARY (0x0000)
153159
#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SECONDARY (0x0001)
154160
#define MPI3_IOCFACTS_PROTOCOL_SAS (0x0010)
@@ -161,10 +167,12 @@ struct mpi3_ioc_facts_data {
161167
#define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK (0x0000ff00)
162168
#define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT (8)
163169
#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK (0x00000030)
170+
#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_SHIFT (4)
164171
#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_NOT_STARTED (0x00000000)
165172
#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_IN_PROGRESS (0x00000010)
166173
#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_COMPLETE (0x00000020)
167174
#define MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK (0x0000000f)
175+
#define MPI3_IOCFACTS_FLAGS_PERSONALITY_SHIFT (0)
168176
#define MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA (0x00000000)
169177
#define MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR (0x00000002)
170178
#define MPI3_IOCFACTS_IO_THROTTLE_DATA_LENGTH_NOT_REQUIRED (0x0000)
@@ -204,6 +212,7 @@ struct mpi3_create_request_queue_request {
204212
};
205213

206214
#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_MASK (0x80)
215+
#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SHIFT (7)
207216
#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80)
208217
#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00)
209218
#define MPI3_CREATE_REQUEST_QUEUE_SIZE_MINIMUM (2)
@@ -237,10 +246,12 @@ struct mpi3_create_reply_queue_request {
237246
};
238247

239248
#define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_MASK (0x80)
249+
#define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SHIFT (7)
240250
#define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80)
241251
#define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00)
242252
#define MPI3_CREATE_REPLY_QUEUE_FLAGS_COALESCE_DISABLE (0x02)
243253
#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_MASK (0x01)
254+
#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_SHIFT (0)
244255
#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_DISABLE (0x00)
245256
#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE (0x01)
246257
#define MPI3_CREATE_REPLY_QUEUE_SIZE_MINIMUM (2)
@@ -326,9 +337,11 @@ struct mpi3_event_notification_reply {
326337
};
327338

328339
#define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK (0x01)
340+
#define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_SHIFT (0)
329341
#define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED (0x01)
330342
#define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_NOT_REQUIRED (0x00)
331343
#define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_MASK (0x02)
344+
#define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_SHIFT (1)
332345
#define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_ORIGINAL (0x00)
333346
#define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_REPLAY (0x02)
334347
struct mpi3_event_data_gpio_interrupt {
@@ -487,6 +500,7 @@ struct mpi3_event_sas_topo_phy_entry {
487500
#define MPI3_EVENT_SAS_TOPO_PHY_STATUS_NO_EXIST (0x40)
488501
#define MPI3_EVENT_SAS_TOPO_PHY_STATUS_VACANT (0x80)
489502
#define MPI3_EVENT_SAS_TOPO_PHY_RC_MASK (0x0f)
503+
#define MPI3_EVENT_SAS_TOPO_PHY_RC_SHIFT (0)
490504
#define MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING (0x02)
491505
#define MPI3_EVENT_SAS_TOPO_PHY_RC_PHY_CHANGED (0x03)
492506
#define MPI3_EVENT_SAS_TOPO_PHY_RC_NO_CHANGE (0x04)
@@ -566,13 +580,15 @@ struct mpi3_event_pcie_topo_port_entry {
566580
#define MPI3_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05)
567581
#define MPI3_EVENT_PCIE_TOPO_PS_RESPONDING (0x06)
568582
#define MPI3_EVENT_PCIE_TOPO_PI_LANES_MASK (0xf0)
583+
#define MPI3_EVENT_PCIE_TOPO_PI_LANES_SHIFT (4)
569584
#define MPI3_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00)
570585
#define MPI3_EVENT_PCIE_TOPO_PI_LANES_1 (0x10)
571586
#define MPI3_EVENT_PCIE_TOPO_PI_LANES_2 (0x20)
572587
#define MPI3_EVENT_PCIE_TOPO_PI_LANES_4 (0x30)
573588
#define MPI3_EVENT_PCIE_TOPO_PI_LANES_8 (0x40)
574589
#define MPI3_EVENT_PCIE_TOPO_PI_LANES_16 (0x50)
575590
#define MPI3_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0f)
591+
#define MPI3_EVENT_PCIE_TOPO_PI_RATE_SHIFT (0)
576592
#define MPI3_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00)
577593
#define MPI3_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01)
578594
#define MPI3_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02)
@@ -881,6 +897,7 @@ struct mpi3_pel_req_action_acknowledge {
881897
};
882898

883899
#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_MASK (0x03)
900+
#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_SHIFT (0)
884901
#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_NO_GUIDANCE (0x00)
885902
#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_CONTINUE_OP (0x01)
886903
#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_TRANSITION_TO_FAULT (0x02)
@@ -924,6 +941,7 @@ struct mpi3_ci_download_request {
924941
#define MPI3_CI_DOWNLOAD_MSGFLAGS_FORCE_FMC_ENABLE (0x40)
925942
#define MPI3_CI_DOWNLOAD_MSGFLAGS_SIGNED_NVDATA (0x20)
926943
#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MASK (0x03)
944+
#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SHIFT (0)
927945
#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_FAST (0x00)
928946
#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MEDIUM (0x01)
929947
#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SLOW (0x02)
@@ -953,6 +971,7 @@ struct mpi3_ci_download_reply {
953971
#define MPI3_CI_DOWNLOAD_FLAGS_OFFLINE_ACTIVATION_REQUIRED (0x20)
954972
#define MPI3_CI_DOWNLOAD_FLAGS_KEY_UPDATE_PENDING (0x10)
955973
#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_MASK (0x0e)
974+
#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_SHIFT (1)
956975
#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_NOT_NEEDED (0x00)
957976
#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_AWAITING (0x02)
958977
#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_ONLINE_PENDING (0x04)
@@ -976,9 +995,11 @@ struct mpi3_ci_upload_request {
976995
};
977996

978997
#define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_MASK (0x01)
998+
#define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SHIFT (0)
979999
#define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY (0x00)
9801000
#define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SECONDARY (0x01)
9811001
#define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_MASK (0x02)
1002+
#define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_SHIFT (1)
9821003
#define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_FLASH (0x00)
9831004
#define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_EXECUTABLE (0x02)
9841005
#define MPI3_CTRL_OP_FORCE_FULL_DISCOVERY (0x01)

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