net: phy: microchip_t1s: add c45 direct access in LAN865x internal PHY

JIRA: https://issues.redhat.com/browse/RHEL-57766

commit 18a9187
Author: Parthiban Veerasooran <Parthiban.Veerasooran@microchip.com>
Date:   Mon Sep 9 13:55:07 2024 +0530

    net: phy: microchip_t1s: add c45 direct access in LAN865x internal PHY

    This patch adds c45 registers direct access support in Microchip's
    LAN865x internal PHY.

    OPEN Alliance 10BASE-T1x compliance MAC-PHYs will have both C22 and C45
    registers space. If the PHY is discovered via C22 bus protocol it assumes
    it uses C22 protocol and always uses C22 registers indirect access to
    access C45 registers. This is because, we don't have a clean separation
    between C22/C45 register space and C22/C45 MDIO bus protocols. Resulting,
    PHY C45 registers direct access can't be used which can save multiple SPI
    bus access. To support this feature, set .read_mmd/.write_mmd in the PHY
    driver to call .read_c45/.write_c45 in the OPEN Alliance framework
    drivers/net/ethernet/oa_tc6.c

    Reviewed-by: Andrew Lunn <andrew@lunn.ch>
    Signed-off-by: Parthiban Veerasooran <Parthiban.Veerasooran@microchip.com>
    Link: https://patch.msgid.link/20240909082514.262942-8-Parthiban.Veerasooran@microchip.com
    Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Signed-off-by: Izabela Bakollari <ibakolla@redhat.com>

Author: Izabela Bakollari

drivers/net/phy/microchip_t1s.c

@@ -268,6 +268,34 @@ static int lan86xx_read_status(struct phy_device *phydev)
 	return 0;
 }
 
+/* OPEN Alliance 10BASE-T1x compliance MAC-PHYs will have both C22 and
+ * C45 registers space. If the PHY is discovered via C22 bus protocol it assumes
+ * it uses C22 protocol and always uses C22 registers indirect access to access
+ * C45 registers. This is because, we don't have a clean separation between
+ * C22/C45 register space and C22/C45 MDIO bus protocols. Resulting, PHY C45
+ * registers direct access can't be used which can save multiple SPI bus access.
+ * To support this feature, set .read_mmd/.write_mmd in the PHY driver to call
+ * .read_c45/.write_c45 in the OPEN Alliance framework
+ * drivers/net/ethernet/oa_tc6.c
+ */
+static int lan865x_phy_read_mmd(struct phy_device *phydev, int devnum,
+				u16 regnum)
+{
+	struct mii_bus *bus = phydev->mdio.bus;
+	int addr = phydev->mdio.addr;
+
+	return __mdiobus_c45_read(bus, addr, devnum, regnum);
+}
+
+static int lan865x_phy_write_mmd(struct phy_device *phydev, int devnum,
+				 u16 regnum, u16 val)
+{
+	struct mii_bus *bus = phydev->mdio.bus;
+	int addr = phydev->mdio.addr;
+
+	return __mdiobus_c45_write(bus, addr, devnum, regnum, val);
+}
+
 static struct phy_driver microchip_t1s_driver[] = {
 	{
 		PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1),
@@ -285,6 +313,8 @@ static struct phy_driver microchip_t1s_driver[] = {
 		.features           = PHY_BASIC_T1S_P2MP_FEATURES,
 		.config_init        = lan865x_revb0_config_init,
 		.read_status        = lan86xx_read_status,
+		.read_mmd           = lan865x_phy_read_mmd,
+		.write_mmd          = lan865x_phy_write_mmd,
 		.get_plca_cfg	    = genphy_c45_plca_get_cfg,
 		.set_plca_cfg	    = genphy_c45_plca_set_cfg,
 		.get_plca_status    = genphy_c45_plca_get_status,