KVM: arm64: Eagerly switch ZCR_EL{1,2}

JIRA: https://issues.redhat.com/browse/RHEL-87960

In non-protected KVM modes, while the guest FPSIMD/SVE/SME state is live on the
CPU, the host's active SVE VL may differ from the guest's maximum SVE VL:

* For VHE hosts, when a VM uses NV, ZCR_EL2 contains a value constrained
  by the guest hypervisor, which may be less than or equal to that
  guest's maximum VL.

  Note: in this case the value of ZCR_EL1 is immaterial due to E2H.

* For nVHE/hVHE hosts, ZCR_EL1 contains a value written by the guest,
  which may be less than or greater than the guest's maximum VL.

  Note: in this case hyp code traps host SVE usage and lazily restores
  ZCR_EL2 to the host's maximum VL, which may be greater than the
  guest's maximum VL.

This can be the case between exiting a guest and kvm_arch_vcpu_put_fp().
If a softirq is taken during this period and the softirq handler tries
to use kernel-mode NEON, then the kernel will fail to save the guest's
FPSIMD/SVE state, and will pend a SIGKILL for the current thread.

This happens because kvm_arch_vcpu_ctxsync_fp() binds the guest's live
FPSIMD/SVE state with the guest's maximum SVE VL, and
fpsimd_save_user_state() verifies that the live SVE VL is as expected
before attempting to save the register state:

| if (WARN_ON(sve_get_vl() != vl)) {
|         force_signal_inject(SIGKILL, SI_KERNEL, 0, 0);
|         return;
| }

Fix this and make this a bit easier to reason about by always eagerly
switching ZCR_EL{1,2} at hyp during guest<->host transitions. With this
happening, there's no need to trap host SVE usage, and the nVHE/nVHE
__deactivate_cptr_traps() logic can be simplified to enable host access
to all present FPSIMD/SVE/SME features.

In protected nVHE/hVHE modes, the host's state is always saved/restored
by hyp, and the guest's state is saved prior to exit to the host, so
from the host's PoV the guest never has live FPSIMD/SVE/SME state, and
the host's ZCR_EL1 is never clobbered by hyp.

Fixes: 8c8010d ("KVM: arm64: Save/restore SVE state for nVHE")
Fixes: 2e3cf82 ("KVM: arm64: nv: Ensure correct VL is loaded before saving SVE state")
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
Tested-by: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Fuad Tabba <tabba@google.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20250210195226.1215254-9-mark.rutland@arm.com
Signed-off-by: Marc Zyngier <maz@kernel.org>
(cherry picked from commit 59419f1)
Signed-off-by: Gavin Shan <gshan@redhat.com>
Conflicts:
	Downstream commit 939b186 ported upstream commit 59419f1
	incompletely. Fix it up as below.
	arch/arm64/include/asm/kvm_emulate.h
	Conflict due to missed upstream commit ee14db3 ("KVM: arm64:
	Refactor CPTR trap deactivation") where kvm_reset_cptr_el2() is
	renamed to __deactivate_cptr_traps(). Apply the changes for
	__deactivate_cptr_traps() to kvm_get_reset_cptr_el2(), called by
	kvm_reset_cptr_el2() only. This should have been done by
	downstream commit 939b186, but we didn't.
	arch/arm64/kvm/hyp/nvhe/switch.c
	Conflict due to missed upstream commit ee14db3 ("KVM: arm64:
        Refactor CPTR trap deactivation") where FPSMID32 traps can be
	activated and CPACR_EL1/EL2 are updated accordingly. The logic
	has been dropped by upstream commit 59419f1 and readded by
	the missed upstream commit ee14db3. Keep the logic here.

Author: Gavin Shan

arch/arm64/include/asm/kvm_emulate.h

@@ -625,14 +625,14 @@ static __always_inline u64 kvm_get_reset_cptr_el2(struct kvm_vcpu *vcpu)
 	} else if (has_hvhe()) {
 		val = CPACR_ELx_FPEN;
 
-		if (!vcpu_has_sve(vcpu) || !guest_owns_fp_regs())
+		if (cpus_have_final_cap(ARM64_SVE))
 			val |= CPACR_ELx_ZEN;
 		if (cpus_have_final_cap(ARM64_SME))
 			val |= CPACR_ELx_SMEN;
 	} else {
 		val = CPTR_NVHE_EL2_RES1;
 
-		if (vcpu_has_sve(vcpu) && guest_owns_fp_regs())
+		if (!cpus_have_final_cap(ARM64_SVE))
 			val |= CPTR_EL2_TZ;
 		if (!cpus_have_final_cap(ARM64_SME))
 			val |= CPTR_EL2_TSM;

arch/arm64/kvm/hyp/nvhe/switch.c

@@ -63,6 +63,11 @@ static void __activate_cptr_traps(struct kvm_vcpu *vcpu)
 		if (!guest_owns_fp_regs())
 			val |= CPTR_EL2_TFP;
 	}
+
+	if (!guest_owns_fp_regs())
+		__activate_traps_fpsimd32(vcpu);
+
+	kvm_write_cptr_el2(val);
 }
 
 static void __activate_traps(struct kvm_vcpu *vcpu)