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ice: Implement PTP support for E830 devices
JIRA: https://issues.redhat.com/browse/RHEL-89579 Upstream commit(s): commit f003075 Author: Michal Michalik <michal.michalik@intel.com> Date: Mon Sep 30 14:12:44 2024 +0200 ice: Implement PTP support for E830 devices Add specific functions and definitions for E830 devices to enable PTP support. E830 devices support direct write to GLTSYN_ registers without shadow registers and 64 bit read of PHC time. Enable PTM for E830 device, which is required for cross timestamp and and dependency on PCIE_PTM for ICE_HWTS. Check X86_FEATURE_ART for E830 as it may not be present in the CPU. Cc: Anna-Maria Behnsen <anna-maria@linutronix.de> Cc: Frederic Weisbecker <frederic@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> Co-developed-by: Jacob Keller <jacob.e.keller@intel.com> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Co-developed-by: Milena Olech <milena.olech@intel.com> Signed-off-by: Milena Olech <milena.olech@intel.com> Co-developed-by: Paul Greenwalt <paul.greenwalt@intel.com> Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com> Signed-off-by: Michal Michalik <michal.michalik@intel.com> Co-developed-by: Karol Kolacinski <karol.kolacinski@intel.com> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel) Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> Signed-off-by: Petr Oros <poros@redhat.com>
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‎drivers/net/ethernet/intel/Kconfig‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -351,7 +351,7 @@ config ICE_SWITCHDEV
351351
config ICE_HWTS
352352
bool "Support HW cross-timestamp on platforms with PTM support"
353353
default y
354-
depends on ICE && X86
354+
depends on ICE && X86 && PCIE_PTM
355355
help
356356
Say Y to enable hardware supported cross-timestamping on platforms
357357
with PCIe PTM support. The cross-timestamp is available through

‎drivers/net/ethernet/intel/ice/ice_hw_autogen.h‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -533,10 +533,22 @@
533533
#define PFPM_WUS_MAG_M BIT(1)
534534
#define PFPM_WUS_MNG_M BIT(3)
535535
#define PFPM_WUS_FW_RST_WK_M BIT(31)
536+
#define E830_PRTMAC_TS_TX_MEM_VALID_H 0x001E2020
537+
#define E830_PRTMAC_TS_TX_MEM_VALID_L 0x001E2000
536538
#define E830_PRTMAC_CL01_PS_QNT 0x001E32A0
537539
#define E830_PRTMAC_CL01_PS_QNT_CL0_M GENMASK(15, 0)
538540
#define E830_PRTMAC_CL01_QNT_THR 0x001E3320
539541
#define E830_PRTMAC_CL01_QNT_THR_CL0_M GENMASK(15, 0)
542+
#define E830_PRTTSYN_TXTIME_H(_i) (0x001E5800 + ((_i) * 32))
543+
#define E830_PRTTSYN_TXTIME_L(_i) (0x001E5000 + ((_i) * 32))
544+
#define E830_GLPTM_ART_CTL 0x00088B50
545+
#define E830_GLPTM_ART_CTL_ACTIVE_M BIT(0)
546+
#define E830_GLPTM_ART_TIME_H 0x00088B54
547+
#define E830_GLPTM_ART_TIME_L 0x00088B58
548+
#define E830_GLTSYN_PTMTIME_H(_i) (0x00088B48 + ((_i) * 4))
549+
#define E830_GLTSYN_PTMTIME_L(_i) (0x00088B40 + ((_i) * 4))
550+
#define E830_PFPTM_SEM 0x00088B00
551+
#define E830_PFPTM_SEM_BUSY_M BIT(0)
540552
#define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4))
541553
#define VFINT_DYN_CTLN_CLEARPBA_M BIT(1)
542554

‎drivers/net/ethernet/intel/ice/ice_main.c‎

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4035,8 +4035,7 @@ static void ice_set_pf_caps(struct ice_pf *pf)
40354035
}
40364036

40374037
clear_bit(ICE_FLAG_PTP_SUPPORTED, pf->flags);
4038-
if (func_caps->common_cap.ieee_1588 &&
4039-
!(pf->hw.mac_type == ICE_MAC_E830))
4038+
if (func_caps->common_cap.ieee_1588)
40404039
set_bit(ICE_FLAG_PTP_SUPPORTED, pf->flags);
40414040

40424041
pf->max_pf_txqs = func_caps->common_cap.num_txq;
@@ -5019,6 +5018,12 @@ static int ice_init(struct ice_pf *pf)
50195018
if (err)
50205019
return err;
50215020

5021+
if (pf->hw.mac_type == ICE_MAC_E830) {
5022+
err = pci_enable_ptm(pf->pdev, NULL);
5023+
if (err)
5024+
dev_dbg(ice_pf_to_dev(pf), "PCIe PTM not supported by PCIe bus/controller\n");
5025+
}
5026+
50225027
err = ice_alloc_vsis(pf);
50235028
if (err)
50245029
goto err_alloc_vsis;

‎drivers/net/ethernet/intel/ice/ice_ptp.c‎

Lines changed: 70 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -310,6 +310,15 @@ ice_ptp_read_src_clk_reg(struct ice_pf *pf, struct ptp_system_timestamp *sts)
310310
/* Read the system timestamp pre PHC read */
311311
ptp_read_system_prets(sts);
312312

313+
if (hw->mac_type == ICE_MAC_E830) {
314+
u64 clk_time = rd64(hw, E830_GLTSYN_TIME_L(tmr_idx));
315+
316+
/* Read the system timestamp post PHC read */
317+
ptp_read_system_postts(sts);
318+
319+
return clk_time;
320+
}
321+
313322
lo = rd32(hw, GLTSYN_TIME_L(tmr_idx));
314323

315324
/* Read the system timestamp post PHC read */
@@ -1305,6 +1314,7 @@ ice_ptp_port_phy_stop(struct ice_ptp_port *ptp_port)
13051314

13061315
switch (hw->mac_type) {
13071316
case ICE_MAC_E810:
1317+
case ICE_MAC_E830:
13081318
err = 0;
13091319
break;
13101320
case ICE_MAC_GENERIC:
@@ -1351,6 +1361,7 @@ ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port)
13511361

13521362
switch (hw->mac_type) {
13531363
case ICE_MAC_E810:
1364+
case ICE_MAC_E830:
13541365
err = 0;
13551366
break;
13561367
case ICE_MAC_GENERIC:
@@ -1418,7 +1429,8 @@ void ice_ptp_link_change(struct ice_pf *pf, bool linkup)
14181429

14191430
switch (hw->mac_type) {
14201431
case ICE_MAC_E810:
1421-
/* Do not reconfigure E810 PHY */
1432+
case ICE_MAC_E830:
1433+
/* Do not reconfigure E810 or E830 PHY */
14221434
return;
14231435
case ICE_MAC_GENERIC:
14241436
case ICE_MAC_GENERIC_3K_E825:
@@ -1451,6 +1463,7 @@ static int ice_ptp_cfg_phy_interrupt(struct ice_pf *pf, bool ena, u32 threshold)
14511463

14521464
switch (hw->mac_type) {
14531465
case ICE_MAC_E810:
1466+
case ICE_MAC_E830:
14541467
return 0;
14551468
case ICE_MAC_GENERIC: {
14561469
int quad;
@@ -2204,6 +2217,21 @@ static const struct ice_crosststamp_cfg ice_crosststamp_cfg_e82x = {
22042217
.dev_time_h[1] = GLTSYN_HHTIME_H(1),
22052218
};
22062219

2220+
#ifdef CONFIG_ICE_HWTS
2221+
static const struct ice_crosststamp_cfg ice_crosststamp_cfg_e830 = {
2222+
.lock_reg = E830_PFPTM_SEM,
2223+
.lock_busy = E830_PFPTM_SEM_BUSY_M,
2224+
.ctl_reg = E830_GLPTM_ART_CTL,
2225+
.ctl_active = E830_GLPTM_ART_CTL_ACTIVE_M,
2226+
.art_time_l = E830_GLPTM_ART_TIME_L,
2227+
.art_time_h = E830_GLPTM_ART_TIME_H,
2228+
.dev_time_l[0] = E830_GLTSYN_PTMTIME_L(0),
2229+
.dev_time_h[0] = E830_GLTSYN_PTMTIME_H(0),
2230+
.dev_time_l[1] = E830_GLTSYN_PTMTIME_L(1),
2231+
.dev_time_h[1] = E830_GLTSYN_PTMTIME_H(1),
2232+
};
2233+
2234+
#endif /* CONFIG_ICE_HWTS */
22072235
/**
22082236
* struct ice_crosststamp_ctx - Device cross timestamp context
22092237
* @snapshot: snapshot of system clocks for historic interpolation
@@ -2325,6 +2353,11 @@ static int ice_ptp_getcrosststamp(struct ptp_clock_info *info,
23252353
case ICE_MAC_GENERIC_3K_E825:
23262354
ctx.cfg = &ice_crosststamp_cfg_e82x;
23272355
break;
2356+
#ifdef CONFIG_ICE_HWTS
2357+
case ICE_MAC_E830:
2358+
ctx.cfg = &ice_crosststamp_cfg_e830;
2359+
break;
2360+
#endif /* CONFIG_ICE_HWTS */
23282361
default:
23292362
return -EOPNOTSUPP;
23302363
}
@@ -2660,6 +2693,28 @@ static void ice_ptp_set_funcs_e810(struct ice_pf *pf)
26602693
}
26612694
}
26622695

2696+
/**
2697+
* ice_ptp_set_funcs_e830 - Set specialized functions for E830 support
2698+
* @pf: Board private structure
2699+
*
2700+
* Assign functions to the PTP capabiltiies structure for E830 devices.
2701+
* Functions which operate across all device families should be set directly
2702+
* in ice_ptp_set_caps. Only add functions here which are distinct for E830
2703+
* devices.
2704+
*/
2705+
static void ice_ptp_set_funcs_e830(struct ice_pf *pf)
2706+
{
2707+
#ifdef CONFIG_ICE_HWTS
2708+
if (pcie_ptm_enabled(pf->pdev) && boot_cpu_has(X86_FEATURE_ART))
2709+
pf->ptp.info.getcrosststamp = ice_ptp_getcrosststamp;
2710+
2711+
#endif /* CONFIG_ICE_HWTS */
2712+
/* Rest of the config is the same as base E810 */
2713+
pf->ptp.ice_pin_desc = ice_pin_desc_e810;
2714+
pf->ptp.info.n_pins = ICE_PIN_DESC_ARR_LEN(ice_pin_desc_e810);
2715+
ice_ptp_setup_pin_cfg(pf);
2716+
}
2717+
26632718
/**
26642719
* ice_ptp_set_caps - Set PTP capabilities
26652720
* @pf: Board private structure
@@ -2686,6 +2741,9 @@ static void ice_ptp_set_caps(struct ice_pf *pf)
26862741
case ICE_MAC_E810:
26872742
ice_ptp_set_funcs_e810(pf);
26882743
return;
2744+
case ICE_MAC_E830:
2745+
ice_ptp_set_funcs_e830(pf);
2746+
return;
26892747
case ICE_MAC_GENERIC:
26902748
case ICE_MAC_GENERIC_3K_E825:
26912749
ice_ptp_set_funcs_e82x(pf);
@@ -2846,6 +2904,16 @@ irqreturn_t ice_ptp_ts_irq(struct ice_pf *pf)
28462904

28472905
set_bit(ICE_MISC_THREAD_TX_TSTAMP, pf->misc_thread);
28482906
return IRQ_WAKE_THREAD;
2907+
case ICE_MAC_E830:
2908+
/* E830 can read timestamps in the top half using rd32() */
2909+
if (ice_ptp_process_ts(pf) == ICE_TX_TSTAMP_WORK_PENDING) {
2910+
/* Process outstanding Tx timestamps. If there
2911+
* is more work, re-arm the interrupt to trigger again.
2912+
*/
2913+
wr32(hw, PFINT_OICR, PFINT_OICR_TSYN_TX_M);
2914+
ice_flush(hw);
2915+
}
2916+
return IRQ_HANDLED;
28492917
default:
28502918
return IRQ_HANDLED;
28512919
}
@@ -3231,6 +3299,7 @@ static int ice_ptp_init_port(struct ice_pf *pf, struct ice_ptp_port *ptp_port)
32313299

32323300
switch (hw->mac_type) {
32333301
case ICE_MAC_E810:
3302+
case ICE_MAC_E830:
32343303
case ICE_MAC_GENERIC_3K_E825:
32353304
return ice_ptp_init_tx(pf, &ptp_port->tx, ptp_port->port_num);
32363305
case ICE_MAC_GENERIC:

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