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crypto: octeontx2 - add ctx_val workaround
JIRA: https://issues.redhat.com/browse/RHEL-31478 Upstream Status: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git Conflicts: Minor context differences due to missing commit d887dec. commit e929711 Author: Srujana Challa <schalla@marvell.com> Date: Wed Dec 13 13:00:53 2023 +0530 crypto: octeontx2 - add ctx_val workaround HW has a errata that CPT HW may hit an issue, while processing CPT instructions with CTX_VAL set and CTX_VAL not set. So, this patch adds the code to always set the CTX_VAL as a workaround. Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Štěpán Horáček <shoracek@redhat.com>
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‎drivers/crypto/marvell/octeontx2/cn10k_cpt.c‎

Lines changed: 70 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,76 @@ int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf)
9696
}
9797
EXPORT_SYMBOL_NS_GPL(cn10k_cptvf_lmtst_init, CRYPTO_DEV_OCTEONTX2_CPT);
9898

99+
void cn10k_cpt_hw_ctx_clear(struct pci_dev *pdev,
100+
struct cn10k_cpt_errata_ctx *er_ctx)
101+
{
102+
u64 cptr_dma;
103+
104+
if (!is_dev_cn10ka_ax(pdev))
105+
return;
106+
107+
cptr_dma = er_ctx->cptr_dma & ~(BIT_ULL(60));
108+
cn10k_cpt_ctx_flush(pdev, cptr_dma, true);
109+
dma_unmap_single(&pdev->dev, cptr_dma, CN10K_CPT_HW_CTX_SIZE,
110+
DMA_BIDIRECTIONAL);
111+
kfree(er_ctx->hw_ctx);
112+
}
113+
EXPORT_SYMBOL_NS_GPL(cn10k_cpt_hw_ctx_clear, CRYPTO_DEV_OCTEONTX2_CPT);
114+
115+
void cn10k_cpt_hw_ctx_set(union cn10k_cpt_hw_ctx *hctx, u16 ctx_sz)
116+
{
117+
hctx->w0.aop_valid = 1;
118+
hctx->w0.ctx_hdr_sz = 0;
119+
hctx->w0.ctx_sz = ctx_sz;
120+
hctx->w0.ctx_push_sz = 1;
121+
}
122+
EXPORT_SYMBOL_NS_GPL(cn10k_cpt_hw_ctx_set, CRYPTO_DEV_OCTEONTX2_CPT);
123+
124+
int cn10k_cpt_hw_ctx_init(struct pci_dev *pdev,
125+
struct cn10k_cpt_errata_ctx *er_ctx)
126+
{
127+
union cn10k_cpt_hw_ctx *hctx;
128+
u64 cptr_dma;
129+
130+
er_ctx->cptr_dma = 0;
131+
er_ctx->hw_ctx = NULL;
132+
133+
if (!is_dev_cn10ka_ax(pdev))
134+
return 0;
135+
136+
hctx = kmalloc(CN10K_CPT_HW_CTX_SIZE, GFP_KERNEL);
137+
if (unlikely(!hctx))
138+
return -ENOMEM;
139+
cptr_dma = dma_map_single(&pdev->dev, hctx, CN10K_CPT_HW_CTX_SIZE,
140+
DMA_BIDIRECTIONAL);
141+
142+
cn10k_cpt_hw_ctx_set(hctx, 1);
143+
er_ctx->hw_ctx = hctx;
144+
er_ctx->cptr_dma = cptr_dma | BIT_ULL(60);
145+
146+
return 0;
147+
}
148+
EXPORT_SYMBOL_NS_GPL(cn10k_cpt_hw_ctx_init, CRYPTO_DEV_OCTEONTX2_CPT);
149+
150+
void cn10k_cpt_ctx_flush(struct pci_dev *pdev, u64 cptr, bool inval)
151+
{
152+
struct otx2_cptvf_dev *cptvf = pci_get_drvdata(pdev);
153+
struct otx2_cptlfs_info *lfs = &cptvf->lfs;
154+
u64 reg;
155+
156+
reg = (uintptr_t)cptr >> 7;
157+
if (inval)
158+
reg = reg | BIT_ULL(46);
159+
160+
otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, lfs->lf[0].slot,
161+
OTX2_CPT_LF_CTX_FLUSH, reg);
162+
/* Make sure that the FLUSH operation is complete */
163+
wmb();
164+
otx2_cpt_read64(lfs->reg_base, lfs->blkaddr, lfs->lf[0].slot,
165+
OTX2_CPT_LF_CTX_ERR);
166+
}
167+
EXPORT_SYMBOL_NS_GPL(cn10k_cpt_ctx_flush, CRYPTO_DEV_OCTEONTX2_CPT);
168+
99169
void cptvf_hw_ops_get(struct otx2_cptvf_dev *cptvf)
100170
{
101171
if (test_bit(CN10K_LMTST, &cptvf->cap_flag))

‎drivers/crypto/marvell/octeontx2/cn10k_cpt.h‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,26 @@
88
#include "otx2_cptpf.h"
99
#include "otx2_cptvf.h"
1010

11+
#define CN10K_CPT_HW_CTX_SIZE 256
12+
13+
union cn10k_cpt_hw_ctx {
14+
u64 u;
15+
struct {
16+
u64 reserved_0_47:48;
17+
u64 ctx_push_sz:7;
18+
u64 reserved_55:1;
19+
u64 ctx_hdr_sz:2;
20+
u64 aop_valid:1;
21+
u64 reserved_59:1;
22+
u64 ctx_sz:4;
23+
} w0;
24+
};
25+
26+
struct cn10k_cpt_errata_ctx {
27+
union cn10k_cpt_hw_ctx *hw_ctx;
28+
u64 cptr_dma;
29+
};
30+
1131
static inline u8 cn10k_cpt_get_compcode(union otx2_cpt_res_s *result)
1232
{
1333
return ((struct cn10k_cpt_res_s *)result)->compcode;
@@ -30,6 +50,12 @@ static inline u8 otx2_cpt_get_uc_compcode(union otx2_cpt_res_s *result)
3050

3151
int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf);
3252
int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf);
53+
void cn10k_cpt_ctx_flush(struct pci_dev *pdev, u64 cptr, bool inval);
54+
int cn10k_cpt_hw_ctx_init(struct pci_dev *pdev,
55+
struct cn10k_cpt_errata_ctx *er_ctx);
56+
void cn10k_cpt_hw_ctx_clear(struct pci_dev *pdev,
57+
struct cn10k_cpt_errata_ctx *er_ctx);
58+
void cn10k_cpt_hw_ctx_set(union cn10k_cpt_hw_ctx *hctx, u16 ctx_sz);
3359
void cptvf_hw_ops_get(struct otx2_cptvf_dev *cptvf);
3460

3561
#endif /* __CN10K_CPTLF_H */

‎drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -102,6 +102,8 @@
102102
#define OTX2_CPT_LF_Q_INST_PTR (0x110)
103103
#define OTX2_CPT_LF_Q_GRP_PTR (0x120)
104104
#define OTX2_CPT_LF_NQX(a) (0x400 | (a) << 3)
105+
#define OTX2_CPT_LF_CTX_FLUSH (0x510)
106+
#define OTX2_CPT_LF_CTX_ERR (0x520)
105107
#define OTX2_CPT_RVU_FUNC_BLKADDR_SHIFT 20
106108
/* LMT LF registers */
107109
#define OTX2_CPT_LMT_LFBASE BIT_ULL(OTX2_CPT_RVU_FUNC_BLKADDR_SHIFT)

‎drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,8 @@ struct otx2_cptvf_request {
4747
u32 param2;
4848
u16 dlen;
4949
union otx2_cpt_opcode opcode;
50+
dma_addr_t cptr_dma;
51+
void *cptr;
5052
};
5153

5254
/*

‎drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
1717
#include "otx2_cptvf.h"
1818
#include "otx2_cptvf_algs.h"
1919
#include "otx2_cpt_reqmgr.h"
20+
#include "cn10k_cpt.h"
2021

2122
/* Size of salt in AES GCM mode */
2223
#define AES_GCM_SALT_SIZE 4
@@ -384,6 +385,9 @@ static inline int cpt_enc_dec(struct skcipher_request *req, u32 enc)
384385
req_info->is_trunc_hmac = false;
385386
req_info->ctrl.s.grp = otx2_cpt_get_kcrypto_eng_grp_num(pdev);
386387

388+
req_info->req.cptr = ctx->er_ctx.hw_ctx;
389+
req_info->req.cptr_dma = ctx->er_ctx.cptr_dma;
390+
387391
/*
388392
* We perform an asynchronous send and once
389393
* the request is completed the driver would
@@ -530,6 +534,8 @@ static int otx2_cpt_enc_dec_init(struct crypto_skcipher *stfm)
530534
struct otx2_cpt_enc_ctx *ctx = crypto_skcipher_ctx(stfm);
531535
struct crypto_tfm *tfm = crypto_skcipher_tfm(stfm);
532536
struct crypto_alg *alg = tfm->__crt_alg;
537+
struct pci_dev *pdev;
538+
int ret, cpu_num;
533539

534540
memset(ctx, 0, sizeof(*ctx));
535541
/*
@@ -540,6 +546,15 @@ static int otx2_cpt_enc_dec_init(struct crypto_skcipher *stfm)
540546
crypto_skcipher_set_reqsize(stfm, sizeof(struct otx2_cpt_req_ctx) +
541547
sizeof(struct skcipher_request));
542548

549+
ret = get_se_device(&pdev, &cpu_num);
550+
if (ret)
551+
return ret;
552+
553+
ctx->pdev = pdev;
554+
ret = cn10k_cpt_hw_ctx_init(pdev, &ctx->er_ctx);
555+
if (ret)
556+
return ret;
557+
543558
return cpt_skcipher_fallback_init(ctx, alg);
544559
}
545560

@@ -551,6 +566,7 @@ static void otx2_cpt_skcipher_exit(struct crypto_skcipher *tfm)
551566
crypto_free_skcipher(ctx->fbk_cipher);
552567
ctx->fbk_cipher = NULL;
553568
}
569+
cn10k_cpt_hw_ctx_clear(ctx->pdev, &ctx->er_ctx);
554570
}
555571

556572
static int cpt_aead_fallback_init(struct otx2_cpt_aead_ctx *ctx,
@@ -575,6 +591,8 @@ static int cpt_aead_init(struct crypto_aead *atfm, u8 cipher_type, u8 mac_type)
575591
struct otx2_cpt_aead_ctx *ctx = crypto_aead_ctx(atfm);
576592
struct crypto_tfm *tfm = crypto_aead_tfm(atfm);
577593
struct crypto_alg *alg = tfm->__crt_alg;
594+
struct pci_dev *pdev;
595+
int ret, cpu_num;
578596

579597
ctx->cipher_type = cipher_type;
580598
ctx->mac_type = mac_type;
@@ -631,6 +649,15 @@ static int cpt_aead_init(struct crypto_aead *atfm, u8 cipher_type, u8 mac_type)
631649
}
632650
crypto_aead_set_reqsize(atfm, sizeof(struct otx2_cpt_req_ctx));
633651

652+
ret = get_se_device(&pdev, &cpu_num);
653+
if (ret)
654+
return ret;
655+
656+
ctx->pdev = pdev;
657+
ret = cn10k_cpt_hw_ctx_init(pdev, &ctx->er_ctx);
658+
if (ret)
659+
return ret;
660+
634661
return cpt_aead_fallback_init(ctx, alg);
635662
}
636663

@@ -693,6 +720,7 @@ static void otx2_cpt_aead_exit(struct crypto_aead *tfm)
693720
crypto_free_aead(ctx->fbk_cipher);
694721
ctx->fbk_cipher = NULL;
695722
}
723+
cn10k_cpt_hw_ctx_clear(ctx->pdev, &ctx->er_ctx);
696724
}
697725

698726
static int otx2_cpt_aead_gcm_set_authsize(struct crypto_aead *tfm,
@@ -1298,6 +1326,9 @@ static int cpt_aead_enc_dec(struct aead_request *req, u8 reg_type, u8 enc)
12981326
req_info->is_enc = enc;
12991327
req_info->is_trunc_hmac = false;
13001328

1329+
req_info->req.cptr = ctx->er_ctx.hw_ctx;
1330+
req_info->req.cptr_dma = ctx->er_ctx.cptr_dma;
1331+
13011332
switch (reg_type) {
13021333
case OTX2_CPT_AEAD_ENC_DEC_REQ:
13031334
status = create_aead_input_list(req, enc);

‎drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#include <crypto/skcipher.h>
1010
#include <crypto/aead.h>
1111
#include "otx2_cpt_common.h"
12+
#include "cn10k_cpt.h"
1213

1314
#define OTX2_CPT_MAX_ENC_KEY_SIZE 32
1415
#define OTX2_CPT_MAX_HASH_KEY_SIZE 64
@@ -123,6 +124,8 @@ struct otx2_cpt_enc_ctx {
123124
u8 key_type;
124125
u8 enc_align_len;
125126
struct crypto_skcipher *fbk_cipher;
127+
struct pci_dev *pdev;
128+
struct cn10k_cpt_errata_ctx er_ctx;
126129
};
127130

128131
union otx2_cpt_offset_ctrl {
@@ -161,6 +164,8 @@ struct otx2_cpt_aead_ctx {
161164
struct crypto_shash *hashalg;
162165
struct otx2_cpt_sdesc *sdesc;
163166
struct crypto_aead *fbk_cipher;
167+
struct cn10k_cpt_errata_ctx er_ctx;
168+
struct pci_dev *pdev;
164169
u8 *ipad;
165170
u8 *opad;
166171
u32 enc_key_len;

‎drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -159,7 +159,7 @@ static int process_request(struct pci_dev *pdev, struct otx2_cpt_req_info *req,
159159
cpu_to_be64s(&iq_cmd.cmd.u);
160160
iq_cmd.dptr = info->dptr_baddr | info->gthr_sz << 60;
161161
iq_cmd.rptr = info->rptr_baddr | info->sctr_sz << 60;
162-
iq_cmd.cptr.u = 0;
162+
iq_cmd.cptr.s.cptr = cpt_req->cptr_dma;
163163
iq_cmd.cptr.s.grp = ctrl->s.grp;
164164

165165
/* Fill in the CPT_INST_S type command for HW interpretation */

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