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cxl: core/region - ignore interleave granularity when ways=1
jira LE-4395 Rebuild_History Non-Buildable kernel-6.12.0-55.39.1.el10_0 commit-author Gregory Price <gourry@gourry.net> commit ce32b0c Empty-Commit: Cherry-Pick Conflicts during history rebuild. Will be included in final tarball splat. Ref for failed cherry-pick at: ciq/ciq_backports/kernel-6.12.0-55.39.1.el10_0/ce32b0c9.failed When validating decoder IW/IG when setting up regions, the granularity is irrelevant when iw=1 - all accesses will always route to the only target anyway - so all ig values are "correct". Loosen the requirement that `ig = (parent_iw * parent_ig)` when iw=1. On some Zen5 platforms, the platform BIOS specifies a 256-byte interleave granularity window for host bridges when there is only one target downstream. This leads to Linux rejecting the configuration of a region with a x2 root with two x1 hostbridges. Decoder Programming: root - iw:2 ig:256 hb1 - iw:1 ig:256 (Linux expects 512) hb2 - iw:1 ig:256 (Linux expects 512) ep1 - iw:2 ig:256 ep2 - iw:2 ig:256 This change allows all decoders downstream of a passthrough decoder to also be configured as passthrough (iw:1 ig:X), but still disallows downstream decoders from applying subsequent interleaves. e.g. in the above example if there was another decoder south of hb1 attempting to interleave 2 endpoints - Linux would enforce hb1.ig=512 because the southern decoder would have iw:2 and require ig=pig*piw. [DJ: Fixed up against 6.15-rc1] Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Tested-by: Li Zhijian <lizhijian@fujitsu.com> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250402232552.999634-1-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com> (cherry picked from commit ce32b0c) Signed-off-by: Jonathan Maple <jmaple@ciq.com> # Conflicts: # drivers/cxl/core/region.c
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cxl: core/region - ignore interleave granularity when ways=1
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jira LE-4395
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Rebuild_History Non-Buildable kernel-6.12.0-55.39.1.el10_0
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commit-author Gregory Price <gourry@gourry.net>
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commit ce32b0c9c522e5a69ef9c62a56d6ca08fb036d67
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Empty-Commit: Cherry-Pick Conflicts during history rebuild.
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Will be included in final tarball splat. Ref for failed cherry-pick at:
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ciq/ciq_backports/kernel-6.12.0-55.39.1.el10_0/ce32b0c9.failed
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When validating decoder IW/IG when setting up regions, the granularity
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is irrelevant when iw=1 - all accesses will always route to the only
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target anyway - so all ig values are "correct". Loosen the requirement
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that `ig = (parent_iw * parent_ig)` when iw=1.
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On some Zen5 platforms, the platform BIOS specifies a 256-byte
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interleave granularity window for host bridges when there is only
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one target downstream. This leads to Linux rejecting the configuration
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of a region with a x2 root with two x1 hostbridges.
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Decoder Programming:
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root - iw:2 ig:256
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hb1 - iw:1 ig:256 (Linux expects 512)
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hb2 - iw:1 ig:256 (Linux expects 512)
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ep1 - iw:2 ig:256
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ep2 - iw:2 ig:256
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This change allows all decoders downstream of a passthrough decoder to
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also be configured as passthrough (iw:1 ig:X), but still disallows
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downstream decoders from applying subsequent interleaves.
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e.g. in the above example if there was another decoder south of hb1
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attempting to interleave 2 endpoints - Linux would enforce hb1.ig=512
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because the southern decoder would have iw:2 and require ig=pig*piw.
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[DJ: Fixed up against 6.15-rc1]
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Signed-off-by: Gregory Price <gourry@gourry.net>
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Reviewed-by: Dave Jiang <dave.jiang@intel.com>
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Tested-by: Li Zhijian <lizhijian@fujitsu.com>
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Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
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Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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Reviewed-by: Dan Williams <dan.j.williams@intel.com>
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Link: https://patch.msgid.link/20250402232552.999634-1-gourry@gourry.net
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Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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(cherry picked from commit ce32b0c9c522e5a69ef9c62a56d6ca08fb036d67)
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Signed-off-by: Jonathan Maple <jmaple@ciq.com>
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# Conflicts:
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# drivers/cxl/core/region.c
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diff --cc drivers/cxl/core/region.c
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index dff618c708dc,80caaf14d08a..000000000000
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--- a/drivers/cxl/core/region.c
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+++ b/drivers/cxl/core/region.c
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@@@ -1412,9 -1446,8 +1412,14 @@@ static int cxl_port_setup_targets(struc
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if (test_bit(CXL_REGION_F_AUTO, &cxlr->flags)) {
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if (cxld->interleave_ways != iw ||
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++<<<<<<< HEAD
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+ cxld->interleave_granularity != ig ||
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+ cxld->hpa_range.start != p->res->start ||
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+ cxld->hpa_range.end != p->res->end ||
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++=======
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+ (iw > 1 && cxld->interleave_granularity != ig) ||
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+ !region_res_match_cxl_range(p, &cxld->hpa_range) ||
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++>>>>>>> ce32b0c9c522 (cxl: core/region - ignore interleave granularity when ways=1)
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((cxld->flags & CXL_DECODER_F_ENABLE) == 0)) {
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dev_err(&cxlr->dev,
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"%s:%s %s expected iw: %d ig: %d %pr\n",
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* Unmerged path drivers/cxl/core/region.c

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