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Merge tag 'riscv-for-linus-5.16-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V Fixes for 5.16-rc4 - .rodata is no longer linkd into PT_DYNAMIC. It was not supposed to be there in the first place and resulted in invalid (but unused) entries. This manifests as at least warnings in llvm-readelf - A fix for runtime constants with all-0 upper 32-bits. This should only manifest on MMU=n kernels - A fix for context save/restore on systems using the T-Head vector extensions - A fix for a conflicting "+r"/"r" register constraint in the VDSO getrandom syscall wrapper, which is undefined behavior in clang - A fix for a missing register clobber in the RVV raid6 implementation. This manifests as a NULL pointer reference on some compilers, but could trigger in other ways - Misaligned accesses from userspace at faulting addresses are now handled correctly - A fix for an incorrect optimization that allowed access_ok() to mark invalid addresses as accessible, which can result in userspace triggering BUG()s - A few fixes for build warnings, and an update to Drew's email address * tag 'riscv-for-linus-5.16-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: export boot_cpu_hartid Revert "riscv: Define TASK_SIZE_MAX for __access_ok()" riscv: Fix sparse warning in vendor_extensions/sifive.c Revert "riscv: misaligned: fix sleeping function called during misaligned access handling" MAINTAINERS: Update Drew Fustini's email address RISC-V: uaccess: Wrap the get_user_8 uaccess macro raid6: riscv: Fix NULL pointer dereference caused by a missing clobber RISC-V: vDSO: Correct inline assembly constraints in the getrandom syscall wrapper riscv: vector: Fix context save/restore with xtheadvector riscv: fix runtime constant support for nommu kernels riscv: vdso: Exclude .rodata from the PT_DYNAMIC segment
2 parents fa33adc + c5136ad commit 867b998

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‎.mailmap‎

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@@ -223,6 +223,7 @@ Dmitry Safonov <0x7f454c46@gmail.com> <d.safonov@partner.samsung.com>
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Dmitry Safonov <0x7f454c46@gmail.com> <dsafonov@virtuozzo.com>
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Domen Puncer <domen@coderock.org>
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Douglas Gilbert <dougg@torque.net>
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Drew Fustini <fustini@kernel.org> <drew@pdp7.com>
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Ed L. Cashin <ecashin@coraid.com>
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Elliot Berman <quic_eberman@quicinc.com> <eberman@codeaurora.org>
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Enric Balletbo i Serra <eballetbo@kernel.org> <enric.balletbo@collabora.com>

‎MAINTAINERS‎

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@@ -21388,7 +21388,7 @@ N: spacemit
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K: spacemit
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RISC-V THEAD SoC SUPPORT
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M: Drew Fustini <drew@pdp7.com>
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M: Drew Fustini <fustini@kernel.org>
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M: Guo Ren <guoren@kernel.org>
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M: Fu Wei <wefu@redhat.com>
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L: linux-riscv@lists.infradead.org

‎arch/riscv/include/asm/pgtable.h‎

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@@ -1075,7 +1075,6 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte)
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*/
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#ifdef CONFIG_64BIT
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#define TASK_SIZE_64 (PGDIR_SIZE * PTRS_PER_PGD / 2)
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#define TASK_SIZE_MAX LONG_MAX
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#ifdef CONFIG_COMPAT
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#define TASK_SIZE_32 (_AC(0x80000000, UL) - PAGE_SIZE)

‎arch/riscv/include/asm/runtime-const.h‎

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@@ -206,7 +206,7 @@ static inline void __runtime_fixup_32(__le16 *lui_parcel, __le16 *addi_parcel, u
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addi_insn_mask &= 0x07fff;
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}
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if (lower_immediate & 0x00000fff) {
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if (lower_immediate & 0x00000fff || lui_insn == RISCV_INSN_NOP4) {
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/* replace upper 12 bits of addi with lower 12 bits of val */
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addi_insn &= addi_insn_mask;
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addi_insn |= (lower_immediate & 0x00000fff) << 20;

‎arch/riscv/include/asm/uaccess.h‎

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@@ -127,6 +127,7 @@ do { \
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#ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT
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#define __get_user_8(x, ptr, label) \
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do { \
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u32 __user *__ptr = (u32 __user *)(ptr); \
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u32 __lo, __hi; \
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asm_goto_output( \
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: : label); \
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(x) = (__typeof__(x))((__typeof__((x) - (x)))( \
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(((u64)__hi << 32) | __lo))); \
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} while (0)
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#else /* !CONFIG_CC_HAS_ASM_GOTO_OUTPUT */
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#define __get_user_8(x, ptr, label) \
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do { \

‎arch/riscv/include/asm/vdso/getrandom.h‎

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@@ -18,7 +18,7 @@ static __always_inline ssize_t getrandom_syscall(void *_buffer, size_t _len, uns
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register unsigned int flags asm("a2") = _flags;
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asm volatile ("ecall\n"
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: "+r" (ret)
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: "=r" (ret)
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: "r" (nr), "r" (buffer), "r" (len), "r" (flags)
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: "memory");
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‎arch/riscv/include/asm/vector.h‎

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@@ -205,11 +205,11 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to,
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THEAD_VSETVLI_T4X0E8M8D1
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THEAD_VSB_V_V0T0
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"add t0, t0, t4\n\t"
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THEAD_VSB_V_V0T0
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THEAD_VSB_V_V8T0
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"add t0, t0, t4\n\t"
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THEAD_VSB_V_V0T0
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THEAD_VSB_V_V16T0
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"add t0, t0, t4\n\t"
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THEAD_VSB_V_V0T0
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THEAD_VSB_V_V24T0
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: : "r" (datap) : "memory", "t0", "t4");
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} else {
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asm volatile (
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THEAD_VSETVLI_T4X0E8M8D1
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THEAD_VLB_V_V0T0
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"add t0, t0, t4\n\t"
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THEAD_VLB_V_V0T0
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THEAD_VLB_V_V8T0
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"add t0, t0, t4\n\t"
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THEAD_VLB_V_V0T0
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THEAD_VLB_V_V16T0
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"add t0, t0, t4\n\t"
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THEAD_VLB_V_V24T0
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: : "r" (datap) : "memory", "t0", "t4");
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} else {
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asm volatile (

‎arch/riscv/kernel/setup.c‎

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@@ -50,6 +50,7 @@ atomic_t hart_lottery __section(".sdata")
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#endif
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;
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unsigned long boot_cpu_hartid;
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EXPORT_SYMBOL_GPL(boot_cpu_hartid);
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/*
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* Place kernel memory regions on the resource tree so that

‎arch/riscv/kernel/traps_misaligned.c‎

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@@ -454,7 +454,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs)
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val.data_u64 = 0;
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if (user_mode(regs)) {
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if (copy_from_user_nofault(&val, (u8 __user *)addr, len))
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if (copy_from_user(&val, (u8 __user *)addr, len))
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return -1;
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} else {
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memcpy(&val, (u8 *)addr, len);
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if (user_mode(regs)) {
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if (copy_to_user_nofault((u8 __user *)addr, &val, len))
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if (copy_to_user((u8 __user *)addr, &val, len))
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return -1;
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} else {
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memcpy((u8 *)addr, &val, len);

‎arch/riscv/kernel/vdso/vdso.lds.S‎

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@@ -30,7 +30,7 @@ SECTIONS
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*(.data .data.* .gnu.linkonce.d.*)
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*(.dynbss)
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*(.bss .bss.* .gnu.linkonce.b.*)
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}
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} :text
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.note : { *(.note.*) } :text :note
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