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arm64: dts: s32g: add FlexCAN[0..3] support for s32g2 and s32g3
JIRA: https://issues.redhat.com/browse/RHEL-116642 commit e82bc7c Author: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Date: Mon Feb 24 15:40:16 2025 +0200 arm64: dts: s32g: add FlexCAN[0..3] support for s32g2 and s32g3 Add FlexCAN[0..3] for S32G2 and S32G3 SoCs. Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Jared Kangas <jkangas@redhat.com>
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‎arch/arm64/boot/dts/freescale/s32g2.dtsi‎

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -334,6 +334,32 @@
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clock-names = "dmamux0", "dmamux1";
335335
};
336336

337+
can0: can@401b4000 {
338+
compatible = "nxp,s32g2-flexcan";
339+
reg = <0x401b4000 0xa000>;
340+
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
342+
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
343+
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
344+
interrupt-names = "mb-0", "state", "berr", "mb-1";
345+
clocks = <&clks 9>, <&clks 11>;
346+
clock-names = "ipg", "per";
347+
status = "disabled";
348+
};
349+
350+
can1: can@401be000 {
351+
compatible = "nxp,s32g2-flexcan";
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reg = <0x401be000 0xa000>;
353+
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
357+
interrupt-names = "mb-0", "state", "berr", "mb-1";
358+
clocks = <&clks 9>, <&clks 11>;
359+
clock-names = "ipg", "per";
360+
status = "disabled";
361+
};
362+
337363
uart0: serial@401c8000 {
338364
compatible = "nxp,s32g2-linflexuart",
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"fsl,s32v234-linflexuart";
@@ -400,6 +426,32 @@
400426
clock-names = "dmamux0", "dmamux1";
401427
};
402428

429+
can2: can@402a8000 {
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compatible = "nxp,s32g2-flexcan";
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reg = <0x402a8000 0xa000>;
432+
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mb-0", "state", "berr", "mb-1";
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clocks = <&clks 9>, <&clks 11>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
441+
442+
can3: can@402b2000 {
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compatible = "nxp,s32g2-flexcan";
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reg = <0x402b2000 0xa000>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mb-0", "state", "berr", "mb-1";
450+
clocks = <&clks 9>, <&clks 11>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
454+
403455
uart2: serial@402bc000 {
404456
compatible = "nxp,s32g2-linflexuart",
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"fsl,s32v234-linflexuart";

‎arch/arm64/boot/dts/freescale/s32g3.dtsi‎

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Original file line numberDiff line numberDiff line change
@@ -391,6 +391,34 @@
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clock-names = "dmamux0", "dmamux1";
392392
};
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can0: can@401b4000 {
395+
compatible = "nxp,s32g3-flexcan",
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"nxp,s32g2-flexcan";
397+
reg = <0x401b4000 0xa000>;
398+
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
399+
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
400+
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
401+
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
402+
interrupt-names = "mb-0", "state", "berr", "mb-1";
403+
clocks = <&clks 9>, <&clks 11>;
404+
clock-names = "ipg", "per";
405+
status = "disabled";
406+
};
407+
408+
can1: can@401be000 {
409+
compatible = "nxp,s32g3-flexcan",
410+
"nxp,s32g2-flexcan";
411+
reg = <0x401be000 0xa000>;
412+
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
413+
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
415+
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
416+
interrupt-names = "mb-0", "state", "berr", "mb-1";
417+
clocks = <&clks 9>, <&clks 11>;
418+
clock-names = "ipg", "per";
419+
status = "disabled";
420+
};
421+
394422
uart0: serial@401c8000 {
395423
compatible = "nxp,s32g3-linflexuart",
396424
"fsl,s32v234-linflexuart";
@@ -460,6 +488,34 @@
460488
clock-names = "dmamux0", "dmamux1";
461489
};
462490

491+
can2: can@402a8000 {
492+
compatible = "nxp,s32g3-flexcan",
493+
"nxp,s32g2-flexcan";
494+
reg = <0x402a8000 0xa000>;
495+
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
496+
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
497+
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
498+
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
499+
interrupt-names = "mb-0", "state", "berr", "mb-1";
500+
clocks = <&clks 9>, <&clks 11>;
501+
clock-names = "ipg", "per";
502+
status = "disabled";
503+
};
504+
505+
can3: can@402b2000 {
506+
compatible = "nxp,s32g3-flexcan",
507+
"nxp,s32g2-flexcan";
508+
reg = <0x402b2000 0xa000>;
509+
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
510+
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
511+
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
512+
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
513+
interrupt-names = "mb-0", "state", "berr", "mb-1";
514+
clocks = <&clks 9>, <&clks 11>;
515+
clock-names = "ipg", "per";
516+
status = "disabled";
517+
};
518+
463519
uart2: serial@402bc000 {
464520
compatible = "nxp,s32g3-linflexuart",
465521
"fsl,s32v234-linflexuart";

‎arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi‎

Lines changed: 72 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,60 @@
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*/
99

1010
&pinctrl {
11+
can0_pins: can0-pins {
12+
can0-grp0 {
13+
pinmux = <0x2c1>;
14+
output-enable;
15+
slew-rate = <133>;
16+
};
17+
18+
can0-grp1 {
19+
pinmux = <0x2b0>;
20+
input-enable;
21+
slew-rate = <133>;
22+
};
23+
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can0-grp2 {
25+
pinmux = <0x2012>;
26+
};
27+
};
28+
29+
can2_pins: can2-pins {
30+
can2-grp0 {
31+
pinmux = <0x1b2>;
32+
output-enable;
33+
slew-rate = <133>;
34+
};
35+
36+
can2-grp1 {
37+
pinmux = <0x1c0>;
38+
input-enable;
39+
slew-rate = <133>;
40+
};
41+
42+
can2-grp2 {
43+
pinmux = <0x2782>;
44+
};
45+
};
46+
47+
can3_pins: can3-pins {
48+
can3-grp0 {
49+
pinmux = <0x192>;
50+
output-enable;
51+
slew-rate = <133>;
52+
};
53+
54+
can3-grp1 {
55+
pinmux = <0x1a0>;
56+
input-enable;
57+
slew-rate = <133>;
58+
};
59+
60+
can3-grp2 {
61+
pinmux = <0x2792>;
62+
};
63+
};
64+
1165
i2c0_pins: i2c0-pins {
1266
i2c0-grp0 {
1367
pinmux = <0x101>, <0x111>;
@@ -121,6 +175,24 @@
121175
};
122176
};
123177

178+
&can0 {
179+
pinctrl-names = "default";
180+
pinctrl-0 = <&can0_pins>;
181+
status = "okay";
182+
};
183+
184+
&can2 {
185+
pinctrl-names = "default";
186+
pinctrl-0 = <&can2_pins>;
187+
status = "okay";
188+
};
189+
190+
&can3 {
191+
pinctrl-names = "default";
192+
pinctrl-0 = <&can3_pins>;
193+
status = "okay";
194+
};
195+
124196
&i2c0 {
125197
pinctrl-names = "default", "gpio";
126198
pinctrl-0 = <&i2c0_pins>;

‎arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi‎

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,42 @@
88
*/
99

1010
&pinctrl {
11+
can0_pins: can0-pins {
12+
can0-grp0 {
13+
pinmux = <0x112>;
14+
output-enable;
15+
slew-rate = <133>;
16+
};
17+
18+
can0-grp1 {
19+
pinmux = <0x120>;
20+
input-enable;
21+
slew-rate = <133>;
22+
};
23+
24+
can0-grp2 {
25+
pinmux = <0x2013>;
26+
};
27+
};
28+
29+
can1_pins: can1-pins {
30+
can1-grp0 {
31+
pinmux = <0x132>;
32+
output-enable;
33+
slew-rate = <133>;
34+
};
35+
36+
can1-grp1 {
37+
pinmux = <0x140>;
38+
input-enable;
39+
slew-rate = <133>;
40+
};
41+
42+
can1-grp2 {
43+
pinmux = <0x2772>;
44+
};
45+
};
46+
1147
i2c0_pins: i2c0-pins {
1248
i2c0-grp0 {
1349
pinmux = <0x1f2>, <0x201>;
@@ -93,6 +129,18 @@
93129
};
94130
};
95131

132+
&can0 {
133+
pinctrl-names = "default";
134+
pinctrl-0 = <&can0_pins>;
135+
status = "okay";
136+
};
137+
138+
&can1 {
139+
pinctrl-names = "default";
140+
pinctrl-0 = <&can1_pins>;
141+
status = "okay";
142+
};
143+
96144
&i2c0 {
97145
pinctrl-names = "default", "gpio";
98146
pinctrl-0 = <&i2c0_pins>;

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