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| 1 | +x86/bhi: Define SPEC_CTRL_BHI_DIS_S |
| 2 | + |
| 3 | +jira LE-2015 |
| 4 | +cve CVE-2024-2201 |
| 5 | +Rebuild_History Non-Buildable kernel-5.14.0-427.42.1.el9_4 |
| 6 | +commit-author Daniel Sneddon <daniel.sneddon@linux.intel.com> |
| 7 | +commit 0f4a837615ff925ba62648d280a861adf1582df7 |
| 8 | +Empty-Commit: Cherry-Pick Conflicts during history rebuild. |
| 9 | +Will be included in final tarball splat. Ref for failed cherry-pick at: |
| 10 | +ciq/ciq_backports/kernel-5.14.0-427.42.1.el9_4/0f4a8376.failed |
| 11 | + |
| 12 | +Newer processors supports a hardware control BHI_DIS_S to mitigate |
| 13 | +Branch History Injection (BHI). Setting BHI_DIS_S protects the kernel |
| 14 | +from userspace BHI attacks without having to manually overwrite the |
| 15 | +branch history. |
| 16 | + |
| 17 | +Define MSR_SPEC_CTRL bit BHI_DIS_S and its enumeration CPUID.BHI_CTRL. |
| 18 | +Mitigation is enabled later. |
| 19 | + |
| 20 | + Signed-off-by: Daniel Sneddon <daniel.sneddon@linux.intel.com> |
| 21 | + Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> |
| 22 | + Signed-off-by: Daniel Sneddon <daniel.sneddon@linux.intel.com> |
| 23 | + Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
| 24 | + Reviewed-by: Alexandre Chartre <alexandre.chartre@oracle.com> |
| 25 | + Reviewed-by: Josh Poimboeuf <jpoimboe@kernel.org> |
| 26 | + |
| 27 | +(cherry picked from commit 0f4a837615ff925ba62648d280a861adf1582df7) |
| 28 | + Signed-off-by: Jonathan Maple <jmaple@ciq.com> |
| 29 | + |
| 30 | +# Conflicts: |
| 31 | +# arch/x86/include/asm/cpufeatures.h |
| 32 | +diff --cc arch/x86/include/asm/cpufeatures.h |
| 33 | +index 86f4c8a3ef63,408509070429..000000000000 |
| 34 | +--- a/arch/x86/include/asm/cpufeatures.h |
| 35 | ++++ b/arch/x86/include/asm/cpufeatures.h |
| 36 | +@@@ -462,6 -466,8 +462,11 @@@ |
| 37 | + * Reuse free bits when adding new feature flags! |
| 38 | + */ |
| 39 | + #define X86_FEATURE_AMD_LBR_PMC_FREEZE (21*32+ 0) /* AMD LBR and PMC Freeze */ |
| 40 | +++<<<<<<< HEAD |
| 41 | +++======= |
| 42 | ++ #define X86_FEATURE_CLEAR_BHB_LOOP (21*32+ 1) /* "" Clear branch history at syscall entry using SW loop */ |
| 43 | ++ #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* "" BHI_DIS_S HW control available */ |
| 44 | +++>>>>>>> 0f4a837615ff (x86/bhi: Define SPEC_CTRL_BHI_DIS_S) |
| 45 | + |
| 46 | + /* |
| 47 | + * BUG word(s) |
| 48 | +* Unmerged path arch/x86/include/asm/cpufeatures.h |
| 49 | +diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h |
| 50 | +index 33e66c7fbb2c..e7813d9f6cb7 100644 |
| 51 | +--- a/arch/x86/include/asm/msr-index.h |
| 52 | ++++ b/arch/x86/include/asm/msr-index.h |
| 53 | +@@ -50,10 +50,13 @@ |
| 54 | + #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ |
| 55 | + #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ |
| 56 | + #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) |
| 57 | ++#define SPEC_CTRL_BHI_DIS_S_SHIFT 10 /* Disable Branch History Injection behavior */ |
| 58 | ++#define SPEC_CTRL_BHI_DIS_S BIT(SPEC_CTRL_BHI_DIS_S_SHIFT) |
| 59 | + |
| 60 | + /* A mask for bits which the kernel toggles when controlling mitigations */ |
| 61 | + #define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \ |
| 62 | +- | SPEC_CTRL_RRSBA_DIS_S) |
| 63 | ++ | SPEC_CTRL_RRSBA_DIS_S \ |
| 64 | ++ | SPEC_CTRL_BHI_DIS_S) |
| 65 | + |
| 66 | + #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ |
| 67 | + #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ |
| 68 | +diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c |
| 69 | +index 4e8045574973..b795d46a5c90 100644 |
| 70 | +--- a/arch/x86/kernel/cpu/scattered.c |
| 71 | ++++ b/arch/x86/kernel/cpu/scattered.c |
| 72 | +@@ -27,6 +27,7 @@ static const struct cpuid_bit cpuid_bits[] = { |
| 73 | + { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 }, |
| 74 | + { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 }, |
| 75 | + { X86_FEATURE_RRSBA_CTRL, CPUID_EDX, 2, 0x00000007, 2 }, |
| 76 | ++ { X86_FEATURE_BHI_CTRL, CPUID_EDX, 4, 0x00000007, 2 }, |
| 77 | + { X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 }, |
| 78 | + { X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 }, |
| 79 | + { X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 }, |
| 80 | +diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h |
| 81 | +index aadefcaa9561..da9880d74a0b 100644 |
| 82 | +--- a/arch/x86/kvm/reverse_cpuid.h |
| 83 | ++++ b/arch/x86/kvm/reverse_cpuid.h |
| 84 | +@@ -52,7 +52,7 @@ enum kvm_only_cpuid_leafs { |
| 85 | + #define X86_FEATURE_IPRED_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 1) |
| 86 | + #define KVM_X86_FEATURE_RRSBA_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 2) |
| 87 | + #define X86_FEATURE_DDPD_U KVM_X86_FEATURE(CPUID_7_2_EDX, 3) |
| 88 | +-#define X86_FEATURE_BHI_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 4) |
| 89 | ++#define KVM_X86_FEATURE_BHI_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 4) |
| 90 | + #define X86_FEATURE_MCDT_NO KVM_X86_FEATURE(CPUID_7_2_EDX, 5) |
| 91 | + |
| 92 | + /* CPUID level 0x80000007 (EDX). */ |
| 93 | +@@ -126,6 +126,7 @@ static __always_inline u32 __feature_translate(int x86_feature) |
| 94 | + KVM_X86_TRANSLATE_FEATURE(CONSTANT_TSC); |
| 95 | + KVM_X86_TRANSLATE_FEATURE(PERFMON_V2); |
| 96 | + KVM_X86_TRANSLATE_FEATURE(RRSBA_CTRL); |
| 97 | ++ KVM_X86_TRANSLATE_FEATURE(BHI_CTRL); |
| 98 | + default: |
| 99 | + return x86_feature; |
| 100 | + } |
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