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Merge tag 'bitmap-for-6.18' of https://github.com/norov/linux
Pull bitmap updates from Yury Norov: - FIELD_PREP_WM16() consolidation (Nicolas) - bitmaps for Rust (Burak) - __fls() fix for arc (Kees) * tag 'bitmap-for-6.18' of https://github.com/norov/linux: (25 commits) rust: add dynamic ID pool abstraction for bitmap rust: add find_bit_benchmark_rust module. rust: add bitmap API. rust: add bindings for bitops.h rust: add bindings for bitmap.h phy: rockchip-pcie: switch to FIELD_PREP_WM16 macro clk: sp7021: switch to FIELD_PREP_WM16 macro PCI: dw-rockchip: Switch to FIELD_PREP_WM16 macro PCI: rockchip: Switch to FIELD_PREP_WM16* macros net: stmmac: dwmac-rk: switch to FIELD_PREP_WM16 macro ASoC: rockchip: i2s-tdm: switch to FIELD_PREP_WM16_CONST macro drm/rockchip: dw_hdmi: switch to FIELD_PREP_WM16* macros phy: rockchip-usb: switch to FIELD_PREP_WM16 macro drm/rockchip: inno-hdmi: switch to FIELD_PREP_WM16 macro drm/rockchip: dw_hdmi_qp: switch to FIELD_PREP_WM16 macro phy: rockchip-samsung-dcphy: switch to FIELD_PREP_WM16 macro drm/rockchip: vop2: switch to FIELD_PREP_WM16 macro drm/rockchip: dsi: switch to FIELD_PREP_WM16* macros phy: rockchip-emmc: switch to FIELD_PREP_WM16 macro drm/rockchip: lvds: switch to FIELD_PREP_WM16 macro ...
2 parents d7a018e + 2cdae41 commit 77633c7

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33 files changed

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-339
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33 files changed

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‎MAINTAINERS‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4298,6 +4298,7 @@ F: include/linux/bits.h
42984298
F: include/linux/cpumask.h
42994299
F: include/linux/cpumask_types.h
43004300
F: include/linux/find.h
4301+
F: include/linux/hw_bitfield.h
43014302
F: include/linux/nodemask.h
43024303
F: include/linux/nodemask_types.h
43034304
F: include/uapi/linux/bits.h
@@ -4321,8 +4322,18 @@ F: tools/lib/find_bit.c
43214322
BITMAP API BINDINGS [RUST]
43224323
M: Yury Norov <yury.norov@gmail.com>
43234324
S: Maintained
4325+
F: rust/helpers/bitmap.c
43244326
F: rust/helpers/cpumask.c
43254327

4328+
BITMAP API [RUST]
4329+
M: Alice Ryhl <aliceryhl@google.com>
4330+
M: Burak Emir <bqe@google.com>
4331+
R: Yury Norov <yury.norov@gmail.com>
4332+
S: Maintained
4333+
F: lib/find_bit_benchmark_rust.rs
4334+
F: rust/kernel/bitmap.rs
4335+
F: rust/kernel/id_pool.rs
4336+
43264337
BITOPS API
43274338
M: Yury Norov <yury.norov@gmail.com>
43284339
R: Rasmus Villemoes <linux@rasmusvillemoes.dk>
@@ -4337,6 +4348,11 @@ F: include/linux/bitops.h
43374348
F: lib/test_bitops.c
43384349
F: tools/*/bitops*
43394350

4351+
BITOPS API BINDINGS [RUST]
4352+
M: Yury Norov <yury.norov@gmail.com>
4353+
S: Maintained
4354+
F: rust/helpers/bitops.c
4355+
43404356
BLINKM RGB LED DRIVER
43414357
M: Jan-Simon Moeller <jansimon.moeller@gmx.de>
43424358
S: Maintained

‎arch/arc/include/asm/bitops.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -133,6 +133,8 @@ static inline __attribute__ ((const)) int fls(unsigned int x)
133133
*/
134134
static inline __attribute__ ((const)) unsigned long __fls(unsigned long x)
135135
{
136+
if (__builtin_constant_p(x))
137+
return x ? BITS_PER_LONG - 1 - __builtin_clzl(x) : 0;
136138
/* FLS insn has exactly same semantics as the API */
137139
return __builtin_arc_fls(x);
138140
}

‎drivers/clk/clk-sp7021.c‎

Lines changed: 8 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
#include <linux/clk-provider.h>
88
#include <linux/of.h>
99
#include <linux/bitfield.h>
10+
#include <linux/hw_bitfield.h>
1011
#include <linux/slab.h>
1112
#include <linux/io.h>
1213
#include <linux/err.h>
@@ -38,13 +39,6 @@ enum {
3839
#define MASK_DIVN GENMASK(7, 0)
3940
#define MASK_DIVM GENMASK(14, 8)
4041

41-
/* HIWORD_MASK FIELD_PREP */
42-
#define HWM_FIELD_PREP(mask, value) \
43-
({ \
44-
u64 _m = mask; \
45-
(_m << 16) | FIELD_PREP(_m, value); \
46-
})
47-
4842
struct sp_pll {
4943
struct clk_hw hw;
5044
void __iomem *reg;
@@ -313,15 +307,15 @@ static int plltv_set_rate(struct sp_pll *clk)
313307
u32 r0, r1, r2;
314308

315309
r0 = BIT(clk->bp_bit + 16);
316-
r0 |= HWM_FIELD_PREP(MASK_SEL_FRA, clk->p[SEL_FRA]);
317-
r0 |= HWM_FIELD_PREP(MASK_SDM_MOD, clk->p[SDM_MOD]);
318-
r0 |= HWM_FIELD_PREP(MASK_PH_SEL, clk->p[PH_SEL]);
319-
r0 |= HWM_FIELD_PREP(MASK_NFRA, clk->p[NFRA]);
310+
r0 |= FIELD_PREP_WM16(MASK_SEL_FRA, clk->p[SEL_FRA]);
311+
r0 |= FIELD_PREP_WM16(MASK_SDM_MOD, clk->p[SDM_MOD]);
312+
r0 |= FIELD_PREP_WM16(MASK_PH_SEL, clk->p[PH_SEL]);
313+
r0 |= FIELD_PREP_WM16(MASK_NFRA, clk->p[NFRA]);
320314

321-
r1 = HWM_FIELD_PREP(MASK_DIVR, clk->p[DIVR]);
315+
r1 = FIELD_PREP_WM16(MASK_DIVR, clk->p[DIVR]);
322316

323-
r2 = HWM_FIELD_PREP(MASK_DIVN, clk->p[DIVN] - 1);
324-
r2 |= HWM_FIELD_PREP(MASK_DIVM, clk->p[DIVM] - 1);
317+
r2 = FIELD_PREP_WM16(MASK_DIVN, clk->p[DIVN] - 1);
318+
r2 |= FIELD_PREP_WM16(MASK_DIVM, clk->p[DIVM] - 1);
325319

326320
spin_lock_irqsave(&clk->lock, flags);
327321
writel(r0, clk->reg);

‎drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c‎

Lines changed: 68 additions & 74 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
*/
88

99
#include <linux/clk.h>
10+
#include <linux/hw_bitfield.h>
1011
#include <linux/iopoll.h>
1112
#include <linux/math64.h>
1213
#include <linux/mfd/syscon.h>
@@ -148,7 +149,7 @@
148149
#define DW_MIPI_NEEDS_GRF_CLK BIT(1)
149150

150151
#define PX30_GRF_PD_VO_CON1 0x0438
151-
#define PX30_DSI_FORCETXSTOPMODE (0xf << 7)
152+
#define PX30_DSI_FORCETXSTOPMODE (0xfUL << 7)
152153
#define PX30_DSI_FORCERXMODE BIT(6)
153154
#define PX30_DSI_TURNDISABLE BIT(5)
154155
#define PX30_DSI_LCDC_SEL BIT(0)
@@ -167,16 +168,16 @@
167168
#define RK3399_DSI1_LCDC_SEL BIT(4)
168169

169170
#define RK3399_GRF_SOC_CON22 0x6258
170-
#define RK3399_DSI0_TURNREQUEST (0xf << 12)
171-
#define RK3399_DSI0_TURNDISABLE (0xf << 8)
172-
#define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4)
173-
#define RK3399_DSI0_FORCERXMODE (0xf << 0)
171+
#define RK3399_DSI0_TURNREQUEST (0xfUL << 12)
172+
#define RK3399_DSI0_TURNDISABLE (0xfUL << 8)
173+
#define RK3399_DSI0_FORCETXSTOPMODE (0xfUL << 4)
174+
#define RK3399_DSI0_FORCERXMODE (0xfUL << 0)
174175

175176
#define RK3399_GRF_SOC_CON23 0x625c
176-
#define RK3399_DSI1_TURNDISABLE (0xf << 12)
177-
#define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8)
178-
#define RK3399_DSI1_FORCERXMODE (0xf << 4)
179-
#define RK3399_DSI1_ENABLE (0xf << 0)
177+
#define RK3399_DSI1_TURNDISABLE (0xfUL << 12)
178+
#define RK3399_DSI1_FORCETXSTOPMODE (0xfUL << 8)
179+
#define RK3399_DSI1_FORCERXMODE (0xfUL << 4)
180+
#define RK3399_DSI1_ENABLE (0xfUL << 0)
180181

181182
#define RK3399_GRF_SOC_CON24 0x6260
182183
#define RK3399_TXRX_MASTERSLAVEZ BIT(7)
@@ -186,8 +187,8 @@
186187
#define RK3399_TXRX_TURNREQUEST GENMASK(3, 0)
187188

188189
#define RK3568_GRF_VO_CON2 0x0368
189-
#define RK3568_DSI0_SKEWCALHS (0x1f << 11)
190-
#define RK3568_DSI0_FORCETXSTOPMODE (0xf << 4)
190+
#define RK3568_DSI0_SKEWCALHS (0x1fUL << 11)
191+
#define RK3568_DSI0_FORCETXSTOPMODE (0xfUL << 4)
191192
#define RK3568_DSI0_TURNDISABLE BIT(2)
192193
#define RK3568_DSI0_FORCERXMODE BIT(0)
193194

@@ -197,18 +198,16 @@
197198
* come from. Name GRF_VO_CON3 is assumed.
198199
*/
199200
#define RK3568_GRF_VO_CON3 0x36c
200-
#define RK3568_DSI1_SKEWCALHS (0x1f << 11)
201-
#define RK3568_DSI1_FORCETXSTOPMODE (0xf << 4)
201+
#define RK3568_DSI1_SKEWCALHS (0x1fUL << 11)
202+
#define RK3568_DSI1_FORCETXSTOPMODE (0xfUL << 4)
202203
#define RK3568_DSI1_TURNDISABLE BIT(2)
203204
#define RK3568_DSI1_FORCERXMODE BIT(0)
204205

205206
#define RV1126_GRF_DSIPHY_CON 0x10220
206-
#define RV1126_DSI_FORCETXSTOPMODE (0xf << 4)
207+
#define RV1126_DSI_FORCETXSTOPMODE (0xfUL << 4)
207208
#define RV1126_DSI_TURNDISABLE BIT(2)
208209
#define RV1126_DSI_FORCERXMODE BIT(0)
209210

210-
#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
211-
212211
enum {
213212
DW_DSI_USAGE_IDLE,
214213
DW_DSI_USAGE_DSI,
@@ -1484,14 +1483,13 @@ static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {
14841483
{
14851484
.reg = 0xff450000,
14861485
.lcdsel_grf_reg = PX30_GRF_PD_VO_CON1,
1487-
.lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
1488-
.lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
1489-
PX30_DSI_LCDC_SEL),
1486+
.lcdsel_big = FIELD_PREP_WM16_CONST(PX30_DSI_LCDC_SEL, 0),
1487+
.lcdsel_lit = FIELD_PREP_WM16_CONST(PX30_DSI_LCDC_SEL, 1),
14901488

14911489
.lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1,
1492-
.lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
1493-
PX30_DSI_FORCERXMODE |
1494-
PX30_DSI_FORCETXSTOPMODE),
1490+
.lanecfg1 = FIELD_PREP_WM16_CONST((PX30_DSI_TURNDISABLE |
1491+
PX30_DSI_FORCERXMODE |
1492+
PX30_DSI_FORCETXSTOPMODE), 0),
14951493

14961494
.max_data_lanes = 4,
14971495
},
@@ -1502,9 +1500,9 @@ static const struct rockchip_dw_dsi_chip_data rk3128_chip_data[] = {
15021500
{
15031501
.reg = 0x10110000,
15041502
.lanecfg1_grf_reg = RK3128_GRF_LVDS_CON0,
1505-
.lanecfg1 = HIWORD_UPDATE(0, RK3128_DSI_TURNDISABLE |
1506-
RK3128_DSI_FORCERXMODE |
1507-
RK3128_DSI_FORCETXSTOPMODE),
1503+
.lanecfg1 = FIELD_PREP_WM16_CONST((RK3128_DSI_TURNDISABLE |
1504+
RK3128_DSI_FORCERXMODE |
1505+
RK3128_DSI_FORCETXSTOPMODE), 0),
15081506
.max_data_lanes = 4,
15091507
},
15101508
{ /* sentinel */ }
@@ -1514,16 +1512,16 @@ static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
15141512
{
15151513
.reg = 0xff960000,
15161514
.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1517-
.lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
1518-
.lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
1515+
.lcdsel_big = FIELD_PREP_WM16_CONST(RK3288_DSI0_LCDC_SEL, 0),
1516+
.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_DSI0_LCDC_SEL, 1),
15191517

15201518
.max_data_lanes = 4,
15211519
},
15221520
{
15231521
.reg = 0xff964000,
15241522
.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1525-
.lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1526-
.lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
1523+
.lcdsel_big = FIELD_PREP_WM16_CONST(RK3288_DSI1_LCDC_SEL, 0),
1524+
.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_DSI1_LCDC_SEL, 1),
15271525

15281526
.max_data_lanes = 4,
15291527
},
@@ -1539,13 +1537,13 @@ static int rk3399_dphy_tx1rx1_init(struct phy *phy)
15391537
* Assume ISP0 is supplied by the RX0 dphy.
15401538
*/
15411539
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1542-
HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0));
1540+
FIELD_PREP_WM16(RK3399_TXRX_SRC_SEL_ISP0, 0));
15431541
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1544-
HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));
1542+
FIELD_PREP_WM16(RK3399_TXRX_MASTERSLAVEZ, 0));
15451543
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1546-
HIWORD_UPDATE(0, RK3399_TXRX_BASEDIR));
1544+
FIELD_PREP_WM16(RK3399_TXRX_BASEDIR, 0));
15471545
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1548-
HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));
1546+
FIELD_PREP_WM16(RK3399_DSI1_ENABLE, 0));
15491547

15501548
return 0;
15511549
}
@@ -1559,30 +1557,29 @@ static int rk3399_dphy_tx1rx1_power_on(struct phy *phy)
15591557
usleep_range(100, 150);
15601558

15611559
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1562-
HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));
1560+
FIELD_PREP_WM16(RK3399_TXRX_MASTERSLAVEZ, 0));
15631561
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1564-
HIWORD_UPDATE(RK3399_TXRX_BASEDIR, RK3399_TXRX_BASEDIR));
1562+
FIELD_PREP_WM16(RK3399_TXRX_BASEDIR, 1));
15651563

15661564
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1567-
HIWORD_UPDATE(0, RK3399_DSI1_FORCERXMODE));
1565+
FIELD_PREP_WM16(RK3399_DSI1_FORCERXMODE, 0));
15681566
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1569-
HIWORD_UPDATE(0, RK3399_DSI1_FORCETXSTOPMODE));
1567+
FIELD_PREP_WM16(RK3399_DSI1_FORCETXSTOPMODE, 0));
15701568

15711569
/* Disable lane turn around, which is ignored in receive mode */
15721570
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1573-
HIWORD_UPDATE(0, RK3399_TXRX_TURNREQUEST));
1571+
FIELD_PREP_WM16(RK3399_TXRX_TURNREQUEST, 0));
15741572
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1575-
HIWORD_UPDATE(RK3399_DSI1_TURNDISABLE,
1576-
RK3399_DSI1_TURNDISABLE));
1573+
FIELD_PREP_WM16(RK3399_DSI1_TURNDISABLE, 0xf));
15771574
usleep_range(100, 150);
15781575

15791576
dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
15801577
usleep_range(100, 150);
15811578

15821579
/* Enable dphy lanes */
15831580
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1584-
HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0),
1585-
RK3399_DSI1_ENABLE));
1581+
FIELD_PREP_WM16(RK3399_DSI1_ENABLE,
1582+
GENMASK(dsi->dphy_config.lanes - 1, 0)));
15861583

15871584
usleep_range(100, 150);
15881585

@@ -1594,7 +1591,7 @@ static int rk3399_dphy_tx1rx1_power_off(struct phy *phy)
15941591
struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
15951592

15961593
regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1597-
HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));
1594+
FIELD_PREP_WM16(RK3399_DSI1_ENABLE, 0));
15981595

15991596
return 0;
16001597
}
@@ -1603,41 +1600,38 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
16031600
{
16041601
.reg = 0xff960000,
16051602
.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1606-
.lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
1607-
.lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
1608-
RK3399_DSI0_LCDC_SEL),
1603+
.lcdsel_big = FIELD_PREP_WM16_CONST(RK3399_DSI0_LCDC_SEL, 0),
1604+
.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3399_DSI0_LCDC_SEL, 1),
16091605

16101606
.lanecfg1_grf_reg = RK3399_GRF_SOC_CON22,
1611-
.lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
1612-
RK3399_DSI0_TURNDISABLE |
1613-
RK3399_DSI0_FORCETXSTOPMODE |
1614-
RK3399_DSI0_FORCERXMODE),
1607+
.lanecfg1 = FIELD_PREP_WM16_CONST((RK3399_DSI0_TURNREQUEST |
1608+
RK3399_DSI0_TURNDISABLE |
1609+
RK3399_DSI0_FORCETXSTOPMODE |
1610+
RK3399_DSI0_FORCERXMODE), 0),
16151611

16161612
.flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
16171613
.max_data_lanes = 4,
16181614
},
16191615
{
16201616
.reg = 0xff968000,
16211617
.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1622-
.lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
1623-
.lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
1624-
RK3399_DSI1_LCDC_SEL),
1618+
.lcdsel_big = FIELD_PREP_WM16_CONST(RK3399_DSI1_LCDC_SEL, 0),
1619+
.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3399_DSI1_LCDC_SEL, 1),
1620+
16251621

16261622
.lanecfg1_grf_reg = RK3399_GRF_SOC_CON23,
1627-
.lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
1628-
RK3399_DSI1_FORCETXSTOPMODE |
1629-
RK3399_DSI1_FORCERXMODE |
1630-
RK3399_DSI1_ENABLE),
1623+
.lanecfg1 = FIELD_PREP_WM16_CONST((RK3399_DSI1_TURNDISABLE |
1624+
RK3399_DSI1_FORCETXSTOPMODE |
1625+
RK3399_DSI1_FORCERXMODE |
1626+
RK3399_DSI1_ENABLE), 0),
16311627

16321628
.lanecfg2_grf_reg = RK3399_GRF_SOC_CON24,
1633-
.lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ |
1634-
RK3399_TXRX_ENABLECLK,
1635-
RK3399_TXRX_MASTERSLAVEZ |
1636-
RK3399_TXRX_ENABLECLK |
1637-
RK3399_TXRX_BASEDIR),
1629+
.lanecfg2 = (FIELD_PREP_WM16_CONST(RK3399_TXRX_MASTERSLAVEZ, 1) |
1630+
FIELD_PREP_WM16_CONST(RK3399_TXRX_ENABLECLK, 1) |
1631+
FIELD_PREP_WM16_CONST(RK3399_TXRX_BASEDIR, 0)),
16381632

16391633
.enable_grf_reg = RK3399_GRF_SOC_CON23,
1640-
.enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
1634+
.enable = FIELD_PREP_WM16_CONST(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
16411635

16421636
.flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
16431637
.max_data_lanes = 4,
@@ -1653,19 +1647,19 @@ static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = {
16531647
{
16541648
.reg = 0xfe060000,
16551649
.lanecfg1_grf_reg = RK3568_GRF_VO_CON2,
1656-
.lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI0_SKEWCALHS |
1657-
RK3568_DSI0_FORCETXSTOPMODE |
1658-
RK3568_DSI0_TURNDISABLE |
1659-
RK3568_DSI0_FORCERXMODE),
1650+
.lanecfg1 = (FIELD_PREP_WM16_CONST(RK3568_DSI0_SKEWCALHS, 0) |
1651+
FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCETXSTOPMODE, 0) |
1652+
FIELD_PREP_WM16_CONST(RK3568_DSI0_TURNDISABLE, 0) |
1653+
FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCERXMODE, 0)),
16601654
.max_data_lanes = 4,
16611655
},
16621656
{
16631657
.reg = 0xfe070000,
16641658
.lanecfg1_grf_reg = RK3568_GRF_VO_CON3,
1665-
.lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI1_SKEWCALHS |
1666-
RK3568_DSI1_FORCETXSTOPMODE |
1667-
RK3568_DSI1_TURNDISABLE |
1668-
RK3568_DSI1_FORCERXMODE),
1659+
.lanecfg1 = (FIELD_PREP_WM16_CONST(RK3568_DSI1_SKEWCALHS, 0) |
1660+
FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCETXSTOPMODE, 0) |
1661+
FIELD_PREP_WM16_CONST(RK3568_DSI1_TURNDISABLE, 0) |
1662+
FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCERXMODE, 0)),
16691663
.max_data_lanes = 4,
16701664
},
16711665
{ /* sentinel */ }
@@ -1675,9 +1669,9 @@ static const struct rockchip_dw_dsi_chip_data rv1126_chip_data[] = {
16751669
{
16761670
.reg = 0xffb30000,
16771671
.lanecfg1_grf_reg = RV1126_GRF_DSIPHY_CON,
1678-
.lanecfg1 = HIWORD_UPDATE(0, RV1126_DSI_TURNDISABLE |
1679-
RV1126_DSI_FORCERXMODE |
1680-
RV1126_DSI_FORCETXSTOPMODE),
1672+
.lanecfg1 = (FIELD_PREP_WM16_CONST(RV1126_DSI_TURNDISABLE, 0) |
1673+
FIELD_PREP_WM16_CONST(RV1126_DSI_FORCERXMODE, 0) |
1674+
FIELD_PREP_WM16_CONST(RV1126_DSI_FORCETXSTOPMODE, 0)),
16811675
.max_data_lanes = 4,
16821676
},
16831677
{ /* sentinel */ }

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