tools headers arm64: Sync arm64's cputype.h with the kernel sources

JIRA: https://issues.redhat.com/browse/RHEL-108306

commit 93e4b86
Author: Arnaldo Carvalho de Melo <acme@redhat.com>
Date:   Mon Oct 28 11:13:57 2024 -0300

    tools headers arm64: Sync arm64's cputype.h with the kernel sources

    To get the changes in:

      9247257 ("arm64: cputype: Add Neoverse-N3 definitions")

    That makes this perf source code to be rebuilt:

      CC      /tmp/build/perf-tools/util/arm-spe.o

    The changes in the above patch add MIDR_NEOVERSE_N3, that probably need
    changes in arm-spe.c, so probably we need to add it to that array?  Or
    maybe we need to leave this for later when this is all tested on those
    machines?

      static const struct midr_range neoverse_spe[] = {
              MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
              MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
              MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
              {},
      };

    Mark Rutland recommended about arm-spe.c in a previous update to this
    file:

    "I would not touch this for now -- someone would have to go audit the
    TRMs to check that those other cores have the same encoding, and I think
    it'd be better to do that as a follow-up."

    That addresses this perf build warning:

      Warning: Kernel ABI header differences:
        diff -u tools/arch/arm64/include/asm/cputype.h arch/arm64/include/asm/cputype.h

    Cc: Adrian Hunter <adrian.hunter@intel.com>
    Cc: Catalin Marinas <catalin.marinas@arm.com>
    Cc: Ian Rogers <irogers@google.com>
    Cc: Jiri Olsa <jolsa@kernel.org>
    Cc: Kan Liang <kan.liang@linux.intel.com>
    Cc: Mark Rutland <mark.rutland@arm.com>
    Cc: Namhyung Kim <namhyung@kernel.org>
    Link: https://lore.kernel.org/lkml/Zx-dffKdGsgkhG96@x1
    Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

Signed-off-by: Jeremy Linton <jlinton@redhat.com>

Author: jlinton

tools/arch/arm64/include/asm/cputype.h

@@ -94,6 +94,7 @@
 #define ARM_CPU_PART_NEOVERSE_V3	0xD84
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
+#define ARM_CPU_PART_NEOVERSE_N3	0xD8E
 
 #define APM_CPU_PART_XGENE		0x000
 #define APM_CPU_VAR_POTENZA		0x00
@@ -176,6 +177,7 @@
 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
+#define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)