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ice: remove ice_tspll_params_e825 definitions
JIRA: https://issues.redhat.com/browse/RHEL-104246 Upstream commit(s): commit b14b2d0 Author: Karol Kolacinski <karol.kolacinski@intel.com> Date: Thu May 1 15:54:15 2025 -0700 ice: remove ice_tspll_params_e825 definitions Remove ice_tspll_params_e825 definitions as according to EDS (Electrical Design Specification) doc, E825 devices support only 156.25 MHz TSPLL frequency for both TCXO and TIME_REF clock source. Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel) Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> Signed-off-by: Petr Oros <poros@redhat.com>
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‎drivers/net/ethernet/intel/ice/ice_tspll.c‎

Lines changed: 8 additions & 99 deletions
Original file line numberDiff line numberDiff line change
@@ -80,93 +80,6 @@ ice_tspll_params_e82x e82x_tspll_params[NUM_ICE_TSPLL_FREQ] = {
8080
},
8181
};
8282

83-
static const struct
84-
ice_tspll_params_e825c e825c_tspll_params[NUM_ICE_TSPLL_FREQ] = {
85-
/* ICE_TSPLL_FREQ_25_000 -> 25 MHz */
86-
{
87-
/* ck_refclkfreq */
88-
0x19,
89-
/* ndivratio */
90-
1,
91-
/* fbdiv_intgr */
92-
320,
93-
/* fbdiv_frac */
94-
0,
95-
/* ref1588_ck_div */
96-
0,
97-
},
98-
99-
/* ICE_TSPLL_FREQ_122_880 -> 122.88 MHz */
100-
{
101-
/* ck_refclkfreq */
102-
0x29,
103-
/* ndivratio */
104-
3,
105-
/* fbdiv_intgr */
106-
195,
107-
/* fbdiv_frac */
108-
1342177280UL,
109-
/* ref1588_ck_div */
110-
0,
111-
},
112-
113-
/* ICE_TSPLL_FREQ_125_000 -> 125 MHz */
114-
{
115-
/* ck_refclkfreq */
116-
0x3E,
117-
/* ndivratio */
118-
2,
119-
/* fbdiv_intgr */
120-
128,
121-
/* fbdiv_frac */
122-
0,
123-
/* ref1588_ck_div */
124-
0,
125-
},
126-
127-
/* ICE_TSPLL_FREQ_153_600 -> 153.6 MHz */
128-
{
129-
/* ck_refclkfreq */
130-
0x33,
131-
/* ndivratio */
132-
3,
133-
/* fbdiv_intgr */
134-
156,
135-
/* fbdiv_frac */
136-
1073741824UL,
137-
/* ref1588_ck_div */
138-
0,
139-
},
140-
141-
/* ICE_TSPLL_FREQ_156_250 -> 156.25 MHz */
142-
{
143-
/* ck_refclkfreq */
144-
0x1F,
145-
/* ndivratio */
146-
5,
147-
/* fbdiv_intgr */
148-
256,
149-
/* fbdiv_frac */
150-
0,
151-
/* ref1588_ck_div */
152-
0,
153-
},
154-
155-
/* ICE_TSPLL_FREQ_245_760 -> 245.76 MHz */
156-
{
157-
/* ck_refclkfreq */
158-
0x52,
159-
/* ndivratio */
160-
3,
161-
/* fbdiv_intgr */
162-
97,
163-
/* fbdiv_frac */
164-
2818572288UL,
165-
/* ref1588_ck_div */
166-
0,
167-
},
168-
};
169-
17083
/**
17184
* ice_tspll_clk_freq_str - Convert time_ref_freq to string
17285
* @clk_freq: Clock frequency
@@ -402,7 +315,6 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
402315
union ice_cgu_r16 dw16;
403316
union ice_cgu_r23 dw23;
404317
union ice_cgu_r22 dw22;
405-
union ice_cgu_r24 dw24;
406318
union ice_cgu_r9 dw9;
407319
int err;
408320

@@ -418,9 +330,8 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
418330
return -EINVAL;
419331
}
420332

421-
if (clk_src == ICE_CLK_SRC_TCXO && clk_freq != ICE_TSPLL_FREQ_156_250) {
422-
dev_warn(ice_hw_to_dev(hw),
423-
"TCXO only supports 156.25 MHz frequency\n");
333+
if (clk_freq != ICE_TSPLL_FREQ_156_250) {
334+
dev_warn(ice_hw_to_dev(hw), "Adapter only supports 156.25 MHz frequency\n");
424335
return -EINVAL;
425336
}
426337

@@ -472,7 +383,7 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
472383
return err;
473384

474385
/* Choose the referenced frequency */
475-
dw16.ck_refclkfreq = e825c_tspll_params[clk_freq].ck_refclkfreq;
386+
dw16.ck_refclkfreq = ICE_TSPLL_CK_REFCLKFREQ_E825;
476387
err = ice_write_cgu_reg(hw, ICE_CGU_R16, dw16.val);
477388
if (err)
478389
return err;
@@ -482,8 +393,8 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
482393
if (err)
483394
return err;
484395

485-
dw19.tspll_fbdiv_intgr = e825c_tspll_params[clk_freq].fbdiv_intgr;
486-
dw19.tspll_ndivratio = e825c_tspll_params[clk_freq].ndivratio;
396+
dw19.tspll_fbdiv_intgr = ICE_TSPLL_FBDIV_INTGR_E825;
397+
dw19.tspll_ndivratio = ICE_TSPLL_NDIVRATIO_E825;
487398

488399
err = ice_write_cgu_reg(hw, ICE_CGU_R19, dw19.val);
489400
if (err)
@@ -507,17 +418,15 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
507418
if (err)
508419
return err;
509420

510-
dw23.ref1588_ck_div = e825c_tspll_params[clk_freq].ref1588_ck_div;
421+
dw23.ref1588_ck_div = 0;
511422
dw23.time_ref_sel = clk_src;
512423

513424
err = ice_write_cgu_reg(hw, ICE_CGU_R23, dw23.val);
514425
if (err)
515426
return err;
516427

517-
dw24.val = 0;
518-
dw24.fbdiv_frac = e825c_tspll_params[clk_freq].fbdiv_frac;
519-
520-
err = ice_write_cgu_reg(hw, ICE_CGU_R24, dw24.val);
428+
/* Clear the R24 register. */
429+
err = ice_write_cgu_reg(hw, ICE_CGU_R24, 0);
521430
if (err)
522431
return err;
523432

‎drivers/net/ethernet/intel/ice/ice_tspll.h‎

Lines changed: 3 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -21,24 +21,9 @@ struct ice_tspll_params_e82x {
2121
u32 post_pll_div;
2222
};
2323

24-
/**
25-
* struct ice_tspll_params_e825c - E825-C TSPLL parameters
26-
* @ck_refclkfreq: ck_refclkfreq selection
27-
* @ndivratio: ndiv ratio that goes directly to the PLL
28-
* @fbdiv_intgr: TSPLL integer feedback divisor
29-
* @fbdiv_frac: TSPLL fractional feedback divisor
30-
* @ref1588_ck_div: clock divisor for tspll ref
31-
*
32-
* Clock Generation Unit parameters used to program the PLL based on the
33-
* selected TIME_REF/TCXO frequency.
34-
*/
35-
struct ice_tspll_params_e825c {
36-
u32 ck_refclkfreq;
37-
u32 ndivratio;
38-
u32 fbdiv_intgr;
39-
u32 fbdiv_frac;
40-
u32 ref1588_ck_div;
41-
};
24+
#define ICE_TSPLL_CK_REFCLKFREQ_E825 0x1F
25+
#define ICE_TSPLL_NDIVRATIO_E825 5
26+
#define ICE_TSPLL_FBDIV_INTGR_E825 256
4227

4328
int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable);
4429
int ice_tspll_init(struct ice_hw *hw);

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