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Merge: x86: idle: Fix MONITOR wakeups on Lunar Lake processors
MR: https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-9/-/merge_requests/6130 JIRA: https://issues.redhat.com/browse/RHEL-68394 Signed-off-by: David Arcari <darcari@redhat.com> Approved-by: Steve Best <sbest@redhat.com> Approved-by: Prarit Bhargava <prarit@redhat.com> Approved-by: Tony Camuso <tcamuso@redhat.com> Approved-by: CKI KWF Bot <cki-ci-bot+kwf-gitlab-com@redhat.com> Merged-by: Rado Vrbovsky <rvrbovsk@redhat.com>
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‎arch/x86/kernel/cpu/intel.c‎

Lines changed: 57 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -72,19 +72,19 @@ static bool cpu_model_supports_sld __ro_after_init;
7272
*/
7373
static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c)
7474
{
75-
switch (c->x86_model) {
76-
case INTEL_FAM6_CORE_YONAH:
77-
case INTEL_FAM6_CORE2_MEROM:
78-
case INTEL_FAM6_CORE2_MEROM_L:
79-
case INTEL_FAM6_CORE2_PENRYN:
80-
case INTEL_FAM6_CORE2_DUNNINGTON:
81-
case INTEL_FAM6_NEHALEM:
82-
case INTEL_FAM6_NEHALEM_G:
83-
case INTEL_FAM6_NEHALEM_EP:
84-
case INTEL_FAM6_NEHALEM_EX:
85-
case INTEL_FAM6_WESTMERE:
86-
case INTEL_FAM6_WESTMERE_EP:
87-
case INTEL_FAM6_SANDYBRIDGE:
75+
switch (c->x86_vfm) {
76+
case INTEL_CORE_YONAH:
77+
case INTEL_CORE2_MEROM:
78+
case INTEL_CORE2_MEROM_L:
79+
case INTEL_CORE2_PENRYN:
80+
case INTEL_CORE2_DUNNINGTON:
81+
case INTEL_NEHALEM:
82+
case INTEL_NEHALEM_G:
83+
case INTEL_NEHALEM_EP:
84+
case INTEL_NEHALEM_EX:
85+
case INTEL_WESTMERE:
86+
case INTEL_WESTMERE_EP:
87+
case INTEL_SANDYBRIDGE:
8888
setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP);
8989
}
9090
}
@@ -106,9 +106,9 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
106106
*/
107107
if (c->x86 != 6)
108108
return;
109-
switch (c->x86_model) {
110-
case INTEL_FAM6_XEON_PHI_KNL:
111-
case INTEL_FAM6_XEON_PHI_KNM:
109+
switch (c->x86_vfm) {
110+
case INTEL_XEON_PHI_KNL:
111+
case INTEL_XEON_PHI_KNM:
112112
break;
113113
default:
114114
return;
@@ -134,32 +134,32 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
134134
* - Release note from 20180108 microcode release
135135
*/
136136
struct sku_microcode {
137-
u8 model;
137+
u32 vfm;
138138
u8 stepping;
139139
u32 microcode;
140140
};
141141
static const struct sku_microcode spectre_bad_microcodes[] = {
142-
{ INTEL_FAM6_KABYLAKE, 0x0B, 0x80 },
143-
{ INTEL_FAM6_KABYLAKE, 0x0A, 0x80 },
144-
{ INTEL_FAM6_KABYLAKE, 0x09, 0x80 },
145-
{ INTEL_FAM6_KABYLAKE_L, 0x0A, 0x80 },
146-
{ INTEL_FAM6_KABYLAKE_L, 0x09, 0x80 },
147-
{ INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
148-
{ INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
149-
{ INTEL_FAM6_BROADWELL, 0x04, 0x28 },
150-
{ INTEL_FAM6_BROADWELL_G, 0x01, 0x1b },
151-
{ INTEL_FAM6_BROADWELL_D, 0x02, 0x14 },
152-
{ INTEL_FAM6_BROADWELL_D, 0x03, 0x07000011 },
153-
{ INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 },
154-
{ INTEL_FAM6_HASWELL_L, 0x01, 0x21 },
155-
{ INTEL_FAM6_HASWELL_G, 0x01, 0x18 },
156-
{ INTEL_FAM6_HASWELL, 0x03, 0x23 },
157-
{ INTEL_FAM6_HASWELL_X, 0x02, 0x3b },
158-
{ INTEL_FAM6_HASWELL_X, 0x04, 0x10 },
159-
{ INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a },
142+
{ INTEL_KABYLAKE, 0x0B, 0x80 },
143+
{ INTEL_KABYLAKE, 0x0A, 0x80 },
144+
{ INTEL_KABYLAKE, 0x09, 0x80 },
145+
{ INTEL_KABYLAKE_L, 0x0A, 0x80 },
146+
{ INTEL_KABYLAKE_L, 0x09, 0x80 },
147+
{ INTEL_SKYLAKE_X, 0x03, 0x0100013e },
148+
{ INTEL_SKYLAKE_X, 0x04, 0x0200003c },
149+
{ INTEL_BROADWELL, 0x04, 0x28 },
150+
{ INTEL_BROADWELL_G, 0x01, 0x1b },
151+
{ INTEL_BROADWELL_D, 0x02, 0x14 },
152+
{ INTEL_BROADWELL_D, 0x03, 0x07000011 },
153+
{ INTEL_BROADWELL_X, 0x01, 0x0b000025 },
154+
{ INTEL_HASWELL_L, 0x01, 0x21 },
155+
{ INTEL_HASWELL_G, 0x01, 0x18 },
156+
{ INTEL_HASWELL, 0x03, 0x23 },
157+
{ INTEL_HASWELL_X, 0x02, 0x3b },
158+
{ INTEL_HASWELL_X, 0x04, 0x10 },
159+
{ INTEL_IVYBRIDGE_X, 0x04, 0x42a },
160160
/* Observed in the wild */
161-
{ INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b },
162-
{ INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 },
161+
{ INTEL_SANDYBRIDGE_X, 0x06, 0x61b },
162+
{ INTEL_SANDYBRIDGE_X, 0x07, 0x712 },
163163
};
164164

165165
static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
@@ -173,11 +173,8 @@ static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
173173
if (cpu_has(c, X86_FEATURE_HYPERVISOR))
174174
return false;
175175

176-
if (c->x86 != 6)
177-
return false;
178-
179176
for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
180-
if (c->x86_model == spectre_bad_microcodes[i].model &&
177+
if (c->x86_vfm == spectre_bad_microcodes[i].vfm &&
181178
c->x86_stepping == spectre_bad_microcodes[i].stepping)
182179
return (c->microcode <= spectre_bad_microcodes[i].microcode);
183180
}
@@ -319,7 +316,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
319316
* need the microcode to have already been loaded... so if it is
320317
* not, recommend a BIOS update and disable large pages.
321318
*/
322-
if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
319+
if (c->x86_vfm == INTEL_ATOM_BONNELL && c->x86_stepping <= 2 &&
323320
c->microcode < 0x20e) {
324321
pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
325322
clear_cpu_cap(c, X86_FEATURE_PSE);
@@ -351,17 +348,13 @@ static void early_init_intel(struct cpuinfo_x86 *c)
351348
}
352349

353350
/* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
354-
if (c->x86 == 6) {
355-
switch (c->x86_model) {
356-
case INTEL_FAM6_ATOM_SALTWELL_MID:
357-
case INTEL_FAM6_ATOM_SALTWELL_TABLET:
358-
case INTEL_FAM6_ATOM_SILVERMONT_MID:
359-
case INTEL_FAM6_ATOM_AIRMONT_NP:
360-
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
361-
break;
362-
default:
363-
break;
364-
}
351+
switch (c->x86_vfm) {
352+
case INTEL_ATOM_SALTWELL_MID:
353+
case INTEL_ATOM_SALTWELL_TABLET:
354+
case INTEL_ATOM_SILVERMONT_MID:
355+
case INTEL_ATOM_AIRMONT_NP:
356+
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
357+
break;
365358
}
366359

367360
/*
@@ -400,7 +393,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
400393
* should be false so that __flush_tlb_all() causes CR3 instead of CR4.PGE
401394
* to be modified.
402395
*/
403-
if (c->x86 == 5 && c->x86_model == 9) {
396+
if (c->x86_vfm == INTEL_QUARK_X1000) {
404397
pr_info("Disabling PGE capability bit\n");
405398
setup_clear_cpu_cap(X86_FEATURE_PGE);
406399
}
@@ -632,12 +625,15 @@ static void init_intel(struct cpuinfo_x86 *c)
632625
set_cpu_cap(c, X86_FEATURE_PEBS);
633626
}
634627

635-
if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
636-
(c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
628+
if (boot_cpu_has(X86_FEATURE_CLFLUSH) &&
629+
(c->x86_vfm == INTEL_CORE2_DUNNINGTON ||
630+
c->x86_vfm == INTEL_NEHALEM_EX ||
631+
c->x86_vfm == INTEL_WESTMERE_EX))
637632
set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
638633

639-
if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
640-
((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
634+
if (boot_cpu_has(X86_FEATURE_MWAIT) &&
635+
(c->x86_vfm == INTEL_ATOM_GOLDMONT ||
636+
c->x86_vfm == INTEL_LUNARLAKE_M))
641637
set_cpu_bug(c, X86_BUG_MONITOR);
642638

643639
#ifdef CONFIG_X86_64
@@ -1255,9 +1251,9 @@ void handle_bus_lock(struct pt_regs *regs)
12551251
* feature even though they do not enumerate IA32_CORE_CAPABILITIES.
12561252
*/
12571253
static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {
1258-
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, 0),
1259-
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, 0),
1260-
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, 0),
1254+
X86_MATCH_VFM(INTEL_ICELAKE_X, 0),
1255+
X86_MATCH_VFM(INTEL_ICELAKE_L, 0),
1256+
X86_MATCH_VFM(INTEL_ICELAKE_D, 0),
12611257
{}
12621258
};
12631259

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