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Merge: Update kernel's PCI subsystem to v6.11
MR: https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-9/-/merge_requests/5357 ``` This series updates RHEL9's PCI subsystem with content from upstream v6.11 - Merge tag 'pci-v6.11-fixes-4' of git://git.kernel.org/pub/scm/../pci/pci https://lkml.org/lkml/2024/9/13/ commit b771845 Merge: e936e7d fc8c818 Merge tag 'pci-v6.11-fixes-3' of git://git.kernel.org/pub/scm/../pci/pci https://lkml.org/lkml/2024/9/6/1405 commit 487ee43 Merge: a86b83f 8f62819 4 files changed, 44 insertions(+), 5 deletions(-) Merge tag 'pci-v6.11-fixes-2' of git://git.kernel.org/pub/scm/../pci/pci https://lkml.org/lkml/2024/8/30/1561 commit 8101b27 Merge: 216d163 150b572 3 files changed, 21 insertions(+), 2 deletions(-) Merge tag 'pci-v6.11-fixes-1' of git://git.kernel.org/pub/scm/../pci/pci https://lkml.org/lkml/2024/8/1/1278 commit c0ecd63 Merge: 183d46f 5560a61 2 files changed, 11 insertions(+), 8 deletions(-) Merge tag 'pci-v6.11-changes' of git://git.kernel.org/pub/scm/../pci/pci https://lkml.org/lkml/2024/7/19/844 commit 3f386cb Merge: 8e5c0ab 4565927 105 files changed, 5208 insertions(+), 1932 deletions(-) All but three of patches within the series back-ported cleanly. However, there were a few back-ports where some changes were made to the originating upstream patch due to it either not being quite up to date with more recent changes, or subsequent changes were made during its merge commit. All such occurances are noted in the back-port's commit message with the same changes that occurred upstream being made in the back-port to keep things in sync. v2: Removing back-ports of merge commit df5dd33 "Merge branch 'pci/controller/qcom'" due to prerequisite content that conflicts with other MRs. Will create a separate MR for df5dd33 once the dependent MRs have merged. JIRA: https://issues.redhat.com/browse/RHEL-59033 Signed-off-by: Myron Stowe <mstowe@redhat.com> ``` Approved-by: Andrew Halaney <ahalaney@redhat.com> Approved-by: Jarod Wilson <jarod@redhat.com> Approved-by: Mika Penttilä <mpenttil@redhat.com> Approved-by: John W. Linville <linville@redhat.com> Approved-by: Ivan Vecera <ivecera@redhat.com> Approved-by: CKI KWF Bot <cki-ci-bot+kwf-gitlab-com@redhat.com> Merged-by: Rado Vrbovsky <rvrbovsk@redhat.com>
2 parents 010763e + bd9a250 commit 67448d1

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‎Documentation/PCI/endpoint/pci-endpoint.rst‎

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@@ -172,8 +172,8 @@ by the PCI endpoint function driver.
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* bind: ops to perform when a EPC device has been bound to EPF device
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* unbind: ops to perform when a binding has been lost between a EPC
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device and EPF device
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* linkup: ops to perform when the EPC device has established a
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connection with a host system
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* add_cfs: optional ops to create function specific configfs
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attributes
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The PCI Function driver can then register the PCI EPF driver by using
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pci_epf_register_driver().

‎Documentation/PCI/pciebus-howto.rst‎

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@@ -139,7 +139,7 @@ driver data structure.
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static struct pcie_port_service_driver root_aerdrv = {
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.name = (char *)device_name,
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.id_table = &service_id[0],
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.id_table = service_id,
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.probe = aerdrv_load,
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.remove = aerdrv_unload,

‎Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml‎

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@@ -13,6 +13,35 @@ description: |+
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MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
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with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
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MT7621 PCIe HOST Topology
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.-------.
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| |
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| CPU |
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| |
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'-------'
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|
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|
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|
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v
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.------------------.
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.-----------| HOST/PCI Bridge |------------.
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| '------------------' | Type1
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BUS0 | | | Access
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v v v On Bus0
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.-------------. .-------------. .-------------.
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| VIRTUAL P2P | | VIRTUAL P2P | | VIRTUAL P2P |
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| BUS0 | | BUS0 | | BUS0 |
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| DEV0 | | DEV1 | | DEV2 |
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'-------------' '-------------' '-------------'
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Type0 | Type0 | Type0 |
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Access BUS1 | Access BUS2| Access BUS3|
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On Bus1 v On Bus2 v On Bus3 v
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.----------. .----------. .----------.
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| Device 0 | | Device 0 | | Device 0 |
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| Func 0 | | Func 0 | | Func 0 |
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'----------' '----------' '----------'
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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‎Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml‎

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@@ -69,6 +69,10 @@ properties:
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- const: msi6
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- const: msi7
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operating-points-v2: true
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opp-table:
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type: object
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resets:
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maxItems: 1
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‎Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml‎

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@@ -19,11 +19,10 @@ properties:
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const: qcom,pcie-x1e80100
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reg:
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minItems: 5
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minItems: 6
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maxItems: 6
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reg-names:
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minItems: 5
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items:
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- const: parf # Qualcomm specific registers
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- const: dbi # DesignWare PCIe registers

‎Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: DesignWare based PCIe RC/EP controller on Rockchip SoCs
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maintainers:
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- Shawn Lin <shawn.lin@rock-chips.com>
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- Simon Xue <xxm@rock-chips.com>
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- Heiko Stuebner <heiko@sntech.de>
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description: |+
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Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip
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SoCs.
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properties:
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clocks:
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minItems: 5
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items:
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- description: AHB clock for PCIe master
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- description: AHB clock for PCIe slave
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- description: AHB clock for PCIe dbi
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- description: APB clock for PCIe
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- description: Auxiliary clock for PCIe
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- description: PIPE clock
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- description: Reference clock for PCIe
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clock-names:
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minItems: 5
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items:
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- const: aclk_mst
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- const: aclk_slv
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- const: aclk_dbi
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- const: pclk
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- const: aux
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- const: pipe
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- const: ref
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interrupts:
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minItems: 5
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items:
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- description:
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Combined system interrupt, which is used to signal the following
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interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
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hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi,
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edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app
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- description:
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Combined PM interrupt, which is used to signal the following
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interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
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linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2,
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linkst_out_l0s, pm_dstate_update
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- description:
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Combined message interrupt, which is used to signal the following
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interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
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pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active
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- description:
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Combined legacy interrupt, which is used to signal the following
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interrupts - inta, intb, intc, intd, tx_inta, tx_intb, tx_intc,
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tx_intd
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- description:
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Combined error interrupt, which is used to signal the following
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interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
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tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
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nf_err_rx, f_err_rx, radm_qoverflow
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- description:
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eDMA write channel 0 interrupt
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- description:
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eDMA write channel 1 interrupt
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- description:
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eDMA read channel 0 interrupt
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- description:
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eDMA read channel 1 interrupt
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interrupt-names:
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minItems: 5
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items:
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- const: sys
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- const: pmc
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- const: msg
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- const: legacy
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- const: err
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- const: dma0
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- const: dma1
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- const: dma2
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- const: dma3
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num-lanes: true
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phys:
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maxItems: 1
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phy-names:
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const: pcie-phy
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power-domains:
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maxItems: 1
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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oneOf:
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- const: pipe
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- items:
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- const: pwr
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- const: pipe
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- num-lanes
118+
- phys
119+
- phy-names
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- power-domains
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- resets
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- reset-names
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additionalProperties: true
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...

‎Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: DesignWare based PCIe Endpoint controller on Rockchip SoCs
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9+
maintainers:
10+
- Niklas Cassel <cassel@kernel.org>
11+
12+
description: |+
13+
RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare
14+
PCIe IP and thus inherits all the common properties defined in
15+
snps,dw-pcie-ep.yaml.
16+
17+
allOf:
18+
- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
19+
- $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
20+
21+
properties:
22+
compatible:
23+
enum:
24+
- rockchip,rk3568-pcie-ep
25+
- rockchip,rk3588-pcie-ep
26+
27+
reg:
28+
items:
29+
- description: Data Bus Interface (DBI) registers
30+
- description: Data Bus Interface (DBI) shadow registers
31+
- description: Rockchip designed configuration registers
32+
- description: Memory region used to map remote RC address space
33+
- description: Internal Address Translation Unit (iATU) registers
34+
35+
reg-names:
36+
items:
37+
- const: dbi
38+
- const: dbi2
39+
- const: apb
40+
- const: addr_space
41+
- const: atu
42+
43+
required:
44+
- interrupts
45+
- interrupt-names
46+
47+
unevaluatedProperties: false
48+
49+
examples:
50+
- |
51+
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
52+
#include <dt-bindings/interrupt-controller/arm-gic.h>
53+
#include <dt-bindings/interrupt-controller/irq.h>
54+
#include <dt-bindings/power/rk3588-power.h>
55+
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
56+
57+
soc {
58+
#address-cells = <2>;
59+
#size-cells = <2>;
60+
61+
pcie3x4_ep: pcie-ep@fe150000 {
62+
compatible = "rockchip,rk3588-pcie-ep";
63+
reg = <0xa 0x40000000 0x0 0x00100000>,
64+
<0xa 0x40100000 0x0 0x00100000>,
65+
<0x0 0xfe150000 0x0 0x00010000>,
66+
<0x9 0x00000000 0x0 0x40000000>,
67+
<0xa 0x40300000 0x0 0x00100000>;
68+
reg-names = "dbi", "dbi2", "apb", "addr_space", "atu";
69+
clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
70+
<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
71+
<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
72+
clock-names = "aclk_mst", "aclk_slv",
73+
"aclk_dbi", "pclk",
74+
"aux", "pipe";
75+
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
76+
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
77+
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
78+
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
79+
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>,
80+
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>,
81+
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>,
82+
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>,
83+
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
84+
interrupt-names = "sys", "pmc", "msg", "legacy", "err",
85+
"dma0", "dma1", "dma2", "dma3";
86+
max-link-speed = <3>;
87+
num-lanes = <4>;
88+
phys = <&pcie30phy>;
89+
phy-names = "pcie-phy";
90+
power-domains = <&power RK3588_PD_PCIE>;
91+
resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
92+
reset-names = "pwr", "pipe";
93+
};
94+
};
95+
...

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