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arm64: dts: Add DSPI entries for S32G platforms
JIRA: https://issues.redhat.com/browse/RHEL-116642 commit 06ee2f0 Author: Larisa Grigore <larisa.grigore@nxp.com> Date: Thu May 22 15:51:43 2025 +0100 arm64: dts: Add DSPI entries for S32G platforms S32G3 and S32G2 have the same 6 SPI devices, add the DT entries. Devices are all the same except spi0 has 8 chip selects instead of 5. Clock settings for the chip rely on ATF Firmware [1]. [1]: https://github.com/nxp-auto-linux/arm-trusted-firmware Co-developed-by: Radu Pirea (NXP OSS) <radu-nicolae.pirea@oss.nxp.com> Signed-off-by: Radu Pirea (NXP OSS) <radu-nicolae.pirea@oss.nxp.com> Signed-off-by: Larisa Grigore <Larisa.Grigore@nxp.com> Signed-off-by: James Clark <james.clark@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Jared Kangas <jkangas@redhat.com>
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‎arch/arm64/boot/dts/freescale/s32g2.dtsi‎

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -376,6 +376,45 @@
376376
status = "disabled";
377377
};
378378

379+
spi0: spi@401d4000 {
380+
compatible = "nxp,s32g2-dspi";
381+
reg = <0x401d4000 0x1000>;
382+
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
383+
clocks = <&clks 26>;
384+
clock-names = "dspi";
385+
spi-num-chipselects = <8>;
386+
bus-num = <0>;
387+
dmas = <&edma0 0 7>, <&edma0 0 8>;
388+
dma-names = "tx", "rx";
389+
status = "disabled";
390+
};
391+
392+
spi1: spi@401d8000 {
393+
compatible = "nxp,s32g2-dspi";
394+
reg = <0x401d8000 0x1000>;
395+
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
396+
clocks = <&clks 26>;
397+
clock-names = "dspi";
398+
spi-num-chipselects = <5>;
399+
bus-num = <1>;
400+
dmas = <&edma0 0 10>, <&edma0 0 11>;
401+
dma-names = "tx", "rx";
402+
status = "disabled";
403+
};
404+
405+
spi2: spi@401dc000 {
406+
compatible = "nxp,s32g2-dspi";
407+
reg = <0x401dc000 0x1000>;
408+
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
409+
clocks = <&clks 26>;
410+
clock-names = "dspi";
411+
spi-num-chipselects = <5>;
412+
bus-num = <2>;
413+
dmas = <&edma0 0 13>, <&edma0 0 14>;
414+
dma-names = "tx", "rx";
415+
status = "disabled";
416+
};
417+
379418
i2c0: i2c@401e4000 {
380419
compatible = "nxp,s32g2-i2c";
381420
reg = <0x401e4000 0x1000>;
@@ -460,6 +499,45 @@
460499
status = "disabled";
461500
};
462501

502+
spi3: spi@402c8000 {
503+
compatible = "nxp,s32g2-dspi";
504+
reg = <0x402c8000 0x1000>;
505+
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
506+
clocks = <&clks 26>;
507+
clock-names = "dspi";
508+
spi-num-chipselects = <5>;
509+
bus-num = <3>;
510+
dmas = <&edma0 1 7>, <&edma0 1 8>;
511+
dma-names = "tx", "rx";
512+
status = "disabled";
513+
};
514+
515+
spi4: spi@402cc000 {
516+
compatible = "nxp,s32g2-dspi";
517+
reg = <0x402cc000 0x1000>;
518+
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
519+
clocks = <&clks 26>;
520+
clock-names = "dspi";
521+
spi-num-chipselects = <5>;
522+
bus-num = <4>;
523+
dmas = <&edma0 1 10>, <&edma0 1 11>;
524+
dma-names = "tx", "rx";
525+
status = "disabled";
526+
};
527+
528+
spi5: spi@402d0000 {
529+
compatible = "nxp,s32g2-dspi";
530+
reg = <0x402d0000 0x1000>;
531+
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
532+
clocks = <&clks 26>;
533+
clock-names = "dspi";
534+
spi-num-chipselects = <5>;
535+
bus-num = <5>;
536+
dmas = <&edma0 1 13>, <&edma0 1 14>;
537+
dma-names = "tx", "rx";
538+
status = "disabled";
539+
};
540+
463541
i2c3: i2c@402d8000 {
464542
compatible = "nxp,s32g2-i2c";
465543
reg = <0x402d8000 0x1000>;

‎arch/arm64/boot/dts/freescale/s32g3.dtsi‎

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -435,6 +435,45 @@
435435
status = "disabled";
436436
};
437437

438+
spi0: spi@401d4000 {
439+
compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
440+
reg = <0x401d4000 0x1000>;
441+
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
442+
clocks = <&clks 26>;
443+
clock-names = "dspi";
444+
spi-num-chipselects = <8>;
445+
bus-num = <0>;
446+
dmas = <&edma0 0 7>, <&edma0 0 8>;
447+
dma-names = "tx", "rx";
448+
status = "disabled";
449+
};
450+
451+
spi1: spi@401d8000 {
452+
compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
453+
reg = <0x401d8000 0x1000>;
454+
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
455+
clocks = <&clks 26>;
456+
clock-names = "dspi";
457+
spi-num-chipselects = <5>;
458+
bus-num = <1>;
459+
dmas = <&edma0 0 10>, <&edma0 0 11>;
460+
dma-names = "tx", "rx";
461+
status = "disabled";
462+
};
463+
464+
spi2: spi@401dc000 {
465+
compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
466+
reg = <0x401dc000 0x1000>;
467+
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
468+
clocks = <&clks 26>;
469+
clock-names = "dspi";
470+
spi-num-chipselects = <5>;
471+
bus-num = <2>;
472+
dmas = <&edma0 0 13>, <&edma0 0 14>;
473+
dma-names = "tx", "rx";
474+
status = "disabled";
475+
};
476+
438477
i2c0: i2c@401e4000 {
439478
compatible = "nxp,s32g3-i2c",
440479
"nxp,s32g2-i2c";
@@ -524,6 +563,45 @@
524563
status = "disabled";
525564
};
526565

566+
spi3: spi@402c8000 {
567+
compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
568+
reg = <0x402c8000 0x1000>;
569+
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
570+
clocks = <&clks 26>;
571+
clock-names = "dspi";
572+
spi-num-chipselects = <5>;
573+
bus-num = <3>;
574+
dmas = <&edma0 1 7>, <&edma0 1 8>;
575+
dma-names = "tx", "rx";
576+
status = "disabled";
577+
};
578+
579+
spi4: spi@402cc000 {
580+
compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
581+
reg = <0x402cc000 0x1000>;
582+
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
583+
clocks = <&clks 26>;
584+
clock-names = "dspi";
585+
spi-num-chipselects = <5>;
586+
bus-num = <4>;
587+
dmas = <&edma0 1 10>, <&edma0 1 11>;
588+
dma-names = "tx", "rx";
589+
status = "disabled";
590+
};
591+
592+
spi5: spi@402d0000 {
593+
compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
594+
reg = <0x402d0000 0x1000>;
595+
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
596+
clocks = <&clks 26>;
597+
clock-names = "dspi";
598+
spi-num-chipselects = <5>;
599+
bus-num = <5>;
600+
dmas = <&edma0 1 13>, <&edma0 1 14>;
601+
dma-names = "tx", "rx";
602+
status = "disabled";
603+
};
604+
527605
i2c3: i2c@402d8000 {
528606
compatible = "nxp,s32g3-i2c",
529607
"nxp,s32g2-i2c";

‎arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi‎

Lines changed: 84 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -173,6 +173,78 @@
173173
pinmux = <0x2d40>, <0x2d30>;
174174
};
175175
};
176+
177+
dspi1_pins: dspi1-pins {
178+
dspi1-grp0 {
179+
pinmux = <0x72>;
180+
output-enable;
181+
input-enable;
182+
slew-rate = <150>;
183+
bias-pull-up;
184+
};
185+
186+
dspi1-grp1 {
187+
pinmux = <0x62>;
188+
output-enable;
189+
slew-rate = <150>;
190+
};
191+
192+
dspi1-grp2 {
193+
pinmux = <0x83>;
194+
output-enable;
195+
input-enable;
196+
slew-rate = <150>;
197+
};
198+
199+
dspi1-grp3 {
200+
pinmux = <0x5F0>;
201+
input-enable;
202+
slew-rate = <150>;
203+
bias-pull-up;
204+
};
205+
206+
dspi1-grp4 {
207+
pinmux = <0x3D92>,
208+
<0x3DA2>,
209+
<0x3DB2>;
210+
};
211+
};
212+
213+
dspi5_pins: dspi5-pins {
214+
dspi5-grp0 {
215+
pinmux = <0x93>;
216+
output-enable;
217+
input-enable;
218+
slew-rate = <150>;
219+
};
220+
221+
dspi5-grp1 {
222+
pinmux = <0xA0>;
223+
input-enable;
224+
slew-rate = <150>;
225+
bias-pull-up;
226+
};
227+
228+
dspi5-grp2 {
229+
pinmux = <0x3ED2>,
230+
<0x3EE2>,
231+
<0x3EF2>;
232+
};
233+
234+
dspi5-grp3 {
235+
pinmux = <0xB3>;
236+
output-enable;
237+
slew-rate = <150>;
238+
};
239+
240+
dspi5-grp4 {
241+
pinmux = <0xC3>;
242+
output-enable;
243+
input-enable;
244+
slew-rate = <150>;
245+
bias-pull-up;
246+
};
247+
};
176248
};
177249

178250
&can0 {
@@ -220,3 +292,15 @@
220292
pinctrl-1 = <&i2c4_gpio_pins>;
221293
status = "okay";
222294
};
295+
296+
&spi1 {
297+
pinctrl-0 = <&dspi1_pins>;
298+
pinctrl-names = "default";
299+
status = "okay";
300+
};
301+
302+
&spi5 {
303+
pinctrl-0 = <&dspi5_pins>;
304+
pinctrl-names = "default";
305+
status = "okay";
306+
};

‎arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi‎

Lines changed: 84 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -127,6 +127,78 @@
127127
pinmux = <0x2d40>, <0x2d30>;
128128
};
129129
};
130+
131+
dspi1_pins: dspi1-pins {
132+
dspi1-grp0 {
133+
pinmux = <0x72>;
134+
output-enable;
135+
input-enable;
136+
slew-rate = <150>;
137+
bias-pull-up;
138+
};
139+
140+
dspi1-grp1 {
141+
pinmux = <0x62>;
142+
output-enable;
143+
slew-rate = <150>;
144+
};
145+
146+
dspi1-grp2 {
147+
pinmux = <0x83>;
148+
output-enable;
149+
input-enable;
150+
slew-rate = <150>;
151+
};
152+
153+
dspi1-grp3 {
154+
pinmux = <0x5F0>;
155+
input-enable;
156+
slew-rate = <150>;
157+
bias-pull-up;
158+
};
159+
160+
dspi1-grp4 {
161+
pinmux = <0x3D92>,
162+
<0x3DA2>,
163+
<0x3DB2>;
164+
};
165+
};
166+
167+
dspi5_pins: dspi5-pins {
168+
dspi5-grp0 {
169+
pinmux = <0x93>;
170+
output-enable;
171+
input-enable;
172+
slew-rate = <150>;
173+
};
174+
175+
dspi5-grp1 {
176+
pinmux = <0xA0>;
177+
input-enable;
178+
slew-rate = <150>;
179+
bias-pull-up;
180+
};
181+
182+
dspi5-grp2 {
183+
pinmux = <0x3ED2>,
184+
<0x3EE2>,
185+
<0x3EF2>;
186+
};
187+
188+
dspi5-grp3 {
189+
pinmux = <0xB3>;
190+
output-enable;
191+
slew-rate = <150>;
192+
};
193+
194+
dspi5-grp4 {
195+
pinmux = <0xC3>;
196+
output-enable;
197+
input-enable;
198+
slew-rate = <150>;
199+
bias-pull-up;
200+
};
201+
};
130202
};
131203

132204
&can0 {
@@ -160,6 +232,18 @@
160232
};
161233
};
162234

235+
&spi1 {
236+
pinctrl-0 = <&dspi1_pins>;
237+
pinctrl-names = "default";
238+
status = "okay";
239+
};
240+
241+
&spi5 {
242+
pinctrl-0 = <&dspi5_pins>;
243+
pinctrl-names = "default";
244+
status = "okay";
245+
};
246+
163247
&i2c2 {
164248
pinctrl-names = "default", "gpio";
165249
pinctrl-0 = <&i2c2_pins>;

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