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ice: Add in/out PTP pin delays
JIRA: https://issues.redhat.com/browse/RHEL-89579 Conflicts: - adjusted context conflict due to already applied 53ce716 ("ice: ensure periodic output start time is in the future") Upstream commit(s): commit 9146394 Author: Karol Kolacinski <karol.kolacinski@intel.com> Date: Wed Dec 4 10:46:11 2024 +0100 ice: Add in/out PTP pin delays HW can have different input/output delays for each of the pins. Currently, only E82X adapters have delay compensation based on TSPLL config and E810 adapters have constant 1 ms compensation, both cases only for output delays and the same one for all pins. E825 adapters have different delays for SDP and other pins. Those delays are also based on direction and input delays are different than output ones. This is the main reason for moving delays to pin description structure. Add a field in ice_ptp_pin_desc structure to reflect that. Delay values are based on approximate calculations of HW delays based on HW spec. Implement external timestamp (input) delay compensation. Remove existing definitions and wrappers for periodic output propagation delays. Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> Reviewed-by: Simon Horman <horms@kernel.org> Tested-by: Sunitha Mekala <sunithax.d.mekala@intel.com> (A Contingent worker at Intel) Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> Signed-off-by: Petr Oros <poros@redhat.com>
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‎drivers/net/ethernet/intel/ice/ice_ptp.c‎

Lines changed: 47 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -16,28 +16,28 @@ static const char ice_pin_names[][64] = {
1616
};
1717

1818
static const struct ice_ptp_pin_desc ice_pin_desc_e82x[] = {
19-
/* name, gpio */
20-
{ TIME_SYNC, { 4, -1 }},
21-
{ ONE_PPS, { -1, 5 }},
19+
/* name, gpio, delay */
20+
{ TIME_SYNC, { 4, -1 }, { 0, 0 }},
21+
{ ONE_PPS, { -1, 5 }, { 0, 11 }},
2222
};
2323

2424
static const struct ice_ptp_pin_desc ice_pin_desc_e825c[] = {
25-
/* name, gpio */
26-
{ SDP0, { 0, 0 }},
27-
{ SDP1, { 1, 1 }},
28-
{ SDP2, { 2, 2 }},
29-
{ SDP3, { 3, 3 }},
30-
{ TIME_SYNC, { 4, -1 }},
31-
{ ONE_PPS, { -1, 5 }},
25+
/* name, gpio, delay */
26+
{ SDP0, { 0, 0 }, { 15, 14 }},
27+
{ SDP1, { 1, 1 }, { 15, 14 }},
28+
{ SDP2, { 2, 2 }, { 15, 14 }},
29+
{ SDP3, { 3, 3 }, { 15, 14 }},
30+
{ TIME_SYNC, { 4, -1 }, { 11, 0 }},
31+
{ ONE_PPS, { -1, 5 }, { 0, 9 }},
3232
};
3333

3434
static const struct ice_ptp_pin_desc ice_pin_desc_e810[] = {
35-
/* name, gpio */
36-
{ SDP0, { 0, 0 }},
37-
{ SDP1, { 1, 1 }},
38-
{ SDP2, { 2, 2 }},
39-
{ SDP3, { 3, 3 }},
40-
{ ONE_PPS, { -1, 5 }},
35+
/* name, gpio, delay */
36+
{ SDP0, { 0, 0 }, { 0, 1 }},
37+
{ SDP1, { 1, 1 }, { 0, 1 }},
38+
{ SDP2, { 2, 2 }, { 0, 1 }},
39+
{ SDP3, { 3, 3 }, { 0, 1 }},
40+
{ ONE_PPS, { -1, 5 }, { 0, 1 }},
4141
};
4242

4343
static const char ice_pin_names_nvm[][64] = {
@@ -49,12 +49,12 @@ static const char ice_pin_names_nvm[][64] = {
4949
};
5050

5151
static const struct ice_ptp_pin_desc ice_pin_desc_e810_sma[] = {
52-
/* name, gpio */
53-
{ GNSS, { 1, -1 }},
54-
{ SMA1, { 1, 0 }},
55-
{ UFL1, { -1, 0 }},
56-
{ SMA2, { 3, 2 }},
57-
{ UFL2, { 3, -1 }},
52+
/* name, gpio, delay */
53+
{ GNSS, { 1, -1 }, { 0, 0 }},
54+
{ SMA1, { 1, 0 }, { 0, 1 }},
55+
{ UFL1, { -1, 0 }, { 0, 1 }},
56+
{ SMA2, { 3, 2 }, { 0, 1 }},
57+
{ UFL2, { 3, -1 }, { 0, 0 }},
5858
};
5959

6060
static struct ice_pf *ice_get_ctrl_pf(struct ice_pf *pf)
@@ -1584,18 +1584,29 @@ void ice_ptp_extts_event(struct ice_pf *pf)
15841584
* Event is defined in GLTSYN_EVNT_0 register
15851585
*/
15861586
for (chan = 0; chan < GLTSYN_EVNT_H_IDX_MAX; chan++) {
1587+
int pin_desc_idx;
1588+
15871589
/* Check if channel is enabled */
1588-
if (pf->ptp.ext_ts_irq & (1 << chan)) {
1589-
lo = rd32(hw, GLTSYN_EVNT_L(chan, tmr_idx));
1590-
hi = rd32(hw, GLTSYN_EVNT_H(chan, tmr_idx));
1591-
event.timestamp = (((u64)hi) << 32) | lo;
1592-
event.type = PTP_CLOCK_EXTTS;
1593-
event.index = chan;
1594-
1595-
/* Fire event */
1596-
ptp_clock_event(pf->ptp.clock, &event);
1597-
pf->ptp.ext_ts_irq &= ~(1 << chan);
1590+
if (!(pf->ptp.ext_ts_irq & (1 << chan)))
1591+
continue;
1592+
1593+
lo = rd32(hw, GLTSYN_EVNT_L(chan, tmr_idx));
1594+
hi = rd32(hw, GLTSYN_EVNT_H(chan, tmr_idx));
1595+
event.timestamp = (u64)hi << 32 | lo;
1596+
1597+
/* Add delay compensation */
1598+
pin_desc_idx = ice_ptp_find_pin_idx(pf, PTP_PF_EXTTS, chan);
1599+
if (pin_desc_idx >= 0) {
1600+
const struct ice_ptp_pin_desc *desc;
1601+
1602+
desc = &pf->ptp.ice_pin_desc[pin_desc_idx];
1603+
event.timestamp -= desc->delay[0];
15981604
}
1605+
1606+
event.type = PTP_CLOCK_EXTTS;
1607+
event.index = chan;
1608+
pf->ptp.ext_ts_irq &= ~(1 << chan);
1609+
ptp_clock_event(pf->ptp.clock, &event);
15991610
}
16001611
}
16011612

@@ -1791,9 +1802,9 @@ static int ice_ptp_write_perout(struct ice_hw *hw, unsigned int chan,
17911802
static int ice_ptp_cfg_perout(struct ice_pf *pf, struct ptp_perout_request *rq,
17921803
int on)
17931804
{
1805+
unsigned int gpio_pin, prop_delay_ns;
17941806
u64 clk, period, start, phase;
17951807
struct ice_hw *hw = &pf->hw;
1796-
unsigned int gpio_pin;
17971808
int pin_desc_idx;
17981809

17991810
if (rq->flags & ~PTP_PEROUT_PHASE)
@@ -1804,6 +1815,7 @@ static int ice_ptp_cfg_perout(struct ice_pf *pf, struct ptp_perout_request *rq,
18041815
return -EIO;
18051816

18061817
gpio_pin = pf->ptp.ice_pin_desc[pin_desc_idx].gpio[1];
1818+
prop_delay_ns = pf->ptp.ice_pin_desc[pin_desc_idx].delay[1];
18071819
period = rq->period.sec * NSEC_PER_SEC + rq->period.nsec;
18081820

18091821
/* If we're disabling the output or period is 0, clear out CLKO and TGT
@@ -1836,11 +1848,11 @@ static int ice_ptp_cfg_perout(struct ice_pf *pf, struct ptp_perout_request *rq,
18361848
* from now, so we have time to write it to HW.
18371849
*/
18381850
clk = ice_ptp_read_src_clk_reg(pf, NULL) + NSEC_PER_MSEC * 500;
1839-
if (rq->flags & PTP_PEROUT_PHASE || start <= clk - ice_prop_delay(hw))
1851+
if (rq->flags & PTP_PEROUT_PHASE || start <= clk - prop_delay_ns)
18401852
start = div64_u64(clk + period - 1, period) * period + phase;
18411853

18421854
/* Compensate for propagation delay from the generator to the pin. */
1843-
start -= ice_prop_delay(hw);
1855+
start -= prop_delay_ns;
18441856

18451857
return ice_ptp_write_perout(hw, rq->index, gpio_pin, start, period);
18461858
}

‎drivers/net/ethernet/intel/ice/ice_ptp.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -211,6 +211,7 @@ enum ice_ptp_pin_nvm {
211211
* struct ice_ptp_pin_desc - hardware pin description data
212212
* @name_idx: index of the name of pin in ice_pin_names
213213
* @gpio: the associated GPIO input and output pins
214+
* @delay: input and output signal delays in nanoseconds
214215
*
215216
* Structure describing a PTP-capable GPIO pin that extends ptp_pin_desc array
216217
* for the device. Device families have separate sets of available pins with
@@ -219,6 +220,7 @@ enum ice_ptp_pin_nvm {
219220
struct ice_ptp_pin_desc {
220221
int name_idx;
221222
int gpio[2];
223+
unsigned int delay[2];
222224
};
223225

224226
/**

‎drivers/net/ethernet/intel/ice/ice_ptp_consts.h‎

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -341,8 +341,6 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = {
341341
823437500, /* 823.4375 MHz PLL */
342342
/* nominal_incval */
343343
0x136e44fabULL,
344-
/* pps_delay */
345-
11,
346344
},
347345

348346
/* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
@@ -351,8 +349,6 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = {
351349
783360000, /* 783.36 MHz */
352350
/* nominal_incval */
353351
0x146cc2177ULL,
354-
/* pps_delay */
355-
12,
356352
},
357353

358354
/* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
@@ -361,8 +357,6 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = {
361357
796875000, /* 796.875 MHz */
362358
/* nominal_incval */
363359
0x141414141ULL,
364-
/* pps_delay */
365-
12,
366360
},
367361

368362
/* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
@@ -371,8 +365,6 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = {
371365
816000000, /* 816 MHz */
372366
/* nominal_incval */
373367
0x139b9b9baULL,
374-
/* pps_delay */
375-
12,
376368
},
377369

378370
/* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
@@ -381,8 +373,6 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = {
381373
830078125, /* 830.78125 MHz */
382374
/* nominal_incval */
383375
0x134679aceULL,
384-
/* pps_delay */
385-
11,
386376
},
387377

388378
/* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
@@ -391,8 +381,6 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = {
391381
783360000, /* 783.36 MHz */
392382
/* nominal_incval */
393383
0x146cc2177ULL,
394-
/* pps_delay */
395-
12,
396384
},
397385
};
398386

‎drivers/net/ethernet/intel/ice/ice_ptp_hw.h‎

Lines changed: 0 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -80,15 +80,13 @@ struct ice_phy_reg_info_eth56g {
8080
* struct ice_time_ref_info_e82x
8181
* @pll_freq: Frequency of PLL that drives timer ticks in Hz
8282
* @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L
83-
* @pps_delay: propagation delay of the PPS output signal
8483
*
8584
* Characteristic information for the various TIME_REF sources possible in the
8685
* E822 devices
8786
*/
8887
struct ice_time_ref_info_e82x {
8988
u64 pll_freq;
9089
u64 nominal_incval;
91-
u8 pps_delay;
9290
};
9391

9492
/**
@@ -326,8 +324,6 @@ extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD];
326324
*/
327325
#define ICE_E810_PLL_FREQ 812500000
328326
#define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
329-
#define ICE_E810_OUT_PROP_DELAY_NS 1
330-
#define ICE_E825C_OUT_PROP_DELAY_NS 11
331327

332328
/* Device agnostic functions */
333329
u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
@@ -389,11 +385,6 @@ static inline u64 ice_e82x_nominal_incval(enum ice_time_ref_freq time_ref)
389385
return e82x_time_ref[time_ref].nominal_incval;
390386
}
391387

392-
static inline u64 ice_e82x_pps_delay(enum ice_time_ref_freq time_ref)
393-
{
394-
return e82x_time_ref[time_ref].pps_delay;
395-
}
396-
397388
/* E822 Vernier calibration functions */
398389
int ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset);
399390
int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port);
@@ -434,20 +425,6 @@ int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port);
434425
#define ICE_ETH56G_NOMINAL_THRESH4 0x7777
435426
#define ICE_ETH56G_NOMINAL_TX_THRESH 0x6
436427

437-
static inline u64 ice_prop_delay(const struct ice_hw *hw)
438-
{
439-
switch (hw->ptp.phy_model) {
440-
case ICE_PHY_ETH56G:
441-
return ICE_E825C_OUT_PROP_DELAY_NS;
442-
case ICE_PHY_E810:
443-
return ICE_E810_OUT_PROP_DELAY_NS;
444-
case ICE_PHY_E82X:
445-
return ice_e82x_pps_delay(ice_e82x_time_ref(hw));
446-
default:
447-
return 0;
448-
}
449-
}
450-
451428
/**
452429
* ice_get_base_incval - Get base clock increment value
453430
* @hw: pointer to the HW struct

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