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Merge: Update CXL subsystem with content from v6.16
MR: https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-10/-/merge_requests/1370 # Merge Request Required Information ## Summary of Changes Back-port kernel's CXL subsystem core content from upstream v6.16 ## Approved Development Ticket(s) JIRA: https://issues.redhat.com/browse/RHEL-107284 Resolves: RHEL-107284 Signed-off-by: John W. Linville <linville@redhat.com> Approved-by: Tony Camuso <tcamuso@redhat.com> Approved-by: Charles Mirabile <cmirabil@redhat.com> Approved-by: Rafael Aquini <raquini@redhat.com> Approved-by: Myron Stowe <mstowe@redhat.com> Approved-by: Mark Langsdorf <mlangsdo@redhat.com> Approved-by: CKI KWF Bot <cki-ci-bot+kwf-gitlab-com@redhat.com> Merged-by: Scott Weaver <scweaver@redhat.com>
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Documentation/ABI/testing/sysfs-bus-cxl

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@@ -321,14 +321,13 @@ KernelVersion: v6.0
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Contact: linux-cxl@vger.kernel.org
322322
Description:
323323
(RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
324-
translates from a host physical address range, to a device local
325-
address range. Device-local address ranges are further split
326-
into a 'ram' (volatile memory) range and 'pmem' (persistent
327-
memory) range. The 'mode' attribute emits one of 'ram', 'pmem',
328-
'mixed', or 'none'. The 'mixed' indication is for error cases
329-
when a decoder straddles the volatile/persistent partition
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boundary, and 'none' indicates the decoder is not actively
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decoding, or no DPA allocation policy has been set.
324+
translates from a host physical address range, to a device
325+
local address range. Device-local address ranges are further
326+
split into a 'ram' (volatile memory) range and 'pmem'
327+
(persistent memory) range. The 'mode' attribute emits one of
328+
'ram', 'pmem', or 'none'. The 'none' indicates the decoder is
329+
not actively decoding, or no DPA allocation policy has been
330+
set.
332331

333332
'mode' can be written, when the decoder is in the 'disabled'
334333
state, with either 'ram' or 'pmem' to set the boundaries for the
@@ -571,6 +570,18 @@ Description:
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number to the closest CPU.
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573572

573+
What: /sys/bus/cxl/devices/nvdimm-bridge0/ndbusX/nmemY/cxl/dirty_shutdown
574+
Date: Feb, 2025
575+
KernelVersion: v6.15
576+
Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) The device dirty shutdown count value, which is the number
579+
of times the device could have incurred in potential data loss.
580+
The count is persistent across power loss and wraps back to 0
581+
upon overflow. If this file is not present, the device does not
582+
have the necessary support for dirty tracking.
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584+
574585
What: /sys/bus/cxl/devices/regionZ/accessY/read_latency
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/sys/bus/cxl/devices/regionZ/accessY/write_latency
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Date: Jan, 2024

Documentation/driver-api/cxl/index.rst

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@@ -4,12 +4,22 @@
44
Compute Express Link
55
====================
66

7+
CXL device configuration has a complex handoff between platform (Hardware,
8+
BIOS, EFI), OS (early boot, core kernel, driver), and user policy decisions
9+
that have impacts on each other. The docs here break up configurations steps.
10+
11+
.. toctree::
12+
:maxdepth: 2
13+
:caption: Overview
14+
15+
theory-of-operation
16+
maturity-map
17+
718
.. toctree::
819
:maxdepth: 1
20+
:caption: Linux Kernel Configuration
921

10-
memory-devices
11-
access-coordinates
22+
linux/access-coordinates
1223

13-
maturity-map
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1525
.. only:: subproject and html

Documentation/driver-api/cxl/access-coordinates.rst renamed to Documentation/driver-api/cxl/linux/access-coordinates.rst

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@@ -26,20 +26,20 @@ There can be multiple switches under an RP. There can be multiple RPs under
2626
a CXL Host Bridge (HB). There can be multiple HBs under a CXL Fixed Memory
2727
Window Structure (CFMWS).
2828

29-
An example hierarchy:
29+
An example hierarchy::
3030

31-
> CFMWS 0
32-
> |
33-
> _________|_________
34-
> | |
35-
> ACPI0017-0 ACPI0017-1
36-
> GP0/HB0/ACPI0016-0 GP1/HB1/ACPI0016-1
37-
> | | | |
38-
> RP0 RP1 RP2 RP3
39-
> | | | |
40-
> SW 0 SW 1 SW 2 SW 3
41-
> | | | | | | | |
42-
> EP0 EP1 EP2 EP3 EP4 EP5 EP6 EP7
31+
CFMWS 0
32+
|
33+
_________|_________
34+
| |
35+
ACPI0017-0 ACPI0017-1
36+
GP0/HB0/ACPI0016-0 GP1/HB1/ACPI0016-1
37+
| | | |
38+
RP0 RP1 RP2 RP3
39+
| | | |
40+
SW 0 SW 1 SW 2 SW 3
41+
| | | | | | | |
42+
EP0 EP1 EP2 EP3 EP4 EP5 EP6 EP7
4343

4444
Computation for the example hierarchy:
4545

@@ -82,10 +82,13 @@ this point all the bandwidths are aggregated per each host bridge, which is
8282
also the index for the resulting xarray.
8383

8484
The next step is to take the min() of the per host bridge bandwidth and the
85-
bandwidth from the Generic Port (GP). The bandwidths for the GP is retrieved
86-
via ACPI tables SRAT/HMAT. The min bandwidth are aggregated under the same
85+
bandwidth from the Generic Port (GP). The bandwidths for the GP are retrieved
86+
via ACPI tables SRAT/HMAT. The minimum bandwidth are aggregated under the same
8787
ACPI0017 device to form a new xarray.
8888

8989
Finally, the cxl_region_update_bandwidth() is called and the aggregated
9090
bandwidth from all the members of the last xarray is updated for the
9191
access coordinates residing in the cxl region (cxlr) context.
92+
93+
.. kernel-doc:: drivers/cxl/acpi.c
94+
:identifiers: cxl_acpi_evaluate_qtg_dsm

Documentation/driver-api/cxl/maturity-map.rst

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Original file line numberDiff line numberDiff line change
@@ -51,9 +51,9 @@ in place, but there are several corner cases that are pending closure.
5151

5252
* [2] CXL Window Enumeration
5353

54-
* [0] :ref:`Extended-linear memory-side cache <extended-linear>`
54+
* [2] :ref:`Extended-linear memory-side cache <extended-linear>`
5555
* [0] Low Memory-hole
56-
* [0] Hetero-interleave
56+
* [X] Hetero-interleave
5757

5858
* [2] Switch Enumeration
5959

@@ -130,7 +130,7 @@ Mailbox commands
130130
* [0] Switch CCI
131131
* [3] Timestamp
132132
* [1] PMEM labels
133-
* [0] PMEM GPF / Dirty Shutdown
133+
* [3] PMEM GPF / Dirty Shutdown
134134
* [0] Scan Media
135135

136136
PMU
@@ -173,7 +173,7 @@ Accelerator
173173
User Flow Support
174174
-----------------
175175

176-
* [0] HPA->DPA Address translation (need xormaps export solution)
176+
* [0] Inject & clear poison by HPA
177177

178178
Details
179179
=======

Documentation/driver-api/cxl/memory-devices.rst renamed to Documentation/driver-api/cxl/theory-of-operation.rst

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@@ -1,9 +1,9 @@
11
.. SPDX-License-Identifier: GPL-2.0
22
.. include:: <isonum.txt>
33

4-
===================================
5-
Compute Express Link Memory Devices
6-
===================================
4+
===============================================
5+
Compute Express Link Driver Theory of Operation
6+
===============================================
77

88
A Compute Express Link Memory Device is a CXL component that implements the
99
CXL.mem protocol. It contains some amount of volatile memory, persistent memory,
@@ -14,8 +14,8 @@ that optionally define a device's contribution to an interleaved address
1414
range across multiple devices underneath a host-bridge or interleaved
1515
across host-bridges.
1616

17-
CXL Bus: Theory of Operation
18-
============================
17+
The CXL Bus
18+
===========
1919
Similar to how a RAID driver takes disk objects and assembles them into a new
2020
logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and
2121
assemble them into a CXL.mem decode topology. The need for runtime configuration
@@ -347,6 +347,9 @@ CXL Core
347347
.. kernel-doc:: drivers/cxl/cxl.h
348348
:internal:
349349

350+
.. kernel-doc:: drivers/cxl/acpi.c
351+
:identifiers: add_cxl_resources
352+
350353
.. kernel-doc:: drivers/cxl/core/hdm.c
351354
:doc: cxl core hdm
352355

@@ -371,12 +374,26 @@ CXL Core
371374
.. kernel-doc:: drivers/cxl/core/pmem.c
372375
:doc: cxl pmem
373376

377+
.. kernel-doc:: drivers/cxl/core/pmem.c
378+
:identifiers:
379+
374380
.. kernel-doc:: drivers/cxl/core/regs.c
375381
:doc: cxl registers
376382

383+
.. kernel-doc:: drivers/cxl/core/regs.c
384+
:identifiers:
385+
377386
.. kernel-doc:: drivers/cxl/core/mbox.c
378387
:doc: cxl mbox
379388

389+
.. kernel-doc:: drivers/cxl/core/mbox.c
390+
:identifiers:
391+
392+
.. kernel-doc:: drivers/cxl/core/features.c
393+
:doc: cxl features
394+
395+
See :c:func:`devm_cxl_setup_features` for API details.
396+
380397
CXL Regions
381398
-----------
382399
.. kernel-doc:: drivers/cxl/core/region.c

arch/x86/mm/pat/set_memory.c

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@@ -2290,6 +2290,7 @@ int set_mce_nospec(unsigned long pfn)
22902290
pr_warn("Could not invalidate pfn=0x%lx from 1:1 map\n", pfn);
22912291
return rc;
22922292
}
2293+
EXPORT_SYMBOL_GPL(set_mce_nospec);
22932294

22942295
/* Restore full speculative operation to the pfn. */
22952296
int clear_mce_nospec(unsigned long pfn)

drivers/acpi/numa/hmat.c

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@@ -108,6 +108,45 @@ static struct memory_target *find_mem_target(unsigned int mem_pxm)
108108
return NULL;
109109
}
110110

111+
/**
112+
* hmat_get_extended_linear_cache_size - Retrieve the extended linear cache size
113+
* @backing_res: resource from the backing media
114+
* @nid: node id for the memory region
115+
* @cache_size: (Output) size of extended linear cache.
116+
*
117+
* Return: 0 on success. Errno on failure.
118+
*
119+
*/
120+
int hmat_get_extended_linear_cache_size(struct resource *backing_res, int nid,
121+
resource_size_t *cache_size)
122+
{
123+
unsigned int pxm = node_to_pxm(nid);
124+
struct memory_target *target;
125+
struct target_cache *tcache;
126+
struct resource *res;
127+
128+
target = find_mem_target(pxm);
129+
if (!target)
130+
return -ENOENT;
131+
132+
list_for_each_entry(tcache, &target->caches, node) {
133+
if (tcache->cache_attrs.address_mode !=
134+
NODE_CACHE_ADDR_MODE_EXTENDED_LINEAR)
135+
continue;
136+
137+
res = &target->memregions;
138+
if (!resource_contains(res, backing_res))
139+
continue;
140+
141+
*cache_size = tcache->cache_attrs.size;
142+
return 0;
143+
}
144+
145+
*cache_size = 0;
146+
return 0;
147+
}
148+
EXPORT_SYMBOL_NS_GPL(hmat_get_extended_linear_cache_size, "CXL");
149+
111150
static struct memory_target *acpi_find_genport_target(u32 uid)
112151
{
113152
struct memory_target *target;

drivers/cxl/Kconfig

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@@ -7,6 +7,7 @@ menuconfig CXL_BUS
77
select PCI_DOE
88
select FIRMWARE_TABLE
99
select NUMA_KEEP_MEMINFO if NUMA_MEMBLKS
10+
select FWCTL if CXL_FEATURES
1011
help
1112
CXL is a bus that is electrically compatible with PCI Express, but
1213
layers three protocols on that signalling (CXL.io, CXL.cache, and
@@ -102,6 +103,88 @@ config CXL_MEM
102103

103104
If unsure say 'm'.
104105

106+
config CXL_FEATURES
107+
bool "CXL: Features"
108+
depends on CXL_PCI
109+
help
110+
Enable support for CXL Features. A CXL device that includes a mailbox
111+
supports commands that allows listing, getting, and setting of
112+
optionally defined features such as memory sparing or post package
113+
sparing. Vendors may define custom features for the device.
114+
115+
If unsure say 'n'
116+
117+
config CXL_EDAC_MEM_FEATURES
118+
bool "CXL: EDAC Memory Features"
119+
depends on EXPERT
120+
depends on CXL_MEM
121+
depends on CXL_FEATURES
122+
depends on EDAC >= CXL_BUS
123+
help
124+
The CXL EDAC memory feature is optional and allows host to
125+
control the EDAC memory features configurations of CXL memory
126+
expander devices.
127+
128+
Say 'y' if you have an expert need to change default settings
129+
of a memory RAS feature established by the platform/device.
130+
Otherwise say 'n'.
131+
132+
config CXL_EDAC_SCRUB
133+
bool "Enable CXL Patrol Scrub Control (Patrol Read)"
134+
depends on CXL_EDAC_MEM_FEATURES
135+
depends on EDAC_SCRUB
136+
help
137+
The CXL EDAC scrub control is optional and allows host to
138+
control the scrub feature configurations of CXL memory expander
139+
devices.
140+
141+
When enabled 'cxl_mem' and 'cxl_region' EDAC devices are
142+
published with memory scrub control attributes as described by
143+
Documentation/ABI/testing/sysfs-edac-scrub.
144+
145+
Say 'y' if you have an expert need to change default settings
146+
of a memory scrub feature established by the platform/device
147+
(e.g. scrub rates for the patrol scrub feature).
148+
Otherwise say 'n'.
149+
150+
config CXL_EDAC_ECS
151+
bool "Enable CXL Error Check Scrub (Repair)"
152+
depends on CXL_EDAC_MEM_FEATURES
153+
depends on EDAC_ECS
154+
help
155+
The CXL EDAC ECS control is optional and allows host to
156+
control the ECS feature configurations of CXL memory expander
157+
devices.
158+
159+
When enabled 'cxl_mem' EDAC devices are published with memory
160+
ECS control attributes as described by
161+
Documentation/ABI/testing/sysfs-edac-ecs.
162+
163+
Say 'y' if you have an expert need to change default settings
164+
of a memory ECS feature established by the platform/device.
165+
Otherwise say 'n'.
166+
167+
config CXL_EDAC_MEM_REPAIR
168+
bool "Enable CXL Memory Repair"
169+
depends on CXL_EDAC_MEM_FEATURES
170+
depends on EDAC_MEM_REPAIR
171+
help
172+
The CXL EDAC memory repair control is optional and allows host
173+
to control the memory repair features (e.g. sparing, PPR)
174+
configurations of CXL memory expander devices.
175+
176+
When enabled, the memory repair feature requires an additional
177+
memory of approximately 43KB to store CXL DRAM and CXL general
178+
media event records.
179+
180+
When enabled 'cxl_mem' EDAC devices are published with memory
181+
repair control attributes as described by
182+
Documentation/ABI/testing/sysfs-edac-memory-repair.
183+
184+
Say 'y' if you have an expert need to change default settings
185+
of a memory repair feature established by the platform/device.
186+
Otherwise say 'n'.
187+
105188
config CXL_PORT
106189
default CXL_BUS
107190
tristate
@@ -146,4 +229,8 @@ config CXL_REGION_INVALIDATION_TEST
146229
If unsure, or if this kernel is meant for production environments,
147230
say N.
148231

232+
config CXL_MCE
233+
def_bool y
234+
depends on X86_MCE && MEMORY_FAILURE
235+
149236
endif

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