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32 | 32 | /* MAC Specific Addr 1 Top Reg */ |
33 | 33 | #define LAN865X_REG_MAC_H_SADDR1 0x00010023 |
34 | 34 |
|
| 35 | +/* MAC TSU Timer Increment Register */ |
| 36 | +#define LAN865X_REG_MAC_TSU_TIMER_INCR 0x00010077 |
| 37 | +#define MAC_TSU_TIMER_INCR_COUNT_NANOSECONDS 0x0028 |
| 38 | + |
35 | 39 | struct lan865x_priv { |
36 | 40 | struct work_struct multicast_work; |
37 | 41 | struct net_device *netdev; |
@@ -311,6 +315,8 @@ static int lan865x_net_open(struct net_device *netdev) |
311 | 315 |
|
312 | 316 | phy_start(netdev->phydev); |
313 | 317 |
|
| 318 | + netif_start_queue(netdev); |
| 319 | + |
314 | 320 | return 0; |
315 | 321 | } |
316 | 322 |
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@@ -344,6 +350,21 @@ static int lan865x_probe(struct spi_device *spi) |
344 | 350 | goto free_netdev; |
345 | 351 | } |
346 | 352 |
|
| 353 | + /* LAN865x Rev.B0/B1 configuration parameters from AN1760 |
| 354 | + * As per the Configuration Application Note AN1760 published in the |
| 355 | + * link, https://www.microchip.com/en-us/application-notes/an1760 |
| 356 | + * Revision F (DS60001760G - June 2024), configure the MAC to set time |
| 357 | + * stamping at the end of the Start of Frame Delimiter (SFD) and set the |
| 358 | + * Timer Increment reg to 40 ns to be used as a 25 MHz internal clock. |
| 359 | + */ |
| 360 | + ret = oa_tc6_write_register(priv->tc6, LAN865X_REG_MAC_TSU_TIMER_INCR, |
| 361 | + MAC_TSU_TIMER_INCR_COUNT_NANOSECONDS); |
| 362 | + if (ret) { |
| 363 | + dev_err(&spi->dev, "Failed to config TSU Timer Incr reg: %d\n", |
| 364 | + ret); |
| 365 | + goto oa_tc6_exit; |
| 366 | + } |
| 367 | + |
347 | 368 | /* As per the point s3 in the below errata, SPI receive Ethernet frame |
348 | 369 | * transfer may halt when starting the next frame in the same data block |
349 | 370 | * (chunk) as the end of a previous frame. The RFA field should be |
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