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torvaldstorvalds
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Merge tag 'drm-fixes-2025-04-19' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie: "Easter rc3 pull request, fixes in all the usuals, amdgpu, xe, msm, with some i915/ivpu/mgag200/v3d fixes, then a couple of bits in dma-buf/gem. Hopefully has no easter eggs in it. dma-buf: - Correctly decrement refcounter on errors gem: - Fix test for imported buffers amdgpu: - Cleaner shader sysfs fix - Suspend fix - Fix doorbell free ordering - Video caps fix - DML2 memory allocation optimization - HDP fix i915: - Fix DP DSC configurations that require 3 DSC engines per pipe xe: - Fix LRC address being written too late for GuC - Fix notifier vs folio deadlock - Fix race betwen dma_buf unmap and vram eviction - Fix debugfs handling PXP terminations unconditionally msm: - Display: - Fix to call dpu_plane_atomic_check_pipe() for both SSPPs in case of multi-rect - Fix to validate plane_state pointer before using it in dpu_plane_virtual_atomic_check() - Fix to make sure dereferencing dpu_encoder_phys happens after making sure it is valid in _dpu_encoder_trigger_start() - Remove the remaining intr_tear_rd_ptr which we initialized to -1 because NO_IRQ indices start from 0 now - GPU: - Fix IB_SIZE overflow ivpu: - Fix debugging - Fixes to frequency - Support firmware API 3.28.3 - Flush jobs upon reset mgag200: - Set vblank start to correct values v3d: - Fix Indirect Dispatch" * tag 'drm-fixes-2025-04-19' of https://gitlab.freedesktop.org/drm/kernel: (26 commits) drm/msm/a6xx+: Don't let IB_SIZE overflow drm/xe/pxp: do not queue unneeded terminations from debugfs drm/xe/dma_buf: stop relying on placement in unmap drm/xe/userptr: fix notifier vs folio deadlock drm/xe: Set LRC addresses before guc load drm/mgag200: Fix value in <VBLKSTR> register drm/gem: Internally test import_attach for imported objects drm/amdgpu: Use the right function for hdp flush drm/amd/display/dml2: use vzalloc rather than kzalloc drm/amdgpu: Add back JPEG to video caps for carrizo and newer drm/amdgpu: fix warning of drm_mm_clean drm/amd: Forbid suspending into non-default suspend states drm/amdgpu: use a dummy owner for sysfs triggered cleaner shaders v4 drm/i915/dp: Check for HAS_DSC_3ENGINES while configuring DSC slices drm/i915/display: Add macro for checking 3 DSC engines dma-buf/sw_sync: Decrement refcount on error in sw_sync_ioctl_get_deadline() accel/ivpu: Add cmdq_id to job related logs accel/ivpu: Show NPU frequency in sysfs accel/ivpu: Fix the NPU's DPU frequency calculation accel/ivpu: Update FW Boot API to version 3.28.3 ...
2 parents 8560697 + 0467145 commit 51c7960

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47 files changed

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lines changed

‎drivers/accel/ivpu/ivpu_drv.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
3-
* Copyright (C) 2020-2024 Intel Corporation
3+
* Copyright (C) 2020-2025 Intel Corporation
44
*/
55

66
#include <linux/firmware.h>
@@ -164,7 +164,7 @@ static int ivpu_get_param_ioctl(struct drm_device *dev, void *data, struct drm_f
164164
args->value = vdev->platform;
165165
break;
166166
case DRM_IVPU_PARAM_CORE_CLOCK_RATE:
167-
args->value = ivpu_hw_ratio_to_freq(vdev, vdev->hw->pll.max_ratio);
167+
args->value = ivpu_hw_dpu_max_freq_get(vdev);
168168
break;
169169
case DRM_IVPU_PARAM_NUM_CONTEXTS:
170170
args->value = ivpu_get_context_count(vdev);
@@ -421,9 +421,9 @@ void ivpu_prepare_for_reset(struct ivpu_device *vdev)
421421
{
422422
ivpu_hw_irq_disable(vdev);
423423
disable_irq(vdev->irq);
424-
cancel_work_sync(&vdev->irq_ipc_work);
425-
cancel_work_sync(&vdev->irq_dct_work);
426-
cancel_work_sync(&vdev->context_abort_work);
424+
flush_work(&vdev->irq_ipc_work);
425+
flush_work(&vdev->irq_dct_work);
426+
flush_work(&vdev->context_abort_work);
427427
ivpu_ipc_disable(vdev);
428428
ivpu_mmu_disable(vdev);
429429
}

‎drivers/accel/ivpu/ivpu_fw.c‎

Lines changed: 13 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
3-
* Copyright (C) 2020-2024 Intel Corporation
3+
* Copyright (C) 2020-2025 Intel Corporation
44
*/
55

66
#include <linux/firmware.h>
@@ -233,10 +233,20 @@ static int ivpu_fw_parse(struct ivpu_device *vdev)
233233
fw->dvfs_mode = 0;
234234

235235
fw->sched_mode = ivpu_fw_sched_mode_select(vdev, fw_hdr);
236-
fw->primary_preempt_buf_size = fw_hdr->preemption_buffer_1_size;
237-
fw->secondary_preempt_buf_size = fw_hdr->preemption_buffer_2_size;
238236
ivpu_info(vdev, "Scheduler mode: %s\n", fw->sched_mode ? "HW" : "OS");
239237

238+
if (fw_hdr->preemption_buffer_1_max_size)
239+
fw->primary_preempt_buf_size = fw_hdr->preemption_buffer_1_max_size;
240+
else
241+
fw->primary_preempt_buf_size = fw_hdr->preemption_buffer_1_size;
242+
243+
if (fw_hdr->preemption_buffer_2_max_size)
244+
fw->secondary_preempt_buf_size = fw_hdr->preemption_buffer_2_max_size;
245+
else
246+
fw->secondary_preempt_buf_size = fw_hdr->preemption_buffer_2_size;
247+
ivpu_dbg(vdev, FW_BOOT, "Preemption buffer sizes: primary %u, secondary %u\n",
248+
fw->primary_preempt_buf_size, fw->secondary_preempt_buf_size);
249+
240250
if (fw_hdr->ro_section_start_address && !is_within_range(fw_hdr->ro_section_start_address,
241251
fw_hdr->ro_section_size,
242252
fw_hdr->image_load_address,
@@ -566,7 +576,6 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params
566576

567577
boot_params->magic = VPU_BOOT_PARAMS_MAGIC;
568578
boot_params->vpu_id = to_pci_dev(vdev->drm.dev)->bus->number;
569-
boot_params->frequency = ivpu_hw_pll_freq_get(vdev);
570579

571580
/*
572581
* This param is a debug firmware feature. It switches default clock

‎drivers/accel/ivpu/ivpu_hw.h‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/* SPDX-License-Identifier: GPL-2.0-only */
22
/*
3-
* Copyright (C) 2020-2024 Intel Corporation
3+
* Copyright (C) 2020-2025 Intel Corporation
44
*/
55

66
#ifndef __IVPU_HW_H__
@@ -82,19 +82,19 @@ static inline u64 ivpu_hw_range_size(const struct ivpu_addr_range *range)
8282
return range->end - range->start;
8383
}
8484

85-
static inline u32 ivpu_hw_ratio_to_freq(struct ivpu_device *vdev, u32 ratio)
85+
static inline u32 ivpu_hw_dpu_max_freq_get(struct ivpu_device *vdev)
8686
{
87-
return ivpu_hw_btrs_ratio_to_freq(vdev, ratio);
87+
return ivpu_hw_btrs_dpu_max_freq_get(vdev);
8888
}
8989

90-
static inline void ivpu_hw_irq_clear(struct ivpu_device *vdev)
90+
static inline u32 ivpu_hw_dpu_freq_get(struct ivpu_device *vdev)
9191
{
92-
ivpu_hw_ip_irq_clear(vdev);
92+
return ivpu_hw_btrs_dpu_freq_get(vdev);
9393
}
9494

95-
static inline u32 ivpu_hw_pll_freq_get(struct ivpu_device *vdev)
95+
static inline void ivpu_hw_irq_clear(struct ivpu_device *vdev)
9696
{
97-
return ivpu_hw_btrs_pll_freq_get(vdev);
97+
ivpu_hw_ip_irq_clear(vdev);
9898
}
9999

100100
static inline u32 ivpu_hw_profiling_freq_get(struct ivpu_device *vdev)

‎drivers/accel/ivpu/ivpu_hw_btrs.c‎

Lines changed: 64 additions & 70 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,10 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
3-
* Copyright (C) 2020-2024 Intel Corporation
3+
* Copyright (C) 2020-2025 Intel Corporation
44
*/
55

6+
#include <linux/units.h>
7+
68
#include "ivpu_drv.h"
79
#include "ivpu_hw.h"
810
#include "ivpu_hw_btrs.h"
@@ -28,17 +30,13 @@
2830

2931
#define BTRS_LNL_ALL_IRQ_MASK ((u32)-1)
3032

31-
#define BTRS_MTL_WP_CONFIG_1_TILE_5_3_RATIO WP_CONFIG(MTL_CONFIG_1_TILE, MTL_PLL_RATIO_5_3)
32-
#define BTRS_MTL_WP_CONFIG_1_TILE_4_3_RATIO WP_CONFIG(MTL_CONFIG_1_TILE, MTL_PLL_RATIO_4_3)
33-
#define BTRS_MTL_WP_CONFIG_2_TILE_5_3_RATIO WP_CONFIG(MTL_CONFIG_2_TILE, MTL_PLL_RATIO_5_3)
34-
#define BTRS_MTL_WP_CONFIG_2_TILE_4_3_RATIO WP_CONFIG(MTL_CONFIG_2_TILE, MTL_PLL_RATIO_4_3)
35-
#define BTRS_MTL_WP_CONFIG_0_TILE_PLL_OFF WP_CONFIG(0, 0)
3633

3734
#define PLL_CDYN_DEFAULT 0x80
3835
#define PLL_EPP_DEFAULT 0x80
3936
#define PLL_CONFIG_DEFAULT 0x0
40-
#define PLL_SIMULATION_FREQ 10000000
41-
#define PLL_REF_CLK_FREQ 50000000
37+
#define PLL_REF_CLK_FREQ 50000000ull
38+
#define PLL_RATIO_TO_FREQ(x) ((x) * PLL_REF_CLK_FREQ)
39+
4240
#define PLL_TIMEOUT_US (1500 * USEC_PER_MSEC)
4341
#define IDLE_TIMEOUT_US (5 * USEC_PER_MSEC)
4442
#define TIMEOUT_US (150 * USEC_PER_MSEC)
@@ -62,6 +60,8 @@
6260
#define DCT_ENABLE 0x1
6361
#define DCT_DISABLE 0x0
6462

63+
static u32 pll_ratio_to_dpu_freq(struct ivpu_device *vdev, u32 ratio);
64+
6565
int ivpu_hw_btrs_irqs_clear_with_0_mtl(struct ivpu_device *vdev)
6666
{
6767
REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, BTRS_MTL_ALL_IRQ_MASK);
@@ -156,7 +156,7 @@ static int info_init_mtl(struct ivpu_device *vdev)
156156

157157
hw->tile_fuse = BTRS_MTL_TILE_FUSE_ENABLE_BOTH;
158158
hw->sku = BTRS_MTL_TILE_SKU_BOTH;
159-
hw->config = BTRS_MTL_WP_CONFIG_2_TILE_4_3_RATIO;
159+
hw->config = WP_CONFIG(MTL_CONFIG_2_TILE, MTL_PLL_RATIO_4_3);
160160

161161
return 0;
162162
}
@@ -334,8 +334,8 @@ int ivpu_hw_btrs_wp_drive(struct ivpu_device *vdev, bool enable)
334334

335335
prepare_wp_request(vdev, &wp, enable);
336336

337-
ivpu_dbg(vdev, PM, "PLL workpoint request: %u Hz, config: 0x%x, epp: 0x%x, cdyn: 0x%x\n",
338-
PLL_RATIO_TO_FREQ(wp.target), wp.cfg, wp.epp, wp.cdyn);
337+
ivpu_dbg(vdev, PM, "PLL workpoint request: %lu MHz, config: 0x%x, epp: 0x%x, cdyn: 0x%x\n",
338+
pll_ratio_to_dpu_freq(vdev, wp.target) / HZ_PER_MHZ, wp.cfg, wp.epp, wp.cdyn);
339339

340340
ret = wp_request_send(vdev, &wp);
341341
if (ret) {
@@ -573,6 +573,47 @@ int ivpu_hw_btrs_wait_for_idle(struct ivpu_device *vdev)
573573
return REGB_POLL_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, IDLE, 0x1, IDLE_TIMEOUT_US);
574574
}
575575

576+
static u32 pll_config_get_mtl(struct ivpu_device *vdev)
577+
{
578+
return REGB_RD32(VPU_HW_BTRS_MTL_CURRENT_PLL);
579+
}
580+
581+
static u32 pll_config_get_lnl(struct ivpu_device *vdev)
582+
{
583+
return REGB_RD32(VPU_HW_BTRS_LNL_PLL_FREQ);
584+
}
585+
586+
static u32 pll_ratio_to_dpu_freq_mtl(u16 ratio)
587+
{
588+
return (PLL_RATIO_TO_FREQ(ratio) * 2) / 3;
589+
}
590+
591+
static u32 pll_ratio_to_dpu_freq_lnl(u16 ratio)
592+
{
593+
return PLL_RATIO_TO_FREQ(ratio) / 2;
594+
}
595+
596+
static u32 pll_ratio_to_dpu_freq(struct ivpu_device *vdev, u32 ratio)
597+
{
598+
if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
599+
return pll_ratio_to_dpu_freq_mtl(ratio);
600+
else
601+
return pll_ratio_to_dpu_freq_lnl(ratio);
602+
}
603+
604+
u32 ivpu_hw_btrs_dpu_max_freq_get(struct ivpu_device *vdev)
605+
{
606+
return pll_ratio_to_dpu_freq(vdev, vdev->hw->pll.max_ratio);
607+
}
608+
609+
u32 ivpu_hw_btrs_dpu_freq_get(struct ivpu_device *vdev)
610+
{
611+
if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
612+
return pll_ratio_to_dpu_freq_mtl(pll_config_get_mtl(vdev));
613+
else
614+
return pll_ratio_to_dpu_freq_lnl(pll_config_get_lnl(vdev));
615+
}
616+
576617
/* Handler for IRQs from Buttress core (irqB) */
577618
bool ivpu_hw_btrs_irq_handler_mtl(struct ivpu_device *vdev, int irq)
578619
{
@@ -582,9 +623,12 @@ bool ivpu_hw_btrs_irq_handler_mtl(struct ivpu_device *vdev, int irq)
582623
if (!status)
583624
return false;
584625

585-
if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, FREQ_CHANGE, status))
586-
ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x",
587-
REGB_RD32(VPU_HW_BTRS_MTL_CURRENT_PLL));
626+
if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, FREQ_CHANGE, status)) {
627+
u32 pll = pll_config_get_mtl(vdev);
628+
629+
ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %lu MHz",
630+
pll, pll_ratio_to_dpu_freq_mtl(pll) / HZ_PER_MHZ);
631+
}
588632

589633
if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR, status)) {
590634
ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_HW_BTRS_MTL_ATS_ERR_LOG_0));
@@ -633,8 +677,12 @@ bool ivpu_hw_btrs_irq_handler_lnl(struct ivpu_device *vdev, int irq)
633677
queue_work(system_wq, &vdev->irq_dct_work);
634678
}
635679

636-
if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, FREQ_CHANGE, status))
637-
ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x", REGB_RD32(VPU_HW_BTRS_LNL_PLL_FREQ));
680+
if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, FREQ_CHANGE, status)) {
681+
u32 pll = pll_config_get_lnl(vdev);
682+
683+
ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %lu MHz",
684+
pll, pll_ratio_to_dpu_freq_lnl(pll) / HZ_PER_MHZ);
685+
}
638686

639687
if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, ATS_ERR, status)) {
640688
ivpu_err(vdev, "ATS_ERR LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",
@@ -717,60 +765,6 @@ void ivpu_hw_btrs_dct_set_status(struct ivpu_device *vdev, bool enable, u32 acti
717765
REGB_WR32(VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS, val);
718766
}
719767

720-
static u32 pll_ratio_to_freq_mtl(u32 ratio, u32 config)
721-
{
722-
u32 pll_clock = PLL_REF_CLK_FREQ * ratio;
723-
u32 cpu_clock;
724-
725-
if ((config & 0xff) == MTL_PLL_RATIO_4_3)
726-
cpu_clock = pll_clock * 2 / 4;
727-
else
728-
cpu_clock = pll_clock * 2 / 5;
729-
730-
return cpu_clock;
731-
}
732-
733-
u32 ivpu_hw_btrs_ratio_to_freq(struct ivpu_device *vdev, u32 ratio)
734-
{
735-
struct ivpu_hw_info *hw = vdev->hw;
736-
737-
if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
738-
return pll_ratio_to_freq_mtl(ratio, hw->config);
739-
else
740-
return PLL_RATIO_TO_FREQ(ratio);
741-
}
742-
743-
static u32 pll_freq_get_mtl(struct ivpu_device *vdev)
744-
{
745-
u32 pll_curr_ratio;
746-
747-
pll_curr_ratio = REGB_RD32(VPU_HW_BTRS_MTL_CURRENT_PLL);
748-
pll_curr_ratio &= VPU_HW_BTRS_MTL_CURRENT_PLL_RATIO_MASK;
749-
750-
if (!ivpu_is_silicon(vdev))
751-
return PLL_SIMULATION_FREQ;
752-
753-
return pll_ratio_to_freq_mtl(pll_curr_ratio, vdev->hw->config);
754-
}
755-
756-
static u32 pll_freq_get_lnl(struct ivpu_device *vdev)
757-
{
758-
u32 pll_curr_ratio;
759-
760-
pll_curr_ratio = REGB_RD32(VPU_HW_BTRS_LNL_PLL_FREQ);
761-
pll_curr_ratio &= VPU_HW_BTRS_LNL_PLL_FREQ_RATIO_MASK;
762-
763-
return PLL_RATIO_TO_FREQ(pll_curr_ratio);
764-
}
765-
766-
u32 ivpu_hw_btrs_pll_freq_get(struct ivpu_device *vdev)
767-
{
768-
if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
769-
return pll_freq_get_mtl(vdev);
770-
else
771-
return pll_freq_get_lnl(vdev);
772-
}
773-
774768
u32 ivpu_hw_btrs_telemetry_offset_get(struct ivpu_device *vdev)
775769
{
776770
if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)

‎drivers/accel/ivpu/ivpu_hw_btrs.h‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/* SPDX-License-Identifier: GPL-2.0-only */
22
/*
3-
* Copyright (C) 2020-2024 Intel Corporation
3+
* Copyright (C) 2020-2025 Intel Corporation
44
*/
55

66
#ifndef __IVPU_HW_BTRS_H__
@@ -13,7 +13,6 @@
1313

1414
#define PLL_PROFILING_FREQ_DEFAULT 38400000
1515
#define PLL_PROFILING_FREQ_HIGH 400000000
16-
#define PLL_RATIO_TO_FREQ(x) ((x) * PLL_REF_CLK_FREQ)
1716

1817
#define DCT_DEFAULT_ACTIVE_PERCENT 15u
1918
#define DCT_PERIOD_US 35300u
@@ -32,12 +31,12 @@ int ivpu_hw_btrs_ip_reset(struct ivpu_device *vdev);
3231
void ivpu_hw_btrs_profiling_freq_reg_set_lnl(struct ivpu_device *vdev);
3332
void ivpu_hw_btrs_ats_print_lnl(struct ivpu_device *vdev);
3433
void ivpu_hw_btrs_clock_relinquish_disable_lnl(struct ivpu_device *vdev);
34+
u32 ivpu_hw_btrs_dpu_max_freq_get(struct ivpu_device *vdev);
35+
u32 ivpu_hw_btrs_dpu_freq_get(struct ivpu_device *vdev);
3536
bool ivpu_hw_btrs_irq_handler_mtl(struct ivpu_device *vdev, int irq);
3637
bool ivpu_hw_btrs_irq_handler_lnl(struct ivpu_device *vdev, int irq);
3738
int ivpu_hw_btrs_dct_get_request(struct ivpu_device *vdev, bool *enable);
3839
void ivpu_hw_btrs_dct_set_status(struct ivpu_device *vdev, bool enable, u32 dct_percent);
39-
u32 ivpu_hw_btrs_pll_freq_get(struct ivpu_device *vdev);
40-
u32 ivpu_hw_btrs_ratio_to_freq(struct ivpu_device *vdev, u32 ratio);
4140
u32 ivpu_hw_btrs_telemetry_offset_get(struct ivpu_device *vdev);
4241
u32 ivpu_hw_btrs_telemetry_size_get(struct ivpu_device *vdev);
4342
u32 ivpu_hw_btrs_telemetry_enable_get(struct ivpu_device *vdev);

‎drivers/accel/ivpu/ivpu_job.c‎

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -470,8 +470,8 @@ static void ivpu_job_destroy(struct ivpu_job *job)
470470
struct ivpu_device *vdev = job->vdev;
471471
u32 i;
472472

473-
ivpu_dbg(vdev, JOB, "Job destroyed: id %3u ctx %2d engine %d",
474-
job->job_id, job->file_priv->ctx.id, job->engine_idx);
473+
ivpu_dbg(vdev, JOB, "Job destroyed: id %3u ctx %2d cmdq_id %u engine %d",
474+
job->job_id, job->file_priv->ctx.id, job->cmdq_id, job->engine_idx);
475475

476476
for (i = 0; i < job->bo_count; i++)
477477
if (job->bos[i])
@@ -564,8 +564,8 @@ static int ivpu_job_signal_and_destroy(struct ivpu_device *vdev, u32 job_id, u32
564564
dma_fence_signal(job->done_fence);
565565

566566
trace_job("done", job);
567-
ivpu_dbg(vdev, JOB, "Job complete: id %3u ctx %2d engine %d status 0x%x\n",
568-
job->job_id, job->file_priv->ctx.id, job->engine_idx, job_status);
567+
ivpu_dbg(vdev, JOB, "Job complete: id %3u ctx %2d cmdq_id %u engine %d status 0x%x\n",
568+
job->job_id, job->file_priv->ctx.id, job->cmdq_id, job->engine_idx, job_status);
569569

570570
ivpu_job_destroy(job);
571571
ivpu_stop_job_timeout_detection(vdev);
@@ -664,8 +664,8 @@ static int ivpu_job_submit(struct ivpu_job *job, u8 priority, u32 cmdq_id)
664664
}
665665

666666
trace_job("submit", job);
667-
ivpu_dbg(vdev, JOB, "Job submitted: id %3u ctx %2d engine %d prio %d addr 0x%llx next %d\n",
668-
job->job_id, file_priv->ctx.id, job->engine_idx, cmdq->priority,
667+
ivpu_dbg(vdev, JOB, "Job submitted: id %3u ctx %2d cmdq_id %u engine %d prio %d addr 0x%llx next %d\n",
668+
job->job_id, file_priv->ctx.id, cmdq->id, job->engine_idx, cmdq->priority,
669669
job->cmd_buf_vpu_addr, cmdq->jobq->header.tail);
670670

671671
mutex_unlock(&file_priv->lock);
@@ -777,7 +777,8 @@ static int ivpu_submit(struct drm_file *file, struct ivpu_file_priv *file_priv,
777777
goto err_free_handles;
778778
}
779779

780-
ivpu_dbg(vdev, JOB, "Submit ioctl: ctx %u buf_count %u\n", file_priv->ctx.id, buffer_count);
780+
ivpu_dbg(vdev, JOB, "Submit ioctl: ctx %u cmdq_id %u buf_count %u\n",
781+
file_priv->ctx.id, cmdq_id, buffer_count);
781782

782783
job = ivpu_job_create(file_priv, engine, buffer_count);
783784
if (!job) {

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