Skip to content

Commit 4df9166

Browse files
committed
ice: Refactor E825C PHY registers info struct
jira LE-4694 Rebuild_History Non-Buildable kernel-6.12.0-55.43.1.el10_0 commit-author Karol Kolacinski <karol.kolacinski@intel.com> commit 66a1b7e Simplify ice_phy_reg_info_eth56g struct definition to include base address for the very first quad. Use base address info and 'step' value to determine address for specific PHY quad. Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> Reviewed-by: Simon Horman <horms@kernel.org> Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel) Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> Link: https://patch.msgid.link/20250310174502.3708121-4-anthony.l.nguyen@intel.com Signed-off-by: Paolo Abeni <pabeni@redhat.com> (cherry picked from commit 66a1b7e) Signed-off-by: Jonathan Maple <jmaple@ciq.com>
1 parent 8c0f525 commit 4df9166

File tree

3 files changed

+20
-65
lines changed

3 files changed

+20
-65
lines changed

drivers/net/ethernet/intel/ice/ice_ptp_consts.h

Lines changed: 15 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -10,70 +10,25 @@
1010
/* Constants defined for the PTP 1588 clock hardware. */
1111

1212
const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES] = {
13-
/* ETH56G_PHY_REG_PTP */
14-
{
15-
/* base_addr */
16-
{
17-
0x092000,
18-
0x126000,
19-
0x1BA000,
20-
0x24E000,
21-
0x2E2000,
22-
},
23-
/* step */
24-
0x98,
13+
[ETH56G_PHY_REG_PTP] = {
14+
.base_addr = 0x092000,
15+
.step = 0x98,
2516
},
26-
/* ETH56G_PHY_MEM_PTP */
27-
{
28-
/* base_addr */
29-
{
30-
0x093000,
31-
0x127000,
32-
0x1BB000,
33-
0x24F000,
34-
0x2E3000,
35-
},
36-
/* step */
37-
0x200,
17+
[ETH56G_PHY_MEM_PTP] = {
18+
.base_addr = 0x093000,
19+
.step = 0x200,
3820
},
39-
/* ETH56G_PHY_REG_XPCS */
40-
{
41-
/* base_addr */
42-
{
43-
0x000000,
44-
0x009400,
45-
0x128000,
46-
0x1BC000,
47-
0x250000,
48-
},
49-
/* step */
50-
0x21000,
21+
[ETH56G_PHY_REG_XPCS] = {
22+
.base_addr = 0x000000,
23+
.step = 0x21000,
5124
},
52-
/* ETH56G_PHY_REG_MAC */
53-
{
54-
/* base_addr */
55-
{
56-
0x085000,
57-
0x119000,
58-
0x1AD000,
59-
0x241000,
60-
0x2D5000,
61-
},
62-
/* step */
63-
0x1000,
25+
[ETH56G_PHY_REG_MAC] = {
26+
.base_addr = 0x085000,
27+
.step = 0x1000,
6428
},
65-
/* ETH56G_PHY_REG_GPCS */
66-
{
67-
/* base_addr */
68-
{
69-
0x084000,
70-
0x118000,
71-
0x1AC000,
72-
0x240000,
73-
0x2D4000,
74-
},
75-
/* step */
76-
0x400,
29+
[ETH56G_PHY_REG_GPCS] = {
30+
.base_addr = 0x084000,
31+
.step = 0x400,
7732
},
7833
};
7934

drivers/net/ethernet/intel/ice/ice_ptp_hw.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -998,7 +998,7 @@ static int ice_phy_res_address_eth56g(struct ice_hw *hw, u8 lane,
998998

999999
/* Lanes 4..7 are in fact 0..3 on a second PHY */
10001000
lane %= hw->ptp.ports_per_phy;
1001-
*addr = eth56g_phy_res[res_type].base[0] +
1001+
*addr = eth56g_phy_res[res_type].base_addr +
10021002
lane * eth56g_phy_res[res_type].step + offset;
10031003

10041004
return 0;
@@ -1228,7 +1228,7 @@ static int ice_write_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
12281228
if (port >= hw->ptp.num_lports)
12291229
return -EIO;
12301230

1231-
addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base[0] + offset;
1231+
addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset;
12321232

12331233
return ice_write_phy_eth56g(hw, port, addr, val);
12341234
}
@@ -1253,7 +1253,7 @@ static int ice_read_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
12531253
if (port >= hw->ptp.num_lports)
12541254
return -EIO;
12551255

1256-
addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base[0] + offset;
1256+
addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset;
12571257

12581258
return ice_read_phy_eth56g(hw, port, addr, val);
12591259
}

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -65,14 +65,14 @@ enum ice_eth56g_link_spd {
6565

6666
/**
6767
* struct ice_phy_reg_info_eth56g - ETH56G PHY register parameters
68-
* @base: base address for each PHY block
68+
* @base_addr: base address for each PHY block
6969
* @step: step between PHY lanes
7070
*
7171
* Characteristic information for the various PHY register parameters in the
7272
* ETH56G devices
7373
*/
7474
struct ice_phy_reg_info_eth56g {
75-
u32 base[NUM_ETH56G_PHY_RES];
75+
u32 base_addr;
7676
u32 step;
7777
};
7878

0 commit comments

Comments
 (0)