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x86/bugs: Rename various 'ia32_cap' variables to 'x86_arch_cap_msr'
jira LE-2015 cve CVE-2024-2201 Rebuild_History Non-Buildable kernel-5.14.0-427.42.1.el9_4 commit-author Ingo Molnar <mingo@kernel.org> commit d048573 Empty-Commit: Cherry-Pick Conflicts during history rebuild. Will be included in final tarball splat. Ref for failed cherry-pick at: ciq/ciq_backports/kernel-5.14.0-427.42.1.el9_4/d0485730.failed So we are using the 'ia32_cap' value in a number of places, which got its name from MSR_IA32_ARCH_CAPABILITIES MSR register. But there's very little 'IA32' about it - this isn't 32-bit only code, nor does it originate from there, it's just a historic quirk that many Intel MSR names are prefixed with IA32_. This is already clear from the helper method around the MSR: x86_read_arch_cap_msr(), which doesn't have the IA32 prefix. So rename 'ia32_cap' to 'x86_arch_cap_msr' to be consistent with its role and with the naming of the helper function. Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Nikolay Borisov <nik.borisov@suse.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Sean Christopherson <seanjc@google.com> Link: https://lore.kernel.org/r/9592a18a814368e75f8f4b9d74d3883aa4fd1eaf.1712813475.git.jpoimboe@kernel.org (cherry picked from commit d048573) Signed-off-by: Jonathan Maple <jmaple@ciq.com> # Conflicts: # arch/x86/kernel/apic/apic.c # arch/x86/kernel/cpu/bugs.c # arch/x86/kernel/cpu/common.c
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‎ciq/ciq_backports/kernel-5.14.0-427.42.1.el9_4/d0485730.failed‎

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x86/bugs: Rename various 'ia32_cap' variables to 'x86_arch_cap_msr'
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jira LE-2015
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cve CVE-2024-2201
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Rebuild_History Non-Buildable kernel-5.14.0-427.42.1.el9_4
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commit-author Ingo Molnar <mingo@kernel.org>
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commit d0485730d2189ffe5d986d4e9e191f1e4d5ffd24
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Empty-Commit: Cherry-Pick Conflicts during history rebuild.
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Will be included in final tarball splat. Ref for failed cherry-pick at:
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ciq/ciq_backports/kernel-5.14.0-427.42.1.el9_4/d0485730.failed
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So we are using the 'ia32_cap' value in a number of places,
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which got its name from MSR_IA32_ARCH_CAPABILITIES MSR register.
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But there's very little 'IA32' about it - this isn't 32-bit only
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code, nor does it originate from there, it's just a historic
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quirk that many Intel MSR names are prefixed with IA32_.
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This is already clear from the helper method around the MSR:
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x86_read_arch_cap_msr(), which doesn't have the IA32 prefix.
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So rename 'ia32_cap' to 'x86_arch_cap_msr' to be consistent with
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its role and with the naming of the helper function.
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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Cc: Josh Poimboeuf <jpoimboe@redhat.com>
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Cc: Nikolay Borisov <nik.borisov@suse.com>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Sean Christopherson <seanjc@google.com>
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Link: https://lore.kernel.org/r/9592a18a814368e75f8f4b9d74d3883aa4fd1eaf.1712813475.git.jpoimboe@kernel.org
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(cherry picked from commit d0485730d2189ffe5d986d4e9e191f1e4d5ffd24)
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Signed-off-by: Jonathan Maple <jmaple@ciq.com>
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# Conflicts:
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# arch/x86/kernel/apic/apic.c
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# arch/x86/kernel/cpu/bugs.c
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# arch/x86/kernel/cpu/common.c
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diff --cc arch/x86/kernel/apic/apic.c
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index 2dc0943c5bd4,c342c4aa9c68..000000000000
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--- a/arch/x86/kernel/apic/apic.c
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+++ b/arch/x86/kernel/apic/apic.c
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@@@ -1752,6 -1685,19 +1752,22 @@@ enum
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};
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static int x2apic_state;
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++<<<<<<< HEAD
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++=======
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+ static bool x2apic_hw_locked(void)
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+ {
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+ u64 x86_arch_cap_msr;
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+ u64 msr;
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+
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+ x86_arch_cap_msr = x86_read_arch_cap_msr();
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+ if (x86_arch_cap_msr & ARCH_CAP_XAPIC_DISABLE) {
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+ rdmsrl(MSR_IA32_XAPIC_DISABLE_STATUS, msr);
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+ return (msr & LEGACY_XAPIC_DISABLED);
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+ }
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+ return false;
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+ }
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+
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++>>>>>>> d0485730d218 (x86/bugs: Rename various 'ia32_cap' variables to 'x86_arch_cap_msr')
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static void __x2apic_disable(void)
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{
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u64 msr;
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diff --cc arch/x86/kernel/cpu/bugs.c
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index d1c0c8f6898b,1b0cfc136432..000000000000
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--- a/arch/x86/kernel/cpu/bugs.c
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+++ b/arch/x86/kernel/cpu/bugs.c
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@@@ -61,6 -61,8 +61,11 @@@ EXPORT_SYMBOL_GPL(x86_spec_ctrl_current
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u64 x86_pred_cmd __ro_after_init = PRED_CMD_IBPB;
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EXPORT_SYMBOL_GPL(x86_pred_cmd);
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++<<<<<<< HEAD
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++=======
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+ static u64 __ro_after_init x86_arch_cap_msr;
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+
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++>>>>>>> d0485730d218 (x86/bugs: Rename various 'ia32_cap' variables to 'x86_arch_cap_msr')
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static DEFINE_MUTEX(spec_ctrl_mutex);
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void (*x86_return_thunk)(void) __ro_after_init = __x86_return_thunk;
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@@@ -144,6 -146,8 +149,11 @@@ void __init cpu_select_mitigations(void
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x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK;
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}
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++<<<<<<< HEAD
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++=======
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+ x86_arch_cap_msr = x86_read_arch_cap_msr();
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+
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++>>>>>>> d0485730d218 (x86/bugs: Rename various 'ia32_cap' variables to 'x86_arch_cap_msr')
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/* Select the proper CPU mitigations before patching alternatives: */
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spectre_v1_select_mitigation();
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spectre_v2_select_mitigation();
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@@@ -341,9 -343,8 +351,14 @@@ static void __init taa_select_mitigatio
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* On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
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* update is required.
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*/
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++<<<<<<< HEAD
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+ ia32_cap = x86_read_arch_cap_msr();
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+ if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
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+ !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
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++=======
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+ if ( (x86_arch_cap_msr & ARCH_CAP_MDS_NO) &&
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+ !(x86_arch_cap_msr & ARCH_CAP_TSX_CTRL_MSR))
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++>>>>>>> d0485730d218 (x86/bugs: Rename various 'ia32_cap' variables to 'x86_arch_cap_msr')
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taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
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/*
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@@@ -508,7 -505,7 +523,11 @@@ static void __init rfds_select_mitigati
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if (rfds_mitigation == RFDS_MITIGATION_OFF)
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return;
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++<<<<<<< HEAD
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+ if (x86_read_arch_cap_msr() & ARCH_CAP_RFDS_CLEAR)
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++=======
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+ if (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR)
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++>>>>>>> d0485730d218 (x86/bugs: Rename various 'ia32_cap' variables to 'x86_arch_cap_msr')
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setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF);
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else
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rfds_mitigation = RFDS_MITIGATION_UCODE_NEEDED;
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@@@ -669,8 -664,7 +688,12 @@@ static void __init srbds_select_mitigat
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* are only exposed to SRBDS when TSX is enabled or when CPU is affected
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* by Processor MMIO Stale Data vulnerability.
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*/
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++<<<<<<< HEAD
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+ ia32_cap = x86_read_arch_cap_msr();
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+ if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) &&
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++=======
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+ if ((x86_arch_cap_msr & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) &&
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++>>>>>>> d0485730d218 (x86/bugs: Rename various 'ia32_cap' variables to 'x86_arch_cap_msr')
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!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
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srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
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else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
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@@@ -813,7 -807,7 +836,11 @@@ static void __init gds_select_mitigatio
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/* Will verify below that mitigation _can_ be disabled */
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/* No microcode */
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++<<<<<<< HEAD
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+ if (!(x86_read_arch_cap_msr() & ARCH_CAP_GDS_CTRL)) {
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++=======
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+ if (!(x86_arch_cap_msr & ARCH_CAP_GDS_CTRL)) {
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++>>>>>>> d0485730d218 (x86/bugs: Rename various 'ia32_cap' variables to 'x86_arch_cap_msr')
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if (gds_mitigation == GDS_MITIGATION_FORCE) {
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/*
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* This only needs to be done on the boot CPU so do it
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@@@ -2814,6 -2801,23 +2841,26 @@@ static char *pbrsb_eibrs_state(void
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}
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}
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++<<<<<<< HEAD
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++=======
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+ static const char *spectre_bhi_state(void)
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+ {
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+ if (!boot_cpu_has_bug(X86_BUG_BHI))
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+ return "; BHI: Not affected";
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+ else if (boot_cpu_has(X86_FEATURE_CLEAR_BHB_HW))
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+ return "; BHI: BHI_DIS_S";
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+ else if (boot_cpu_has(X86_FEATURE_CLEAR_BHB_LOOP))
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+ return "; BHI: SW loop, KVM: SW loop";
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+ else if (boot_cpu_has(X86_FEATURE_RETPOLINE) &&
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+ !(x86_arch_cap_msr & ARCH_CAP_RRSBA))
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+ return "; BHI: Retpoline";
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+ else if (boot_cpu_has(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT))
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+ return "; BHI: Syscall hardening, KVM: SW loop";
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+
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+ return "; BHI: Vulnerable (Syscall hardening enabled)";
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+ }
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+
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++>>>>>>> d0485730d218 (x86/bugs: Rename various 'ia32_cap' variables to 'x86_arch_cap_msr')
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static ssize_t spectre_v2_show_state(char *buf)
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{
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if (spectre_v2_enabled == SPECTRE_V2_LFENCE)
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diff --cc arch/x86/kernel/cpu/common.c
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index d70234c30213,605c26c009c8..000000000000
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--- a/arch/x86/kernel/cpu/common.c
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+++ b/arch/x86/kernel/cpu/common.c
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@@@ -1461,11 -1342,16 +1461,17 @@@ static void __init cpu_set_bug_bits(str
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/*
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* AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature
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* flag and protect from vendor-specific bugs via the whitelist.
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- *
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- * Don't use AutoIBRS when SNP is enabled because it degrades host
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- * userspace indirect branch performance.
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*/
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++<<<<<<< HEAD
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+ if ((ia32_cap & ARCH_CAP_IBRS_ALL) || cpu_has(c, X86_FEATURE_AUTOIBRS)) {
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++=======
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+ if ((x86_arch_cap_msr & ARCH_CAP_IBRS_ALL) ||
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+ (cpu_has(c, X86_FEATURE_AUTOIBRS) &&
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+ !cpu_feature_enabled(X86_FEATURE_SEV_SNP))) {
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++>>>>>>> d0485730d218 (x86/bugs: Rename various 'ia32_cap' variables to 'x86_arch_cap_msr')
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setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
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if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) &&
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- !(ia32_cap & ARCH_CAP_PBRSB_NO))
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+ !(x86_arch_cap_msr & ARCH_CAP_PBRSB_NO))
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setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB);
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}
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@@@ -1525,8 -1411,7 +1531,12 @@@
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}
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if (!cpu_has(c, X86_FEATURE_BTC_NO)) {
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++<<<<<<< HEAD
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+ if (cpu_matches(cpu_vuln_blacklist, RETBLEED) ||
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+ ((ia32_cap & ARCH_CAP_RSBA) && !cpu_in_retbleed_whitelist(c)))
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++=======
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+ if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (x86_arch_cap_msr & ARCH_CAP_RSBA))
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++>>>>>>> d0485730d218 (x86/bugs: Rename various 'ia32_cap' variables to 'x86_arch_cap_msr')
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setup_force_cpu_bug(X86_BUG_RETBLEED);
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}
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* Unmerged path arch/x86/kernel/apic/apic.c
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* Unmerged path arch/x86/kernel/cpu/bugs.c
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* Unmerged path arch/x86/kernel/cpu/common.c

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