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Merge: zl3073x: backport the driver into RHEL9
MR: https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-9/-/merge_requests/7159 JIRA: https://issues.redhat.com/browse/RHEL-105063 Depends: !7157 Depends: !7158 This backports zl3073x DPLL driver. Signed-off-by: Ivan Vecera <ivecera@redhat.com> Approved-by: Michal Schmidt <mschmidt@redhat.com> Approved-by: Petr Oros <poros@redhat.com> Approved-by: CKI KWF Bot <cki-ci-bot+kwf-gitlab-com@redhat.com> Merged-by: Patrick Talbert <ptalbert@redhat.com>
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‎Documentation/devicetree/bindings/dpll/dpll-device.yaml‎

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dpll/dpll-device.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Digital Phase-Locked Loop (DPLL) Device
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maintainers:
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- Ivan Vecera <ivecera@redhat.com>
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description:
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Digital Phase-Locked Loop (DPLL) device is used for precise clock
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synchronization in networking and telecom hardware. The device can
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have one or more channels (DPLLs) and one or more physical input and
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output pins. Each DPLL channel can either produce pulse-per-clock signal
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or drive ethernet equipment clock. The type of each channel can be
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indicated by dpll-types property.
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properties:
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$nodename:
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pattern: "^dpll(@.*)?$"
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"#address-cells":
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const: 0
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"#size-cells":
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const: 0
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dpll-types:
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description: List of DPLL channel types, one per DPLL instance.
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$ref: /schemas/types.yaml#/definitions/non-unique-string-array
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items:
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enum: [pps, eec]
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input-pins:
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type: object
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description: DPLL input pins
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unevaluatedProperties: false
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properties:
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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patternProperties:
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"^pin@[0-9a-f]+$":
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$ref: /schemas/dpll/dpll-pin.yaml
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unevaluatedProperties: false
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required:
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- "#address-cells"
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- "#size-cells"
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output-pins:
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type: object
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description: DPLL output pins
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unevaluatedProperties: false
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properties:
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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patternProperties:
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"^pin@[0-9]+$":
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$ref: /schemas/dpll/dpll-pin.yaml
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unevaluatedProperties: false
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required:
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- "#address-cells"
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- "#size-cells"
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additionalProperties: true

‎Documentation/devicetree/bindings/dpll/dpll-pin.yaml‎

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dpll/dpll-pin.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: DPLL Pin
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maintainers:
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- Ivan Vecera <ivecera@redhat.com>
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description: |
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The DPLL pin is either a physical input or output pin that is provided
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by a DPLL( Digital Phase-Locked Loop) device. The pin is identified by
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its physical order number that is stored in reg property and can have
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an additional set of properties like supported (allowed) frequencies,
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label, type and may support embedded sync.
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Note that the pin in this context has nothing to do with pinctrl.
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properties:
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reg:
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description: Hardware index of the DPLL pin.
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maxItems: 1
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connection-type:
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description: Connection type of the pin
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$ref: /schemas/types.yaml#/definitions/string
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enum: [ext, gnss, int, mux, synce]
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esync-control:
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description: Indicates whether the pin supports embedded sync functionality.
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type: boolean
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label:
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description: String exposed as the pin board label
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$ref: /schemas/types.yaml#/definitions/string
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supported-frequencies-hz:
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description: List of supported frequencies for this pin, expressed in Hz.
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required:
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- reg
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additionalProperties: false

‎Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml‎

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dpll/microchip,zl30731.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip Azurite DPLL device
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maintainers:
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- Ivan Vecera <ivecera@redhat.com>
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description:
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Microchip Azurite DPLL (ZL3073x) is a family of DPLL devices that
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provides up to 5 independent DPLL channels, up to 10 differential or
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single-ended inputs and 10 differential or 20 single-ended outputs.
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These devices support both I2C and SPI interfaces.
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properties:
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compatible:
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enum:
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- microchip,zl30731
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- microchip,zl30732
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- microchip,zl30733
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- microchip,zl30734
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- microchip,zl30735
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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allOf:
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- $ref: /schemas/dpll/dpll-device.yaml#
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- $ref: /schemas/spi/spi-peripheral-props.yaml#
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unevaluatedProperties: false
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examples:
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- |
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i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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dpll@70 {
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compatible = "microchip,zl30732";
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reg = <0x70>;
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dpll-types = "pps", "eec";
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input-pins {
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#address-cells = <1>;
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#size-cells = <0>;
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pin@0 { /* REF0P */
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reg = <0>;
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connection-type = "ext";
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label = "Input 0";
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supported-frequencies-hz = /bits/ 64 <1 1000>;
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};
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};
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output-pins {
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#address-cells = <1>;
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#size-cells = <0>;
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pin@3 { /* OUT1N */
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reg = <3>;
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connection-type = "gnss";
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esync-control;
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label = "Output 1";
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supported-frequencies-hz = /bits/ 64 <1 10000>;
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};
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};
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};
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};
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- |
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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dpll@70 {
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compatible = "microchip,zl30731";
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reg = <0x70>;
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spi-max-frequency = <12500000>;
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dpll-types = "pps";
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input-pins {
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#address-cells = <1>;
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#size-cells = <0>;
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pin@0 { /* REF0P */
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reg = <0>;
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connection-type = "ext";
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label = "Input 0";
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supported-frequencies-hz = /bits/ 64 <1 1000>;
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};
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};
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output-pins {
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#address-cells = <1>;
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#size-cells = <0>;
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pin@3 { /* OUT1N */
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reg = <3>;
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connection-type = "gnss";
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esync-control;
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label = "Output 1";
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supported-frequencies-hz = /bits/ 64 <1 10000>;
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};
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};
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};
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};
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...

‎Documentation/networking/devlink/index.rst‎

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prestera
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iosm
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sfc
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zl3073x

‎Documentation/networking/devlink/zl3073x.rst‎

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.. SPDX-License-Identifier: GPL-2.0
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=======================
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zl3073x devlink support
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=======================
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This document describes the devlink features implemented by the ``zl3073x``
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device driver.
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Parameters
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==========
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.. list-table:: Generic parameters implemented
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:widths: 5 5 90
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* - Name
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- Mode
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- Notes
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* - ``clock_id``
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- driverinit
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- Set the clock ID that is used by the driver for registering DPLL devices
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and pins.
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Info versions
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=============
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The ``zl3073x`` driver reports the following versions
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.. list-table:: devlink info versions implemented
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:widths: 5 5 5 90
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* - Name
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- Type
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- Example
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- Description
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* - ``asic.id``
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- fixed
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- 1E94
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- Chip identification number
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* - ``asic.rev``
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- fixed
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- 300
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- Chip revision number
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* - ``fw``
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- running
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- 7006
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- Firmware version number
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* - ``custom_cfg``
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- running
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- 1.3.0.1
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- Device configuration version customized by OEM

‎MAINTAINERS‎

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M: Jiri Pirko <jiri@resnulli.us>
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L: netdev@vger.kernel.org
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S: Supported
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F: Documentation/devicetree/bindings/dpll/dpll-device.yaml
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F: Documentation/devicetree/bindings/dpll/dpll-pin.yaml
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F: Documentation/driver-api/dpll.rst
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F: drivers/dpll/*
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F: include/linux/dpll.h
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S: Supported
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F: drivers/net/wireless/microchip/wilc1000/
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MICROCHIP ZL3073X DRIVER
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M: Ivan Vecera <ivecera@redhat.com>
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M: Prathosh Satish <Prathosh.Satish@microchip.com>
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L: netdev@vger.kernel.org
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S: Supported
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F: Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml
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F: drivers/dpll/zl3073x/
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MICROSEMI MIPS SOCS
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M: Alexandre Belloni <alexandre.belloni@bootlin.com>
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M: UNGLinuxDriver@microchip.com

‎drivers/Kconfig‎

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source "drivers/ptp/Kconfig"
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source "drivers/dpll/Kconfig"
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source "drivers/pinctrl/Kconfig"
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source "drivers/gpio/Kconfig"
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source "drivers/hte/Kconfig"
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source "drivers/dpll/Kconfig"
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endmenu

‎drivers/dpll/Kconfig‎

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# Generic DPLL drivers configuration
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#
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menu "DPLL device support"
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config DPLL
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bool
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source "drivers/dpll/zl3073x/Kconfig"
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endmenu

‎drivers/dpll/Makefile‎

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dpll-y += dpll_core.o
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dpll-y += dpll_netlink.o
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dpll-y += dpll_nl.o
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obj-$(CONFIG_ZL3073X) += zl3073x/

‎drivers/dpll/zl3073x/Kconfig‎

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# SPDX-License-Identifier: GPL-2.0-only
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config ZL3073X
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tristate "Microchip Azurite DPLL/PTP/SyncE devices" if COMPILE_TEST
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depends on NET
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select DPLL
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select NET_DEVLINK
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select REGMAP
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help
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This driver supports Microchip Azurite family DPLL/PTP/SyncE
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devices that support up to 5 independent DPLL channels,
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10 input pins and up to 20 output pins.
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To compile this driver as a module, choose M here. The module
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will be called zl3073x.
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config ZL3073X_I2C
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tristate "I2C bus implementation for Microchip Azurite devices"
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depends on I2C && NET
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select REGMAP_I2C
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select ZL3073X
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help
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This is I2C bus implementation for Microchip Azurite DPLL/PTP/SyncE
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devices.
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To compile this driver as a module, choose M here: the module will
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be called zl3073x_i2c.
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config ZL3073X_SPI
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tristate "SPI bus implementation for Microchip Azurite devices"
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depends on NET && SPI
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select REGMAP_SPI
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select ZL3073X
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help
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This is SPI bus implementation for Microchip Azurite DPLL/PTP/SyncE
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devices.
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To compile this driver as a module, choose M here: the module will
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be called zl3073x_spi.

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