@@ -805,77 +805,65 @@ static int i801_simple_transaction(struct i801_priv *priv, union i2c_smbus_data
805805 return 0 ;
806806}
807807
808- /* Block transaction function */
809- static int i801_block_transaction (struct i801_priv * priv , union i2c_smbus_data * data ,
810- u8 addr , u8 hstcmd , char read_write , int command )
808+ static int i801_smbus_block_transaction (struct i801_priv * priv , union i2c_smbus_data * data ,
809+ u8 addr , u8 hstcmd , char read_write , int command )
811810{
812- int result = 0 ;
813- unsigned char hostc ;
814-
815811 if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA )
816812 data -> block [0 ] = I2C_SMBUS_BLOCK_MAX ;
817813 else if (data -> block [0 ] < 1 || data -> block [0 ] > I2C_SMBUS_BLOCK_MAX )
818814 return - EPROTO ;
819815
820- switch (command ) {
821- case I2C_SMBUS_BLOCK_DATA :
822- i801_set_hstadd (priv , addr , read_write );
823- outb_p (hstcmd , SMBHSTCMD (priv ));
824- break ;
825- case I2C_SMBUS_I2C_BLOCK_DATA :
826- /*
827- * NB: page 240 of ICH5 datasheet shows that the R/#W
828- * bit should be cleared here, even when reading.
829- * However if SPD Write Disable is set (Lynx Point and later),
830- * the read will fail if we don't set the R/#W bit.
831- */
832- i801_set_hstadd (priv , addr ,
833- priv -> original_hstcfg & SMBHSTCFG_SPD_WD ?
834- read_write : I2C_SMBUS_WRITE );
835- if (read_write == I2C_SMBUS_READ ) {
836- /* NB: page 240 of ICH5 datasheet also shows
837- * that DATA1 is the cmd field when reading
838- */
839- outb_p (hstcmd , SMBHSTDAT1 (priv ));
840- } else
841- outb_p (hstcmd , SMBHSTCMD (priv ));
842-
843- if (read_write == I2C_SMBUS_WRITE ) {
844- /* set I2C_EN bit in configuration register */
845- pci_read_config_byte (priv -> pci_dev , SMBHSTCFG , & hostc );
846- pci_write_config_byte (priv -> pci_dev , SMBHSTCFG ,
847- hostc | SMBHSTCFG_I2C_EN );
848- } else if (!(priv -> features & FEATURE_I2C_BLOCK_READ )) {
849- dev_err (& priv -> pci_dev -> dev ,
850- "I2C block read is unsupported!\n" );
851- return - EOPNOTSUPP ;
852- }
853- break ;
854- case I2C_SMBUS_BLOCK_PROC_CALL :
816+ if (command == I2C_SMBUS_BLOCK_PROC_CALL )
855817 /* Needs to be flagged as write transaction */
856818 i801_set_hstadd (priv , addr , I2C_SMBUS_WRITE );
819+ else
820+ i801_set_hstadd (priv , addr , read_write );
821+ outb_p (hstcmd , SMBHSTCMD (priv ));
822+
823+ if (priv -> features & FEATURE_BLOCK_BUFFER )
824+ return i801_block_transaction_by_block (priv , data , read_write , command );
825+ else
826+ return i801_block_transaction_byte_by_byte (priv , data , read_write , command );
827+ }
828+
829+ static int i801_i2c_block_transaction (struct i801_priv * priv , union i2c_smbus_data * data ,
830+ u8 addr , u8 hstcmd , char read_write , int command )
831+ {
832+ int result ;
833+ u8 hostc ;
834+
835+ if (data -> block [0 ] < 1 || data -> block [0 ] > I2C_SMBUS_BLOCK_MAX )
836+ return - EPROTO ;
837+ /*
838+ * NB: page 240 of ICH5 datasheet shows that the R/#W bit should be cleared here,
839+ * even when reading. However if SPD Write Disable is set (Lynx Point and later),
840+ * the read will fail if we don't set the R/#W bit.
841+ */
842+ i801_set_hstadd (priv , addr ,
843+ priv -> original_hstcfg & SMBHSTCFG_SPD_WD ? read_write : I2C_SMBUS_WRITE );
844+
845+ /* NB: page 240 of ICH5 datasheet shows that DATA1 is the cmd field when reading */
846+ if (read_write == I2C_SMBUS_READ )
847+ outb_p (hstcmd , SMBHSTDAT1 (priv ));
848+ else
857849 outb_p (hstcmd , SMBHSTCMD (priv ));
858- break ;
850+
851+ if (read_write == I2C_SMBUS_WRITE ) {
852+ /* set I2C_EN bit in configuration register */
853+ pci_read_config_byte (priv -> pci_dev , SMBHSTCFG , & hostc );
854+ pci_write_config_byte (priv -> pci_dev , SMBHSTCFG , hostc | SMBHSTCFG_I2C_EN );
855+ } else if (!(priv -> features & FEATURE_I2C_BLOCK_READ )) {
856+ pci_err (priv -> pci_dev , "I2C block read is unsupported!\n" );
857+ return - EOPNOTSUPP ;
859858 }
860859
861- /* Experience has shown that the block buffer can only be used for
862- SMBus (not I2C) block transactions, even though the datasheet
863- doesn't mention this limitation. */
864- if ((priv -> features & FEATURE_BLOCK_BUFFER ) &&
865- command != I2C_SMBUS_I2C_BLOCK_DATA )
866- result = i801_block_transaction_by_block (priv , data ,
867- read_write ,
868- command );
869- else
870- result = i801_block_transaction_byte_by_byte (priv , data ,
871- read_write ,
872- command );
860+ /* Block buffer isn't supported for I2C block transactions */
861+ result = i801_block_transaction_byte_by_byte (priv , data , read_write , command );
873862
874- if (command == I2C_SMBUS_I2C_BLOCK_DATA
875- && read_write == I2C_SMBUS_WRITE ) {
876- /* restore saved configuration register value */
863+ /* restore saved configuration register value */
864+ if (read_write == I2C_SMBUS_WRITE )
877865 pci_write_config_byte (priv -> pci_dev , SMBHSTCFG , hostc );
878- }
866+
879867 return result ;
880868}
881869
@@ -906,10 +894,10 @@ static s32 i801_access(struct i2c_adapter *adap, u16 addr,
906894 outb_p (inb_p (SMBAUXCTL (priv )) & (~SMBAUXCTL_CRC ),
907895 SMBAUXCTL (priv ));
908896
909- if (size == I2C_SMBUS_BLOCK_DATA ||
910- size == I2C_SMBUS_I2C_BLOCK_DATA ||
911- size == I2C_SMBUS_BLOCK_PROC_CALL )
912- ret = i801_block_transaction (priv , data , addr , command , read_write , size );
897+ if (size == I2C_SMBUS_BLOCK_DATA || size == I2C_SMBUS_BLOCK_PROC_CALL )
898+ ret = i801_smbus_block_transaction ( priv , data , addr , command , read_write , size );
899+ else if ( size == I2C_SMBUS_I2C_BLOCK_DATA )
900+ ret = i801_i2c_block_transaction (priv , data , addr , command , read_write , size );
913901 else
914902 ret = i801_simple_transaction (priv , data , addr , command , read_write , size );
915903
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