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x86/mce/therm_throt: Mask out read-only and reserved MSR bits
jira LE-3201 Rebuild_History Non-Buildable kernel-rt-4.18.0-553.22.1.rt7.363.el8_10 commit-author Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> commit 5a43b87 Empty-Commit: Cherry-Pick Conflicts during history rebuild. Will be included in final tarball splat. Ref for failed cherry-pick at: ciq/ciq_backports/kernel-rt-4.18.0-553.22.1.rt7.363.el8_10/5a43b87b.failed While writing to MSR IA32_THERM_STATUS/IA32_PKG_THERM_STATUS, avoid writing 1 to read only and reserved fields because updating some fields generates exception. [ bp: Vertically align for better readability. ] Fixes: f665620 ("x86/mce/therm_throt: Optimize notifications of thermal throttle") Reported-by: Dominik Brodowski <linux@dominikbrodowski.net> Tested-by: Dominik Brodowski <linux@dominikbrodowski.net> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: x86-ml <x86@kernel.org> Link: https://lkml.kernel.org/r/20191128150824.22413-1-srinivas.pandruvada@linux.intel.com (cherry picked from commit 5a43b87) Signed-off-by: Jonathan Maple <jmaple@ciq.com> # Conflicts: # drivers/thermal/intel/therm_throt.c
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‎ciq/ciq_backports/kernel-rt-4.18.0-553.22.1.rt7.363.el8_10/5a43b87b.failed‎

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x86/mce/therm_throt: Mask out read-only and reserved MSR bits
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jira LE-3201
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Rebuild_History Non-Buildable kernel-rt-4.18.0-553.22.1.rt7.363.el8_10
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commit-author Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
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commit 5a43b87b3c62ad149ba6e9d0d3e5c0e5da02a5ca
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Empty-Commit: Cherry-Pick Conflicts during history rebuild.
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Will be included in final tarball splat. Ref for failed cherry-pick at:
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ciq/ciq_backports/kernel-rt-4.18.0-553.22.1.rt7.363.el8_10/5a43b87b.failed
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While writing to MSR IA32_THERM_STATUS/IA32_PKG_THERM_STATUS, avoid
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writing 1 to read only and reserved fields because updating some fields
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generates exception.
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[ bp: Vertically align for better readability. ]
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Fixes: f6656208f04e ("x86/mce/therm_throt: Optimize notifications of thermal throttle")
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Reported-by: Dominik Brodowski <linux@dominikbrodowski.net>
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Tested-by: Dominik Brodowski <linux@dominikbrodowski.net>
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Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
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Signed-off-by: Borislav Petkov <bp@suse.de>
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Cc: "H. Peter Anvin" <hpa@zytor.com>
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Cc: Ingo Molnar <mingo@redhat.com>
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Cc: linux-edac <linux-edac@vger.kernel.org>
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Cc: Thomas Gleixner <tglx@linutronix.de>
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Cc: Tony Luck <tony.luck@intel.com>
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Cc: x86-ml <x86@kernel.org>
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Link: https://lkml.kernel.org/r/20191128150824.22413-1-srinivas.pandruvada@linux.intel.com
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(cherry picked from commit 5a43b87b3c62ad149ba6e9d0d3e5c0e5da02a5ca)
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Signed-off-by: Jonathan Maple <jmaple@ciq.com>
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# Conflicts:
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# drivers/thermal/intel/therm_throt.c
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diff --cc drivers/thermal/intel/therm_throt.c
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index dd55d96efeff,b38010b541d6..000000000000
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--- a/drivers/thermal/intel/therm_throt.c
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+++ b/drivers/thermal/intel/therm_throt.c
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@@@ -134,6 -192,112 +134,115 @@@ static const struct attribute_group the
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#define CORE_LEVEL 0
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#define PACKAGE_LEVEL 1
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++<<<<<<< HEAD:drivers/thermal/intel/therm_throt.c
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++=======
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+ #define THERM_THROT_POLL_INTERVAL HZ
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+ #define THERM_STATUS_PROCHOT_LOG BIT(1)
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+
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+ #define THERM_STATUS_CLEAR_CORE_MASK (BIT(1) | BIT(3) | BIT(5) | BIT(7) | BIT(9) | BIT(11) | BIT(13) | BIT(15))
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+ #define THERM_STATUS_CLEAR_PKG_MASK (BIT(1) | BIT(3) | BIT(5) | BIT(7) | BIT(9) | BIT(11))
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+
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+ static void clear_therm_status_log(int level)
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+ {
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+ int msr;
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+ u64 mask, msr_val;
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+
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+ if (level == CORE_LEVEL) {
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+ msr = MSR_IA32_THERM_STATUS;
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+ mask = THERM_STATUS_CLEAR_CORE_MASK;
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+ } else {
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+ msr = MSR_IA32_PACKAGE_THERM_STATUS;
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+ mask = THERM_STATUS_CLEAR_PKG_MASK;
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+ }
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+
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+ rdmsrl(msr, msr_val);
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+ msr_val &= mask;
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+ wrmsrl(msr, msr_val & ~THERM_STATUS_PROCHOT_LOG);
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+ }
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+
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+ static void get_therm_status(int level, bool *proc_hot, u8 *temp)
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+ {
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+ int msr;
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+ u64 msr_val;
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+
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+ if (level == CORE_LEVEL)
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+ msr = MSR_IA32_THERM_STATUS;
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+ else
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+ msr = MSR_IA32_PACKAGE_THERM_STATUS;
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+
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+ rdmsrl(msr, msr_val);
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+ if (msr_val & THERM_STATUS_PROCHOT_LOG)
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+ *proc_hot = true;
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+ else
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+ *proc_hot = false;
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+
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+ *temp = (msr_val >> 16) & 0x7F;
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+ }
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+
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+ static void throttle_active_work(struct work_struct *work)
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+ {
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+ struct _thermal_state *state = container_of(to_delayed_work(work),
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+ struct _thermal_state, therm_work);
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+ unsigned int i, avg, this_cpu = smp_processor_id();
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+ u64 now = get_jiffies_64();
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+ bool hot;
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+ u8 temp;
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+
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+ get_therm_status(state->level, &hot, &temp);
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+ /* temperature value is offset from the max so lesser means hotter */
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+ if (!hot && temp > state->baseline_temp) {
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+ if (state->rate_control_active)
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+ pr_info("CPU%d: %s temperature/speed normal (total events = %lu)\n",
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+ this_cpu,
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+ state->level == CORE_LEVEL ? "Core" : "Package",
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+ state->count);
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+
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+ state->rate_control_active = false;
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+ return;
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+ }
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+
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+ if (time_before64(now, state->next_check) &&
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+ state->rate_control_active)
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+ goto re_arm;
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+
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+ state->next_check = now + CHECK_INTERVAL;
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+
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+ if (state->count != state->last_count) {
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+ /* There was one new thermal interrupt */
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+ state->last_count = state->count;
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+ state->average = 0;
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+ state->sample_count = 0;
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+ state->sample_index = 0;
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+ }
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+
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+ state->temp_samples[state->sample_index] = temp;
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+ state->sample_count++;
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+ state->sample_index = (state->sample_index + 1) % ARRAY_SIZE(state->temp_samples);
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+ if (state->sample_count < ARRAY_SIZE(state->temp_samples))
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+ goto re_arm;
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+
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+ avg = 0;
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+ for (i = 0; i < ARRAY_SIZE(state->temp_samples); ++i)
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+ avg += state->temp_samples[i];
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+
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+ avg /= ARRAY_SIZE(state->temp_samples);
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+
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+ if (state->average > avg) {
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+ pr_warn("CPU%d: %s temperature is above threshold, cpu clock is throttled (total events = %lu)\n",
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+ this_cpu,
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+ state->level == CORE_LEVEL ? "Core" : "Package",
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+ state->count);
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+ state->rate_control_active = true;
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+ }
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+
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+ state->average = avg;
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+
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+ re_arm:
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+ clear_therm_status_log(state->level);
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+ schedule_delayed_work_on(this_cpu, &state->therm_work, THERM_THROT_POLL_INTERVAL);
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+ }
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+
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++>>>>>>> 5a43b87b3c62 (x86/mce/therm_throt: Mask out read-only and reserved MSR bits):arch/x86/kernel/cpu/mce/therm_throt.c
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/***
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* therm_throt_process - Process thermal throttling event from interrupt
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* @curr: Whether the condition is current or not (boolean), since the
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* Unmerged path drivers/thermal/intel/therm_throt.c

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