Skip to content

Commit 3328d17

Browse files
Marc Zyngieroupton
Marc Zyngier
authored and
oupton
committed
KVM: arm64: Remove __vcpu_{read,write}_sys_reg_{from,to}_cpu()
There is no point having __vcpu_{read,write}_sys_reg_{from,to}_cpu() exposed to the rest of the kernel, as the only callers are in sys_regs.c. Move them where they below, which is another opportunity to simplify things a bit. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20250817121926.217900-5-maz@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
1 parent ec0ab05 commit 3328d17

File tree

2 files changed

+80
-111
lines changed

2 files changed

+80
-111
lines changed

‎arch/arm64/include/asm/kvm_host.h‎

Lines changed: 0 additions & 107 deletions
Original file line numberDiff line numberDiff line change
@@ -1161,113 +1161,6 @@ u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u64);
11611161
u64 vcpu_read_sys_reg(const struct kvm_vcpu *, enum vcpu_sysreg);
11621162
void vcpu_write_sys_reg(struct kvm_vcpu *, u64, enum vcpu_sysreg);
11631163

1164-
static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
1165-
{
1166-
/*
1167-
* *** VHE ONLY ***
1168-
*
1169-
* System registers listed in the switch are not saved on every
1170-
* exit from the guest but are only saved on vcpu_put.
1171-
*
1172-
* SYSREGS_ON_CPU *MUST* be checked before using this helper.
1173-
*
1174-
* Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
1175-
* should never be listed below, because the guest cannot modify its
1176-
* own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
1177-
* thread when emulating cross-VCPU communication.
1178-
*/
1179-
if (!has_vhe())
1180-
return false;
1181-
1182-
switch (reg) {
1183-
case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break;
1184-
case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break;
1185-
case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break;
1186-
case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break;
1187-
case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break;
1188-
case TCR2_EL1: *val = read_sysreg_s(SYS_TCR2_EL12); break;
1189-
case PIR_EL1: *val = read_sysreg_s(SYS_PIR_EL12); break;
1190-
case PIRE0_EL1: *val = read_sysreg_s(SYS_PIRE0_EL12); break;
1191-
case POR_EL1: *val = read_sysreg_s(SYS_POR_EL12); break;
1192-
case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break;
1193-
case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break;
1194-
case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break;
1195-
case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break;
1196-
case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break;
1197-
case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break;
1198-
case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
1199-
case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break;
1200-
case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
1201-
case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break;
1202-
case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break;
1203-
case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
1204-
case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break;
1205-
case SPSR_EL1: *val = read_sysreg_s(SYS_SPSR_EL12); break;
1206-
case PAR_EL1: *val = read_sysreg_par(); break;
1207-
case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break;
1208-
case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break;
1209-
case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
1210-
case ZCR_EL1: *val = read_sysreg_s(SYS_ZCR_EL12); break;
1211-
case SCTLR2_EL1: *val = read_sysreg_s(SYS_SCTLR2_EL12); break;
1212-
default: return false;
1213-
}
1214-
1215-
return true;
1216-
}
1217-
1218-
static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
1219-
{
1220-
/*
1221-
* *** VHE ONLY ***
1222-
*
1223-
* System registers listed in the switch are not restored on every
1224-
* entry to the guest but are only restored on vcpu_load.
1225-
*
1226-
* SYSREGS_ON_CPU *MUST* be checked before using this helper.
1227-
*
1228-
* Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
1229-
* should never be listed below, because the MPIDR should only be set
1230-
* once, before running the VCPU, and never changed later.
1231-
*/
1232-
if (!has_vhe())
1233-
return false;
1234-
1235-
switch (reg) {
1236-
case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
1237-
case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
1238-
case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
1239-
case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
1240-
case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
1241-
case TCR2_EL1: write_sysreg_s(val, SYS_TCR2_EL12); break;
1242-
case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break;
1243-
case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break;
1244-
case POR_EL1: write_sysreg_s(val, SYS_POR_EL12); break;
1245-
case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
1246-
case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
1247-
case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
1248-
case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
1249-
case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
1250-
case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
1251-
case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
1252-
case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
1253-
case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
1254-
case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
1255-
case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
1256-
case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
1257-
case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
1258-
case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break;
1259-
case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
1260-
case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
1261-
case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
1262-
case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
1263-
case ZCR_EL1: write_sysreg_s(val, SYS_ZCR_EL12); break;
1264-
case SCTLR2_EL1: write_sysreg_s(val, SYS_SCTLR2_EL12); break;
1265-
default: return false;
1266-
}
1267-
1268-
return true;
1269-
}
1270-
12711164
struct kvm_vm_stat {
12721165
struct kvm_vm_stat_generic generic;
12731166
};

‎arch/arm64/kvm/sys_regs.c‎

Lines changed: 80 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -216,6 +216,82 @@ static void locate_register(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg,
216216
}
217217
}
218218

219+
static u64 read_sr_from_cpu(enum vcpu_sysreg reg)
220+
{
221+
u64 val = 0x8badf00d8badf00d;
222+
223+
switch (reg) {
224+
case SCTLR_EL1: val = read_sysreg_s(SYS_SCTLR_EL12); break;
225+
case CPACR_EL1: val = read_sysreg_s(SYS_CPACR_EL12); break;
226+
case TTBR0_EL1: val = read_sysreg_s(SYS_TTBR0_EL12); break;
227+
case TTBR1_EL1: val = read_sysreg_s(SYS_TTBR1_EL12); break;
228+
case TCR_EL1: val = read_sysreg_s(SYS_TCR_EL12); break;
229+
case TCR2_EL1: val = read_sysreg_s(SYS_TCR2_EL12); break;
230+
case PIR_EL1: val = read_sysreg_s(SYS_PIR_EL12); break;
231+
case PIRE0_EL1: val = read_sysreg_s(SYS_PIRE0_EL12); break;
232+
case POR_EL1: val = read_sysreg_s(SYS_POR_EL12); break;
233+
case ESR_EL1: val = read_sysreg_s(SYS_ESR_EL12); break;
234+
case AFSR0_EL1: val = read_sysreg_s(SYS_AFSR0_EL12); break;
235+
case AFSR1_EL1: val = read_sysreg_s(SYS_AFSR1_EL12); break;
236+
case FAR_EL1: val = read_sysreg_s(SYS_FAR_EL12); break;
237+
case MAIR_EL1: val = read_sysreg_s(SYS_MAIR_EL12); break;
238+
case VBAR_EL1: val = read_sysreg_s(SYS_VBAR_EL12); break;
239+
case CONTEXTIDR_EL1: val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
240+
case AMAIR_EL1: val = read_sysreg_s(SYS_AMAIR_EL12); break;
241+
case CNTKCTL_EL1: val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
242+
case ELR_EL1: val = read_sysreg_s(SYS_ELR_EL12); break;
243+
case SPSR_EL1: val = read_sysreg_s(SYS_SPSR_EL12); break;
244+
case ZCR_EL1: val = read_sysreg_s(SYS_ZCR_EL12); break;
245+
case SCTLR2_EL1: val = read_sysreg_s(SYS_SCTLR2_EL12); break;
246+
case TPIDR_EL0: val = read_sysreg_s(SYS_TPIDR_EL0); break;
247+
case TPIDRRO_EL0: val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
248+
case TPIDR_EL1: val = read_sysreg_s(SYS_TPIDR_EL1); break;
249+
case PAR_EL1: val = read_sysreg_par(); break;
250+
case DACR32_EL2: val = read_sysreg_s(SYS_DACR32_EL2); break;
251+
case IFSR32_EL2: val = read_sysreg_s(SYS_IFSR32_EL2); break;
252+
case DBGVCR32_EL2: val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
253+
default: WARN_ON_ONCE(1);
254+
}
255+
256+
return val;
257+
}
258+
259+
static void write_sr_to_cpu(enum vcpu_sysreg reg, u64 val)
260+
{
261+
switch (reg) {
262+
case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
263+
case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
264+
case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
265+
case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
266+
case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
267+
case TCR2_EL1: write_sysreg_s(val, SYS_TCR2_EL12); break;
268+
case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break;
269+
case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break;
270+
case POR_EL1: write_sysreg_s(val, SYS_POR_EL12); break;
271+
case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
272+
case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
273+
case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
274+
case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
275+
case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
276+
case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
277+
case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
278+
case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
279+
case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
280+
case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
281+
case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break;
282+
case ZCR_EL1: write_sysreg_s(val, SYS_ZCR_EL12); break;
283+
case SCTLR2_EL1: write_sysreg_s(val, SYS_SCTLR2_EL12); break;
284+
case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
285+
case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
286+
case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
287+
case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
288+
case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
289+
case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
290+
case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
291+
default: WARN_ON_ONCE(1);
292+
}
293+
}
294+
219295
u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg)
220296
{
221297
struct sr_loc loc = {};
@@ -246,13 +322,13 @@ u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg)
246322

247323
if (loc.loc & SR_LOC_LOADED) {
248324
enum vcpu_sysreg map_reg = reg;
249-
u64 val = 0x8badf00d8badf00d;
250325

251326
if (loc.loc & SR_LOC_MAPPED)
252327
map_reg = loc.map_reg;
253328

254-
if (!(loc.loc & SR_LOC_XLATED) &&
255-
__vcpu_read_sys_reg_from_cpu(map_reg, &val)) {
329+
if (!(loc.loc & SR_LOC_XLATED)) {
330+
u64 val = read_sr_from_cpu(map_reg);
331+
256332
if (reg >= __SANITISED_REG_START__)
257333
val = kvm_vcpu_apply_reg_masks(vcpu, reg, val);
258334

@@ -304,7 +380,7 @@ void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, enum vcpu_sysreg reg)
304380
else
305381
xlated_val = val;
306382

307-
__vcpu_write_sys_reg_to_cpu(xlated_val, map_reg);
383+
write_sr_to_cpu(map_reg, xlated_val);
308384

309385
/*
310386
* Fall through to write the backing store anyway, which

0 commit comments

Comments
 (0)