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Khairul Anuar Romlibroonie
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spi: cadence-qspi: defer runtime support on socfpga if reset bit is enabled
Enabling runtime PM allows the kernel to gate clocks and power to idle devices. On SoCFPGA, a warm reset does not fully reinitialize these domains.This leaves devices suspended and powered down, preventing U-Boot or the kernel from reusing them after a warm reset, which breaks the boot process. Fixes: 4892b37 ("mtd: spi-nor: cadence-quadspi: Add runtime PM support") CC: stable@vger.kernel.org # 6.12+ Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com> Reviewed-by: Niravkumar L Rabara <nirav.rabara@altera.com> Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com> Link: https://patch.msgid.link/910aad68ba5d948919a7b90fa85a2fadb687229b.1757491372.git.khairul.anuar.romli@altera.com Signed-off-by: Mark Brown <broonie@kernel.org>
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drivers/spi/spi-cadence-quadspi.c

Lines changed: 36 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_CS_CNT_MAX);
4646
#define CQSPI_DMA_SET_MASK BIT(7)
4747
#define CQSPI_SUPPORT_DEVICE_RESET BIT(8)
4848
#define CQSPI_DISABLE_STIG_MODE BIT(9)
49+
#define CQSPI_DISABLE_RUNTIME_PM BIT(10)
4950

5051
/* Capabilities */
5152
#define CQSPI_SUPPORTS_OCTAL BIT(0)
@@ -1468,14 +1469,17 @@ static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
14681469
int ret;
14691470
struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);
14701471
struct device *dev = &cqspi->pdev->dev;
1472+
const struct cqspi_driver_platdata *ddata = of_device_get_match_data(dev);
14711473

14721474
if (refcount_read(&cqspi->inflight_ops) == 0)
14731475
return -ENODEV;
14741476

1475-
ret = pm_runtime_resume_and_get(dev);
1476-
if (ret) {
1477-
dev_err(&mem->spi->dev, "resume failed with %d\n", ret);
1478-
return ret;
1477+
if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) {
1478+
ret = pm_runtime_resume_and_get(dev);
1479+
if (ret) {
1480+
dev_err(&mem->spi->dev, "resume failed with %d\n", ret);
1481+
return ret;
1482+
}
14791483
}
14801484

14811485
if (!refcount_read(&cqspi->refcount))
@@ -1491,7 +1495,8 @@ static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
14911495

14921496
ret = cqspi_mem_process(mem, op);
14931497

1494-
pm_runtime_put_autosuspend(dev);
1498+
if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM)))
1499+
pm_runtime_put_autosuspend(dev);
14951500

14961501
if (ret)
14971502
dev_err(&mem->spi->dev, "operation failed with %d\n", ret);
@@ -1985,24 +1990,30 @@ static int cqspi_probe(struct platform_device *pdev)
19851990
goto probe_setup_failed;
19861991
}
19871992

1988-
pm_runtime_enable(dev);
1989-
1990-
pm_runtime_set_autosuspend_delay(dev, CQSPI_AUTOSUSPEND_TIMEOUT);
1991-
pm_runtime_use_autosuspend(dev);
1992-
pm_runtime_get_noresume(dev);
1993+
if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) {
1994+
pm_runtime_enable(dev);
1995+
pm_runtime_set_autosuspend_delay(dev, CQSPI_AUTOSUSPEND_TIMEOUT);
1996+
pm_runtime_use_autosuspend(dev);
1997+
pm_runtime_get_noresume(dev);
1998+
}
19931999

19942000
ret = spi_register_controller(host);
19952001
if (ret) {
19962002
dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
19972003
goto probe_setup_failed;
19982004
}
19992005

2000-
pm_runtime_put_autosuspend(dev);
2006+
if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) {
2007+
pm_runtime_put_autosuspend(dev);
2008+
pm_runtime_mark_last_busy(dev);
2009+
pm_runtime_put_autosuspend(dev);
2010+
}
20012011

20022012
return 0;
20032013
probe_setup_failed:
20042014
cqspi_controller_enable(cqspi, 0);
2005-
pm_runtime_disable(dev);
2015+
if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM)))
2016+
pm_runtime_disable(dev);
20062017
probe_reset_failed:
20072018
if (cqspi->is_jh7110)
20082019
cqspi_jh7110_disable_clk(pdev, cqspi);
@@ -2013,7 +2024,11 @@ static int cqspi_probe(struct platform_device *pdev)
20132024

20142025
static void cqspi_remove(struct platform_device *pdev)
20152026
{
2027+
const struct cqspi_driver_platdata *ddata;
20162028
struct cqspi_st *cqspi = platform_get_drvdata(pdev);
2029+
struct device *dev = &pdev->dev;
2030+
2031+
ddata = of_device_get_match_data(dev);
20172032

20182033
refcount_set(&cqspi->refcount, 0);
20192034

@@ -2026,14 +2041,17 @@ static void cqspi_remove(struct platform_device *pdev)
20262041
if (cqspi->rx_chan)
20272042
dma_release_channel(cqspi->rx_chan);
20282043

2029-
if (pm_runtime_get_sync(&pdev->dev) >= 0)
2030-
clk_disable(cqspi->clk);
2044+
if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM)))
2045+
if (pm_runtime_get_sync(&pdev->dev) >= 0)
2046+
clk_disable(cqspi->clk);
20312047

20322048
if (cqspi->is_jh7110)
20332049
cqspi_jh7110_disable_clk(pdev, cqspi);
20342050

2035-
pm_runtime_put_sync(&pdev->dev);
2036-
pm_runtime_disable(&pdev->dev);
2051+
if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) {
2052+
pm_runtime_put_sync(&pdev->dev);
2053+
pm_runtime_disable(&pdev->dev);
2054+
}
20372055
}
20382056

20392057
static int cqspi_runtime_suspend(struct device *dev)
@@ -2112,7 +2130,8 @@ static const struct cqspi_driver_platdata socfpga_qspi = {
21122130
.quirks = CQSPI_DISABLE_DAC_MODE
21132131
| CQSPI_NO_SUPPORT_WR_COMPLETION
21142132
| CQSPI_SLOW_SRAM
2115-
| CQSPI_DISABLE_STIG_MODE,
2133+
| CQSPI_DISABLE_STIG_MODE
2134+
| CQSPI_DISABLE_RUNTIME_PM,
21162135
};
21172136

21182137
static const struct cqspi_driver_platdata versal_ospi = {

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