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platform/x86/intel/pmc: Remove unnecessary declarations in header
JIRA: https://issues.redhat.com/browse/RHEL-47465 commit 9eeeb2a Author: Xi Pardee <xi.pardee@linux.intel.com> Date: Fri Feb 14 13:44:10 2025 -0800 platform/x86/intel/pmc: Remove unnecessary declarations in header Remove unnecessary declarations in header file. Variable that are used by only one .c file are removed from header file and changed to be static in their corresponding .c file. Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com> Link: https://lore.kernel.org/r/20250214214416.10150-3-xi.pardee@linux.intel.com Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Steve Best <sbest@redhat.com>
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9 files changed

+122
-248
lines changed

9 files changed

+122
-248
lines changed

‎drivers/platform/x86/intel/pmc/adl.c‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
#include "core.h"
1212

1313
/* Alder Lake: PGD PFET Enable Ack Status Register(s) bitmap */
14-
const struct pmc_bit_map adl_pfear_map[] = {
14+
static const struct pmc_bit_map adl_pfear_map[] = {
1515
{"SPI/eSPI", BIT(2)},
1616
{"XHCI", BIT(3)},
1717
{"SPA", BIT(4)},
@@ -54,7 +54,7 @@ const struct pmc_bit_map adl_pfear_map[] = {
5454
{}
5555
};
5656

57-
const struct pmc_bit_map *ext_adl_pfear_map[] = {
57+
static const struct pmc_bit_map *ext_adl_pfear_map[] = {
5858
/*
5959
* Check intel_pmc_core_ids[] users of cnp_reg_map for
6060
* a list of core SoCs using this.
@@ -63,7 +63,7 @@ const struct pmc_bit_map *ext_adl_pfear_map[] = {
6363
NULL
6464
};
6565

66-
const struct pmc_bit_map adl_ltr_show_map[] = {
66+
static const struct pmc_bit_map adl_ltr_show_map[] = {
6767
{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
6868
{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
6969
{"SATA", CNP_PMC_LTR_SATA},
@@ -100,7 +100,7 @@ const struct pmc_bit_map adl_ltr_show_map[] = {
100100
{}
101101
};
102102

103-
const struct pmc_bit_map adl_clocksource_status_map[] = {
103+
static const struct pmc_bit_map adl_clocksource_status_map[] = {
104104
{"CLKPART1_OFF_STS", BIT(0)},
105105
{"CLKPART2_OFF_STS", BIT(1)},
106106
{"CLKPART3_OFF_STS", BIT(2)},
@@ -128,7 +128,7 @@ const struct pmc_bit_map adl_clocksource_status_map[] = {
128128
{}
129129
};
130130

131-
const struct pmc_bit_map adl_power_gating_status_0_map[] = {
131+
static const struct pmc_bit_map adl_power_gating_status_0_map[] = {
132132
{"PMC_PGD0_PG_STS", BIT(0)},
133133
{"DMI_PGD0_PG_STS", BIT(1)},
134134
{"ESPISPI_PGD0_PG_STS", BIT(2)},
@@ -158,7 +158,7 @@ const struct pmc_bit_map adl_power_gating_status_0_map[] = {
158158
{}
159159
};
160160

161-
const struct pmc_bit_map adl_power_gating_status_1_map[] = {
161+
static const struct pmc_bit_map adl_power_gating_status_1_map[] = {
162162
{"USBR0_PGD0_PG_STS", BIT(0)},
163163
{"SMT1_PGD0_PG_STS", BIT(2)},
164164
{"CSMERTC_PGD0_PG_STS", BIT(6)},
@@ -170,14 +170,14 @@ const struct pmc_bit_map adl_power_gating_status_1_map[] = {
170170
{}
171171
};
172172

173-
const struct pmc_bit_map adl_power_gating_status_2_map[] = {
173+
static const struct pmc_bit_map adl_power_gating_status_2_map[] = {
174174
{"THC0_PGD0_PG_STS", BIT(7)},
175175
{"THC1_PGD0_PG_STS", BIT(8)},
176176
{"SPF_PGD0_PG_STS", BIT(14)},
177177
{}
178178
};
179179

180-
const struct pmc_bit_map adl_d3_status_0_map[] = {
180+
static const struct pmc_bit_map adl_d3_status_0_map[] = {
181181
{"ISH_D3_STS", BIT(2)},
182182
{"LPSS_D3_STS", BIT(3)},
183183
{"XDCI_D3_STS", BIT(4)},
@@ -193,13 +193,13 @@ const struct pmc_bit_map adl_d3_status_0_map[] = {
193193
{}
194194
};
195195

196-
const struct pmc_bit_map adl_d3_status_1_map[] = {
196+
static const struct pmc_bit_map adl_d3_status_1_map[] = {
197197
{"GBE_D3_STS", BIT(19)},
198198
{"CNVI_D3_STS", BIT(27)},
199199
{}
200200
};
201201

202-
const struct pmc_bit_map adl_d3_status_2_map[] = {
202+
static const struct pmc_bit_map adl_d3_status_2_map[] = {
203203
{"CSMERTC_D3_STS", BIT(1)},
204204
{"CSE_D3_STS", BIT(4)},
205205
{"KVMCC_D3_STS", BIT(5)},
@@ -210,20 +210,20 @@ const struct pmc_bit_map adl_d3_status_2_map[] = {
210210
{}
211211
};
212212

213-
const struct pmc_bit_map adl_d3_status_3_map[] = {
213+
static const struct pmc_bit_map adl_d3_status_3_map[] = {
214214
{"THC0_D3_STS", BIT(14)},
215215
{"THC1_D3_STS", BIT(15)},
216216
{}
217217
};
218218

219-
const struct pmc_bit_map adl_vnn_req_status_0_map[] = {
219+
static const struct pmc_bit_map adl_vnn_req_status_0_map[] = {
220220
{"ISH_VNN_REQ_STS", BIT(2)},
221221
{"ESPISPI_VNN_REQ_STS", BIT(18)},
222222
{"DSP_VNN_REQ_STS", BIT(19)},
223223
{}
224224
};
225225

226-
const struct pmc_bit_map adl_vnn_req_status_1_map[] = {
226+
static const struct pmc_bit_map adl_vnn_req_status_1_map[] = {
227227
{"NPK_VNN_REQ_STS", BIT(4)},
228228
{"EXI_VNN_REQ_STS", BIT(9)},
229229
{"GBE_VNN_REQ_STS", BIT(19)},
@@ -232,7 +232,7 @@ const struct pmc_bit_map adl_vnn_req_status_1_map[] = {
232232
{}
233233
};
234234

235-
const struct pmc_bit_map adl_vnn_req_status_2_map[] = {
235+
static const struct pmc_bit_map adl_vnn_req_status_2_map[] = {
236236
{"CSMERTC_VNN_REQ_STS", BIT(1)},
237237
{"CSE_VNN_REQ_STS", BIT(4)},
238238
{"SMT1_VNN_REQ_STS", BIT(8)},
@@ -245,12 +245,12 @@ const struct pmc_bit_map adl_vnn_req_status_2_map[] = {
245245
{}
246246
};
247247

248-
const struct pmc_bit_map adl_vnn_req_status_3_map[] = {
248+
static const struct pmc_bit_map adl_vnn_req_status_3_map[] = {
249249
{"GPIOCOM5_VNN_REQ_STS", BIT(11)},
250250
{}
251251
};
252252

253-
const struct pmc_bit_map adl_vnn_misc_status_map[] = {
253+
static const struct pmc_bit_map adl_vnn_misc_status_map[] = {
254254
{"CPU_C10_REQ_STS", BIT(0)},
255255
{"PCIe_LPM_En_REQ_STS", BIT(3)},
256256
{"ITH_REQ_STS", BIT(5)},
@@ -265,7 +265,7 @@ const struct pmc_bit_map adl_vnn_misc_status_map[] = {
265265
{}
266266
};
267267

268-
const struct pmc_bit_map *adl_lpm_maps[] = {
268+
static const struct pmc_bit_map *adl_lpm_maps[] = {
269269
adl_clocksource_status_map,
270270
adl_power_gating_status_0_map,
271271
adl_power_gating_status_1_map,

‎drivers/platform/x86/intel/pmc/arl.c‎

Lines changed: 29 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@
2020

2121
static const u8 ARL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};
2222

23-
const struct pmc_bit_map arl_socs_ltr_show_map[] = {
23+
static const struct pmc_bit_map arl_socs_ltr_show_map[] = {
2424
{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
2525
{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
2626
{"SATA", CNP_PMC_LTR_SATA},
@@ -60,7 +60,7 @@ const struct pmc_bit_map arl_socs_ltr_show_map[] = {
6060
{}
6161
};
6262

63-
const struct pmc_bit_map arl_socs_clocksource_status_map[] = {
63+
static const struct pmc_bit_map arl_socs_clocksource_status_map[] = {
6464
{"AON2_OFF_STS", BIT(0)},
6565
{"AON3_OFF_STS", BIT(1)},
6666
{"AON4_OFF_STS", BIT(2)},
@@ -88,7 +88,7 @@ const struct pmc_bit_map arl_socs_clocksource_status_map[] = {
8888
{}
8989
};
9090

91-
const struct pmc_bit_map arl_socs_power_gating_status_0_map[] = {
91+
static const struct pmc_bit_map arl_socs_power_gating_status_0_map[] = {
9292
{"PMC_PGD0_PG_STS", BIT(0)},
9393
{"DMI_PGD0_PG_STS", BIT(1)},
9494
{"ESPISPI_PGD0_PG_STS", BIT(2)},
@@ -124,7 +124,7 @@ const struct pmc_bit_map arl_socs_power_gating_status_0_map[] = {
124124
{}
125125
};
126126

127-
const struct pmc_bit_map arl_socs_power_gating_status_1_map[] = {
127+
static const struct pmc_bit_map arl_socs_power_gating_status_1_map[] = {
128128
{"USBR0_PGD0_PG_STS", BIT(0)},
129129
{"SUSRAM_PGD0_PG_STS", BIT(1)},
130130
{"SMT1_PGD0_PG_STS", BIT(2)},
@@ -160,7 +160,7 @@ const struct pmc_bit_map arl_socs_power_gating_status_1_map[] = {
160160
{}
161161
};
162162

163-
const struct pmc_bit_map arl_socs_power_gating_status_2_map[] = {
163+
static const struct pmc_bit_map arl_socs_power_gating_status_2_map[] = {
164164
{"PSF8_PGD0_PG_STS", BIT(0)},
165165
{"FIA_PGD0_PG_STS", BIT(1)},
166166
{"SOC_D2D_PGD3_PG_STS", BIT(2)},
@@ -188,7 +188,7 @@ const struct pmc_bit_map arl_socs_power_gating_status_2_map[] = {
188188
{}
189189
};
190190

191-
const struct pmc_bit_map arl_socs_d3_status_2_map[] = {
191+
static const struct pmc_bit_map arl_socs_d3_status_2_map[] = {
192192
{"CSMERTC_D3_STS", BIT(1)},
193193
{"SUSRAM_D3_STS", BIT(2)},
194194
{"CSE_D3_STS", BIT(4)},
@@ -207,21 +207,21 @@ const struct pmc_bit_map arl_socs_d3_status_2_map[] = {
207207
{}
208208
};
209209

210-
const struct pmc_bit_map arl_socs_d3_status_3_map[] = {
210+
static const struct pmc_bit_map arl_socs_d3_status_3_map[] = {
211211
{"GBETSN_D3_STS", BIT(13)},
212212
{"THC0_D3_STS", BIT(14)},
213213
{"THC1_D3_STS", BIT(15)},
214214
{"ACE_D3_STS", BIT(23)},
215215
{}
216216
};
217217

218-
const struct pmc_bit_map arl_socs_vnn_req_status_3_map[] = {
218+
static const struct pmc_bit_map arl_socs_vnn_req_status_3_map[] = {
219219
{"DTS0_VNN_REQ_STS", BIT(7)},
220220
{"GPIOCOM5_VNN_REQ_STS", BIT(11)},
221221
{}
222222
};
223223

224-
const struct pmc_bit_map *arl_socs_lpm_maps[] = {
224+
static const struct pmc_bit_map *arl_socs_lpm_maps[] = {
225225
arl_socs_clocksource_status_map,
226226
arl_socs_power_gating_status_0_map,
227227
arl_socs_power_gating_status_1_map,
@@ -239,7 +239,7 @@ const struct pmc_bit_map *arl_socs_lpm_maps[] = {
239239
NULL
240240
};
241241

242-
const struct pmc_bit_map arl_socs_pfear_map[] = {
242+
static const struct pmc_bit_map arl_socs_pfear_map[] = {
243243
{"RSVD64", BIT(0)},
244244
{"RSVD65", BIT(1)},
245245
{"RSVD66", BIT(2)},
@@ -250,13 +250,13 @@ const struct pmc_bit_map arl_socs_pfear_map[] = {
250250
{}
251251
};
252252

253-
const struct pmc_bit_map *ext_arl_socs_pfear_map[] = {
253+
static const struct pmc_bit_map *ext_arl_socs_pfear_map[] = {
254254
mtl_socm_pfear_map,
255255
arl_socs_pfear_map,
256256
NULL
257257
};
258258

259-
const struct pmc_reg_map arl_socs_reg_map = {
259+
static const struct pmc_reg_map arl_socs_reg_map = {
260260
.pfear_sts = ext_arl_socs_pfear_map,
261261
.ppfear_buckets = ARL_SOCS_PPFEAR_NUM_ENTRIES,
262262
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
@@ -284,7 +284,7 @@ const struct pmc_reg_map arl_socs_reg_map = {
284284
.pson_residency_counter_step = TGL_PSON_RES_COUNTER_STEP,
285285
};
286286

287-
const struct pmc_bit_map arl_pchs_ltr_show_map[] = {
287+
static const struct pmc_bit_map arl_pchs_ltr_show_map[] = {
288288
{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
289289
{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
290290
{"SATA", CNP_PMC_LTR_SATA},
@@ -324,7 +324,7 @@ const struct pmc_bit_map arl_pchs_ltr_show_map[] = {
324324
{}
325325
};
326326

327-
const struct pmc_bit_map arl_pchs_clocksource_status_map[] = {
327+
static const struct pmc_bit_map arl_pchs_clocksource_status_map[] = {
328328
{"AON2_OFF_STS", BIT(0)},
329329
{"AON3_OFF_STS", BIT(1)},
330330
{"AON4_OFF_STS", BIT(2)},
@@ -359,7 +359,7 @@ const struct pmc_bit_map arl_pchs_clocksource_status_map[] = {
359359
{}
360360
};
361361

362-
const struct pmc_bit_map arl_pchs_power_gating_status_0_map[] = {
362+
static const struct pmc_bit_map arl_pchs_power_gating_status_0_map[] = {
363363
{"PMC_PGD0_PG_STS", BIT(0)},
364364
{"DMI_PGD0_PG_STS", BIT(1)},
365365
{"ESPISPI_PGD0_PG_STS", BIT(2)},
@@ -395,7 +395,7 @@ const struct pmc_bit_map arl_pchs_power_gating_status_0_map[] = {
395395
{}
396396
};
397397

398-
const struct pmc_bit_map arl_pchs_power_gating_status_1_map[] = {
398+
static const struct pmc_bit_map arl_pchs_power_gating_status_1_map[] = {
399399
{"USBR0_PGD0_PG_STS", BIT(0)},
400400
{"SUSRAM_PGD0_PG_STS", BIT(1)},
401401
{"SMT1_PGD0_PG_STS", BIT(2)},
@@ -431,7 +431,7 @@ const struct pmc_bit_map arl_pchs_power_gating_status_1_map[] = {
431431
{}
432432
};
433433

434-
const struct pmc_bit_map arl_pchs_power_gating_status_2_map[] = {
434+
static const struct pmc_bit_map arl_pchs_power_gating_status_2_map[] = {
435435
{"U3FPW2_PGD0_PG_STS", BIT(0)},
436436
{"FIA_PGD0_PG_STS", BIT(1)},
437437
{"FIACPCB_X_PGD0_PG_STS", BIT(2)},
@@ -458,7 +458,7 @@ const struct pmc_bit_map arl_pchs_power_gating_status_2_map[] = {
458458
{}
459459
};
460460

461-
const struct pmc_bit_map arl_pchs_d3_status_0_map[] = {
461+
static const struct pmc_bit_map arl_pchs_d3_status_0_map[] = {
462462
{"SPF_D3_STS", BIT(0)},
463463
{"LPSS_D3_STS", BIT(3)},
464464
{"XDCI_D3_STS", BIT(4)},
@@ -475,7 +475,7 @@ const struct pmc_bit_map arl_pchs_d3_status_0_map[] = {
475475
{}
476476
};
477477

478-
const struct pmc_bit_map arl_pchs_d3_status_1_map[] = {
478+
static const struct pmc_bit_map arl_pchs_d3_status_1_map[] = {
479479
{"GBETSN1_D3_STS", BIT(14)},
480480
{"GBE_D3_STS", BIT(19)},
481481
{"ITSS_D3_STS", BIT(23)},
@@ -484,7 +484,7 @@ const struct pmc_bit_map arl_pchs_d3_status_1_map[] = {
484484
{}
485485
};
486486

487-
const struct pmc_bit_map arl_pchs_d3_status_2_map[] = {
487+
static const struct pmc_bit_map arl_pchs_d3_status_2_map[] = {
488488
{"CSMERTC_D3_STS", BIT(1)},
489489
{"SUSRAM_D3_STS", BIT(2)},
490490
{"CSE_D3_STS", BIT(4)},
@@ -505,7 +505,7 @@ const struct pmc_bit_map arl_pchs_d3_status_2_map[] = {
505505
{}
506506
};
507507

508-
const struct pmc_bit_map arl_pchs_d3_status_3_map[] = {
508+
static const struct pmc_bit_map arl_pchs_d3_status_3_map[] = {
509509
{"ESE_D3_STS", BIT(3)},
510510
{"GBETSN_D3_STS", BIT(13)},
511511
{"THC0_D3_STS", BIT(14)},
@@ -514,13 +514,13 @@ const struct pmc_bit_map arl_pchs_d3_status_3_map[] = {
514514
{}
515515
};
516516

517-
const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[] = {
517+
static const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[] = {
518518
{"FIA_VNN_REQ_STS", BIT(17)},
519519
{"ESPISPI_VNN_REQ_STS", BIT(18)},
520520
{}
521521
};
522522

523-
const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[] = {
523+
static const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[] = {
524524
{"NPK_VNN_REQ_STS", BIT(4)},
525525
{"DFXAGG_VNN_REQ_STS", BIT(8)},
526526
{"EXI_VNN_REQ_STS", BIT(9)},
@@ -531,7 +531,7 @@ const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[] = {
531531
{}
532532
};
533533

534-
const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[] = {
534+
static const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[] = {
535535
{"FIA2_VNN_REQ_STS", BIT(0)},
536536
{"CSMERTC_VNN_REQ_STS", BIT(1)},
537537
{"CSE_VNN_REQ_STS", BIT(4)},
@@ -549,15 +549,15 @@ const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[] = {
549549
{}
550550
};
551551

552-
const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[] = {
552+
static const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[] = {
553553
{"ESE_VNN_REQ_STS", BIT(3)},
554554
{"DTS0_VNN_REQ_STS", BIT(7)},
555555
{"GPIOCOM5_VNN_REQ_STS", BIT(11)},
556556
{"FIA1_VNN_REQ_STS", BIT(12)},
557557
{}
558558
};
559559

560-
const struct pmc_bit_map arl_pchs_vnn_misc_status_map[] = {
560+
static const struct pmc_bit_map arl_pchs_vnn_misc_status_map[] = {
561561
{"CPU_C10_REQ_STS", BIT(0)},
562562
{"TS_OFF_REQ_STS", BIT(1)},
563563
{"PNDE_MET_REQ_STS", BIT(2)},
@@ -587,7 +587,7 @@ const struct pmc_bit_map arl_pchs_vnn_misc_status_map[] = {
587587
{}
588588
};
589589

590-
const struct pmc_bit_map arl_pchs_signal_status_map[] = {
590+
static const struct pmc_bit_map arl_pchs_signal_status_map[] = {
591591
{"LSX_Wake0_STS", BIT(0)},
592592
{"LSX_Wake1_STS", BIT(1)},
593593
{"LSX_Wake2_STS", BIT(2)},
@@ -607,7 +607,7 @@ const struct pmc_bit_map arl_pchs_signal_status_map[] = {
607607
{}
608608
};
609609

610-
const struct pmc_bit_map *arl_pchs_lpm_maps[] = {
610+
static const struct pmc_bit_map *arl_pchs_lpm_maps[] = {
611611
arl_pchs_clocksource_status_map,
612612
arl_pchs_power_gating_status_0_map,
613613
arl_pchs_power_gating_status_1_map,
@@ -625,7 +625,7 @@ const struct pmc_bit_map *arl_pchs_lpm_maps[] = {
625625
NULL
626626
};
627627

628-
const struct pmc_reg_map arl_pchs_reg_map = {
628+
static const struct pmc_reg_map arl_pchs_reg_map = {
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.pfear_sts = ext_arl_socs_pfear_map,
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.ppfear_buckets = ARL_SOCS_PPFEAR_NUM_ENTRIES,
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.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,

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