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Mamatha Inamdar
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tools/perf/pmu-events/powerpc: Add support for compat events in json
JIRA: https://issues.redhat.com/browse/RHEL-75636 commit 86f45d0 Author: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Date: Thu Oct 10 20:21:06 2024 +0530 tools/perf/pmu-events/powerpc: Add support for compat events in json perf list picks the events supported for specific platform from pmu-events/arch/powerpc/<platform>. Example power10 events are in pmu-events/arch/powerpc/power10, power9 events are part of pmu-events/arch/powerpc/power9. The decision of which platform to pick is determined based on PVR value in powerpc. The PVR value is matched from pmu-events/arch/powerpc/mapfile.csv Example: Format: PVR,Version,JSON/file/pathname,Type 0x004[bcd][[:xdigit:]]{4},1,power8,core 0x0066[[:xdigit:]]{4},1,power8,core 0x004e[[:xdigit:]]{4},1,power9,core 0x0080[[:xdigit:]]{4},1,power10,core 0x0082[[:xdigit:]]{4},1,power10,core The code gets the PVR from system using get_cpuid_str function in arch/powerpc/util/headers.c ( from SPRN_PVR ) and compares with value from mapfile.csv In case of compat mode, say when partition is booted in a power9 mode when the system is a power10, add an entry to pick the ISA architected events from "pmu-events/arch/powerpc/compat". Add json file generic-events.json which will contain these events which is supported in compat mode. Suggested-by: Madhavan Srinivasan <maddy@linux.ibm.com> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Tested-by: Disha Goel <disgoel@linux.ibm.com> Cc: akanksha@linux.ibm.com Cc: hbathini@linux.ibm.com Cc: kjain@linux.ibm.com Cc: linuxppc-dev@lists.ozlabs.org Link: https://lore.kernel.org/r/20241010145107.51211-1-atrajeev@linux.vnet.ibm.com Signed-off-by: Namhyung Kim <namhyung@kernel.org> Signed-off-by: Mamatha Inamdar <minamdar@redhat.com>
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‎tools/perf/pmu-events/arch/powerpc/compat/generic-events.json‎

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[
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{
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"EventCode": "0x600F4",
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"EventName": "PM_CYC",
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"BriefDescription": "Processor cycles."
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},
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{
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"EventCode": "0x100F2",
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"EventName": "PM_CYC_INST_CMPL",
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"BriefDescription": "1 or more ppc insts finished"
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},
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{
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"EventCode": "0x100f4",
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"EventName": "PM_FLOP_CMPL",
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"BriefDescription": "Floating Point Operations Finished."
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},
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{
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"EventCode": "0x100F6",
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"EventName": "PM_L1_ITLB_MISS",
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"BriefDescription": "Number of I-ERAT reloads."
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},
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{
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"EventCode": "0x100F8",
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"EventName": "PM_NO_INST_AVAIL",
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"BriefDescription": "Number of cycles the ICT has no itags assigned to this thread."
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},
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{
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"EventCode": "0x100fc",
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"EventName": "PM_LD_CMPL",
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"BriefDescription": "Load instruction completed."
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},
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{
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"EventCode": "0x200F0",
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"EventName": "PM_ST_CMPL",
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"BriefDescription": "Stores completed from S2Q (2nd-level store queue)."
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},
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{
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"EventCode": "0x200F2",
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"EventName": "PM_INST_DISP",
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"BriefDescription": "PowerPC instruction dispatched."
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},
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{
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"EventCode": "0x200F4",
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"EventName": "PM_RUN_CYC",
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"BriefDescription": "Processor cycles gated by the run latch."
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},
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{
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"EventCode": "0x200F6",
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"EventName": "PM_L1_DTLB_RELOAD",
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"BriefDescription": "DERAT Reloaded due to a DERAT miss."
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},
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{
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"EventCode": "0x200FA",
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"EventName": "PM_BR_TAKEN_CMPL",
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"BriefDescription": "Branch Taken instruction completed."
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},
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{
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"EventCode": "0x200FC",
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"EventName": "PM_L1_ICACHE_MISS",
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"BriefDescription": "Demand instruction cache miss."
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},
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{
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"EventCode": "0x200FE",
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"EventName": "PM_L1_RELOAD_FROM_MEM",
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"BriefDescription": "L1 Dcache reload from memory"
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},
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{
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"EventCode": "0x300F0",
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"EventName": "PM_ST_MISS_L1",
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"BriefDescription": "Store Missed L1"
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},
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{
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"EventCode": "0x300FC",
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"EventName": "PM_DTLB_MISS",
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"BriefDescription": "Data PTEG reload"
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},
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{
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"EventCode": "0x300FE",
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"EventName": "PM_DATA_FROM_L3MISS",
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"BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)"
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},
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{
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"EventCode": "0x400F0",
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"EventName": "PM_LD_MISS_L1",
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"BriefDescription": "L1 Dcache load miss"
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},
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{
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"EventCode": "0x400F2",
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"EventName": "PM_CYC_INST_DISP",
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"BriefDescription": "Cycle when instruction(s) dispatched."
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},
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{
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"EventCode": "0x400F6",
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"EventName": "PM_BR_MPRED_CMPL",
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"BriefDescription": "A mispredicted branch completed. Includes direction and target."
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},
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{
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"EventCode": "0x400FA",
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"EventName": "PM_RUN_INST_CMPL",
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"BriefDescription": "PowerPC instruction completed while the run latch is set."
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},
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{
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"EventCode": "0x400FC",
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"EventName": "PM_ITLB_MISS",
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"BriefDescription": "Instruction TLB reload (after a miss), all page sizes. Includes only demand misses."
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},
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{
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"EventCode": "0x400fe",
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"EventName": "PM_LD_NOT_CACHED",
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"BriefDescription": "Load data not cached."
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},
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{
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"EventCode": "0x500fa",
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"EventName": "PM_INST_CMPL",
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"BriefDescription": "Instructions."
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}
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]

‎tools/perf/pmu-events/arch/powerpc/mapfile.csv‎

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0x004e[[:xdigit:]]{4},1,power9,core
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0x0080[[:xdigit:]]{4},1,power10,core
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0x0082[[:xdigit:]]{4},1,power10,core
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0x00ffffff,1,compat,core

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