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Merge: Support to handle compatible mode PVR for perf
MR: https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-9/-/merge_requests/6242 Description: Support to handle compatible mode PVR for perf JIRA: https://issues.redhat.com/browse/RHEL-75636 Build Info: https://brewweb.engineering.redhat.com/brew/taskinfo?taskID=66443824 Tested: Verified Brew build test kernel RPMs Signed-off-by: Mamatha Inamdar <minamdar@redhat.com> Approved-by: Steve Best <sbest@redhat.com> Approved-by: Tony Camuso <tcamuso@redhat.com> Approved-by: CKI KWF Bot <cki-ci-bot+kwf-gitlab-com@redhat.com> Merged-by: Rado Vrbovsky <rvrbovsk@redhat.com>
2 parents 8db6275 + 7c7f7c9 commit 0d14165

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‎tools/perf/arch/powerpc/util/header.c‎

Lines changed: 31 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,18 @@
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#include "utils_header.h"
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#include "metricgroup.h"
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#include <api/fs/fs.h>
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#include <sys/auxv.h>
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static bool is_compat_mode(void)
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{
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u64 base_platform = getauxval(AT_BASE_PLATFORM);
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u64 platform = getauxval(AT_PLATFORM);
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if (!strcmp((char *)platform, (char *)base_platform))
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return false;
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return true;
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}
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int
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get_cpuid(char *buffer, size_t sz)
@@ -33,8 +45,26 @@ char *
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get_cpuid_str(struct perf_pmu *pmu __maybe_unused)
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{
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char *bufp;
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unsigned long pvr;
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/*
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* IBM Power System supports compatible mode. That is
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* Nth generation platform can support previous generation
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* OS in a mode called compatibile mode. For ex. LPAR can be
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* booted in a Power9 mode when the system is a Power10.
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*
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* In the compatible mode, care must be taken when generating
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* PVR value. When read, PVR will be of the AT_BASE_PLATFORM
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* To support generic events, return 0x00ffffff as pvr when
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* booted in compat mode. Based on this pvr value, json will
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* pick events from pmu-events/arch/powerpc/compat
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*/
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if (!is_compat_mode())
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pvr = mfspr(SPRN_PVR);
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else
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pvr = 0x00ffffff;
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if (asprintf(&bufp, "0x%.8lx", mfspr(SPRN_PVR)) < 0)
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if (asprintf(&bufp, "0x%.8lx", pvr) < 0)
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bufp = NULL;
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return bufp;

‎tools/perf/pmu-events/arch/powerpc/compat/generic-events.json‎

Lines changed: 117 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,117 @@
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[
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{
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"EventCode": "0x600F4",
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"EventName": "PM_CYC",
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"BriefDescription": "Processor cycles."
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},
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{
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"EventCode": "0x100F2",
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"EventName": "PM_CYC_INST_CMPL",
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"BriefDescription": "1 or more ppc insts finished"
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},
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{
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"EventCode": "0x100f4",
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"EventName": "PM_FLOP_CMPL",
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"BriefDescription": "Floating Point Operations Finished."
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},
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{
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"EventCode": "0x100F6",
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"EventName": "PM_L1_ITLB_MISS",
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"BriefDescription": "Number of I-ERAT reloads."
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},
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{
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"EventCode": "0x100F8",
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"EventName": "PM_NO_INST_AVAIL",
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"BriefDescription": "Number of cycles the ICT has no itags assigned to this thread."
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},
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{
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"EventCode": "0x100fc",
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"EventName": "PM_LD_CMPL",
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"BriefDescription": "Load instruction completed."
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},
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{
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"EventCode": "0x200F0",
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"EventName": "PM_ST_CMPL",
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"BriefDescription": "Stores completed from S2Q (2nd-level store queue)."
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},
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{
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"EventCode": "0x200F2",
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"EventName": "PM_INST_DISP",
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"BriefDescription": "PowerPC instruction dispatched."
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},
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{
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"EventCode": "0x200F4",
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"EventName": "PM_RUN_CYC",
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"BriefDescription": "Processor cycles gated by the run latch."
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},
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{
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"EventCode": "0x200F6",
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"EventName": "PM_L1_DTLB_RELOAD",
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"BriefDescription": "DERAT Reloaded due to a DERAT miss."
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},
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{
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"EventCode": "0x200FA",
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"EventName": "PM_BR_TAKEN_CMPL",
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"BriefDescription": "Branch Taken instruction completed."
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},
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{
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"EventCode": "0x200FC",
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"EventName": "PM_L1_ICACHE_MISS",
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"BriefDescription": "Demand instruction cache miss."
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},
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{
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"EventCode": "0x200FE",
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"EventName": "PM_L1_RELOAD_FROM_MEM",
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"BriefDescription": "L1 Dcache reload from memory"
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},
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{
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"EventCode": "0x300F0",
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"EventName": "PM_ST_MISS_L1",
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"BriefDescription": "Store Missed L1"
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},
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{
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"EventCode": "0x300FC",
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"EventName": "PM_DTLB_MISS",
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"BriefDescription": "Data PTEG reload"
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},
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{
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"EventCode": "0x300FE",
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"EventName": "PM_DATA_FROM_L3MISS",
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"BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)"
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},
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{
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"EventCode": "0x400F0",
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"EventName": "PM_LD_MISS_L1",
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"BriefDescription": "L1 Dcache load miss"
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},
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{
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"EventCode": "0x400F2",
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"EventName": "PM_CYC_INST_DISP",
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"BriefDescription": "Cycle when instruction(s) dispatched."
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},
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{
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"EventCode": "0x400F6",
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"EventName": "PM_BR_MPRED_CMPL",
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"BriefDescription": "A mispredicted branch completed. Includes direction and target."
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},
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{
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"EventCode": "0x400FA",
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"EventName": "PM_RUN_INST_CMPL",
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"BriefDescription": "PowerPC instruction completed while the run latch is set."
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},
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{
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"EventCode": "0x400FC",
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"EventName": "PM_ITLB_MISS",
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"BriefDescription": "Instruction TLB reload (after a miss), all page sizes. Includes only demand misses."
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},
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{
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"EventCode": "0x400fe",
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"EventName": "PM_LD_NOT_CACHED",
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"BriefDescription": "Load data not cached."
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},
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{
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"EventCode": "0x500fa",
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"EventName": "PM_INST_CMPL",
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"BriefDescription": "Instructions."
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}
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]

‎tools/perf/pmu-events/arch/powerpc/mapfile.csv‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,3 +16,4 @@
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0x004e[[:xdigit:]]{4},1,power9,core
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0x0080[[:xdigit:]]{4},1,power10,core
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0x0082[[:xdigit:]]{4},1,power10,core
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0x00ffffff,1,compat,core

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