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perf vendor events arm64: Update FUJITSU-MONAKA pmu event
JIRA: https://issues.redhat.com/browse/RHEL-78200 upstream ======== commit ce3d5af Author: Kotaro, Tokai <fj0635gf@aa.jp.fujitsu.com> Date: Wed Jun 18 15:35:42 2025 +0900 description =========== Update pmu events for FUJITSU-MONAKA. And, also updated common-and-microarch.json. FUJITSU-MONAKA PMU Events Specification v1.1 and Errata v1.0 URL: https://github.com/fujitsu/FUJITSU-MONAKA Arm Architecture Reference Version L.b URL: https://developer.arm.com/documentation/ddi0487/lb/?lang=en Signed-off-by: Kotaro, Tokai <fj0635gf@aa.jp.fujitsu.com> Reviewed-by: James Clark <james.clark@linaro.org> Link: https://lore.kernel.org/r/20250618063618.1244363-1-fj0635gf@aa.jp.fujitsu.com Signed-off-by: Namhyung Kim <namhyung@kernel.org> Signed-off-by: Anubhav Shelat <ashelat@redhat.com>
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‎tools/perf/pmu-events/arch/arm64/common-and-microarch.json‎

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"EventCode": "0x8324",
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"EventName": "L1I_CACHE_REFILL_PERCYC",
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"BriefDescription": "Level 1 instruction or unified cache refills in progress."
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},
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{
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"EventCode": "0x8431",
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"EventName": "ASE_FP_VREDUCE_SPEC",
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"BriefDescription": "Floating-point operation_speculatively_executed, Advanced SIMD pairwise or reduction."
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},
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{
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"EventCode": "0x8432",
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"EventName": "SVE_FP_PREDUCE_SPEC",
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"BriefDescription": "Floating-point operation_speculatively_executed, Advanced SIMD pairwise add step or pairwise reduce step."
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},
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{
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"EventCode": "0x8443",
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"EventName": "ASE_FP_BF16_MIN_SPEC",
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"BriefDescription": "Advanced SIMD data processing operation speculatively_executed, smallest type is BFloat16 floating-point."
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},
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{
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"EventCode": "0x8444",
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"EventName": "ASE_FP_FP8_MIN_SPEC",
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"BriefDescription": "Advanced SIMD data processing operation speculatively_executed, smallest type is 8-bit floating-point."
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},
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{
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"EventCode": "0x844B",
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"EventName": "ASE_SVE_FP_BF16_MIN_SPEC",
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"BriefDescription": "Advanced SIMD data processing or SVE data processing operation speculatively_executed, smallest type is BFloat16 floating-point."
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},
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{
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"EventCode": "0x844C",
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"EventName": "ASE_SVE_FP_FP8_MIN_SPEC",
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"BriefDescription": "Advanced SIMD data processing or SVE data processing operation speculatively_executed, smallest type is 8-bit floating-point."
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},
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{
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"EventCode": "0x8463",
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"EventName": "SVE_FP_BF16_MIN_SPEC",
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"BriefDescription": "SVE data processing operation speculatively_executed, smallest type is BFloat16 floating-point."
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},
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{
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"EventCode": "0x8464",
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"EventName": "SVE_FP_FP8_MIN_SPEC",
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"BriefDescription": "SVE data processing operation speculatively_executed, smallest type is 8-bit floating-point."
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},
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{
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"EventCode": "0x8473",
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"EventName": "FP_BF16_MIN_SPEC",
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"BriefDescription": "Floating-point operation speculatively_executed, smallest type is BFloat16 floating-point."
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},
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{
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"EventCode": "0x8474",
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"EventName": "FP_FP8_MIN_SPEC",
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"BriefDescription": "Floating-point operation speculatively_executed, smallest type is 8-bit floating-point."
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},
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{
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"EventCode": "0x8483",
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"EventName": "FP_BF16_FIXED_MIN_OPS_SPEC",
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"BriefDescription": "Non-scalable element arithmetic operations speculatively executed, smallest type is BFloat16 floating-point."
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},
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{
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"EventCode": "0x8484",
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"EventName": "FP_FP8_FIXED_MIN_OPS_SPEC",
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"BriefDescription": "Non-scalable element arithmetic operations speculatively executed, smallest type is 8-bit floating-point."
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},
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{
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"EventCode": "0x848B",
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"EventName": "FP_BF16_SCALE_MIN_OPS_SPEC",
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"BriefDescription": "Scalable element arithmetic operations speculatively executed, smallest type is BFloat16 floating-point."
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},
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{
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"EventCode": "0x848C",
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"EventName": "FP_FP8_SCALE_MIN_OPS_SPEC",
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"BriefDescription": "Scalable element arithmetic operations speculatively executed, smallest type is 8-bit floating-point."
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}
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]

‎tools/perf/pmu-events/arch/arm64/fujitsu/monaka/core-imp-def.json‎

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[
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{
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"ArchStdEvent": "L1I_CACHE_PRF",
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"BriefDescription": "This event counts fetch counted by either Level 1 instruction hardware prefetch or Level 1 instruction software prefetch."
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"BriefDescription": "This event counts L1I_CACHE caused by hardware prefetch or software prefetch."
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}
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]

‎tools/perf/pmu-events/arch/arm64/fujitsu/monaka/cycle_accounting.json‎

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{
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"EventCode": "0x0184",
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"EventName": "LD_COMP_WAIT",
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"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access."
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"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache, L3 cache and memory access."
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},
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{
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"EventCode": "0x0185",
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"EventName": "LD_COMP_WAIT_EX",
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"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access."
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"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache, L3 cache and memory access."
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},
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{
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"EventCode": "0x0186",

‎tools/perf/pmu-events/arch/arm64/fujitsu/monaka/exception.json‎

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},
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{
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"ArchStdEvent": "EXC_SMC",
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"BriefDescription": "This event counts only Secure Monitor Call exceptions. The counter does not increment on SMC instructions trapped as a Hyp Trap exception."
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"BriefDescription": "This event counts only Secure Monitor Call exceptions. This event does not increment on SMC instructions trapped as a Hyp Trap exception."
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},
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{
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"ArchStdEvent": "EXC_HVC",

‎tools/perf/pmu-events/arch/arm64/fujitsu/monaka/fp_operation.json‎

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{
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"EventCode": "0x0105",
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"EventName": "FP_MV_SPEC",
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"BriefDescription": "This event counts architecturally executed floating-point move operations."
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"BriefDescription": "This event counts architecturally executed floating-point move operation."
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},
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{
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"EventCode": "0x0112",
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},
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{
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"ArchStdEvent": "ASE_SVE_FP_SPEC",
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"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point operations."
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"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point operation."
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},
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{
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"ArchStdEvent": "FP_HP_SPEC",
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},
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{
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"ArchStdEvent": "ASE_SVE_FP_HP_SPEC",
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"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE half-precision floating-point operations."
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"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE half-precision floating-point operation."
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},
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{
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"ArchStdEvent": "FP_SP_SPEC",
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},
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{
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"ArchStdEvent": "ASE_SVE_FP_SP_SPEC",
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"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE single-precision floating-point operations."
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"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE single-precision floating-point operation."
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},
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{
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"ArchStdEvent": "FP_DP_SPEC",
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},
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{
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"ArchStdEvent": "ASE_SVE_FP_DP_SPEC",
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"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE double-precision floating-point operations."
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"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE double-precision floating-point operation."
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},
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{
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"ArchStdEvent": "FP_DIV_SPEC",
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},
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{
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"ArchStdEvent": "ASE_SVE_FP_DIV_SPEC",
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"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point divide operations."
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"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point divide operation."
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},
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{
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"ArchStdEvent": "FP_SQRT_SPEC",
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},
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{
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"ArchStdEvent": "ASE_SVE_FP_SQRT_SPEC",
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"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point square root operations."
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"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point square root operation."
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},
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{
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"ArchStdEvent": "ASE_FP_FMA_SPEC",
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},
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{
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"ArchStdEvent": "ASE_SVE_FP_FMA_SPEC",
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"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point FMA operations."
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"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point FMA operation."
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},
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{
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"ArchStdEvent": "FP_MUL_SPEC",
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"BriefDescription": "This event counts architecturally executed floating-point multiply operations."
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"BriefDescription": "This event counts architecturally executed floating-point multiply operation."
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},
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{
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"ArchStdEvent": "ASE_FP_MUL_SPEC",
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},
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{
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"ArchStdEvent": "ASE_SVE_FP_MUL_SPEC",
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"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point multiply operations."
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"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point multiply operation."
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},
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{
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"ArchStdEvent": "FP_ADDSUB_SPEC",
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"BriefDescription": "This event counts architecturally executed floating-point add or subtract operations."
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"BriefDescription": "This event counts architecturally executed floating-point add or subtract operation."
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},
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{
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"ArchStdEvent": "ASE_FP_ADDSUB_SPEC",
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},
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{
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"ArchStdEvent": "ASE_SVE_FP_ADDSUB_SPEC",
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"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point add or subtract operations."
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"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point add or subtract operation."
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},
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{
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"ArchStdEvent": "ASE_FP_RECPE_SPEC",
155-
"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point reciprocal estimate operations."
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"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point reciprocal estimate operation."
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},
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{
158158
"ArchStdEvent": "SVE_FP_RECPE_SPEC",
159-
"BriefDescription": "This event counts architecturally executed SVE floating-point reciprocal estimate operations."
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"BriefDescription": "This event counts architecturally executed SVE floating-point reciprocal estimate operation."
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},
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{
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"ArchStdEvent": "ASE_SVE_FP_RECPE_SPEC",
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"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point reciprocal estimate operations."
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"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point reciprocal estimate operation."
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},
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{
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"ArchStdEvent": "ASE_FP_CVT_SPEC",
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},
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{
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"ArchStdEvent": "ASE_SVE_FP_CVT_SPEC",
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"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point convert operations."
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"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point convert operation."
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},
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{
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"ArchStdEvent": "SVE_FP_AREDUCE_SPEC",
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"BriefDescription": "This event counts architecturally executed SVE floating-point accumulating reduction operations."
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"BriefDescription": "This event counts architecturally executed SVE floating-point accumulating reduction operation."
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},
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{
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"ArchStdEvent": "ASE_FP_PREDUCE_SPEC",
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"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point pairwise add step operations."
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"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point pairwise add step operation."
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},
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{
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"ArchStdEvent": "SVE_FP_VREDUCE_SPEC",
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"BriefDescription": "This event counts architecturally executed SVE floating-point vector reduction operation."
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},
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{
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"ArchStdEvent": "ASE_SVE_FP_VREDUCE_SPEC",
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"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point vector reduction operations."
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"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point vector reduction operation."
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},
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{
194194
"ArchStdEvent": "FP_SCALE_OPS_SPEC",
195-
"BriefDescription": "This event counts architecturally executed SVE arithmetic operations. See FP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by (128 / CSIZE) and by twice that amount for operations that would also be counted by SVE_FP_FMA_SPEC."
195+
"BriefDescription": "This event counts architecturally executed SVE arithmetic operation. See FP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by (128 / CSIZE) and by twice that amount for operations that would also be counted by SVE_FP_FMA_SPEC."
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},
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{
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"ArchStdEvent": "FP_FIXED_OPS_SPEC",
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"BriefDescription": "This event counts architecturally executed v8SIMD&FP arithmetic operations. See FP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. The event counter is incremented by the specified number of elements for Advanced SIMD operations or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
199+
"BriefDescription": "This event counts architecturally executed v8SIMD&FP arithmetic operation. See FP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the specified number of elements for Advanced SIMD operations or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
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},
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{
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"ArchStdEvent": "ASE_SVE_FP_DOT_SPEC",
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{
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"ArchStdEvent": "ASE_SVE_FP_MMLA_SPEC",
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"BriefDescription": "This event counts architecturally executed microarchitectural Advanced SIMD or SVE floating-point matrix multiply operation."
208+
},
209+
{
210+
"ArchStdEvent": "ASE_FP_VREDUCE_SPEC",
211+
"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point vector reduction operation."
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},
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{
214+
"ArchStdEvent": "SVE_FP_PREDUCE_SPEC",
215+
"BriefDescription": "This event counts architecturally executed SVE floating-point pairwise add step operation."
216+
},
217+
{
218+
"ArchStdEvent": "ASE_FP_BF16_MIN_SPEC",
219+
"BriefDescription": "This event counts architecturally executed Advanced SIMD data processing operations, smallest type is BFloat16 floating-point."
220+
},
221+
{
222+
"ArchStdEvent": "ASE_FP_FP8_MIN_SPEC",
223+
"BriefDescription": "This event counts architecturally executed Advanced SIMD data processing operations, smallest type is 8-bit floating-point."
224+
},
225+
{
226+
"ArchStdEvent": "ASE_SVE_FP_BF16_MIN_SPEC",
227+
"BriefDescription": "This event counts architecturally executed Advanced SIMD data processing or SVE data processing operations, smallest type is BFloat16 floating-point."
228+
},
229+
{
230+
"ArchStdEvent": "ASE_SVE_FP_FP8_MIN_SPEC",
231+
"BriefDescription": "This event counts architecturally executed Advanced SIMD data processing or SVE data processing operations, smallest type is 8-bit floating-point."
232+
},
233+
{
234+
"ArchStdEvent": "SVE_FP_BF16_MIN_SPEC",
235+
"BriefDescription": "This event counts architecturally executed SVE data processing operations, smallest type is BFloat16 floating-point."
236+
},
237+
{
238+
"ArchStdEvent": "SVE_FP_FP8_MIN_SPEC",
239+
"BriefDescription": "This event counts architecturally executed SVE data processing operations, smallest type is 8-bit floating-point."
240+
},
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{
242+
"ArchStdEvent": "FP_BF16_MIN_SPEC",
243+
"BriefDescription": "This event counts architecturally executed data processing operations, smallest type is BFloat16 floating-point."
244+
},
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{
246+
"ArchStdEvent": "FP_FP8_MIN_SPEC",
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"BriefDescription": "This event counts architecturally executed data processing operations, smallest type is 8-bit floating-point."
248+
},
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{
250+
"ArchStdEvent": "FP_BF16_FIXED_MIN_OPS_SPEC",
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"BriefDescription": "This event counts architecturally executed non-scalable element arithmetic operations, smallest type is BFloat16 floating-point."
252+
},
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{
254+
"ArchStdEvent": "FP_FP8_FIXED_MIN_OPS_SPEC",
255+
"BriefDescription": "This event counts architecturally executed non-scalable element arithmetic operations, smallest type is 8-bit floating-point."
256+
},
257+
{
258+
"ArchStdEvent": "FP_BF16_SCALE_MIN_OPS_SPEC",
259+
"BriefDescription": "This event counts architecturally executed scalable element arithmetic operations, smallest type is BFloat16 floating-point."
260+
},
261+
{
262+
"ArchStdEvent": "FP_FP8_SCALE_MIN_OPS_SPEC",
263+
"BriefDescription": "This event counts architecturally executed scalable element arithmetic operations, smallest type is 8-bit floating-point."
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}
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]

‎tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l1d_cache.json‎

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},
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{
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"ArchStdEvent": "L1D_CACHE_HWPRF",
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"BriefDescription": "This event counts access counted by L1D_CACHE that is due to a hardware prefetch."
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"BriefDescription": "This event counts L1D_CACHE caused by hardware prefetch."
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL_HWPRF",
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"BriefDescription": "This event counts hardware prefetch counted by L1D_CACHE_HWPRF that causes a refill of the Level 1 data cache from outside of the Level 1 data cache."
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"BriefDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch."
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},
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{
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"ArchStdEvent": "L1D_CACHE_HIT_RD",
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},
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{
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"ArchStdEvent": "L1D_CACHE_PRF",
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"BriefDescription": "This event counts fetch counted by either Level 1 data hardware prefetch or Level 1 data software prefetch."
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"BriefDescription": "This event counts L1D_CACHE caused by hardware prefetch or software prefetch."
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL_PRF",
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"BriefDescription": "This event counts hardware prefetch counted by L1D_CACHE_PRF that causes a refill of the Level 1 data cache from outside of the Level 1 data cache."
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"BriefDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch or software prefetch."
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},
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{
110110
"ArchStdEvent": "L1D_CACHE_REFILL_PERCYC",
111-
"BriefDescription": "The counter counts by the number of cache refills counted by L1D_CACHE_REFILL in progress on each Processor cycle."
111+
"BriefDescription": "This counter counts by the number of cache refills counted by L1D_CACHE_REFILL in progress on each Processor cycle."
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}
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]

‎tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l1i_cache.json‎

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},
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{
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"ArchStdEvent": "L1I_CACHE_HWPRF",
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"BriefDescription": "This event counts access counted by L1I_CACHE that is due to a hardware prefetch."
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"BriefDescription": "This event counts L1I_CACHE caused by hardware prefetch."
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},
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{
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"ArchStdEvent": "L1I_CACHE_REFILL_HWPRF",
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"BriefDescription": "This event counts hardware prefetch counted by L1I_CACHE_HWPRF that causes a refill of the Level 1 instruction cache from outside of the Level 1 instruction cache."
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"BriefDescription": "This event counts L1I_CACHE_REFILL caused by hardware prefetch."
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},
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{
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"ArchStdEvent": "L1I_CACHE_HIT_RD",
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},
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{
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"ArchStdEvent": "L1I_CACHE_REFILL_PRF",
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"BriefDescription": "This event counts hardware prefetch counted by L1I_CACHE_PRF that causes a refill of the Level 1 instruction cache from outside of the Level 1 instruction cache."
46+
"BriefDescription": "This event counts L1I_CACHE_REFILL caused by hardware prefetch or software prefetch."
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},
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{
4949
"ArchStdEvent": "L1I_CACHE_REFILL_PERCYC",
50-
"BriefDescription": "The counter counts by the number of cache refills counted by L1I_CACHE_REFILL in progress on each Processor cycle."
50+
"BriefDescription": "This counter counts by the number of cache refills counted by L1I_CACHE_REFILL in progress on each Processor cycle."
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}
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]

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