perf/x86/intel/ds: Add PEBS format 6

JIRA: https://issues.redhat.com/browse/RHEL-47444

upstream
========
commit b8c3a25
Author: Kan Liang <kan.liang@linux.intel.com>
Date: Mon Dec 16 12:45:02 2024 -0800

description
===========
The only difference between 5 and 6 is the new counters snapshotting
group, without the following counters snapshotting enabling patches,
it's impossible to utilize the feature in a PEBS record. It's safe to
share the same code path with format 5.

Add format 6, so the end user can at least utilize the legacy PEBS
features.

Fixes: a932aa0 ("perf/x86: Add Lunar Lake and Arrow Lake support")
    Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Cc: stable@vger.kernel.org
    Link: https://lore.kernel.org/r/20241216204505.748363-1-kan.liang@linux.intel.com

Signed-off-by: Michael Petlan <mpetlan@redhat.com>

Author: rfmvh

arch/x86/events/intel/ds.c

@@ -2507,6 +2507,7 @@ void __init intel_ds_init(void)
 			x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
 			break;
 
+		case 6:
 		case 5:
 			x86_pmu.pebs_ept = 1;
 			fallthrough;