aarch64: Use aarch64_cpu::registers traits

Signed-off-by: Akira Moroo <retrage01@gmail.com>

Author: retrage

src/arch/aarch64/paging.rs

@@ -4,8 +4,10 @@
 
 use core::ops::RangeInclusive;
 
-use aarch64_cpu::{asm::barrier, registers::*};
-use tock_registers::interfaces::{ReadWriteable, Readable, Writeable};
+use aarch64_cpu::{
+    asm::barrier,
+    registers::{Readable, Writeable, *},
+};
 
 use self::interface::Mmu;
 
@@ -287,7 +289,10 @@ impl interface::Mmu for MemoryManagementUnit {
         barrier::isb(barrier::SY);
 
         // Enable the MMU and turn on data and instruction caching.
-        SCTLR_EL1.modify(SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable + SCTLR_EL1::I::Cacheable);
+        SCTLR_EL1.modify_no_read(
+            SCTLR_EL1.extract(),
+            SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable + SCTLR_EL1::I::Cacheable,
+        );
 
         // Force MMU init to complete before next instruction.
         barrier::isb(barrier::SY);

src/arch/aarch64/simd.rs

@@ -2,8 +2,7 @@
 // Copyright (C) 2023 Akira Moroo
 
 use aarch64_cpu::registers::*;
-use tock_registers::interfaces::ReadWriteable;
 
 pub fn setup_simd() {
-    CPACR_EL1.modify(CPACR_EL1::FPEN::TrapNothing);
+    CPACR_EL1.modify_no_read(CPACR_EL1.extract(), CPACR_EL1::FPEN::TrapNothing);
 }