diff --git a/.gitmodules b/.gitmodules index 57abac9f..bbb58b88 100644 --- a/.gitmodules +++ b/.gitmodules @@ -19,3 +19,6 @@ [submodule "third_party/hamsternz-displayport"] path = third_party/hamsternz-displayport url = https://github.com/hamsternz/DisplayPort_Verilog.git +[submodule "third_party/litepcie"] + path = third_party/litepcie + url = https://github.com/enjoy-digital/litepcie diff --git a/Makefile b/Makefile index 6097c021..37880f38 100644 --- a/Makefile +++ b/Makefile @@ -22,8 +22,8 @@ ENVIRONMENT_FILE ?= conf/${TOOLCHAIN}/environment.yml # FIXME: make this dynamic: https://github.com/SymbiFlow/fpga-tool-perf/issues/75 SYMBIFLOW_ARCHIVE = symbiflow.tar.xz -SYMBIFLOW_URL = https://storage.googleapis.com/symbiflow-arch-defs/artifacts/prod/foss-fpga-tools/symbiflow-arch-defs/continuous/install/80/20201020-195452/symbiflow-arch-defs-install-2f55fb8f.tar.xz -SYMBIFLOW_URL_200T = https://storage.googleapis.com/symbiflow-arch-defs/artifacts/prod/foss-fpga-tools/symbiflow-arch-defs/continuous/install-200t/23/20201020-195721/symbiflow-arch-defs-install-200t-2f55fb8f.tar.xz +SYMBIFLOW_URL = https://storage.googleapis.com/symbiflow-arch-defs/artifacts/prod/foss-fpga-tools/symbiflow-arch-defs/continuous/install/88/20201104-094013/symbiflow-arch-defs-install-5f35cd60.tar.xz +SYMBIFLOW_URL_200T = https://storage.googleapis.com/symbiflow-arch-defs/artifacts/prod/foss-fpga-tools/symbiflow-arch-defs/continuous/install-200t/31/20201104-094254/symbiflow-arch-defs-install-200t-5f35cd60.tar.xz QUICKLOGIC_ARCHIVE = quicklogic.tar.xz QUICKLOGIC_URL = https://quicklogic-my.sharepoint.com/:u:/p/kkumar/EWuqtXJmalROpI2L5XeewMIBRYVCY8H4yc10nlli-Xq79g?download=1 diff --git a/other/boards.json b/other/boards.json index 05a0a351..513a4c6a 100644 --- a/other/boards.json +++ b/other/boards.json @@ -29,6 +29,11 @@ "device": "a200t", "package": "sbg484-1" }, + "netv2": { + "family": "xc7", + "device": "a100t", + "package": "fgg484-2" + }, "icebreaker": { "family": "ice40", "device": "up5k", diff --git a/other/vendors.json b/other/vendors.json index d658c753..508454c2 100644 --- a/other/vendors.json +++ b/other/vendors.json @@ -1,6 +1,6 @@ { "xilinx": { - "boards": ["arty-a35t", "arty-a100t", "basys3", "zybo", "nexys-video"], + "boards": ["arty-a35t", "arty-a100t", "basys3", "zybo", "nexys-video", "netv2"], "toolchains": ["vivado", "yosys-vivado", "vpr", "vpr-fasm2bels", "nextpnr-xilinx", "nextpnr-xilinx-fasm2bels"] }, "lattice": { diff --git a/project/netv2-pcie.json b/project/netv2-pcie.json new file mode 100644 index 00000000..ae929496 --- /dev/null +++ b/project/netv2-pcie.json @@ -0,0 +1,26 @@ +{ + "srcs": [ + "third_party/vexriscv-verilog/VexRiscv_Lite.v", + "third_party/litepcie/litepcie/phy/xilinx_s7_gen2_x1/pcie_s7_support.v", + "third_party/litepcie/litepcie/phy/xilinx_s7_gen2_x1/pcie_pipe_clock.v", + "third_party/litepcie/litepcie/phy/xilinx_s7_gen2_x1/pcie_s7.xci", + "src/netv2-pcie/top.v" + + ], + "top": "top", + "name": "netv2-pcie", + "data": [ + "src/netv2-pcie/mem.init", + "src/netv2-pcie/mem_1.init", + "src/netv2-pcie/mem_2.init", + "src/netv2-pcie/edid_mem.init" + ], + "clocks": { + "clk50": 20.0 + }, + "vendors": { + "xilinx": ["netv2"] + }, + "required_toolchains": ["vivado"] + +} diff --git a/src/netv2-pcie/constr/netv2.xdc b/src/netv2-pcie/constr/netv2.xdc new file mode 100644 index 00000000..a633bf52 --- /dev/null +++ b/src/netv2-pcie/constr/netv2.xdc @@ -0,0 +1,624 @@ +################################################################################ +# IO constraints +################################################################################ +# clk50:0 +set_property LOC J19 [get_ports {clk50}] +set_property IOSTANDARD LVCMOS33 [get_ports {clk50}] + +# flash:0.cs_n +set_property LOC T19 [get_ports {flash_cs_n}] +set_property IOSTANDARD LVCMOS33 [get_ports {flash_cs_n}] + +# flash:0.mosi +set_property LOC P22 [get_ports {flash_mosi}] +set_property IOSTANDARD LVCMOS33 [get_ports {flash_mosi}] + +# flash:0.miso +set_property LOC R22 [get_ports {flash_miso}] +set_property IOSTANDARD LVCMOS33 [get_ports {flash_miso}] + +# flash:0.wp +set_property LOC P21 [get_ports {flash_wp}] +set_property IOSTANDARD LVCMOS33 [get_ports {flash_wp}] + +# flash:0.hold +set_property LOC R21 [get_ports {flash_hold}] +set_property IOSTANDARD LVCMOS33 [get_ports {flash_hold}] + +# ddram:0.a +set_property LOC U6 [get_ports {ddram_a[0]}] +set_property SLEW FAST [get_ports {ddram_a[0]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_a[0]}] + +# ddram:0.a +set_property LOC V4 [get_ports {ddram_a[1]}] +set_property SLEW FAST [get_ports {ddram_a[1]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_a[1]}] + +# ddram:0.a +set_property LOC W5 [get_ports {ddram_a[2]}] +set_property SLEW FAST [get_ports {ddram_a[2]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_a[2]}] + +# ddram:0.a +set_property LOC V5 [get_ports {ddram_a[3]}] +set_property SLEW FAST [get_ports {ddram_a[3]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_a[3]}] + +# ddram:0.a +set_property LOC AA1 [get_ports {ddram_a[4]}] +set_property SLEW FAST [get_ports {ddram_a[4]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_a[4]}] + +# ddram:0.a +set_property LOC Y2 [get_ports {ddram_a[5]}] +set_property SLEW FAST [get_ports {ddram_a[5]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_a[5]}] + +# ddram:0.a +set_property LOC AB1 [get_ports {ddram_a[6]}] +set_property SLEW FAST [get_ports {ddram_a[6]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_a[6]}] + +# ddram:0.a +set_property LOC AB3 [get_ports {ddram_a[7]}] +set_property SLEW FAST [get_ports {ddram_a[7]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_a[7]}] + +# ddram:0.a +set_property LOC AB2 [get_ports {ddram_a[8]}] +set_property SLEW FAST [get_ports {ddram_a[8]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_a[8]}] + +# ddram:0.a +set_property LOC Y3 [get_ports {ddram_a[9]}] +set_property SLEW FAST [get_ports {ddram_a[9]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_a[9]}] + +# ddram:0.a +set_property LOC W6 [get_ports {ddram_a[10]}] +set_property SLEW FAST [get_ports {ddram_a[10]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_a[10]}] + +# ddram:0.a +set_property LOC Y1 [get_ports {ddram_a[11]}] +set_property SLEW FAST [get_ports {ddram_a[11]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_a[11]}] + +# ddram:0.a +set_property LOC V2 [get_ports {ddram_a[12]}] +set_property SLEW FAST [get_ports {ddram_a[12]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_a[12]}] + +# ddram:0.a +set_property LOC AA3 [get_ports {ddram_a[13]}] +set_property SLEW FAST [get_ports {ddram_a[13]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_a[13]}] + +# ddram:0.ba +set_property LOC U5 [get_ports {ddram_ba[0]}] +set_property SLEW FAST [get_ports {ddram_ba[0]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_ba[0]}] + +# ddram:0.ba +set_property LOC W4 [get_ports {ddram_ba[1]}] +set_property SLEW FAST [get_ports {ddram_ba[1]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_ba[1]}] + +# ddram:0.ba +set_property LOC V7 [get_ports {ddram_ba[2]}] +set_property SLEW FAST [get_ports {ddram_ba[2]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_ba[2]}] + +# ddram:0.ras_n +set_property LOC Y9 [get_ports {ddram_ras_n}] +set_property SLEW FAST [get_ports {ddram_ras_n}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_ras_n}] + +# ddram:0.cas_n +set_property LOC Y7 [get_ports {ddram_cas_n}] +set_property SLEW FAST [get_ports {ddram_cas_n}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_cas_n}] + +# ddram:0.we_n +set_property LOC V8 [get_ports {ddram_we_n}] +set_property SLEW FAST [get_ports {ddram_we_n}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_we_n}] + +# ddram:0.dm +set_property LOC G1 [get_ports {ddram_dm[0]}] +set_property SLEW FAST [get_ports {ddram_dm[0]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dm[0]}] + +# ddram:0.dm +set_property LOC H4 [get_ports {ddram_dm[1]}] +set_property SLEW FAST [get_ports {ddram_dm[1]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dm[1]}] + +# ddram:0.dm +set_property LOC M5 [get_ports {ddram_dm[2]}] +set_property SLEW FAST [get_ports {ddram_dm[2]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dm[2]}] + +# ddram:0.dm +set_property LOC L3 [get_ports {ddram_dm[3]}] +set_property SLEW FAST [get_ports {ddram_dm[3]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dm[3]}] + +# ddram:0.dq +set_property LOC C2 [get_ports {ddram_dq[0]}] +set_property SLEW FAST [get_ports {ddram_dq[0]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[0]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[0]}] + +# ddram:0.dq +set_property LOC F1 [get_ports {ddram_dq[1]}] +set_property SLEW FAST [get_ports {ddram_dq[1]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[1]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[1]}] + +# ddram:0.dq +set_property LOC B1 [get_ports {ddram_dq[2]}] +set_property SLEW FAST [get_ports {ddram_dq[2]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[2]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[2]}] + +# ddram:0.dq +set_property LOC F3 [get_ports {ddram_dq[3]}] +set_property SLEW FAST [get_ports {ddram_dq[3]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[3]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[3]}] + +# ddram:0.dq +set_property LOC A1 [get_ports {ddram_dq[4]}] +set_property SLEW FAST [get_ports {ddram_dq[4]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[4]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[4]}] + +# ddram:0.dq +set_property LOC D2 [get_ports {ddram_dq[5]}] +set_property SLEW FAST [get_ports {ddram_dq[5]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[5]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[5]}] + +# ddram:0.dq +set_property LOC B2 [get_ports {ddram_dq[6]}] +set_property SLEW FAST [get_ports {ddram_dq[6]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[6]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[6]}] + +# ddram:0.dq +set_property LOC E2 [get_ports {ddram_dq[7]}] +set_property SLEW FAST [get_ports {ddram_dq[7]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[7]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[7]}] + +# ddram:0.dq +set_property LOC J5 [get_ports {ddram_dq[8]}] +set_property SLEW FAST [get_ports {ddram_dq[8]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[8]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[8]}] + +# ddram:0.dq +set_property LOC H3 [get_ports {ddram_dq[9]}] +set_property SLEW FAST [get_ports {ddram_dq[9]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[9]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[9]}] + +# ddram:0.dq +set_property LOC K1 [get_ports {ddram_dq[10]}] +set_property SLEW FAST [get_ports {ddram_dq[10]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[10]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[10]}] + +# ddram:0.dq +set_property LOC H2 [get_ports {ddram_dq[11]}] +set_property SLEW FAST [get_ports {ddram_dq[11]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[11]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[11]}] + +# ddram:0.dq +set_property LOC J1 [get_ports {ddram_dq[12]}] +set_property SLEW FAST [get_ports {ddram_dq[12]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[12]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[12]}] + +# ddram:0.dq +set_property LOC G2 [get_ports {ddram_dq[13]}] +set_property SLEW FAST [get_ports {ddram_dq[13]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[13]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[13]}] + +# ddram:0.dq +set_property LOC H5 [get_ports {ddram_dq[14]}] +set_property SLEW FAST [get_ports {ddram_dq[14]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[14]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[14]}] + +# ddram:0.dq +set_property LOC G3 [get_ports {ddram_dq[15]}] +set_property SLEW FAST [get_ports {ddram_dq[15]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[15]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[15]}] + +# ddram:0.dq +set_property LOC N2 [get_ports {ddram_dq[16]}] +set_property SLEW FAST [get_ports {ddram_dq[16]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[16]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[16]}] + +# ddram:0.dq +set_property LOC M6 [get_ports {ddram_dq[17]}] +set_property SLEW FAST [get_ports {ddram_dq[17]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[17]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[17]}] + +# ddram:0.dq +set_property LOC P1 [get_ports {ddram_dq[18]}] +set_property SLEW FAST [get_ports {ddram_dq[18]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[18]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[18]}] + +# ddram:0.dq +set_property LOC N5 [get_ports {ddram_dq[19]}] +set_property SLEW FAST [get_ports {ddram_dq[19]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[19]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[19]}] + +# ddram:0.dq +set_property LOC P2 [get_ports {ddram_dq[20]}] +set_property SLEW FAST [get_ports {ddram_dq[20]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[20]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[20]}] + +# ddram:0.dq +set_property LOC N4 [get_ports {ddram_dq[21]}] +set_property SLEW FAST [get_ports {ddram_dq[21]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[21]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[21]}] + +# ddram:0.dq +set_property LOC R1 [get_ports {ddram_dq[22]}] +set_property SLEW FAST [get_ports {ddram_dq[22]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[22]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[22]}] + +# ddram:0.dq +set_property LOC P6 [get_ports {ddram_dq[23]}] +set_property SLEW FAST [get_ports {ddram_dq[23]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[23]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[23]}] + +# ddram:0.dq +set_property LOC K3 [get_ports {ddram_dq[24]}] +set_property SLEW FAST [get_ports {ddram_dq[24]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[24]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[24]}] + +# ddram:0.dq +set_property LOC M2 [get_ports {ddram_dq[25]}] +set_property SLEW FAST [get_ports {ddram_dq[25]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[25]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[25]}] + +# ddram:0.dq +set_property LOC K4 [get_ports {ddram_dq[26]}] +set_property SLEW FAST [get_ports {ddram_dq[26]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[26]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[26]}] + +# ddram:0.dq +set_property LOC M3 [get_ports {ddram_dq[27]}] +set_property SLEW FAST [get_ports {ddram_dq[27]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[27]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[27]}] + +# ddram:0.dq +set_property LOC J6 [get_ports {ddram_dq[28]}] +set_property SLEW FAST [get_ports {ddram_dq[28]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[28]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[28]}] + +# ddram:0.dq +set_property LOC L5 [get_ports {ddram_dq[29]}] +set_property SLEW FAST [get_ports {ddram_dq[29]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[29]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[29]}] + +# ddram:0.dq +set_property LOC J4 [get_ports {ddram_dq[30]}] +set_property SLEW FAST [get_ports {ddram_dq[30]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[30]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[30]}] + +# ddram:0.dq +set_property LOC K6 [get_ports {ddram_dq[31]}] +set_property SLEW FAST [get_ports {ddram_dq[31]}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_dq[31]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[31]}] + +# ddram:0.dqs_p +set_property LOC E1 [get_ports {ddram_dqs_p[0]}] +set_property SLEW FAST [get_ports {ddram_dqs_p[0]}] +set_property IOSTANDARD DIFF_SSTL15_R [get_ports {ddram_dqs_p[0]}] + +# ddram:0.dqs_p +set_property LOC K2 [get_ports {ddram_dqs_p[1]}] +set_property SLEW FAST [get_ports {ddram_dqs_p[1]}] +set_property IOSTANDARD DIFF_SSTL15_R [get_ports {ddram_dqs_p[1]}] + +# ddram:0.dqs_p +set_property LOC P5 [get_ports {ddram_dqs_p[2]}] +set_property SLEW FAST [get_ports {ddram_dqs_p[2]}] +set_property IOSTANDARD DIFF_SSTL15_R [get_ports {ddram_dqs_p[2]}] + +# ddram:0.dqs_p +set_property LOC M1 [get_ports {ddram_dqs_p[3]}] +set_property SLEW FAST [get_ports {ddram_dqs_p[3]}] +set_property IOSTANDARD DIFF_SSTL15_R [get_ports {ddram_dqs_p[3]}] + +# ddram:0.dqs_n +set_property LOC D1 [get_ports {ddram_dqs_n[0]}] +set_property SLEW FAST [get_ports {ddram_dqs_n[0]}] +set_property IOSTANDARD DIFF_SSTL15_R [get_ports {ddram_dqs_n[0]}] + +# ddram:0.dqs_n +set_property LOC J2 [get_ports {ddram_dqs_n[1]}] +set_property SLEW FAST [get_ports {ddram_dqs_n[1]}] +set_property IOSTANDARD DIFF_SSTL15_R [get_ports {ddram_dqs_n[1]}] + +# ddram:0.dqs_n +set_property LOC P4 [get_ports {ddram_dqs_n[2]}] +set_property SLEW FAST [get_ports {ddram_dqs_n[2]}] +set_property IOSTANDARD DIFF_SSTL15_R [get_ports {ddram_dqs_n[2]}] + +# ddram:0.dqs_n +set_property LOC L1 [get_ports {ddram_dqs_n[3]}] +set_property SLEW FAST [get_ports {ddram_dqs_n[3]}] +set_property IOSTANDARD DIFF_SSTL15_R [get_ports {ddram_dqs_n[3]}] + +# ddram:0.clk_p +set_property LOC R3 [get_ports {ddram_clk_p}] +set_property SLEW FAST [get_ports {ddram_clk_p}] +set_property IOSTANDARD DIFF_SSTL15_R [get_ports {ddram_clk_p}] + +# ddram:0.clk_n +set_property LOC R2 [get_ports {ddram_clk_n}] +set_property SLEW FAST [get_ports {ddram_clk_n}] +set_property IOSTANDARD DIFF_SSTL15_R [get_ports {ddram_clk_n}] + +# ddram:0.cke +set_property LOC Y8 [get_ports {ddram_cke}] +set_property SLEW FAST [get_ports {ddram_cke}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_cke}] + +# ddram:0.odt +set_property LOC W9 [get_ports {ddram_odt}] +set_property SLEW FAST [get_ports {ddram_odt}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_odt}] + +# ddram:0.reset_n +set_property LOC AB5 [get_ports {ddram_reset_n}] +set_property SLEW FAST [get_ports {ddram_reset_n}] +set_property IOSTANDARD LVCMOS15 [get_ports {ddram_reset_n}] + +# ddram:0.cs_n +set_property LOC V9 [get_ports {ddram_cs_n}] +set_property SLEW FAST [get_ports {ddram_cs_n}] +set_property IOSTANDARD SSTL15_R [get_ports {ddram_cs_n}] + +# eth_clocks:0.ref_clk +set_property LOC D17 [get_ports {eth_clocks_ref_clk}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_ref_clk}] + +# eth:0.rst_n +set_property LOC F16 [get_ports {eth_rst_n}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rst_n}] + +# eth:0.rx_data +set_property LOC A20 [get_ports {eth_rx_data[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[0]}] + +# eth:0.rx_data +set_property LOC B18 [get_ports {eth_rx_data[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[1]}] + +# eth:0.crs_dv +set_property LOC C20 [get_ports {eth_crs_dv}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_crs_dv}] + +# eth:0.tx_en +set_property LOC A19 [get_ports {eth_tx_en}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_en}] + +# eth:0.tx_data +set_property LOC C18 [get_ports {eth_tx_data[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[0]}] + +# eth:0.tx_data +set_property LOC C19 [get_ports {eth_tx_data[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[1]}] + +# eth:0.mdc +set_property LOC F14 [get_ports {eth_mdc}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdc}] + +# eth:0.mdio +set_property LOC F13 [get_ports {eth_mdio}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdio}] + +# eth:0.rx_er +set_property LOC B20 [get_ports {eth_rx_er}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_er}] + +# eth:0.int_n +set_property LOC D21 [get_ports {eth_int_n}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_int_n}] + +# pcie_x1:0.rst_n +set_property LOC E18 [get_ports {pcie_x1_rst_n}] +set_property IOSTANDARD LVCMOS33 [get_ports {pcie_x1_rst_n}] + +# pcie_x1:0.clk_p +set_property LOC F10 [get_ports {pcie_x1_clk_p}] + +# pcie_x1:0.clk_n +set_property LOC E10 [get_ports {pcie_x1_clk_n}] + +# pcie_x1:0.rx_p +set_property LOC D11 [get_ports {pcie_x1_rx_p}] + +# pcie_x1:0.rx_n +set_property LOC C11 [get_ports {pcie_x1_rx_n}] + +# pcie_x1:0.tx_p +set_property LOC D5 [get_ports {pcie_x1_tx_p}] + +# pcie_x1:0.tx_n +set_property LOC C5 [get_ports {pcie_x1_tx_n}] + +# hdmi_in:0.clk_p +set_property LOC L19 [get_ports {hdmi_in0_clk_p}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_in0_clk_p}] + +# hdmi_in:0.clk_n +set_property LOC L20 [get_ports {hdmi_in0_clk_n}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_in0_clk_n}] + +# hdmi_in:0.data0_p +set_property LOC K21 [get_ports {hdmi_in0_data0_p}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_in0_data0_p}] + +# hdmi_in:0.data0_n +set_property LOC K22 [get_ports {hdmi_in0_data0_n}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_in0_data0_n}] + +# hdmi_in:0.data1_p +set_property LOC J20 [get_ports {hdmi_in0_data1_p}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_in0_data1_p}] + +# hdmi_in:0.data1_n +set_property LOC J21 [get_ports {hdmi_in0_data1_n}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_in0_data1_n}] + +# hdmi_in:0.data2_p +set_property LOC J22 [get_ports {hdmi_in0_data2_p}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_in0_data2_p}] + +# hdmi_in:0.data2_n +set_property LOC H22 [get_ports {hdmi_in0_data2_n}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_in0_data2_n}] + +# hdmi_in:0.scl +set_property LOC T18 [get_ports {hdmi_in0_scl}] +set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_in0_scl}] + +# hdmi_in:0.sda +set_property LOC V18 [get_ports {hdmi_in0_sda}] +set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_in0_sda}] + +# hdmi_in:0.sda_pu +set_property LOC G20 [get_ports {hdmi_in0_sda_pu}] +set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_in0_sda_pu}] + +# hdmi_in:0.sda_pd +set_property LOC F20 [get_ports {hdmi_in0_sda_pd}] +set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_in0_sda_pd}] + +# hdmi_out:0.clk_p +set_property LOC W19 [get_ports {hdmi_out0_clk_p}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_out0_clk_p}] + +# hdmi_out:0.clk_n +set_property LOC W20 [get_ports {hdmi_out0_clk_n}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_out0_clk_n}] + +# hdmi_out:0.data0_p +set_property LOC W21 [get_ports {hdmi_out0_data0_p}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_out0_data0_p}] + +# hdmi_out:0.data0_n +set_property LOC W22 [get_ports {hdmi_out0_data0_n}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_out0_data0_n}] + +# hdmi_out:0.data1_p +set_property LOC U20 [get_ports {hdmi_out0_data1_p}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_out0_data1_p}] + +# hdmi_out:0.data1_n +set_property LOC V20 [get_ports {hdmi_out0_data1_n}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_out0_data1_n}] + +# hdmi_out:0.data2_p +set_property LOC T21 [get_ports {hdmi_out0_data2_p}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_out0_data2_p}] + +# hdmi_out:0.data2_n +set_property LOC U21 [get_ports {hdmi_out0_data2_n}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_out0_data2_n}] + +################################################################################ +# Design constraints +################################################################################ + +################################################################################ +# Clock constraints +################################################################################ + + +create_clock -name clk50 -period 20.0 [get_nets clk50] + +create_clock -name dna_clk -period 20.0 [get_nets dna_clk] + +create_clock -name icap_clk -period 160.0 [get_nets icap_clk] + +create_clock -name eth_clocks_ref_clk -period 20.0 [get_nets eth_clocks_ref_clk] + +create_clock -name eth_rx_clk -period 20.0 [get_nets eth_rx_clk] + +create_clock -name eth_tx_clk -period 20.0 [get_nets eth_tx_clk] + +create_clock -name pcie_x1_clk_p -period 10.0 [get_nets pcie_x1_clk_p] + +create_clock -name hdmi_in0_clk_p -period 13.468 [get_nets hdmi_in0_clk_p] + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -asynchronous + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets pcie_clk]] -asynchronous + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets hdmi_in0_pix_clk]] -asynchronous + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets pix1p25x_clk]] -asynchronous + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets hdmi_in0_pix5x_clk]] -asynchronous + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets hdmi_out0_pix_clk]] -asynchronous + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets hdmi_out0_pix5x_clk]] -asynchronous + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets dna_clk]] -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -asynchronous + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets icap_clk]] -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -asynchronous + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets hdmi_in0_pix_clk]] -group [get_clocks -include_generated_clocks -of [get_nets pix1p25x_clk]] -asynchronous + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets hdmi_in0_pix_clk]] -group [get_clocks -include_generated_clocks -of [get_nets hdmi_in0_pix5x_clk]] -asynchronous + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets pix1p25x_clk]] -group [get_clocks -include_generated_clocks -of [get_nets hdmi_in0_pix5x_clk]] -asynchronous + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets hdmi_out0_pix_clk]] -group [get_clocks -include_generated_clocks -of [get_nets hdmi_out0_pix5x_clk]] -asynchronous + +################################################################################ +# False path constraints +################################################################################ + + +set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}] + +set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]] + +set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]] \ No newline at end of file diff --git a/src/netv2-pcie/edid_mem.init b/src/netv2-pcie/edid_mem.init new file mode 100644 index 00000000..a0c76ca4 --- /dev/null +++ b/src/netv2-pcie/edid_mem.init @@ -0,0 +1,256 @@ +0 +ff +ff +ff +ff +ff +ff +0 +5 +b8 +4e +54 +0 +0 +0 +0 +13 +1c +1 +3 +80 +35 +1e +78 +a +3d +85 +a6 +56 +4a +9a +24 +12 +50 +54 +0 +0 +0 +d1 +c0 +d1 +c0 +d1 +c0 +d1 +c0 +d1 +c0 +d1 +c0 +d1 +c0 +d1 +c0 +1 +1d +80 +18 +71 +38 +2d +40 +53 +2c +45 +0 +dd +c +11 +0 +0 +1e +2 +3a +80 +18 +71 +38 +2d +40 +53 +2c +45 +0 +dd +c +11 +0 +0 +1e +0 +0 +0 +fd +0 +38 +3d +1e +53 +f +0 +a +20 +20 +20 +20 +20 +20 +0 +0 +0 +fc +0 +41 +6c +70 +68 +61 +6d +61 +78 +a +20 +20 +20 +20 +1 +3e +2 +3 +21 +f1 +4e +90 +4 +3 +1 +14 +12 +5 +1f +10 +13 +0 +0 +0 +0 +23 +9 +7 +7 +83 +1 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+153c +5dc0 +5dcc +6 +1448 +5de0 +5dec +6 +cd18c6ea diff --git a/src/netv2-pcie/mem_1.init b/src/netv2-pcie/mem_1.init new file mode 100644 index 00000000..e69de29b diff --git a/src/netv2-pcie/mem_2.init b/src/netv2-pcie/mem_2.init new file mode 100644 index 00000000..82380c68 --- /dev/null +++ b/src/netv2-pcie/mem_2.init @@ -0,0 +1,36 @@ +4e +65 +54 +56 +32 +20 +4c +69 +74 +65 +58 +20 +53 +6f +43 +20 +32 +30 +32 +30 +2d +31 +31 +2d +30 +36 +20 +31 +31 +3a +33 +36 +3a +32 +34 +0 diff --git a/src/netv2-pcie/top.v b/src/netv2-pcie/top.v new file mode 100644 index 00000000..8bafb3b6 --- /dev/null +++ b/src/netv2-pcie/top.v @@ -0,0 +1,41181 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by Migen (--------) & LiteX (c0ba03ef) on 2020-11-06 11:36:30 +//-------------------------------------------------------------------------------- +module top( + (* dont_touch = "true" *) input wire clk50, + output wire flash_cs_n, + output wire flash_mosi, + input wire flash_miso, + input wire flash_wp, + input wire flash_hold, + output wire [13:0] ddram_a, + output wire [2:0] ddram_ba, + output wire ddram_ras_n, + output wire ddram_cas_n, + output wire ddram_we_n, + output wire [3:0] ddram_dm, + inout wire [31:0] ddram_dq, + inout wire [3:0] ddram_dqs_p, + inout wire [3:0] ddram_dqs_n, + output wire ddram_clk_p, + output wire ddram_clk_n, + output wire ddram_cke, + output wire ddram_odt, + output wire ddram_reset_n, + output wire ddram_cs_n, + (* dont_touch = "true" *) output wire eth_clocks_ref_clk, + output wire eth_rst_n, + input wire [1:0] eth_rx_data, + input wire eth_crs_dv, + output reg eth_tx_en, + output reg [1:0] eth_tx_data, + output wire eth_mdc, + inout wire eth_mdio, + input wire eth_rx_er, + input wire eth_int_n, + input wire pcie_x1_rst_n, + (* dont_touch = "true" *) input wire pcie_x1_clk_p, + input wire pcie_x1_clk_n, + input wire pcie_x1_rx_p, + input wire pcie_x1_rx_n, + output wire pcie_x1_tx_p, + output wire pcie_x1_tx_n, + (* dont_touch = "true" *) input wire hdmi_in0_clk_p, + input wire hdmi_in0_clk_n, + input wire hdmi_in0_data0_p, + input wire hdmi_in0_data0_n, + input wire hdmi_in0_data1_p, + input wire hdmi_in0_data1_n, + input wire hdmi_in0_data2_p, + input wire hdmi_in0_data2_n, + input wire hdmi_in0_scl, + input wire hdmi_in0_sda, + output wire hdmi_in0_sda_pu, + output wire hdmi_in0_sda_pd, + output wire hdmi_out0_clk_p, + output wire hdmi_out0_clk_n, + output wire hdmi_out0_data0_p, + output wire hdmi_out0_data0_n, + output wire hdmi_out0_data1_p, + output wire hdmi_out0_data1_n, + output wire hdmi_out0_data2_p, + output wire hdmi_out0_data2_n +); + +reg netv2_soccontroller_reset_storage = 1'd0; +reg netv2_soccontroller_reset_re = 1'd0; +reg [31:0] netv2_soccontroller_scratch_storage = 32'd305419896; +reg netv2_soccontroller_scratch_re = 1'd0; +wire [31:0] netv2_soccontroller_bus_errors_status; +wire netv2_soccontroller_bus_errors_we; +wire netv2_soccontroller_bus_errors_re; +wire netv2_soccontroller_reset; +wire netv2_soccontroller_bus_error; +reg [31:0] netv2_soccontroller_bus_errors = 32'd0; +wire netv2_cpu_reset; +reg [31:0] netv2_cpu_interrupt = 32'd0; +wire [29:0] netv2_cpu_ibus_adr; +wire [31:0] netv2_cpu_ibus_dat_w; +wire [31:0] netv2_cpu_ibus_dat_r; +wire [3:0] netv2_cpu_ibus_sel; +wire netv2_cpu_ibus_cyc; +wire netv2_cpu_ibus_stb; +wire netv2_cpu_ibus_ack; +wire netv2_cpu_ibus_we; +wire [2:0] netv2_cpu_ibus_cti; +wire [1:0] netv2_cpu_ibus_bte; +wire netv2_cpu_ibus_err; +wire [29:0] netv2_cpu_dbus_adr; +wire [31:0] netv2_cpu_dbus_dat_w; +wire [31:0] netv2_cpu_dbus_dat_r; +wire [3:0] netv2_cpu_dbus_sel; +wire netv2_cpu_dbus_cyc; +wire netv2_cpu_dbus_stb; +wire netv2_cpu_dbus_ack; +wire netv2_cpu_dbus_we; +wire [2:0] netv2_cpu_dbus_cti; +wire [1:0] netv2_cpu_dbus_bte; +wire netv2_cpu_dbus_err; +reg [31:0] netv2_vexriscv = 32'd0; +wire [29:0] netv2_netv2_ram_bus_adr; +wire [31:0] netv2_netv2_ram_bus_dat_w; +wire [31:0] netv2_netv2_ram_bus_dat_r; +wire [3:0] netv2_netv2_ram_bus_sel; +wire netv2_netv2_ram_bus_cyc; +wire netv2_netv2_ram_bus_stb; +reg netv2_netv2_ram_bus_ack = 1'd0; +wire netv2_netv2_ram_bus_we; +wire [2:0] netv2_netv2_ram_bus_cti; +wire [1:0] netv2_netv2_ram_bus_bte; +reg netv2_netv2_ram_bus_err = 1'd0; +wire [12:0] netv2_netv2_adr; +wire [31:0] netv2_netv2_dat_r; +wire [29:0] netv2_ram_bus_ram_bus_adr; +wire [31:0] netv2_ram_bus_ram_bus_dat_w; +wire [31:0] netv2_ram_bus_ram_bus_dat_r; +wire [3:0] netv2_ram_bus_ram_bus_sel; +wire netv2_ram_bus_ram_bus_cyc; +wire netv2_ram_bus_ram_bus_stb; +reg netv2_ram_bus_ram_bus_ack = 1'd0; +wire netv2_ram_bus_ram_bus_we; +wire [2:0] netv2_ram_bus_ram_bus_cti; +wire [1:0] netv2_ram_bus_ram_bus_bte; +reg netv2_ram_bus_ram_bus_err = 1'd0; +wire [10:0] netv2_ram_adr; +wire [31:0] netv2_ram_dat_r; +reg [3:0] netv2_ram_we = 4'd0; +wire [31:0] netv2_ram_dat_w; +wire netv2_uartcrossover_rxtx_re; +wire [7:0] netv2_uartcrossover_rxtx_r; +wire netv2_uartcrossover_rxtx_we; +wire [7:0] netv2_uartcrossover_rxtx_w; +wire netv2_uartcrossover_txfull_status; +wire netv2_uartcrossover_txfull_we; +wire netv2_uartcrossover_txfull_re; +wire netv2_uartcrossover_rxempty_status; +wire netv2_uartcrossover_rxempty_we; +wire netv2_uartcrossover_rxempty_re; +wire netv2_uartcrossover_irq; +wire netv2_uartcrossover_tx_status; +reg netv2_uartcrossover_tx_pending = 1'd0; +wire netv2_uartcrossover_tx_trigger; +reg netv2_uartcrossover_tx_clear = 1'd0; +reg netv2_uartcrossover_tx_old_trigger = 1'd0; +wire netv2_uartcrossover_rx_status; +reg netv2_uartcrossover_rx_pending = 1'd0; +wire netv2_uartcrossover_rx_trigger; +reg netv2_uartcrossover_rx_clear = 1'd0; +reg netv2_uartcrossover_rx_old_trigger = 1'd0; +wire netv2_uartcrossover_eventmanager_status_re; +wire [1:0] netv2_uartcrossover_eventmanager_status_r; +wire netv2_uartcrossover_eventmanager_status_we; +reg [1:0] netv2_uartcrossover_eventmanager_status_w = 2'd0; +wire netv2_uartcrossover_eventmanager_pending_re; +wire [1:0] netv2_uartcrossover_eventmanager_pending_r; +wire netv2_uartcrossover_eventmanager_pending_we; +reg [1:0] netv2_uartcrossover_eventmanager_pending_w = 2'd0; +reg [1:0] netv2_uartcrossover_eventmanager_storage = 2'd0; +reg netv2_uartcrossover_eventmanager_re = 1'd0; +wire netv2_uartcrossover_txempty_status; +wire netv2_uartcrossover_txempty_we; +wire netv2_uartcrossover_txempty_re; +wire netv2_uartcrossover_rxfull_status; +wire netv2_uartcrossover_rxfull_we; +wire netv2_uartcrossover_rxfull_re; +wire netv2_uartcrossover_uartcrossover_sink_valid; +wire netv2_uartcrossover_uartcrossover_sink_ready; +wire netv2_uartcrossover_uartcrossover_sink_first; +wire netv2_uartcrossover_uartcrossover_sink_last; +wire [7:0] netv2_uartcrossover_uartcrossover_sink_payload_data; +wire netv2_uartcrossover_uartcrossover_source_valid; +wire netv2_uartcrossover_uartcrossover_source_ready; +wire netv2_uartcrossover_uartcrossover_source_first; +wire netv2_uartcrossover_uartcrossover_source_last; +wire [7:0] netv2_uartcrossover_uartcrossover_source_payload_data; +wire netv2_uartcrossover_tx_fifo_sink_valid; +wire netv2_uartcrossover_tx_fifo_sink_ready; +reg netv2_uartcrossover_tx_fifo_sink_first = 1'd0; +reg netv2_uartcrossover_tx_fifo_sink_last = 1'd0; +wire [7:0] netv2_uartcrossover_tx_fifo_sink_payload_data; +wire netv2_uartcrossover_tx_fifo_source_valid; +wire netv2_uartcrossover_tx_fifo_source_ready; +wire netv2_uartcrossover_tx_fifo_source_first; +wire netv2_uartcrossover_tx_fifo_source_last; +wire [7:0] netv2_uartcrossover_tx_fifo_source_payload_data; +wire netv2_uartcrossover_tx_fifo_re; +reg netv2_uartcrossover_tx_fifo_readable = 1'd0; +wire netv2_uartcrossover_tx_fifo_syncfifo_we; +wire netv2_uartcrossover_tx_fifo_syncfifo_writable; +wire netv2_uartcrossover_tx_fifo_syncfifo_re; +wire netv2_uartcrossover_tx_fifo_syncfifo_readable; +wire [9:0] netv2_uartcrossover_tx_fifo_syncfifo_din; +wire [9:0] netv2_uartcrossover_tx_fifo_syncfifo_dout; +reg [4:0] netv2_uartcrossover_tx_fifo_level0 = 5'd0; +reg netv2_uartcrossover_tx_fifo_replace = 1'd0; +reg [3:0] netv2_uartcrossover_tx_fifo_produce = 4'd0; +reg [3:0] netv2_uartcrossover_tx_fifo_consume = 4'd0; +reg [3:0] netv2_uartcrossover_tx_fifo_wrport_adr = 4'd0; +wire [9:0] netv2_uartcrossover_tx_fifo_wrport_dat_r; +wire netv2_uartcrossover_tx_fifo_wrport_we; +wire [9:0] netv2_uartcrossover_tx_fifo_wrport_dat_w; +wire netv2_uartcrossover_tx_fifo_do_read; +wire [3:0] netv2_uartcrossover_tx_fifo_rdport_adr; +wire [9:0] netv2_uartcrossover_tx_fifo_rdport_dat_r; +wire netv2_uartcrossover_tx_fifo_rdport_re; +wire [4:0] netv2_uartcrossover_tx_fifo_level1; +wire [7:0] netv2_uartcrossover_tx_fifo_fifo_in_payload_data; +wire netv2_uartcrossover_tx_fifo_fifo_in_first; +wire netv2_uartcrossover_tx_fifo_fifo_in_last; +wire [7:0] netv2_uartcrossover_tx_fifo_fifo_out_payload_data; +wire netv2_uartcrossover_tx_fifo_fifo_out_first; +wire netv2_uartcrossover_tx_fifo_fifo_out_last; +wire netv2_uartcrossover_rx_fifo_sink_valid; +wire netv2_uartcrossover_rx_fifo_sink_ready; +wire netv2_uartcrossover_rx_fifo_sink_first; +wire netv2_uartcrossover_rx_fifo_sink_last; +wire [7:0] netv2_uartcrossover_rx_fifo_sink_payload_data; +wire netv2_uartcrossover_rx_fifo_source_valid; +wire netv2_uartcrossover_rx_fifo_source_ready; +wire netv2_uartcrossover_rx_fifo_source_first; +wire netv2_uartcrossover_rx_fifo_source_last; +wire [7:0] netv2_uartcrossover_rx_fifo_source_payload_data; +wire netv2_uartcrossover_rx_fifo_re; +reg netv2_uartcrossover_rx_fifo_readable = 1'd0; +wire netv2_uartcrossover_rx_fifo_syncfifo_we; +wire netv2_uartcrossover_rx_fifo_syncfifo_writable; +wire netv2_uartcrossover_rx_fifo_syncfifo_re; +wire netv2_uartcrossover_rx_fifo_syncfifo_readable; +wire [9:0] netv2_uartcrossover_rx_fifo_syncfifo_din; +wire [9:0] netv2_uartcrossover_rx_fifo_syncfifo_dout; +reg [4:0] netv2_uartcrossover_rx_fifo_level0 = 5'd0; +reg netv2_uartcrossover_rx_fifo_replace = 1'd0; +reg [3:0] netv2_uartcrossover_rx_fifo_produce = 4'd0; +reg [3:0] netv2_uartcrossover_rx_fifo_consume = 4'd0; +reg [3:0] netv2_uartcrossover_rx_fifo_wrport_adr = 4'd0; +wire [9:0] netv2_uartcrossover_rx_fifo_wrport_dat_r; +wire netv2_uartcrossover_rx_fifo_wrport_we; +wire [9:0] netv2_uartcrossover_rx_fifo_wrport_dat_w; +wire netv2_uartcrossover_rx_fifo_do_read; +wire [3:0] netv2_uartcrossover_rx_fifo_rdport_adr; +wire [9:0] netv2_uartcrossover_rx_fifo_rdport_dat_r; +wire netv2_uartcrossover_rx_fifo_rdport_re; +wire [4:0] netv2_uartcrossover_rx_fifo_level1; +wire [7:0] netv2_uartcrossover_rx_fifo_fifo_in_payload_data; +wire netv2_uartcrossover_rx_fifo_fifo_in_first; +wire netv2_uartcrossover_rx_fifo_fifo_in_last; +wire [7:0] netv2_uartcrossover_rx_fifo_fifo_out_payload_data; +wire netv2_uartcrossover_rx_fifo_fifo_out_first; +wire netv2_uartcrossover_rx_fifo_fifo_out_last; +wire netv2_xover_rxtx_re; +wire [7:0] netv2_xover_rxtx_r; +wire netv2_xover_rxtx_we; +wire [7:0] netv2_xover_rxtx_w; +wire netv2_xover_txfull_status; +wire netv2_xover_txfull_we; +wire netv2_xover_txfull_re; +wire netv2_xover_rxempty_status; +wire netv2_xover_rxempty_we; +wire netv2_xover_rxempty_re; +wire netv2_xover_irq; +wire netv2_xover_tx_status; +reg netv2_xover_tx_pending = 1'd0; +wire netv2_xover_tx_trigger; +reg netv2_xover_tx_clear = 1'd0; +reg netv2_xover_tx_old_trigger = 1'd0; +wire netv2_xover_rx_status; +reg netv2_xover_rx_pending = 1'd0; +wire netv2_xover_rx_trigger; +reg netv2_xover_rx_clear = 1'd0; +reg netv2_xover_rx_old_trigger = 1'd0; +wire netv2_xover_eventmanager_status_re; +wire [1:0] netv2_xover_eventmanager_status_r; +wire netv2_xover_eventmanager_status_we; +reg [1:0] netv2_xover_eventmanager_status_w = 2'd0; +wire netv2_xover_eventmanager_pending_re; +wire [1:0] netv2_xover_eventmanager_pending_r; +wire netv2_xover_eventmanager_pending_we; +reg [1:0] netv2_xover_eventmanager_pending_w = 2'd0; +reg [1:0] netv2_xover_eventmanager_storage = 2'd0; +reg netv2_xover_eventmanager_re = 1'd0; +wire netv2_xover_txempty_status; +wire netv2_xover_txempty_we; +wire netv2_xover_txempty_re; +wire netv2_xover_rxfull_status; +wire netv2_xover_rxfull_we; +wire netv2_xover_rxfull_re; +wire netv2_xover_uart_sink_valid; +wire netv2_xover_uart_sink_ready; +wire netv2_xover_uart_sink_first; +wire netv2_xover_uart_sink_last; +wire [7:0] netv2_xover_uart_sink_payload_data; +wire netv2_xover_uart_source_valid; +wire netv2_xover_uart_source_ready; +wire netv2_xover_uart_source_first; +wire netv2_xover_uart_source_last; +wire [7:0] netv2_xover_uart_source_payload_data; +wire netv2_xover_tx_fifo_sink_valid; +wire netv2_xover_tx_fifo_sink_ready; +reg netv2_xover_tx_fifo_sink_first = 1'd0; +reg netv2_xover_tx_fifo_sink_last = 1'd0; +wire [7:0] netv2_xover_tx_fifo_sink_payload_data; +reg netv2_xover_tx_fifo_source_valid = 1'd0; +wire netv2_xover_tx_fifo_source_ready; +reg netv2_xover_tx_fifo_source_first = 1'd0; +reg netv2_xover_tx_fifo_source_last = 1'd0; +reg [7:0] netv2_xover_tx_fifo_source_payload_data = 8'd0; +wire netv2_xover_rx_fifo_sink_valid; +wire netv2_xover_rx_fifo_sink_ready; +wire netv2_xover_rx_fifo_sink_first; +wire netv2_xover_rx_fifo_sink_last; +wire [7:0] netv2_xover_rx_fifo_sink_payload_data; +reg netv2_xover_rx_fifo_source_valid = 1'd0; +wire netv2_xover_rx_fifo_source_ready; +reg netv2_xover_rx_fifo_source_first = 1'd0; +reg netv2_xover_rx_fifo_source_last = 1'd0; +reg [7:0] netv2_xover_rx_fifo_source_payload_data = 8'd0; +reg [31:0] netv2_load_storage = 32'd0; +reg netv2_load_re = 1'd0; +reg [31:0] netv2_reload_storage = 32'd0; +reg netv2_reload_re = 1'd0; +reg netv2_en_storage = 1'd0; +reg netv2_en_re = 1'd0; +reg netv2_update_value_storage = 1'd0; +reg netv2_update_value_re = 1'd0; +reg [31:0] netv2_value_status = 32'd0; +wire netv2_value_we; +wire netv2_value_re; +wire netv2_irq; +wire netv2_zero_status; +reg netv2_zero_pending = 1'd0; +wire netv2_zero_trigger; +reg netv2_zero_clear = 1'd0; +reg netv2_zero_old_trigger = 1'd0; +wire netv2_eventmanager_status_re; +wire netv2_eventmanager_status_r; +wire netv2_eventmanager_status_we; +wire netv2_eventmanager_status_w; +wire netv2_eventmanager_pending_re; +wire netv2_eventmanager_pending_r; +wire netv2_eventmanager_pending_we; +wire netv2_eventmanager_pending_w; +reg netv2_eventmanager_storage = 1'd0; +reg netv2_eventmanager_re = 1'd0; +reg [31:0] netv2_value = 32'd0; +wire crg_reset_re; +wire crg_reset_r; +wire crg_reset_we; +reg crg_reset_w = 1'd0; +(* dont_touch = "true" *) wire sys_clk; +wire sys_rst; +wire sys4x_clk; +wire sys4x_dqs_clk; +wire clk200_clk; +wire clk200_rst; +wire clk100_clk; +wire clk100_rst; +wire eth_clk; +wire eth_rst; +reg crg_reset = 1'd0; +wire crg_locked; +wire crg_clkin; +wire crg_clkout0; +wire crg_clkout_buf0; +wire crg_clkout1; +wire crg_clkout_buf1; +wire crg_clkout2; +wire crg_clkout_buf2; +wire crg_clkout3; +wire crg_clkout_buf3; +wire crg_clkout4; +wire crg_clkout_buf4; +wire crg_clkout5; +wire crg_clkout_buf5; +reg [3:0] crg_reset_counter = 4'd15; +reg crg_ic_reset = 1'd1; +reg [56:0] dna_status = 57'd0; +wire dna_we; +wire dna_re; +wire dna_do; +reg [6:0] dna_count = 7'd0; +(* dont_touch = "true" *) wire dna_clk; +reg [11:0] xadc_temperature_status = 12'd0; +wire xadc_temperature_we; +wire xadc_temperature_re; +reg [11:0] xadc_vccint_status = 12'd0; +wire xadc_vccint_we; +wire xadc_vccint_re; +reg [11:0] xadc_vccaux_status = 12'd0; +wire xadc_vccaux_we; +wire xadc_vccaux_re; +reg [11:0] xadc_vccbram_status = 12'd0; +wire xadc_vccbram_we; +wire xadc_vccbram_re; +reg xadc_eoc_status = 1'd0; +wire xadc_eoc_we; +wire xadc_eoc_re; +reg xadc_eos_status = 1'd0; +wire xadc_eos_we; +wire xadc_eos_re; +wire [7:0] xadc_alarm; +wire xadc_ot; +wire xadc_busy; +wire [6:0] xadc_channel; +wire xadc_eoc; +wire xadc_eos; +reg xadc_dwe = 1'd0; +reg xadc_den = 1'd0; +wire xadc_drdy; +reg [6:0] xadc_dadr = 7'd0; +reg [15:0] xadc_di = 16'd0; +wire [15:0] xadc_do; +reg xadc_drp_en = 1'd0; +wire [4:0] icap_addr; +wire [31:0] icap_data; +wire icap_send; +reg icap_done = 1'd0; +(* dont_touch = "true" *) reg icap_clk = 1'd0; +reg icap_rst = 1'd0; +reg [3:0] icap_icap_clk_counter = 4'd0; +wire icap_i; +wire icap_o; +reg icap_toggle_i = 1'd0; +wire icap_toggle_o; +reg icap_toggle_o_r = 1'd0; +reg icap_csib = 1'd1; +reg [31:0] icap__i = 32'd0; +reg [3:0] icap_counter = 4'd0; +reg [4:0] icap_addr_storage = 5'd0; +reg icap_addr_re = 1'd0; +reg [31:0] icap_data_storage = 32'd0; +reg icap_data_re = 1'd0; +reg icap_send_storage = 1'd0; +reg icap_send_re = 1'd0; +wire icap_done_status; +wire icap_done_we; +wire icap_done_re; +reg flash_pads_clk = 1'd0; +reg flash_pads_cs_n = 1'd0; +reg flash_pads_mosi = 1'd0; +wire flash_pads_miso; +wire flash_start0; +wire [7:0] flash_length0; +reg flash_done0 = 1'd0; +reg flash_irq = 1'd0; +wire [39:0] flash_mosi1; +reg [39:0] flash_miso1 = 40'd0; +wire flash_cs; +wire flash_loopback; +reg [15:0] flash_clk_divider0 = 16'd4; +reg flash_start1 = 1'd0; +wire [7:0] flash_length1; +reg [15:0] flash_control_storage = 16'd0; +reg flash_control_re = 1'd0; +wire flash_done1; +wire flash_status_status; +wire flash_status_we; +wire flash_status_re; +reg [39:0] flash_mosi_storage = 40'd0; +reg flash_mosi_re = 1'd0; +wire [39:0] flash_miso_status; +wire flash_miso_we; +wire flash_miso_re; +wire flash_sel; +reg flash_cs_storage = 1'd1; +reg flash_cs_re = 1'd0; +reg flash_loopback_storage = 1'd0; +reg flash_loopback_re = 1'd0; +reg flash_clk_enable = 1'd0; +reg flash_cs_enable = 1'd0; +reg [5:0] flash_count = 6'd0; +reg flash_mosi_latch = 1'd0; +reg flash_miso_latch = 1'd0; +reg [15:0] flash_clk_divider1 = 16'd0; +wire flash_clk_rise; +wire flash_clk_fall; +reg [39:0] flash_mosi_data = 40'd0; +reg [5:0] flash_mosi_sel = 6'd0; +reg [39:0] flash_miso_data = 40'd0; +reg a7ddrphy_rst_storage = 1'd0; +reg a7ddrphy_rst_re = 1'd0; +reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8; +reg a7ddrphy_half_sys8x_taps_re = 1'd0; +reg a7ddrphy_wlevel_en_storage = 1'd0; +reg a7ddrphy_wlevel_en_re = 1'd0; +wire a7ddrphy_wlevel_strobe_re; +wire a7ddrphy_wlevel_strobe_r; +wire a7ddrphy_wlevel_strobe_we; +reg a7ddrphy_wlevel_strobe_w = 1'd0; +reg [3:0] a7ddrphy_dly_sel_storage = 4'd0; +reg a7ddrphy_dly_sel_re = 1'd0; +wire a7ddrphy_rdly_dq_rst_re; +wire a7ddrphy_rdly_dq_rst_r; +wire a7ddrphy_rdly_dq_rst_we; +reg a7ddrphy_rdly_dq_rst_w = 1'd0; +wire a7ddrphy_rdly_dq_inc_re; +wire a7ddrphy_rdly_dq_inc_r; +wire a7ddrphy_rdly_dq_inc_we; +reg a7ddrphy_rdly_dq_inc_w = 1'd0; +wire a7ddrphy_rdly_dq_bitslip_rst_re; +wire a7ddrphy_rdly_dq_bitslip_rst_r; +wire a7ddrphy_rdly_dq_bitslip_rst_we; +reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +wire a7ddrphy_rdly_dq_bitslip_re; +wire a7ddrphy_rdly_dq_bitslip_r; +wire a7ddrphy_rdly_dq_bitslip_we; +reg a7ddrphy_rdly_dq_bitslip_w = 1'd0; +wire a7ddrphy_wdly_dq_bitslip_rst_re; +wire a7ddrphy_wdly_dq_bitslip_rst_r; +wire a7ddrphy_wdly_dq_bitslip_rst_we; +reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +wire a7ddrphy_wdly_dq_bitslip_re; +wire a7ddrphy_wdly_dq_bitslip_r; +wire a7ddrphy_wdly_dq_bitslip_we; +reg a7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg [1:0] a7ddrphy_rdphase_storage = 2'd2; +reg a7ddrphy_rdphase_re = 1'd0; +reg [1:0] a7ddrphy_wrphase_storage = 2'd3; +reg a7ddrphy_wrphase_re = 1'd0; +wire [13:0] a7ddrphy_dfi_p0_address; +wire [2:0] a7ddrphy_dfi_p0_bank; +wire a7ddrphy_dfi_p0_cas_n; +wire a7ddrphy_dfi_p0_cs_n; +wire a7ddrphy_dfi_p0_ras_n; +wire a7ddrphy_dfi_p0_we_n; +wire a7ddrphy_dfi_p0_cke; +wire a7ddrphy_dfi_p0_odt; +wire a7ddrphy_dfi_p0_reset_n; +wire a7ddrphy_dfi_p0_act_n; +wire [63:0] a7ddrphy_dfi_p0_wrdata; +wire a7ddrphy_dfi_p0_wrdata_en; +wire [7:0] a7ddrphy_dfi_p0_wrdata_mask; +wire a7ddrphy_dfi_p0_rddata_en; +reg [63:0] a7ddrphy_dfi_p0_rddata = 64'd0; +wire a7ddrphy_dfi_p0_rddata_valid; +wire [13:0] a7ddrphy_dfi_p1_address; +wire [2:0] a7ddrphy_dfi_p1_bank; +wire a7ddrphy_dfi_p1_cas_n; +wire a7ddrphy_dfi_p1_cs_n; +wire a7ddrphy_dfi_p1_ras_n; +wire a7ddrphy_dfi_p1_we_n; +wire a7ddrphy_dfi_p1_cke; +wire a7ddrphy_dfi_p1_odt; +wire a7ddrphy_dfi_p1_reset_n; +wire a7ddrphy_dfi_p1_act_n; +wire [63:0] a7ddrphy_dfi_p1_wrdata; +wire a7ddrphy_dfi_p1_wrdata_en; +wire [7:0] a7ddrphy_dfi_p1_wrdata_mask; +wire a7ddrphy_dfi_p1_rddata_en; +reg [63:0] a7ddrphy_dfi_p1_rddata = 64'd0; +wire a7ddrphy_dfi_p1_rddata_valid; +wire [13:0] a7ddrphy_dfi_p2_address; +wire [2:0] a7ddrphy_dfi_p2_bank; +wire a7ddrphy_dfi_p2_cas_n; +wire a7ddrphy_dfi_p2_cs_n; +wire a7ddrphy_dfi_p2_ras_n; +wire a7ddrphy_dfi_p2_we_n; +wire a7ddrphy_dfi_p2_cke; +wire a7ddrphy_dfi_p2_odt; +wire a7ddrphy_dfi_p2_reset_n; +wire a7ddrphy_dfi_p2_act_n; +wire [63:0] a7ddrphy_dfi_p2_wrdata; +wire a7ddrphy_dfi_p2_wrdata_en; +wire [7:0] a7ddrphy_dfi_p2_wrdata_mask; +wire a7ddrphy_dfi_p2_rddata_en; +reg [63:0] a7ddrphy_dfi_p2_rddata = 64'd0; +wire a7ddrphy_dfi_p2_rddata_valid; +wire [13:0] a7ddrphy_dfi_p3_address; +wire [2:0] a7ddrphy_dfi_p3_bank; +wire a7ddrphy_dfi_p3_cas_n; +wire a7ddrphy_dfi_p3_cs_n; +wire a7ddrphy_dfi_p3_ras_n; +wire a7ddrphy_dfi_p3_we_n; +wire a7ddrphy_dfi_p3_cke; +wire a7ddrphy_dfi_p3_odt; +wire a7ddrphy_dfi_p3_reset_n; +wire a7ddrphy_dfi_p3_act_n; +wire [63:0] a7ddrphy_dfi_p3_wrdata; +wire a7ddrphy_dfi_p3_wrdata_en; +wire [7:0] a7ddrphy_dfi_p3_wrdata_mask; +wire a7ddrphy_dfi_p3_rddata_en; +reg [63:0] a7ddrphy_dfi_p3_rddata = 64'd0; +wire a7ddrphy_dfi_p3_rddata_valid; +wire a7ddrphy_sd_clk_se_nodelay; +reg a7ddrphy_dqs_oe = 1'd0; +wire a7ddrphy_dqs_preamble; +wire a7ddrphy_dqs_postamble; +wire a7ddrphy_dqs_oe_delay_tappeddelayline; +reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg a7ddrphy_dqspattern0 = 1'd0; +reg a7ddrphy_dqspattern1 = 1'd0; +reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0; +wire a7ddrphy_dqs_o_no_delay0; +wire a7ddrphy_dqs_t0; +reg [7:0] a7ddrphy_bitslip00 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0; +wire a7ddrphy0; +wire a7ddrphy_dqs_o_no_delay1; +wire a7ddrphy_dqs_t1; +reg [7:0] a7ddrphy_bitslip10 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0; +wire a7ddrphy1; +wire a7ddrphy_dqs_o_no_delay2; +wire a7ddrphy_dqs_t2; +reg [7:0] a7ddrphy_bitslip20 = 8'd0; +reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0; +wire a7ddrphy2; +wire a7ddrphy_dqs_o_no_delay3; +wire a7ddrphy_dqs_t3; +reg [7:0] a7ddrphy_bitslip30 = 8'd0; +reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0; +wire a7ddrphy3; +reg [7:0] a7ddrphy_bitslip01 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0; +reg [7:0] a7ddrphy_bitslip11 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0; +reg [7:0] a7ddrphy_bitslip21 = 8'd0; +reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0; +reg [7:0] a7ddrphy_bitslip31 = 8'd0; +reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0; +wire a7ddrphy_dq_oe; +wire a7ddrphy_dq_oe_delay_tappeddelayline; +reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire a7ddrphy_dq_o_nodelay0; +wire a7ddrphy_dq_i_nodelay0; +wire a7ddrphy_dq_i_delayed0; +wire a7ddrphy_dq_t0; +reg [7:0] a7ddrphy_bitslip02 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0; +wire [7:0] a7ddrphy_bitslip03; +reg [7:0] a7ddrphy_bitslip04 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0; +wire a7ddrphy_dq_o_nodelay1; +wire a7ddrphy_dq_i_nodelay1; +wire a7ddrphy_dq_i_delayed1; +wire a7ddrphy_dq_t1; +reg [7:0] a7ddrphy_bitslip12 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0; +wire [7:0] a7ddrphy_bitslip13; +reg [7:0] a7ddrphy_bitslip14 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0; +wire a7ddrphy_dq_o_nodelay2; +wire a7ddrphy_dq_i_nodelay2; +wire a7ddrphy_dq_i_delayed2; +wire a7ddrphy_dq_t2; +reg [7:0] a7ddrphy_bitslip22 = 8'd0; +reg [2:0] a7ddrphy_bitslip2_value2 = 3'd7; +reg [15:0] a7ddrphy_bitslip2_r2 = 16'd0; +wire [7:0] a7ddrphy_bitslip23; +reg [7:0] a7ddrphy_bitslip24 = 8'd0; +reg [2:0] a7ddrphy_bitslip2_value3 = 3'd7; +reg [15:0] a7ddrphy_bitslip2_r3 = 16'd0; +wire a7ddrphy_dq_o_nodelay3; +wire a7ddrphy_dq_i_nodelay3; +wire a7ddrphy_dq_i_delayed3; +wire a7ddrphy_dq_t3; +reg [7:0] a7ddrphy_bitslip32 = 8'd0; +reg [2:0] a7ddrphy_bitslip3_value2 = 3'd7; +reg [15:0] a7ddrphy_bitslip3_r2 = 16'd0; +wire [7:0] a7ddrphy_bitslip33; +reg [7:0] a7ddrphy_bitslip34 = 8'd0; +reg [2:0] a7ddrphy_bitslip3_value3 = 3'd7; +reg [15:0] a7ddrphy_bitslip3_r3 = 16'd0; +wire a7ddrphy_dq_o_nodelay4; +wire a7ddrphy_dq_i_nodelay4; +wire a7ddrphy_dq_i_delayed4; +wire a7ddrphy_dq_t4; +reg [7:0] a7ddrphy_bitslip40 = 8'd0; +reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip41; +reg [7:0] a7ddrphy_bitslip42 = 8'd0; +reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay5; +wire a7ddrphy_dq_i_nodelay5; +wire a7ddrphy_dq_i_delayed5; +wire a7ddrphy_dq_t5; +reg [7:0] a7ddrphy_bitslip50 = 8'd0; +reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip51; +reg [7:0] a7ddrphy_bitslip52 = 8'd0; +reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay6; +wire a7ddrphy_dq_i_nodelay6; +wire a7ddrphy_dq_i_delayed6; +wire a7ddrphy_dq_t6; +reg [7:0] a7ddrphy_bitslip60 = 8'd0; +reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip61; +reg [7:0] a7ddrphy_bitslip62 = 8'd0; +reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay7; +wire a7ddrphy_dq_i_nodelay7; +wire a7ddrphy_dq_i_delayed7; +wire a7ddrphy_dq_t7; +reg [7:0] a7ddrphy_bitslip70 = 8'd0; +reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip71; +reg [7:0] a7ddrphy_bitslip72 = 8'd0; +reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay8; +wire a7ddrphy_dq_i_nodelay8; +wire a7ddrphy_dq_i_delayed8; +wire a7ddrphy_dq_t8; +reg [7:0] a7ddrphy_bitslip80 = 8'd0; +reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip81; +reg [7:0] a7ddrphy_bitslip82 = 8'd0; +reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay9; +wire a7ddrphy_dq_i_nodelay9; +wire a7ddrphy_dq_i_delayed9; +wire a7ddrphy_dq_t9; +reg [7:0] a7ddrphy_bitslip90 = 8'd0; +reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip91; +reg [7:0] a7ddrphy_bitslip92 = 8'd0; +reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay10; +wire a7ddrphy_dq_i_nodelay10; +wire a7ddrphy_dq_i_delayed10; +wire a7ddrphy_dq_t10; +reg [7:0] a7ddrphy_bitslip100 = 8'd0; +reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip101; +reg [7:0] a7ddrphy_bitslip102 = 8'd0; +reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay11; +wire a7ddrphy_dq_i_nodelay11; +wire a7ddrphy_dq_i_delayed11; +wire a7ddrphy_dq_t11; +reg [7:0] a7ddrphy_bitslip110 = 8'd0; +reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip111; +reg [7:0] a7ddrphy_bitslip112 = 8'd0; +reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay12; +wire a7ddrphy_dq_i_nodelay12; +wire a7ddrphy_dq_i_delayed12; +wire a7ddrphy_dq_t12; +reg [7:0] a7ddrphy_bitslip120 = 8'd0; +reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip121; +reg [7:0] a7ddrphy_bitslip122 = 8'd0; +reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay13; +wire a7ddrphy_dq_i_nodelay13; +wire a7ddrphy_dq_i_delayed13; +wire a7ddrphy_dq_t13; +reg [7:0] a7ddrphy_bitslip130 = 8'd0; +reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip131; +reg [7:0] a7ddrphy_bitslip132 = 8'd0; +reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay14; +wire a7ddrphy_dq_i_nodelay14; +wire a7ddrphy_dq_i_delayed14; +wire a7ddrphy_dq_t14; +reg [7:0] a7ddrphy_bitslip140 = 8'd0; +reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip141; +reg [7:0] a7ddrphy_bitslip142 = 8'd0; +reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay15; +wire a7ddrphy_dq_i_nodelay15; +wire a7ddrphy_dq_i_delayed15; +wire a7ddrphy_dq_t15; +reg [7:0] a7ddrphy_bitslip150 = 8'd0; +reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip151; +reg [7:0] a7ddrphy_bitslip152 = 8'd0; +reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay16; +wire a7ddrphy_dq_i_nodelay16; +wire a7ddrphy_dq_i_delayed16; +wire a7ddrphy_dq_t16; +reg [7:0] a7ddrphy_bitslip160 = 8'd0; +reg [2:0] a7ddrphy_bitslip16_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip16_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip161; +reg [7:0] a7ddrphy_bitslip162 = 8'd0; +reg [2:0] a7ddrphy_bitslip16_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip16_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay17; +wire a7ddrphy_dq_i_nodelay17; +wire a7ddrphy_dq_i_delayed17; +wire a7ddrphy_dq_t17; +reg [7:0] a7ddrphy_bitslip170 = 8'd0; +reg [2:0] a7ddrphy_bitslip17_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip17_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip171; +reg [7:0] a7ddrphy_bitslip172 = 8'd0; +reg [2:0] a7ddrphy_bitslip17_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip17_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay18; +wire a7ddrphy_dq_i_nodelay18; +wire a7ddrphy_dq_i_delayed18; +wire a7ddrphy_dq_t18; +reg [7:0] a7ddrphy_bitslip180 = 8'd0; +reg [2:0] a7ddrphy_bitslip18_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip18_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip181; +reg [7:0] a7ddrphy_bitslip182 = 8'd0; +reg [2:0] a7ddrphy_bitslip18_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip18_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay19; +wire a7ddrphy_dq_i_nodelay19; +wire a7ddrphy_dq_i_delayed19; +wire a7ddrphy_dq_t19; +reg [7:0] a7ddrphy_bitslip190 = 8'd0; +reg [2:0] a7ddrphy_bitslip19_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip19_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip191; +reg [7:0] a7ddrphy_bitslip192 = 8'd0; +reg [2:0] a7ddrphy_bitslip19_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip19_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay20; +wire a7ddrphy_dq_i_nodelay20; +wire a7ddrphy_dq_i_delayed20; +wire a7ddrphy_dq_t20; +reg [7:0] a7ddrphy_bitslip200 = 8'd0; +reg [2:0] a7ddrphy_bitslip20_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip20_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip201; +reg [7:0] a7ddrphy_bitslip202 = 8'd0; +reg [2:0] a7ddrphy_bitslip20_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip20_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay21; +wire a7ddrphy_dq_i_nodelay21; +wire a7ddrphy_dq_i_delayed21; +wire a7ddrphy_dq_t21; +reg [7:0] a7ddrphy_bitslip210 = 8'd0; +reg [2:0] a7ddrphy_bitslip21_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip21_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip211; +reg [7:0] a7ddrphy_bitslip212 = 8'd0; +reg [2:0] a7ddrphy_bitslip21_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip21_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay22; +wire a7ddrphy_dq_i_nodelay22; +wire a7ddrphy_dq_i_delayed22; +wire a7ddrphy_dq_t22; +reg [7:0] a7ddrphy_bitslip220 = 8'd0; +reg [2:0] a7ddrphy_bitslip22_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip22_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip221; +reg [7:0] a7ddrphy_bitslip222 = 8'd0; +reg [2:0] a7ddrphy_bitslip22_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip22_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay23; +wire a7ddrphy_dq_i_nodelay23; +wire a7ddrphy_dq_i_delayed23; +wire a7ddrphy_dq_t23; +reg [7:0] a7ddrphy_bitslip230 = 8'd0; +reg [2:0] a7ddrphy_bitslip23_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip23_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip231; +reg [7:0] a7ddrphy_bitslip232 = 8'd0; +reg [2:0] a7ddrphy_bitslip23_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip23_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay24; +wire a7ddrphy_dq_i_nodelay24; +wire a7ddrphy_dq_i_delayed24; +wire a7ddrphy_dq_t24; +reg [7:0] a7ddrphy_bitslip240 = 8'd0; +reg [2:0] a7ddrphy_bitslip24_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip24_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip241; +reg [7:0] a7ddrphy_bitslip242 = 8'd0; +reg [2:0] a7ddrphy_bitslip24_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip24_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay25; +wire a7ddrphy_dq_i_nodelay25; +wire a7ddrphy_dq_i_delayed25; +wire a7ddrphy_dq_t25; +reg [7:0] a7ddrphy_bitslip250 = 8'd0; +reg [2:0] a7ddrphy_bitslip25_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip25_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip251; +reg [7:0] a7ddrphy_bitslip252 = 8'd0; +reg [2:0] a7ddrphy_bitslip25_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip25_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay26; +wire a7ddrphy_dq_i_nodelay26; +wire a7ddrphy_dq_i_delayed26; +wire a7ddrphy_dq_t26; +reg [7:0] a7ddrphy_bitslip260 = 8'd0; +reg [2:0] a7ddrphy_bitslip26_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip26_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip261; +reg [7:0] a7ddrphy_bitslip262 = 8'd0; +reg [2:0] a7ddrphy_bitslip26_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip26_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay27; +wire a7ddrphy_dq_i_nodelay27; +wire a7ddrphy_dq_i_delayed27; +wire a7ddrphy_dq_t27; +reg [7:0] a7ddrphy_bitslip270 = 8'd0; +reg [2:0] a7ddrphy_bitslip27_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip27_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip271; +reg [7:0] a7ddrphy_bitslip272 = 8'd0; +reg [2:0] a7ddrphy_bitslip27_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip27_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay28; +wire a7ddrphy_dq_i_nodelay28; +wire a7ddrphy_dq_i_delayed28; +wire a7ddrphy_dq_t28; +reg [7:0] a7ddrphy_bitslip280 = 8'd0; +reg [2:0] a7ddrphy_bitslip28_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip28_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip281; +reg [7:0] a7ddrphy_bitslip282 = 8'd0; +reg [2:0] a7ddrphy_bitslip28_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip28_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay29; +wire a7ddrphy_dq_i_nodelay29; +wire a7ddrphy_dq_i_delayed29; +wire a7ddrphy_dq_t29; +reg [7:0] a7ddrphy_bitslip290 = 8'd0; +reg [2:0] a7ddrphy_bitslip29_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip29_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip291; +reg [7:0] a7ddrphy_bitslip292 = 8'd0; +reg [2:0] a7ddrphy_bitslip29_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip29_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay30; +wire a7ddrphy_dq_i_nodelay30; +wire a7ddrphy_dq_i_delayed30; +wire a7ddrphy_dq_t30; +reg [7:0] a7ddrphy_bitslip300 = 8'd0; +reg [2:0] a7ddrphy_bitslip30_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip30_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip301; +reg [7:0] a7ddrphy_bitslip302 = 8'd0; +reg [2:0] a7ddrphy_bitslip30_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip30_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay31; +wire a7ddrphy_dq_i_nodelay31; +wire a7ddrphy_dq_i_delayed31; +wire a7ddrphy_dq_t31; +reg [7:0] a7ddrphy_bitslip310 = 8'd0; +reg [2:0] a7ddrphy_bitslip31_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip31_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip311; +reg [7:0] a7ddrphy_bitslip312 = 8'd0; +reg [2:0] a7ddrphy_bitslip31_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip31_r1 = 16'd0; +reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +wire [13:0] netv2_sdram_inti_p0_address; +wire [2:0] netv2_sdram_inti_p0_bank; +reg netv2_sdram_inti_p0_cas_n = 1'd1; +reg netv2_sdram_inti_p0_cs_n = 1'd1; +reg netv2_sdram_inti_p0_ras_n = 1'd1; +reg netv2_sdram_inti_p0_we_n = 1'd1; +wire netv2_sdram_inti_p0_cke; +wire netv2_sdram_inti_p0_odt; +wire netv2_sdram_inti_p0_reset_n; +reg netv2_sdram_inti_p0_act_n = 1'd1; +wire [63:0] netv2_sdram_inti_p0_wrdata; +wire netv2_sdram_inti_p0_wrdata_en; +wire [7:0] netv2_sdram_inti_p0_wrdata_mask; +wire netv2_sdram_inti_p0_rddata_en; +reg [63:0] netv2_sdram_inti_p0_rddata = 64'd0; +reg netv2_sdram_inti_p0_rddata_valid = 1'd0; +wire [13:0] netv2_sdram_inti_p1_address; +wire [2:0] netv2_sdram_inti_p1_bank; +reg netv2_sdram_inti_p1_cas_n = 1'd1; +reg netv2_sdram_inti_p1_cs_n = 1'd1; +reg netv2_sdram_inti_p1_ras_n = 1'd1; +reg netv2_sdram_inti_p1_we_n = 1'd1; +wire netv2_sdram_inti_p1_cke; +wire netv2_sdram_inti_p1_odt; +wire netv2_sdram_inti_p1_reset_n; +reg netv2_sdram_inti_p1_act_n = 1'd1; +wire [63:0] netv2_sdram_inti_p1_wrdata; +wire netv2_sdram_inti_p1_wrdata_en; +wire [7:0] netv2_sdram_inti_p1_wrdata_mask; +wire netv2_sdram_inti_p1_rddata_en; +reg [63:0] netv2_sdram_inti_p1_rddata = 64'd0; +reg netv2_sdram_inti_p1_rddata_valid = 1'd0; +wire [13:0] netv2_sdram_inti_p2_address; +wire [2:0] netv2_sdram_inti_p2_bank; +reg netv2_sdram_inti_p2_cas_n = 1'd1; +reg netv2_sdram_inti_p2_cs_n = 1'd1; +reg netv2_sdram_inti_p2_ras_n = 1'd1; +reg netv2_sdram_inti_p2_we_n = 1'd1; +wire netv2_sdram_inti_p2_cke; +wire netv2_sdram_inti_p2_odt; +wire netv2_sdram_inti_p2_reset_n; +reg netv2_sdram_inti_p2_act_n = 1'd1; +wire [63:0] netv2_sdram_inti_p2_wrdata; +wire netv2_sdram_inti_p2_wrdata_en; +wire [7:0] netv2_sdram_inti_p2_wrdata_mask; +wire netv2_sdram_inti_p2_rddata_en; +reg [63:0] netv2_sdram_inti_p2_rddata = 64'd0; +reg netv2_sdram_inti_p2_rddata_valid = 1'd0; +wire [13:0] netv2_sdram_inti_p3_address; +wire [2:0] netv2_sdram_inti_p3_bank; +reg netv2_sdram_inti_p3_cas_n = 1'd1; +reg netv2_sdram_inti_p3_cs_n = 1'd1; +reg netv2_sdram_inti_p3_ras_n = 1'd1; +reg netv2_sdram_inti_p3_we_n = 1'd1; +wire netv2_sdram_inti_p3_cke; +wire netv2_sdram_inti_p3_odt; +wire netv2_sdram_inti_p3_reset_n; +reg netv2_sdram_inti_p3_act_n = 1'd1; +wire [63:0] netv2_sdram_inti_p3_wrdata; +wire netv2_sdram_inti_p3_wrdata_en; +wire [7:0] netv2_sdram_inti_p3_wrdata_mask; +wire netv2_sdram_inti_p3_rddata_en; +reg [63:0] netv2_sdram_inti_p3_rddata = 64'd0; +reg netv2_sdram_inti_p3_rddata_valid = 1'd0; +wire [13:0] netv2_sdram_slave_p0_address; +wire [2:0] netv2_sdram_slave_p0_bank; +wire netv2_sdram_slave_p0_cas_n; +wire netv2_sdram_slave_p0_cs_n; +wire netv2_sdram_slave_p0_ras_n; +wire netv2_sdram_slave_p0_we_n; +wire netv2_sdram_slave_p0_cke; +wire netv2_sdram_slave_p0_odt; +wire netv2_sdram_slave_p0_reset_n; +wire netv2_sdram_slave_p0_act_n; +wire [63:0] netv2_sdram_slave_p0_wrdata; +wire netv2_sdram_slave_p0_wrdata_en; +wire [7:0] netv2_sdram_slave_p0_wrdata_mask; +wire netv2_sdram_slave_p0_rddata_en; +reg [63:0] netv2_sdram_slave_p0_rddata = 64'd0; +reg netv2_sdram_slave_p0_rddata_valid = 1'd0; +wire [13:0] netv2_sdram_slave_p1_address; +wire [2:0] netv2_sdram_slave_p1_bank; +wire netv2_sdram_slave_p1_cas_n; +wire netv2_sdram_slave_p1_cs_n; +wire netv2_sdram_slave_p1_ras_n; +wire netv2_sdram_slave_p1_we_n; +wire netv2_sdram_slave_p1_cke; +wire netv2_sdram_slave_p1_odt; +wire netv2_sdram_slave_p1_reset_n; +wire netv2_sdram_slave_p1_act_n; +wire [63:0] netv2_sdram_slave_p1_wrdata; +wire netv2_sdram_slave_p1_wrdata_en; +wire [7:0] netv2_sdram_slave_p1_wrdata_mask; +wire netv2_sdram_slave_p1_rddata_en; +reg [63:0] netv2_sdram_slave_p1_rddata = 64'd0; +reg netv2_sdram_slave_p1_rddata_valid = 1'd0; +wire [13:0] netv2_sdram_slave_p2_address; +wire [2:0] netv2_sdram_slave_p2_bank; +wire netv2_sdram_slave_p2_cas_n; +wire netv2_sdram_slave_p2_cs_n; +wire netv2_sdram_slave_p2_ras_n; +wire netv2_sdram_slave_p2_we_n; +wire netv2_sdram_slave_p2_cke; +wire netv2_sdram_slave_p2_odt; +wire netv2_sdram_slave_p2_reset_n; +wire netv2_sdram_slave_p2_act_n; +wire [63:0] netv2_sdram_slave_p2_wrdata; +wire netv2_sdram_slave_p2_wrdata_en; +wire [7:0] netv2_sdram_slave_p2_wrdata_mask; +wire netv2_sdram_slave_p2_rddata_en; +reg [63:0] netv2_sdram_slave_p2_rddata = 64'd0; +reg netv2_sdram_slave_p2_rddata_valid = 1'd0; +wire [13:0] netv2_sdram_slave_p3_address; +wire [2:0] netv2_sdram_slave_p3_bank; +wire netv2_sdram_slave_p3_cas_n; +wire netv2_sdram_slave_p3_cs_n; +wire netv2_sdram_slave_p3_ras_n; +wire netv2_sdram_slave_p3_we_n; +wire netv2_sdram_slave_p3_cke; +wire netv2_sdram_slave_p3_odt; +wire netv2_sdram_slave_p3_reset_n; +wire netv2_sdram_slave_p3_act_n; +wire [63:0] netv2_sdram_slave_p3_wrdata; +wire netv2_sdram_slave_p3_wrdata_en; +wire [7:0] netv2_sdram_slave_p3_wrdata_mask; +wire netv2_sdram_slave_p3_rddata_en; +reg [63:0] netv2_sdram_slave_p3_rddata = 64'd0; +reg netv2_sdram_slave_p3_rddata_valid = 1'd0; +reg [13:0] netv2_sdram_master_p0_address = 14'd0; +reg [2:0] netv2_sdram_master_p0_bank = 3'd0; +reg netv2_sdram_master_p0_cas_n = 1'd1; +reg netv2_sdram_master_p0_cs_n = 1'd1; +reg netv2_sdram_master_p0_ras_n = 1'd1; +reg netv2_sdram_master_p0_we_n = 1'd1; +reg netv2_sdram_master_p0_cke = 1'd0; +reg netv2_sdram_master_p0_odt = 1'd0; +reg netv2_sdram_master_p0_reset_n = 1'd0; +reg netv2_sdram_master_p0_act_n = 1'd1; +reg [63:0] netv2_sdram_master_p0_wrdata = 64'd0; +reg netv2_sdram_master_p0_wrdata_en = 1'd0; +reg [7:0] netv2_sdram_master_p0_wrdata_mask = 8'd0; +reg netv2_sdram_master_p0_rddata_en = 1'd0; +wire [63:0] netv2_sdram_master_p0_rddata; +wire netv2_sdram_master_p0_rddata_valid; +reg [13:0] netv2_sdram_master_p1_address = 14'd0; +reg [2:0] netv2_sdram_master_p1_bank = 3'd0; +reg netv2_sdram_master_p1_cas_n = 1'd1; +reg netv2_sdram_master_p1_cs_n = 1'd1; +reg netv2_sdram_master_p1_ras_n = 1'd1; +reg netv2_sdram_master_p1_we_n = 1'd1; +reg netv2_sdram_master_p1_cke = 1'd0; +reg netv2_sdram_master_p1_odt = 1'd0; +reg netv2_sdram_master_p1_reset_n = 1'd0; +reg netv2_sdram_master_p1_act_n = 1'd1; +reg [63:0] netv2_sdram_master_p1_wrdata = 64'd0; +reg netv2_sdram_master_p1_wrdata_en = 1'd0; +reg [7:0] netv2_sdram_master_p1_wrdata_mask = 8'd0; +reg netv2_sdram_master_p1_rddata_en = 1'd0; +wire [63:0] netv2_sdram_master_p1_rddata; +wire netv2_sdram_master_p1_rddata_valid; +reg [13:0] netv2_sdram_master_p2_address = 14'd0; +reg [2:0] netv2_sdram_master_p2_bank = 3'd0; +reg netv2_sdram_master_p2_cas_n = 1'd1; +reg netv2_sdram_master_p2_cs_n = 1'd1; +reg netv2_sdram_master_p2_ras_n = 1'd1; +reg netv2_sdram_master_p2_we_n = 1'd1; +reg netv2_sdram_master_p2_cke = 1'd0; +reg netv2_sdram_master_p2_odt = 1'd0; +reg netv2_sdram_master_p2_reset_n = 1'd0; +reg netv2_sdram_master_p2_act_n = 1'd1; +reg [63:0] netv2_sdram_master_p2_wrdata = 64'd0; +reg netv2_sdram_master_p2_wrdata_en = 1'd0; +reg [7:0] netv2_sdram_master_p2_wrdata_mask = 8'd0; +reg netv2_sdram_master_p2_rddata_en = 1'd0; +wire [63:0] netv2_sdram_master_p2_rddata; +wire netv2_sdram_master_p2_rddata_valid; +reg [13:0] netv2_sdram_master_p3_address = 14'd0; +reg [2:0] netv2_sdram_master_p3_bank = 3'd0; +reg netv2_sdram_master_p3_cas_n = 1'd1; +reg netv2_sdram_master_p3_cs_n = 1'd1; +reg netv2_sdram_master_p3_ras_n = 1'd1; +reg netv2_sdram_master_p3_we_n = 1'd1; +reg netv2_sdram_master_p3_cke = 1'd0; +reg netv2_sdram_master_p3_odt = 1'd0; +reg netv2_sdram_master_p3_reset_n = 1'd0; +reg netv2_sdram_master_p3_act_n = 1'd1; +reg [63:0] netv2_sdram_master_p3_wrdata = 64'd0; +reg netv2_sdram_master_p3_wrdata_en = 1'd0; +reg [7:0] netv2_sdram_master_p3_wrdata_mask = 8'd0; +reg netv2_sdram_master_p3_rddata_en = 1'd0; +wire [63:0] netv2_sdram_master_p3_rddata; +wire netv2_sdram_master_p3_rddata_valid; +wire netv2_sdram_sel; +wire netv2_sdram_cke; +wire netv2_sdram_odt; +wire netv2_sdram_reset_n; +reg [3:0] netv2_sdram_storage = 4'd1; +reg netv2_sdram_re = 1'd0; +reg [5:0] netv2_sdram_phaseinjector0_command_storage = 6'd0; +reg netv2_sdram_phaseinjector0_command_re = 1'd0; +wire netv2_sdram_phaseinjector0_command_issue_re; +wire netv2_sdram_phaseinjector0_command_issue_r; +wire netv2_sdram_phaseinjector0_command_issue_we; +reg netv2_sdram_phaseinjector0_command_issue_w = 1'd0; +reg [13:0] netv2_sdram_phaseinjector0_address_storage = 14'd0; +reg netv2_sdram_phaseinjector0_address_re = 1'd0; +reg [2:0] netv2_sdram_phaseinjector0_baddress_storage = 3'd0; +reg netv2_sdram_phaseinjector0_baddress_re = 1'd0; +reg [63:0] netv2_sdram_phaseinjector0_wrdata_storage = 64'd0; +reg netv2_sdram_phaseinjector0_wrdata_re = 1'd0; +reg [63:0] netv2_sdram_phaseinjector0_rddata_status = 64'd0; +wire netv2_sdram_phaseinjector0_rddata_we; +wire netv2_sdram_phaseinjector0_rddata_re; +reg [5:0] netv2_sdram_phaseinjector1_command_storage = 6'd0; +reg netv2_sdram_phaseinjector1_command_re = 1'd0; +wire netv2_sdram_phaseinjector1_command_issue_re; +wire netv2_sdram_phaseinjector1_command_issue_r; +wire netv2_sdram_phaseinjector1_command_issue_we; +reg netv2_sdram_phaseinjector1_command_issue_w = 1'd0; +reg [13:0] netv2_sdram_phaseinjector1_address_storage = 14'd0; +reg netv2_sdram_phaseinjector1_address_re = 1'd0; +reg [2:0] netv2_sdram_phaseinjector1_baddress_storage = 3'd0; +reg netv2_sdram_phaseinjector1_baddress_re = 1'd0; +reg [63:0] netv2_sdram_phaseinjector1_wrdata_storage = 64'd0; +reg netv2_sdram_phaseinjector1_wrdata_re = 1'd0; +reg [63:0] netv2_sdram_phaseinjector1_rddata_status = 64'd0; +wire netv2_sdram_phaseinjector1_rddata_we; +wire netv2_sdram_phaseinjector1_rddata_re; +reg [5:0] netv2_sdram_phaseinjector2_command_storage = 6'd0; +reg netv2_sdram_phaseinjector2_command_re = 1'd0; +wire netv2_sdram_phaseinjector2_command_issue_re; +wire netv2_sdram_phaseinjector2_command_issue_r; +wire netv2_sdram_phaseinjector2_command_issue_we; +reg netv2_sdram_phaseinjector2_command_issue_w = 1'd0; +reg [13:0] netv2_sdram_phaseinjector2_address_storage = 14'd0; +reg netv2_sdram_phaseinjector2_address_re = 1'd0; +reg [2:0] netv2_sdram_phaseinjector2_baddress_storage = 3'd0; +reg netv2_sdram_phaseinjector2_baddress_re = 1'd0; +reg [63:0] netv2_sdram_phaseinjector2_wrdata_storage = 64'd0; +reg netv2_sdram_phaseinjector2_wrdata_re = 1'd0; +reg [63:0] netv2_sdram_phaseinjector2_rddata_status = 64'd0; +wire netv2_sdram_phaseinjector2_rddata_we; +wire netv2_sdram_phaseinjector2_rddata_re; +reg [5:0] netv2_sdram_phaseinjector3_command_storage = 6'd0; +reg netv2_sdram_phaseinjector3_command_re = 1'd0; +wire netv2_sdram_phaseinjector3_command_issue_re; +wire netv2_sdram_phaseinjector3_command_issue_r; +wire netv2_sdram_phaseinjector3_command_issue_we; +reg netv2_sdram_phaseinjector3_command_issue_w = 1'd0; +reg [13:0] netv2_sdram_phaseinjector3_address_storage = 14'd0; +reg netv2_sdram_phaseinjector3_address_re = 1'd0; +reg [2:0] netv2_sdram_phaseinjector3_baddress_storage = 3'd0; +reg netv2_sdram_phaseinjector3_baddress_re = 1'd0; +reg [63:0] netv2_sdram_phaseinjector3_wrdata_storage = 64'd0; +reg netv2_sdram_phaseinjector3_wrdata_re = 1'd0; +reg [63:0] netv2_sdram_phaseinjector3_rddata_status = 64'd0; +wire netv2_sdram_phaseinjector3_rddata_we; +wire netv2_sdram_phaseinjector3_rddata_re; +wire netv2_sdram_interface_bank0_valid; +wire netv2_sdram_interface_bank0_ready; +wire netv2_sdram_interface_bank0_we; +wire [20:0] netv2_sdram_interface_bank0_addr; +wire netv2_sdram_interface_bank0_lock; +wire netv2_sdram_interface_bank0_wdata_ready; +wire netv2_sdram_interface_bank0_rdata_valid; +wire netv2_sdram_interface_bank1_valid; +wire netv2_sdram_interface_bank1_ready; +wire netv2_sdram_interface_bank1_we; +wire [20:0] netv2_sdram_interface_bank1_addr; +wire netv2_sdram_interface_bank1_lock; +wire netv2_sdram_interface_bank1_wdata_ready; +wire netv2_sdram_interface_bank1_rdata_valid; +wire netv2_sdram_interface_bank2_valid; +wire netv2_sdram_interface_bank2_ready; +wire netv2_sdram_interface_bank2_we; +wire [20:0] netv2_sdram_interface_bank2_addr; +wire netv2_sdram_interface_bank2_lock; +wire netv2_sdram_interface_bank2_wdata_ready; +wire netv2_sdram_interface_bank2_rdata_valid; +wire netv2_sdram_interface_bank3_valid; +wire netv2_sdram_interface_bank3_ready; +wire netv2_sdram_interface_bank3_we; +wire [20:0] netv2_sdram_interface_bank3_addr; +wire netv2_sdram_interface_bank3_lock; +wire netv2_sdram_interface_bank3_wdata_ready; +wire netv2_sdram_interface_bank3_rdata_valid; +wire netv2_sdram_interface_bank4_valid; +wire netv2_sdram_interface_bank4_ready; +wire netv2_sdram_interface_bank4_we; +wire [20:0] netv2_sdram_interface_bank4_addr; +wire netv2_sdram_interface_bank4_lock; +wire netv2_sdram_interface_bank4_wdata_ready; +wire netv2_sdram_interface_bank4_rdata_valid; +wire netv2_sdram_interface_bank5_valid; +wire netv2_sdram_interface_bank5_ready; +wire netv2_sdram_interface_bank5_we; +wire [20:0] netv2_sdram_interface_bank5_addr; +wire netv2_sdram_interface_bank5_lock; +wire netv2_sdram_interface_bank5_wdata_ready; +wire netv2_sdram_interface_bank5_rdata_valid; +wire netv2_sdram_interface_bank6_valid; +wire netv2_sdram_interface_bank6_ready; +wire netv2_sdram_interface_bank6_we; +wire [20:0] netv2_sdram_interface_bank6_addr; +wire netv2_sdram_interface_bank6_lock; +wire netv2_sdram_interface_bank6_wdata_ready; +wire netv2_sdram_interface_bank6_rdata_valid; +wire netv2_sdram_interface_bank7_valid; +wire netv2_sdram_interface_bank7_ready; +wire netv2_sdram_interface_bank7_we; +wire [20:0] netv2_sdram_interface_bank7_addr; +wire netv2_sdram_interface_bank7_lock; +wire netv2_sdram_interface_bank7_wdata_ready; +wire netv2_sdram_interface_bank7_rdata_valid; +reg [255:0] netv2_sdram_interface_wdata = 256'd0; +reg [31:0] netv2_sdram_interface_wdata_we = 32'd0; +wire [255:0] netv2_sdram_interface_rdata; +reg [13:0] netv2_sdram_dfi_p0_address = 14'd0; +reg [2:0] netv2_sdram_dfi_p0_bank = 3'd0; +reg netv2_sdram_dfi_p0_cas_n = 1'd1; +reg netv2_sdram_dfi_p0_cs_n = 1'd1; +reg netv2_sdram_dfi_p0_ras_n = 1'd1; +reg netv2_sdram_dfi_p0_we_n = 1'd1; +wire netv2_sdram_dfi_p0_cke; +wire netv2_sdram_dfi_p0_odt; +wire netv2_sdram_dfi_p0_reset_n; +reg netv2_sdram_dfi_p0_act_n = 1'd1; +wire [63:0] netv2_sdram_dfi_p0_wrdata; +reg netv2_sdram_dfi_p0_wrdata_en = 1'd0; +wire [7:0] netv2_sdram_dfi_p0_wrdata_mask; +reg netv2_sdram_dfi_p0_rddata_en = 1'd0; +wire [63:0] netv2_sdram_dfi_p0_rddata; +wire netv2_sdram_dfi_p0_rddata_valid; +reg [13:0] netv2_sdram_dfi_p1_address = 14'd0; +reg [2:0] netv2_sdram_dfi_p1_bank = 3'd0; +reg netv2_sdram_dfi_p1_cas_n = 1'd1; +reg netv2_sdram_dfi_p1_cs_n = 1'd1; +reg netv2_sdram_dfi_p1_ras_n = 1'd1; +reg netv2_sdram_dfi_p1_we_n = 1'd1; +wire netv2_sdram_dfi_p1_cke; +wire netv2_sdram_dfi_p1_odt; +wire netv2_sdram_dfi_p1_reset_n; +reg netv2_sdram_dfi_p1_act_n = 1'd1; +wire [63:0] netv2_sdram_dfi_p1_wrdata; +reg netv2_sdram_dfi_p1_wrdata_en = 1'd0; +wire [7:0] netv2_sdram_dfi_p1_wrdata_mask; +reg netv2_sdram_dfi_p1_rddata_en = 1'd0; +wire [63:0] netv2_sdram_dfi_p1_rddata; +wire netv2_sdram_dfi_p1_rddata_valid; +reg [13:0] netv2_sdram_dfi_p2_address = 14'd0; +reg [2:0] netv2_sdram_dfi_p2_bank = 3'd0; +reg netv2_sdram_dfi_p2_cas_n = 1'd1; +reg netv2_sdram_dfi_p2_cs_n = 1'd1; +reg netv2_sdram_dfi_p2_ras_n = 1'd1; +reg netv2_sdram_dfi_p2_we_n = 1'd1; +wire netv2_sdram_dfi_p2_cke; +wire netv2_sdram_dfi_p2_odt; +wire netv2_sdram_dfi_p2_reset_n; +reg netv2_sdram_dfi_p2_act_n = 1'd1; +wire [63:0] netv2_sdram_dfi_p2_wrdata; +reg netv2_sdram_dfi_p2_wrdata_en = 1'd0; +wire [7:0] netv2_sdram_dfi_p2_wrdata_mask; +reg netv2_sdram_dfi_p2_rddata_en = 1'd0; +wire [63:0] netv2_sdram_dfi_p2_rddata; +wire netv2_sdram_dfi_p2_rddata_valid; +reg [13:0] netv2_sdram_dfi_p3_address = 14'd0; +reg [2:0] netv2_sdram_dfi_p3_bank = 3'd0; +reg netv2_sdram_dfi_p3_cas_n = 1'd1; +reg netv2_sdram_dfi_p3_cs_n = 1'd1; +reg netv2_sdram_dfi_p3_ras_n = 1'd1; +reg netv2_sdram_dfi_p3_we_n = 1'd1; +wire netv2_sdram_dfi_p3_cke; +wire netv2_sdram_dfi_p3_odt; +wire netv2_sdram_dfi_p3_reset_n; +reg netv2_sdram_dfi_p3_act_n = 1'd1; +wire [63:0] netv2_sdram_dfi_p3_wrdata; +reg netv2_sdram_dfi_p3_wrdata_en = 1'd0; +wire [7:0] netv2_sdram_dfi_p3_wrdata_mask; +reg netv2_sdram_dfi_p3_rddata_en = 1'd0; +wire [63:0] netv2_sdram_dfi_p3_rddata; +wire netv2_sdram_dfi_p3_rddata_valid; +reg netv2_sdram_cmd_valid = 1'd0; +reg netv2_sdram_cmd_ready = 1'd0; +reg netv2_sdram_cmd_last = 1'd0; +reg [13:0] netv2_sdram_cmd_payload_a = 14'd0; +reg [2:0] netv2_sdram_cmd_payload_ba = 3'd0; +reg netv2_sdram_cmd_payload_cas = 1'd0; +reg netv2_sdram_cmd_payload_ras = 1'd0; +reg netv2_sdram_cmd_payload_we = 1'd0; +reg netv2_sdram_cmd_payload_is_read = 1'd0; +reg netv2_sdram_cmd_payload_is_write = 1'd0; +wire netv2_sdram_wants_refresh; +wire netv2_sdram_wants_zqcs; +wire netv2_sdram_timer_wait; +wire netv2_sdram_timer_done0; +wire [9:0] netv2_sdram_timer_count0; +wire netv2_sdram_timer_done1; +reg [9:0] netv2_sdram_timer_count1 = 10'd781; +wire netv2_sdram_postponer_req_i; +reg netv2_sdram_postponer_req_o = 1'd0; +reg netv2_sdram_postponer_count = 1'd0; +reg netv2_sdram_sequencer_start0 = 1'd0; +wire netv2_sdram_sequencer_done0; +wire netv2_sdram_sequencer_start1; +reg netv2_sdram_sequencer_done1 = 1'd0; +reg [5:0] netv2_sdram_sequencer_counter = 6'd0; +reg netv2_sdram_sequencer_count = 1'd0; +wire netv2_sdram_zqcs_timer_wait; +wire netv2_sdram_zqcs_timer_done0; +wire [26:0] netv2_sdram_zqcs_timer_count0; +wire netv2_sdram_zqcs_timer_done1; +reg [26:0] netv2_sdram_zqcs_timer_count1 = 27'd99999999; +reg netv2_sdram_zqcs_executer_start = 1'd0; +reg netv2_sdram_zqcs_executer_done = 1'd0; +reg [4:0] netv2_sdram_zqcs_executer_counter = 5'd0; +wire netv2_sdram_bankmachine0_req_valid; +wire netv2_sdram_bankmachine0_req_ready; +wire netv2_sdram_bankmachine0_req_we; +wire [20:0] netv2_sdram_bankmachine0_req_addr; +wire netv2_sdram_bankmachine0_req_lock; +reg netv2_sdram_bankmachine0_req_wdata_ready = 1'd0; +reg netv2_sdram_bankmachine0_req_rdata_valid = 1'd0; +wire netv2_sdram_bankmachine0_refresh_req; +reg netv2_sdram_bankmachine0_refresh_gnt = 1'd0; +reg netv2_sdram_bankmachine0_cmd_valid = 1'd0; +reg netv2_sdram_bankmachine0_cmd_ready = 1'd0; +reg [13:0] netv2_sdram_bankmachine0_cmd_payload_a = 14'd0; +wire [2:0] netv2_sdram_bankmachine0_cmd_payload_ba; +reg netv2_sdram_bankmachine0_cmd_payload_cas = 1'd0; +reg netv2_sdram_bankmachine0_cmd_payload_ras = 1'd0; +reg netv2_sdram_bankmachine0_cmd_payload_we = 1'd0; +reg netv2_sdram_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg netv2_sdram_bankmachine0_cmd_payload_is_read = 1'd0; +reg netv2_sdram_bankmachine0_cmd_payload_is_write = 1'd0; +reg netv2_sdram_bankmachine0_auto_precharge = 1'd0; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; +reg netv2_sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg netv2_sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] netv2_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_valid; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_ready; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_first; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_last; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; +wire [20:0] netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +wire [23:0] netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +wire [23:0] netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +reg [3:0] netv2_sdram_bankmachine0_cmd_buffer_lookahead_level = 4'd0; +reg netv2_sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] netv2_sdram_bankmachine0_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] netv2_sdram_bankmachine0_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] netv2_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] netv2_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we; +wire [23:0] netv2_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_do_read; +wire [2:0] netv2_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr; +wire [23:0] netv2_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +wire netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +wire netv2_sdram_bankmachine0_cmd_buffer_sink_valid; +wire netv2_sdram_bankmachine0_cmd_buffer_sink_ready; +wire netv2_sdram_bankmachine0_cmd_buffer_sink_first; +wire netv2_sdram_bankmachine0_cmd_buffer_sink_last; +wire netv2_sdram_bankmachine0_cmd_buffer_sink_payload_we; +wire [20:0] netv2_sdram_bankmachine0_cmd_buffer_sink_payload_addr; +reg netv2_sdram_bankmachine0_cmd_buffer_source_valid = 1'd0; +wire netv2_sdram_bankmachine0_cmd_buffer_source_ready; +reg netv2_sdram_bankmachine0_cmd_buffer_source_first = 1'd0; +reg netv2_sdram_bankmachine0_cmd_buffer_source_last = 1'd0; +reg netv2_sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] netv2_sdram_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] netv2_sdram_bankmachine0_row = 14'd0; +reg netv2_sdram_bankmachine0_row_opened = 1'd0; +wire netv2_sdram_bankmachine0_row_hit; +reg netv2_sdram_bankmachine0_row_open = 1'd0; +reg netv2_sdram_bankmachine0_row_close = 1'd0; +reg netv2_sdram_bankmachine0_row_col_n_addr_sel = 1'd0; +wire netv2_sdram_bankmachine0_twtpcon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine0_twtpcon_count = 3'd0; +wire netv2_sdram_bankmachine0_trccon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine0_trccon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine0_trccon_count = 3'd0; +wire netv2_sdram_bankmachine0_trascon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine0_trascon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine0_trascon_count = 3'd0; +wire netv2_sdram_bankmachine1_req_valid; +wire netv2_sdram_bankmachine1_req_ready; +wire netv2_sdram_bankmachine1_req_we; +wire [20:0] netv2_sdram_bankmachine1_req_addr; +wire netv2_sdram_bankmachine1_req_lock; +reg netv2_sdram_bankmachine1_req_wdata_ready = 1'd0; +reg netv2_sdram_bankmachine1_req_rdata_valid = 1'd0; +wire netv2_sdram_bankmachine1_refresh_req; +reg netv2_sdram_bankmachine1_refresh_gnt = 1'd0; +reg netv2_sdram_bankmachine1_cmd_valid = 1'd0; +reg netv2_sdram_bankmachine1_cmd_ready = 1'd0; +reg [13:0] netv2_sdram_bankmachine1_cmd_payload_a = 14'd0; +wire [2:0] netv2_sdram_bankmachine1_cmd_payload_ba; +reg netv2_sdram_bankmachine1_cmd_payload_cas = 1'd0; +reg netv2_sdram_bankmachine1_cmd_payload_ras = 1'd0; +reg netv2_sdram_bankmachine1_cmd_payload_we = 1'd0; +reg netv2_sdram_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg netv2_sdram_bankmachine1_cmd_payload_is_read = 1'd0; +reg netv2_sdram_bankmachine1_cmd_payload_is_write = 1'd0; +reg netv2_sdram_bankmachine1_auto_precharge = 1'd0; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; +reg netv2_sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg netv2_sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] netv2_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_valid; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_ready; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_first; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_last; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; +wire [20:0] netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +wire [23:0] netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +wire [23:0] netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +reg [3:0] netv2_sdram_bankmachine1_cmd_buffer_lookahead_level = 4'd0; +reg netv2_sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] netv2_sdram_bankmachine1_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] netv2_sdram_bankmachine1_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] netv2_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] netv2_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we; +wire [23:0] netv2_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_do_read; +wire [2:0] netv2_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr; +wire [23:0] netv2_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +wire netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +wire netv2_sdram_bankmachine1_cmd_buffer_sink_valid; +wire netv2_sdram_bankmachine1_cmd_buffer_sink_ready; +wire netv2_sdram_bankmachine1_cmd_buffer_sink_first; +wire netv2_sdram_bankmachine1_cmd_buffer_sink_last; +wire netv2_sdram_bankmachine1_cmd_buffer_sink_payload_we; +wire [20:0] netv2_sdram_bankmachine1_cmd_buffer_sink_payload_addr; +reg netv2_sdram_bankmachine1_cmd_buffer_source_valid = 1'd0; +wire netv2_sdram_bankmachine1_cmd_buffer_source_ready; +reg netv2_sdram_bankmachine1_cmd_buffer_source_first = 1'd0; +reg netv2_sdram_bankmachine1_cmd_buffer_source_last = 1'd0; +reg netv2_sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] netv2_sdram_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] netv2_sdram_bankmachine1_row = 14'd0; +reg netv2_sdram_bankmachine1_row_opened = 1'd0; +wire netv2_sdram_bankmachine1_row_hit; +reg netv2_sdram_bankmachine1_row_open = 1'd0; +reg netv2_sdram_bankmachine1_row_close = 1'd0; +reg netv2_sdram_bankmachine1_row_col_n_addr_sel = 1'd0; +wire netv2_sdram_bankmachine1_twtpcon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine1_twtpcon_count = 3'd0; +wire netv2_sdram_bankmachine1_trccon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine1_trccon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine1_trccon_count = 3'd0; +wire netv2_sdram_bankmachine1_trascon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine1_trascon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine1_trascon_count = 3'd0; +wire netv2_sdram_bankmachine2_req_valid; +wire netv2_sdram_bankmachine2_req_ready; +wire netv2_sdram_bankmachine2_req_we; +wire [20:0] netv2_sdram_bankmachine2_req_addr; +wire netv2_sdram_bankmachine2_req_lock; +reg netv2_sdram_bankmachine2_req_wdata_ready = 1'd0; +reg netv2_sdram_bankmachine2_req_rdata_valid = 1'd0; +wire netv2_sdram_bankmachine2_refresh_req; +reg netv2_sdram_bankmachine2_refresh_gnt = 1'd0; +reg netv2_sdram_bankmachine2_cmd_valid = 1'd0; +reg netv2_sdram_bankmachine2_cmd_ready = 1'd0; +reg [13:0] netv2_sdram_bankmachine2_cmd_payload_a = 14'd0; +wire [2:0] netv2_sdram_bankmachine2_cmd_payload_ba; +reg netv2_sdram_bankmachine2_cmd_payload_cas = 1'd0; +reg netv2_sdram_bankmachine2_cmd_payload_ras = 1'd0; +reg netv2_sdram_bankmachine2_cmd_payload_we = 1'd0; +reg netv2_sdram_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg netv2_sdram_bankmachine2_cmd_payload_is_read = 1'd0; +reg netv2_sdram_bankmachine2_cmd_payload_is_write = 1'd0; +reg netv2_sdram_bankmachine2_auto_precharge = 1'd0; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; +reg netv2_sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg netv2_sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] netv2_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_valid; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_ready; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_first; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_last; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; +wire [20:0] netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +wire [23:0] netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +wire [23:0] netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +reg [3:0] netv2_sdram_bankmachine2_cmd_buffer_lookahead_level = 4'd0; +reg netv2_sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] netv2_sdram_bankmachine2_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] netv2_sdram_bankmachine2_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] netv2_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] netv2_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we; +wire [23:0] netv2_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_do_read; +wire [2:0] netv2_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr; +wire [23:0] netv2_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +wire netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +wire netv2_sdram_bankmachine2_cmd_buffer_sink_valid; +wire netv2_sdram_bankmachine2_cmd_buffer_sink_ready; +wire netv2_sdram_bankmachine2_cmd_buffer_sink_first; +wire netv2_sdram_bankmachine2_cmd_buffer_sink_last; +wire netv2_sdram_bankmachine2_cmd_buffer_sink_payload_we; +wire [20:0] netv2_sdram_bankmachine2_cmd_buffer_sink_payload_addr; +reg netv2_sdram_bankmachine2_cmd_buffer_source_valid = 1'd0; +wire netv2_sdram_bankmachine2_cmd_buffer_source_ready; +reg netv2_sdram_bankmachine2_cmd_buffer_source_first = 1'd0; +reg netv2_sdram_bankmachine2_cmd_buffer_source_last = 1'd0; +reg netv2_sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] netv2_sdram_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] netv2_sdram_bankmachine2_row = 14'd0; +reg netv2_sdram_bankmachine2_row_opened = 1'd0; +wire netv2_sdram_bankmachine2_row_hit; +reg netv2_sdram_bankmachine2_row_open = 1'd0; +reg netv2_sdram_bankmachine2_row_close = 1'd0; +reg netv2_sdram_bankmachine2_row_col_n_addr_sel = 1'd0; +wire netv2_sdram_bankmachine2_twtpcon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine2_twtpcon_count = 3'd0; +wire netv2_sdram_bankmachine2_trccon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine2_trccon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine2_trccon_count = 3'd0; +wire netv2_sdram_bankmachine2_trascon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine2_trascon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine2_trascon_count = 3'd0; +wire netv2_sdram_bankmachine3_req_valid; +wire netv2_sdram_bankmachine3_req_ready; +wire netv2_sdram_bankmachine3_req_we; +wire [20:0] netv2_sdram_bankmachine3_req_addr; +wire netv2_sdram_bankmachine3_req_lock; +reg netv2_sdram_bankmachine3_req_wdata_ready = 1'd0; +reg netv2_sdram_bankmachine3_req_rdata_valid = 1'd0; +wire netv2_sdram_bankmachine3_refresh_req; +reg netv2_sdram_bankmachine3_refresh_gnt = 1'd0; +reg netv2_sdram_bankmachine3_cmd_valid = 1'd0; +reg netv2_sdram_bankmachine3_cmd_ready = 1'd0; +reg [13:0] netv2_sdram_bankmachine3_cmd_payload_a = 14'd0; +wire [2:0] netv2_sdram_bankmachine3_cmd_payload_ba; +reg netv2_sdram_bankmachine3_cmd_payload_cas = 1'd0; +reg netv2_sdram_bankmachine3_cmd_payload_ras = 1'd0; +reg netv2_sdram_bankmachine3_cmd_payload_we = 1'd0; +reg netv2_sdram_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg netv2_sdram_bankmachine3_cmd_payload_is_read = 1'd0; +reg netv2_sdram_bankmachine3_cmd_payload_is_write = 1'd0; +reg netv2_sdram_bankmachine3_auto_precharge = 1'd0; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; +reg netv2_sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg netv2_sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] netv2_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_valid; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_ready; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_first; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_last; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; +wire [20:0] netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +wire [23:0] netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +wire [23:0] netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +reg [3:0] netv2_sdram_bankmachine3_cmd_buffer_lookahead_level = 4'd0; +reg netv2_sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] netv2_sdram_bankmachine3_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] netv2_sdram_bankmachine3_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] netv2_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] netv2_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we; +wire [23:0] netv2_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_do_read; +wire [2:0] netv2_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr; +wire [23:0] netv2_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +wire netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +wire netv2_sdram_bankmachine3_cmd_buffer_sink_valid; +wire netv2_sdram_bankmachine3_cmd_buffer_sink_ready; +wire netv2_sdram_bankmachine3_cmd_buffer_sink_first; +wire netv2_sdram_bankmachine3_cmd_buffer_sink_last; +wire netv2_sdram_bankmachine3_cmd_buffer_sink_payload_we; +wire [20:0] netv2_sdram_bankmachine3_cmd_buffer_sink_payload_addr; +reg netv2_sdram_bankmachine3_cmd_buffer_source_valid = 1'd0; +wire netv2_sdram_bankmachine3_cmd_buffer_source_ready; +reg netv2_sdram_bankmachine3_cmd_buffer_source_first = 1'd0; +reg netv2_sdram_bankmachine3_cmd_buffer_source_last = 1'd0; +reg netv2_sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] netv2_sdram_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] netv2_sdram_bankmachine3_row = 14'd0; +reg netv2_sdram_bankmachine3_row_opened = 1'd0; +wire netv2_sdram_bankmachine3_row_hit; +reg netv2_sdram_bankmachine3_row_open = 1'd0; +reg netv2_sdram_bankmachine3_row_close = 1'd0; +reg netv2_sdram_bankmachine3_row_col_n_addr_sel = 1'd0; +wire netv2_sdram_bankmachine3_twtpcon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine3_twtpcon_count = 3'd0; +wire netv2_sdram_bankmachine3_trccon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine3_trccon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine3_trccon_count = 3'd0; +wire netv2_sdram_bankmachine3_trascon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine3_trascon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine3_trascon_count = 3'd0; +wire netv2_sdram_bankmachine4_req_valid; +wire netv2_sdram_bankmachine4_req_ready; +wire netv2_sdram_bankmachine4_req_we; +wire [20:0] netv2_sdram_bankmachine4_req_addr; +wire netv2_sdram_bankmachine4_req_lock; +reg netv2_sdram_bankmachine4_req_wdata_ready = 1'd0; +reg netv2_sdram_bankmachine4_req_rdata_valid = 1'd0; +wire netv2_sdram_bankmachine4_refresh_req; +reg netv2_sdram_bankmachine4_refresh_gnt = 1'd0; +reg netv2_sdram_bankmachine4_cmd_valid = 1'd0; +reg netv2_sdram_bankmachine4_cmd_ready = 1'd0; +reg [13:0] netv2_sdram_bankmachine4_cmd_payload_a = 14'd0; +wire [2:0] netv2_sdram_bankmachine4_cmd_payload_ba; +reg netv2_sdram_bankmachine4_cmd_payload_cas = 1'd0; +reg netv2_sdram_bankmachine4_cmd_payload_ras = 1'd0; +reg netv2_sdram_bankmachine4_cmd_payload_we = 1'd0; +reg netv2_sdram_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg netv2_sdram_bankmachine4_cmd_payload_is_read = 1'd0; +reg netv2_sdram_bankmachine4_cmd_payload_is_write = 1'd0; +reg netv2_sdram_bankmachine4_auto_precharge = 1'd0; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready; +reg netv2_sdram_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg netv2_sdram_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] netv2_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_valid; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_ready; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_first; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_last; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we; +wire [20:0] netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +wire [23:0] netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +wire [23:0] netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +reg [3:0] netv2_sdram_bankmachine4_cmd_buffer_lookahead_level = 4'd0; +reg netv2_sdram_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] netv2_sdram_bankmachine4_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] netv2_sdram_bankmachine4_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] netv2_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] netv2_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we; +wire [23:0] netv2_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_do_read; +wire [2:0] netv2_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr; +wire [23:0] netv2_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +wire netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +wire netv2_sdram_bankmachine4_cmd_buffer_sink_valid; +wire netv2_sdram_bankmachine4_cmd_buffer_sink_ready; +wire netv2_sdram_bankmachine4_cmd_buffer_sink_first; +wire netv2_sdram_bankmachine4_cmd_buffer_sink_last; +wire netv2_sdram_bankmachine4_cmd_buffer_sink_payload_we; +wire [20:0] netv2_sdram_bankmachine4_cmd_buffer_sink_payload_addr; +reg netv2_sdram_bankmachine4_cmd_buffer_source_valid = 1'd0; +wire netv2_sdram_bankmachine4_cmd_buffer_source_ready; +reg netv2_sdram_bankmachine4_cmd_buffer_source_first = 1'd0; +reg netv2_sdram_bankmachine4_cmd_buffer_source_last = 1'd0; +reg netv2_sdram_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] netv2_sdram_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] netv2_sdram_bankmachine4_row = 14'd0; +reg netv2_sdram_bankmachine4_row_opened = 1'd0; +wire netv2_sdram_bankmachine4_row_hit; +reg netv2_sdram_bankmachine4_row_open = 1'd0; +reg netv2_sdram_bankmachine4_row_close = 1'd0; +reg netv2_sdram_bankmachine4_row_col_n_addr_sel = 1'd0; +wire netv2_sdram_bankmachine4_twtpcon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine4_twtpcon_count = 3'd0; +wire netv2_sdram_bankmachine4_trccon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine4_trccon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine4_trccon_count = 3'd0; +wire netv2_sdram_bankmachine4_trascon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine4_trascon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine4_trascon_count = 3'd0; +wire netv2_sdram_bankmachine5_req_valid; +wire netv2_sdram_bankmachine5_req_ready; +wire netv2_sdram_bankmachine5_req_we; +wire [20:0] netv2_sdram_bankmachine5_req_addr; +wire netv2_sdram_bankmachine5_req_lock; +reg netv2_sdram_bankmachine5_req_wdata_ready = 1'd0; +reg netv2_sdram_bankmachine5_req_rdata_valid = 1'd0; +wire netv2_sdram_bankmachine5_refresh_req; +reg netv2_sdram_bankmachine5_refresh_gnt = 1'd0; +reg netv2_sdram_bankmachine5_cmd_valid = 1'd0; +reg netv2_sdram_bankmachine5_cmd_ready = 1'd0; +reg [13:0] netv2_sdram_bankmachine5_cmd_payload_a = 14'd0; +wire [2:0] netv2_sdram_bankmachine5_cmd_payload_ba; +reg netv2_sdram_bankmachine5_cmd_payload_cas = 1'd0; +reg netv2_sdram_bankmachine5_cmd_payload_ras = 1'd0; +reg netv2_sdram_bankmachine5_cmd_payload_we = 1'd0; +reg netv2_sdram_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg netv2_sdram_bankmachine5_cmd_payload_is_read = 1'd0; +reg netv2_sdram_bankmachine5_cmd_payload_is_write = 1'd0; +reg netv2_sdram_bankmachine5_auto_precharge = 1'd0; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready; +reg netv2_sdram_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg netv2_sdram_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] netv2_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_valid; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_ready; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_first; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_last; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we; +wire [20:0] netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +wire [23:0] netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +wire [23:0] netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +reg [3:0] netv2_sdram_bankmachine5_cmd_buffer_lookahead_level = 4'd0; +reg netv2_sdram_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] netv2_sdram_bankmachine5_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] netv2_sdram_bankmachine5_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] netv2_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] netv2_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we; +wire [23:0] netv2_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_do_read; +wire [2:0] netv2_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr; +wire [23:0] netv2_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +wire netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +wire netv2_sdram_bankmachine5_cmd_buffer_sink_valid; +wire netv2_sdram_bankmachine5_cmd_buffer_sink_ready; +wire netv2_sdram_bankmachine5_cmd_buffer_sink_first; +wire netv2_sdram_bankmachine5_cmd_buffer_sink_last; +wire netv2_sdram_bankmachine5_cmd_buffer_sink_payload_we; +wire [20:0] netv2_sdram_bankmachine5_cmd_buffer_sink_payload_addr; +reg netv2_sdram_bankmachine5_cmd_buffer_source_valid = 1'd0; +wire netv2_sdram_bankmachine5_cmd_buffer_source_ready; +reg netv2_sdram_bankmachine5_cmd_buffer_source_first = 1'd0; +reg netv2_sdram_bankmachine5_cmd_buffer_source_last = 1'd0; +reg netv2_sdram_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] netv2_sdram_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] netv2_sdram_bankmachine5_row = 14'd0; +reg netv2_sdram_bankmachine5_row_opened = 1'd0; +wire netv2_sdram_bankmachine5_row_hit; +reg netv2_sdram_bankmachine5_row_open = 1'd0; +reg netv2_sdram_bankmachine5_row_close = 1'd0; +reg netv2_sdram_bankmachine5_row_col_n_addr_sel = 1'd0; +wire netv2_sdram_bankmachine5_twtpcon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine5_twtpcon_count = 3'd0; +wire netv2_sdram_bankmachine5_trccon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine5_trccon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine5_trccon_count = 3'd0; +wire netv2_sdram_bankmachine5_trascon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine5_trascon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine5_trascon_count = 3'd0; +wire netv2_sdram_bankmachine6_req_valid; +wire netv2_sdram_bankmachine6_req_ready; +wire netv2_sdram_bankmachine6_req_we; +wire [20:0] netv2_sdram_bankmachine6_req_addr; +wire netv2_sdram_bankmachine6_req_lock; +reg netv2_sdram_bankmachine6_req_wdata_ready = 1'd0; +reg netv2_sdram_bankmachine6_req_rdata_valid = 1'd0; +wire netv2_sdram_bankmachine6_refresh_req; +reg netv2_sdram_bankmachine6_refresh_gnt = 1'd0; +reg netv2_sdram_bankmachine6_cmd_valid = 1'd0; +reg netv2_sdram_bankmachine6_cmd_ready = 1'd0; +reg [13:0] netv2_sdram_bankmachine6_cmd_payload_a = 14'd0; +wire [2:0] netv2_sdram_bankmachine6_cmd_payload_ba; +reg netv2_sdram_bankmachine6_cmd_payload_cas = 1'd0; +reg netv2_sdram_bankmachine6_cmd_payload_ras = 1'd0; +reg netv2_sdram_bankmachine6_cmd_payload_we = 1'd0; +reg netv2_sdram_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg netv2_sdram_bankmachine6_cmd_payload_is_read = 1'd0; +reg netv2_sdram_bankmachine6_cmd_payload_is_write = 1'd0; +reg netv2_sdram_bankmachine6_auto_precharge = 1'd0; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready; +reg netv2_sdram_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg netv2_sdram_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] netv2_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_valid; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_ready; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_first; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_last; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we; +wire [20:0] netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +wire [23:0] netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +wire [23:0] netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +reg [3:0] netv2_sdram_bankmachine6_cmd_buffer_lookahead_level = 4'd0; +reg netv2_sdram_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] netv2_sdram_bankmachine6_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] netv2_sdram_bankmachine6_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] netv2_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] netv2_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we; +wire [23:0] netv2_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_do_read; +wire [2:0] netv2_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr; +wire [23:0] netv2_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +wire netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +wire netv2_sdram_bankmachine6_cmd_buffer_sink_valid; +wire netv2_sdram_bankmachine6_cmd_buffer_sink_ready; +wire netv2_sdram_bankmachine6_cmd_buffer_sink_first; +wire netv2_sdram_bankmachine6_cmd_buffer_sink_last; +wire netv2_sdram_bankmachine6_cmd_buffer_sink_payload_we; +wire [20:0] netv2_sdram_bankmachine6_cmd_buffer_sink_payload_addr; +reg netv2_sdram_bankmachine6_cmd_buffer_source_valid = 1'd0; +wire netv2_sdram_bankmachine6_cmd_buffer_source_ready; +reg netv2_sdram_bankmachine6_cmd_buffer_source_first = 1'd0; +reg netv2_sdram_bankmachine6_cmd_buffer_source_last = 1'd0; +reg netv2_sdram_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] netv2_sdram_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] netv2_sdram_bankmachine6_row = 14'd0; +reg netv2_sdram_bankmachine6_row_opened = 1'd0; +wire netv2_sdram_bankmachine6_row_hit; +reg netv2_sdram_bankmachine6_row_open = 1'd0; +reg netv2_sdram_bankmachine6_row_close = 1'd0; +reg netv2_sdram_bankmachine6_row_col_n_addr_sel = 1'd0; +wire netv2_sdram_bankmachine6_twtpcon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine6_twtpcon_count = 3'd0; +wire netv2_sdram_bankmachine6_trccon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine6_trccon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine6_trccon_count = 3'd0; +wire netv2_sdram_bankmachine6_trascon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine6_trascon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine6_trascon_count = 3'd0; +wire netv2_sdram_bankmachine7_req_valid; +wire netv2_sdram_bankmachine7_req_ready; +wire netv2_sdram_bankmachine7_req_we; +wire [20:0] netv2_sdram_bankmachine7_req_addr; +wire netv2_sdram_bankmachine7_req_lock; +reg netv2_sdram_bankmachine7_req_wdata_ready = 1'd0; +reg netv2_sdram_bankmachine7_req_rdata_valid = 1'd0; +wire netv2_sdram_bankmachine7_refresh_req; +reg netv2_sdram_bankmachine7_refresh_gnt = 1'd0; +reg netv2_sdram_bankmachine7_cmd_valid = 1'd0; +reg netv2_sdram_bankmachine7_cmd_ready = 1'd0; +reg [13:0] netv2_sdram_bankmachine7_cmd_payload_a = 14'd0; +wire [2:0] netv2_sdram_bankmachine7_cmd_payload_ba; +reg netv2_sdram_bankmachine7_cmd_payload_cas = 1'd0; +reg netv2_sdram_bankmachine7_cmd_payload_ras = 1'd0; +reg netv2_sdram_bankmachine7_cmd_payload_we = 1'd0; +reg netv2_sdram_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg netv2_sdram_bankmachine7_cmd_payload_is_read = 1'd0; +reg netv2_sdram_bankmachine7_cmd_payload_is_write = 1'd0; +reg netv2_sdram_bankmachine7_auto_precharge = 1'd0; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready; +reg netv2_sdram_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg netv2_sdram_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] netv2_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_valid; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_ready; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_first; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_last; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we; +wire [20:0] netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +wire [23:0] netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +wire [23:0] netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +reg [3:0] netv2_sdram_bankmachine7_cmd_buffer_lookahead_level = 4'd0; +reg netv2_sdram_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] netv2_sdram_bankmachine7_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] netv2_sdram_bankmachine7_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] netv2_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] netv2_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we; +wire [23:0] netv2_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_do_read; +wire [2:0] netv2_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr; +wire [23:0] netv2_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +wire netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +wire netv2_sdram_bankmachine7_cmd_buffer_sink_valid; +wire netv2_sdram_bankmachine7_cmd_buffer_sink_ready; +wire netv2_sdram_bankmachine7_cmd_buffer_sink_first; +wire netv2_sdram_bankmachine7_cmd_buffer_sink_last; +wire netv2_sdram_bankmachine7_cmd_buffer_sink_payload_we; +wire [20:0] netv2_sdram_bankmachine7_cmd_buffer_sink_payload_addr; +reg netv2_sdram_bankmachine7_cmd_buffer_source_valid = 1'd0; +wire netv2_sdram_bankmachine7_cmd_buffer_source_ready; +reg netv2_sdram_bankmachine7_cmd_buffer_source_first = 1'd0; +reg netv2_sdram_bankmachine7_cmd_buffer_source_last = 1'd0; +reg netv2_sdram_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] netv2_sdram_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] netv2_sdram_bankmachine7_row = 14'd0; +reg netv2_sdram_bankmachine7_row_opened = 1'd0; +wire netv2_sdram_bankmachine7_row_hit; +reg netv2_sdram_bankmachine7_row_open = 1'd0; +reg netv2_sdram_bankmachine7_row_close = 1'd0; +reg netv2_sdram_bankmachine7_row_col_n_addr_sel = 1'd0; +wire netv2_sdram_bankmachine7_twtpcon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine7_twtpcon_count = 3'd0; +wire netv2_sdram_bankmachine7_trccon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine7_trccon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine7_trccon_count = 3'd0; +wire netv2_sdram_bankmachine7_trascon_valid; +(* dont_touch = "true" *) reg netv2_sdram_bankmachine7_trascon_ready = 1'd0; +reg [2:0] netv2_sdram_bankmachine7_trascon_count = 3'd0; +wire netv2_sdram_ras_allowed; +wire netv2_sdram_cas_allowed; +wire [1:0] netv2_sdram_rdcmdphase; +wire [1:0] netv2_sdram_wrcmdphase; +reg netv2_sdram_choose_cmd_want_reads = 1'd0; +reg netv2_sdram_choose_cmd_want_writes = 1'd0; +reg netv2_sdram_choose_cmd_want_cmds = 1'd0; +reg netv2_sdram_choose_cmd_want_activates = 1'd0; +wire netv2_sdram_choose_cmd_cmd_valid; +reg netv2_sdram_choose_cmd_cmd_ready = 1'd0; +wire [13:0] netv2_sdram_choose_cmd_cmd_payload_a; +wire [2:0] netv2_sdram_choose_cmd_cmd_payload_ba; +reg netv2_sdram_choose_cmd_cmd_payload_cas = 1'd0; +reg netv2_sdram_choose_cmd_cmd_payload_ras = 1'd0; +reg netv2_sdram_choose_cmd_cmd_payload_we = 1'd0; +wire netv2_sdram_choose_cmd_cmd_payload_is_cmd; +wire netv2_sdram_choose_cmd_cmd_payload_is_read; +wire netv2_sdram_choose_cmd_cmd_payload_is_write; +reg [7:0] netv2_sdram_choose_cmd_valids = 8'd0; +wire [7:0] netv2_sdram_choose_cmd_request; +reg [2:0] netv2_sdram_choose_cmd_grant = 3'd0; +wire netv2_sdram_choose_cmd_ce; +reg netv2_sdram_choose_req_want_reads = 1'd0; +reg netv2_sdram_choose_req_want_writes = 1'd0; +reg netv2_sdram_choose_req_want_cmds = 1'd0; +reg netv2_sdram_choose_req_want_activates = 1'd0; +wire netv2_sdram_choose_req_cmd_valid; +reg netv2_sdram_choose_req_cmd_ready = 1'd0; +wire [13:0] netv2_sdram_choose_req_cmd_payload_a; +wire [2:0] netv2_sdram_choose_req_cmd_payload_ba; +reg netv2_sdram_choose_req_cmd_payload_cas = 1'd0; +reg netv2_sdram_choose_req_cmd_payload_ras = 1'd0; +reg netv2_sdram_choose_req_cmd_payload_we = 1'd0; +wire netv2_sdram_choose_req_cmd_payload_is_cmd; +wire netv2_sdram_choose_req_cmd_payload_is_read; +wire netv2_sdram_choose_req_cmd_payload_is_write; +reg [7:0] netv2_sdram_choose_req_valids = 8'd0; +wire [7:0] netv2_sdram_choose_req_request; +reg [2:0] netv2_sdram_choose_req_grant = 3'd0; +wire netv2_sdram_choose_req_ce; +reg [13:0] netv2_sdram_nop_a = 14'd0; +reg [2:0] netv2_sdram_nop_ba = 3'd0; +reg [1:0] netv2_sdram_steerer_sel0 = 2'd0; +reg [1:0] netv2_sdram_steerer_sel1 = 2'd0; +reg [1:0] netv2_sdram_steerer_sel2 = 2'd0; +reg [1:0] netv2_sdram_steerer_sel3 = 2'd0; +reg netv2_sdram_steerer0 = 1'd1; +reg netv2_sdram_steerer1 = 1'd1; +reg netv2_sdram_steerer2 = 1'd1; +reg netv2_sdram_steerer3 = 1'd1; +reg netv2_sdram_steerer4 = 1'd1; +reg netv2_sdram_steerer5 = 1'd1; +reg netv2_sdram_steerer6 = 1'd1; +reg netv2_sdram_steerer7 = 1'd1; +wire netv2_sdram_trrdcon_valid; +(* dont_touch = "true" *) reg netv2_sdram_trrdcon_ready = 1'd0; +reg netv2_sdram_trrdcon_count = 1'd0; +wire netv2_sdram_tfawcon_valid; +(* dont_touch = "true" *) reg netv2_sdram_tfawcon_ready = 1'd1; +wire [2:0] netv2_sdram_tfawcon_count; +reg [4:0] netv2_sdram_tfawcon_window = 5'd0; +wire netv2_sdram_tccdcon_valid; +(* dont_touch = "true" *) reg netv2_sdram_tccdcon_ready = 1'd0; +reg netv2_sdram_tccdcon_count = 1'd0; +wire netv2_sdram_twtrcon_valid; +(* dont_touch = "true" *) reg netv2_sdram_twtrcon_ready = 1'd0; +reg [2:0] netv2_sdram_twtrcon_count = 3'd0; +wire netv2_sdram_read_available; +wire netv2_sdram_write_available; +reg netv2_sdram_en0 = 1'd0; +wire netv2_sdram_max_time0; +reg [4:0] netv2_sdram_time0 = 5'd0; +reg netv2_sdram_en1 = 1'd0; +wire netv2_sdram_max_time1; +reg [3:0] netv2_sdram_time1 = 4'd0; +wire netv2_sdram_go_to_refresh; +wire netv2_port_flush; +wire netv2_port_cmd_valid; +wire netv2_port_cmd_ready; +wire netv2_port_cmd_last; +wire netv2_port_cmd_payload_we; +wire [23:0] netv2_port_cmd_payload_addr; +wire netv2_port_wdata_valid; +wire netv2_port_wdata_ready; +wire [255:0] netv2_port_wdata_payload_data; +wire [31:0] netv2_port_wdata_payload_we; +wire netv2_port_rdata_valid; +wire netv2_port_rdata_ready; +wire [255:0] netv2_port_rdata_payload_data; +wire [29:0] netv2_wb_sdram_adr; +wire [31:0] netv2_wb_sdram_dat_w; +reg [31:0] netv2_wb_sdram_dat_r = 32'd0; +wire [3:0] netv2_wb_sdram_sel; +wire netv2_wb_sdram_cyc; +wire netv2_wb_sdram_stb; +reg netv2_wb_sdram_ack = 1'd0; +wire netv2_wb_sdram_we; +wire [2:0] netv2_wb_sdram_cti; +wire [1:0] netv2_wb_sdram_bte; +reg netv2_wb_sdram_err = 1'd0; +wire [29:0] netv2_interface_adr; +wire [255:0] netv2_interface_dat_w; +wire [255:0] netv2_interface_dat_r; +wire [31:0] netv2_interface_sel; +reg netv2_interface_cyc = 1'd0; +reg netv2_interface_stb = 1'd0; +wire netv2_interface_ack; +reg netv2_interface_we = 1'd0; +wire [1:0] netv2_data_port_adr; +wire [255:0] netv2_data_port_dat_r; +reg [31:0] netv2_data_port_we = 32'd0; +reg [255:0] netv2_data_port_dat_w = 256'd0; +reg netv2_write_from_slave = 1'd0; +reg [2:0] netv2_adr_offset_r = 3'd0; +wire [1:0] netv2_tag_port_adr; +wire [31:0] netv2_tag_port_dat_r; +reg netv2_tag_port_we = 1'd0; +wire [31:0] netv2_tag_port_dat_w; +wire [30:0] netv2_tag_do_tag; +wire netv2_tag_do_dirty; +wire [30:0] netv2_tag_di_tag; +reg netv2_tag_di_dirty = 1'd0; +reg netv2_word_clr = 1'd0; +reg netv2_word_inc = 1'd0; +reg netv2_cmd_consumed = 1'd0; +reg netv2_wdata_consumed = 1'd0; +wire netv2_ack_cmd; +wire netv2_ack_wdata; +wire netv2_ack_rdata; +reg ethphy_reset_storage = 1'd0; +reg ethphy_reset_re = 1'd0; +(* dont_touch = "true" *) wire eth_rx_clk; +wire eth_rx_rst; +(* dont_touch = "true" *) wire eth_tx_clk; +wire eth_tx_rst; +wire ethphy_reset0; +wire ethphy_reset1; +reg [8:0] ethphy_counter = 9'd0; +wire ethphy_counter_done; +wire ethphy_counter_ce; +wire ethphy_liteethphyrmiitx_sink_sink_valid; +wire ethphy_liteethphyrmiitx_sink_sink_ready; +wire ethphy_liteethphyrmiitx_sink_sink_first; +wire ethphy_liteethphyrmiitx_sink_sink_last; +wire [7:0] ethphy_liteethphyrmiitx_sink_sink_payload_data; +wire ethphy_liteethphyrmiitx_sink_sink_payload_last_be; +wire ethphy_liteethphyrmiitx_sink_sink_payload_error; +wire ethphy_liteethphyrmiitx_converter_sink_valid; +wire ethphy_liteethphyrmiitx_converter_sink_ready; +reg ethphy_liteethphyrmiitx_converter_sink_first = 1'd0; +reg ethphy_liteethphyrmiitx_converter_sink_last = 1'd0; +wire [7:0] ethphy_liteethphyrmiitx_converter_sink_payload_data; +wire ethphy_liteethphyrmiitx_converter_source_valid; +wire ethphy_liteethphyrmiitx_converter_source_ready; +wire ethphy_liteethphyrmiitx_converter_source_first; +wire ethphy_liteethphyrmiitx_converter_source_last; +wire [1:0] ethphy_liteethphyrmiitx_converter_source_payload_data; +wire ethphy_liteethphyrmiitx_converter_converter_sink_valid; +wire ethphy_liteethphyrmiitx_converter_converter_sink_ready; +wire ethphy_liteethphyrmiitx_converter_converter_sink_first; +wire ethphy_liteethphyrmiitx_converter_converter_sink_last; +reg [7:0] ethphy_liteethphyrmiitx_converter_converter_sink_payload_data = 8'd0; +wire ethphy_liteethphyrmiitx_converter_converter_source_valid; +wire ethphy_liteethphyrmiitx_converter_converter_source_ready; +wire ethphy_liteethphyrmiitx_converter_converter_source_first; +wire ethphy_liteethphyrmiitx_converter_converter_source_last; +reg [1:0] ethphy_liteethphyrmiitx_converter_converter_source_payload_data = 2'd0; +wire ethphy_liteethphyrmiitx_converter_converter_source_payload_valid_token_count; +reg [1:0] ethphy_liteethphyrmiitx_converter_converter_mux = 2'd0; +wire ethphy_liteethphyrmiitx_converter_converter_first; +wire ethphy_liteethphyrmiitx_converter_converter_last; +wire ethphy_liteethphyrmiitx_converter_source_source_valid; +wire ethphy_liteethphyrmiitx_converter_source_source_ready; +wire ethphy_liteethphyrmiitx_converter_source_source_first; +wire ethphy_liteethphyrmiitx_converter_source_source_last; +wire [1:0] ethphy_liteethphyrmiitx_converter_source_source_payload_data; +wire ethphy_liteethphyrmiirx_source_source_valid; +wire ethphy_liteethphyrmiirx_source_source_ready; +wire ethphy_liteethphyrmiirx_source_source_first; +wire ethphy_liteethphyrmiirx_source_source_last; +wire [7:0] ethphy_liteethphyrmiirx_source_source_payload_data; +reg ethphy_liteethphyrmiirx_source_source_payload_last_be = 1'd0; +reg ethphy_liteethphyrmiirx_source_source_payload_error = 1'd0; +wire ethphy_liteethphyrmiirx_converter_sink_valid0; +wire ethphy_liteethphyrmiirx_converter_sink_ready; +reg ethphy_liteethphyrmiirx_converter_sink_first = 1'd0; +reg ethphy_liteethphyrmiirx_converter_sink_last = 1'd0; +wire [1:0] ethphy_liteethphyrmiirx_converter_sink_payload_data; +wire ethphy_liteethphyrmiirx_converter_source_valid; +wire ethphy_liteethphyrmiirx_converter_source_ready; +wire ethphy_liteethphyrmiirx_converter_source_first; +wire ethphy_liteethphyrmiirx_converter_source_last; +reg [7:0] ethphy_liteethphyrmiirx_converter_source_payload_data = 8'd0; +wire ethphy_liteethphyrmiirx_converter_converter_sink_valid; +wire ethphy_liteethphyrmiirx_converter_converter_sink_ready; +wire ethphy_liteethphyrmiirx_converter_converter_sink_first; +wire ethphy_liteethphyrmiirx_converter_converter_sink_last; +wire [1:0] ethphy_liteethphyrmiirx_converter_converter_sink_payload_data; +wire ethphy_liteethphyrmiirx_converter_converter_source_valid; +wire ethphy_liteethphyrmiirx_converter_converter_source_ready; +reg ethphy_liteethphyrmiirx_converter_converter_source_first = 1'd0; +reg ethphy_liteethphyrmiirx_converter_converter_source_last = 1'd0; +reg [7:0] ethphy_liteethphyrmiirx_converter_converter_source_payload_data = 8'd0; +reg [2:0] ethphy_liteethphyrmiirx_converter_converter_source_payload_valid_token_count = 3'd0; +reg [1:0] ethphy_liteethphyrmiirx_converter_converter_demux = 2'd0; +wire ethphy_liteethphyrmiirx_converter_converter_load_part; +reg ethphy_liteethphyrmiirx_converter_converter_strobe_all = 1'd0; +wire ethphy_liteethphyrmiirx_converter_source_source_valid; +wire ethphy_liteethphyrmiirx_converter_source_source_ready; +wire ethphy_liteethphyrmiirx_converter_source_source_first; +wire ethphy_liteethphyrmiirx_converter_source_source_last; +wire [7:0] ethphy_liteethphyrmiirx_converter_source_source_payload_data; +reg ethphy_liteethphyrmiirx_converter_reset = 1'd0; +reg ethphy_liteethphyrmiirx_converter_sink_valid1 = 1'd0; +reg [1:0] ethphy_liteethphyrmiirx_converter_sink_data = 2'd0; +reg ethphy_liteethphyrmiirx_crs_dv = 1'd0; +reg ethphy_liteethphyrmiirx_crs_dv_d = 1'd0; +reg [1:0] ethphy_liteethphyrmiirx_rx_data = 2'd0; +wire ethphy_mdc; +wire ethphy_oe; +wire ethphy_w; +reg [2:0] ethphy__w_storage = 3'd0; +reg ethphy__w_re = 1'd0; +reg ethphy_r = 1'd0; +reg ethphy__r_status = 1'd0; +wire ethphy__r_we; +wire ethphy__r_re; +wire ethphy_data_w; +wire ethphy_data_oe; +wire ethphy_data_r; +wire ethcore_mac_tx_gap_inserter_sink_valid; +reg ethcore_mac_tx_gap_inserter_sink_ready = 1'd0; +wire ethcore_mac_tx_gap_inserter_sink_first; +wire ethcore_mac_tx_gap_inserter_sink_last; +wire [7:0] ethcore_mac_tx_gap_inserter_sink_payload_data; +wire ethcore_mac_tx_gap_inserter_sink_payload_last_be; +wire ethcore_mac_tx_gap_inserter_sink_payload_error; +reg ethcore_mac_tx_gap_inserter_source_valid = 1'd0; +wire ethcore_mac_tx_gap_inserter_source_ready; +reg ethcore_mac_tx_gap_inserter_source_first = 1'd0; +reg ethcore_mac_tx_gap_inserter_source_last = 1'd0; +reg [7:0] ethcore_mac_tx_gap_inserter_source_payload_data = 8'd0; +reg ethcore_mac_tx_gap_inserter_source_payload_last_be = 1'd0; +reg ethcore_mac_tx_gap_inserter_source_payload_error = 1'd0; +reg [3:0] ethcore_mac_tx_gap_inserter_counter = 4'd0; +reg [31:0] ethcore_mac_preamble_errors_status = 32'd0; +reg [31:0] ethcore_mac_crc_errors_status = 32'd0; +wire ethcore_mac_preamble_inserter_sink_valid; +reg ethcore_mac_preamble_inserter_sink_ready = 1'd0; +wire ethcore_mac_preamble_inserter_sink_first; +wire ethcore_mac_preamble_inserter_sink_last; +wire [7:0] ethcore_mac_preamble_inserter_sink_payload_data; +wire ethcore_mac_preamble_inserter_sink_payload_last_be; +wire ethcore_mac_preamble_inserter_sink_payload_error; +reg ethcore_mac_preamble_inserter_source_valid = 1'd0; +wire ethcore_mac_preamble_inserter_source_ready; +reg ethcore_mac_preamble_inserter_source_first = 1'd0; +reg ethcore_mac_preamble_inserter_source_last = 1'd0; +reg [7:0] ethcore_mac_preamble_inserter_source_payload_data = 8'd0; +wire ethcore_mac_preamble_inserter_source_payload_last_be; +reg ethcore_mac_preamble_inserter_source_payload_error = 1'd0; +reg [63:0] ethcore_mac_preamble_inserter_preamble = 64'd15372286728091293013; +reg [2:0] ethcore_mac_preamble_inserter_count = 3'd0; +wire ethcore_mac_preamble_checker_sink_valid; +reg ethcore_mac_preamble_checker_sink_ready = 1'd0; +wire ethcore_mac_preamble_checker_sink_first; +wire ethcore_mac_preamble_checker_sink_last; +wire [7:0] ethcore_mac_preamble_checker_sink_payload_data; +wire ethcore_mac_preamble_checker_sink_payload_last_be; +wire ethcore_mac_preamble_checker_sink_payload_error; +reg ethcore_mac_preamble_checker_source_valid = 1'd0; +wire ethcore_mac_preamble_checker_source_ready; +reg ethcore_mac_preamble_checker_source_first = 1'd0; +reg ethcore_mac_preamble_checker_source_last = 1'd0; +wire [7:0] ethcore_mac_preamble_checker_source_payload_data; +wire ethcore_mac_preamble_checker_source_payload_last_be; +reg ethcore_mac_preamble_checker_source_payload_error = 1'd0; +reg ethcore_mac_preamble_checker_error = 1'd0; +wire ethcore_mac_liteethmaccrc32inserter_sink_valid; +reg ethcore_mac_liteethmaccrc32inserter_sink_ready = 1'd0; +wire ethcore_mac_liteethmaccrc32inserter_sink_first; +wire ethcore_mac_liteethmaccrc32inserter_sink_last; +wire [7:0] ethcore_mac_liteethmaccrc32inserter_sink_payload_data; +wire ethcore_mac_liteethmaccrc32inserter_sink_payload_last_be; +wire ethcore_mac_liteethmaccrc32inserter_sink_payload_error; +reg ethcore_mac_liteethmaccrc32inserter_source_valid = 1'd0; +wire ethcore_mac_liteethmaccrc32inserter_source_ready; +reg ethcore_mac_liteethmaccrc32inserter_source_first = 1'd0; +reg ethcore_mac_liteethmaccrc32inserter_source_last = 1'd0; +reg [7:0] ethcore_mac_liteethmaccrc32inserter_source_payload_data = 8'd0; +reg ethcore_mac_liteethmaccrc32inserter_source_payload_last_be = 1'd0; +reg ethcore_mac_liteethmaccrc32inserter_source_payload_error = 1'd0; +reg [7:0] ethcore_mac_liteethmaccrc32inserter_data0 = 8'd0; +wire [31:0] ethcore_mac_liteethmaccrc32inserter_value; +wire ethcore_mac_liteethmaccrc32inserter_error; +wire [7:0] ethcore_mac_liteethmaccrc32inserter_data1; +wire [31:0] ethcore_mac_liteethmaccrc32inserter_last; +reg [31:0] ethcore_mac_liteethmaccrc32inserter_next = 32'd0; +reg [31:0] ethcore_mac_liteethmaccrc32inserter_reg = 32'd4294967295; +reg ethcore_mac_liteethmaccrc32inserter_ce = 1'd0; +reg ethcore_mac_liteethmaccrc32inserter_reset = 1'd0; +reg [1:0] ethcore_mac_liteethmaccrc32inserter_cnt = 2'd3; +wire ethcore_mac_liteethmaccrc32inserter_cnt_done; +reg ethcore_mac_liteethmaccrc32inserter_is_ongoing0 = 1'd0; +reg ethcore_mac_liteethmaccrc32inserter_is_ongoing1 = 1'd0; +wire ethcore_mac_crc32_inserter_sink_valid; +wire ethcore_mac_crc32_inserter_sink_ready; +wire ethcore_mac_crc32_inserter_sink_first; +wire ethcore_mac_crc32_inserter_sink_last; +wire [7:0] ethcore_mac_crc32_inserter_sink_payload_data; +wire ethcore_mac_crc32_inserter_sink_payload_last_be; +wire ethcore_mac_crc32_inserter_sink_payload_error; +reg ethcore_mac_crc32_inserter_source_valid = 1'd0; +wire ethcore_mac_crc32_inserter_source_ready; +reg ethcore_mac_crc32_inserter_source_first = 1'd0; +reg ethcore_mac_crc32_inserter_source_last = 1'd0; +reg [7:0] ethcore_mac_crc32_inserter_source_payload_data = 8'd0; +reg ethcore_mac_crc32_inserter_source_payload_last_be = 1'd0; +reg ethcore_mac_crc32_inserter_source_payload_error = 1'd0; +wire ethcore_mac_liteethmaccrc32checker_sink_sink_valid; +reg ethcore_mac_liteethmaccrc32checker_sink_sink_ready = 1'd0; +wire ethcore_mac_liteethmaccrc32checker_sink_sink_first; +wire ethcore_mac_liteethmaccrc32checker_sink_sink_last; +wire [7:0] ethcore_mac_liteethmaccrc32checker_sink_sink_payload_data; +wire ethcore_mac_liteethmaccrc32checker_sink_sink_payload_last_be; +wire ethcore_mac_liteethmaccrc32checker_sink_sink_payload_error; +wire ethcore_mac_liteethmaccrc32checker_source_source_valid; +wire ethcore_mac_liteethmaccrc32checker_source_source_ready; +reg ethcore_mac_liteethmaccrc32checker_source_source_first = 1'd0; +wire ethcore_mac_liteethmaccrc32checker_source_source_last; +wire [7:0] ethcore_mac_liteethmaccrc32checker_source_source_payload_data; +wire ethcore_mac_liteethmaccrc32checker_source_source_payload_last_be; +reg ethcore_mac_liteethmaccrc32checker_source_source_payload_error = 1'd0; +wire ethcore_mac_liteethmaccrc32checker_error; +wire [7:0] ethcore_mac_liteethmaccrc32checker_crc_data0; +wire [31:0] ethcore_mac_liteethmaccrc32checker_crc_value; +wire ethcore_mac_liteethmaccrc32checker_crc_error; +wire [7:0] ethcore_mac_liteethmaccrc32checker_crc_data1; +wire [31:0] ethcore_mac_liteethmaccrc32checker_crc_last; +reg [31:0] ethcore_mac_liteethmaccrc32checker_crc_next = 32'd0; +reg [31:0] ethcore_mac_liteethmaccrc32checker_crc_reg = 32'd4294967295; +reg ethcore_mac_liteethmaccrc32checker_crc_ce = 1'd0; +reg ethcore_mac_liteethmaccrc32checker_crc_reset = 1'd0; +reg ethcore_mac_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_sink_ready; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_sink_first; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_sink_last; +wire [7:0] ethcore_mac_liteethmaccrc32checker_syncfifo_sink_payload_data; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_sink_payload_error; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_source_valid; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_source_ready; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_source_first; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_source_last; +wire [7:0] ethcore_mac_liteethmaccrc32checker_syncfifo_source_payload_data; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_source_payload_last_be; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_source_payload_error; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_we; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_writable; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_re; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_readable; +wire [11:0] ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_din; +wire [11:0] ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_dout; +reg [2:0] ethcore_mac_liteethmaccrc32checker_syncfifo_level = 3'd0; +reg ethcore_mac_liteethmaccrc32checker_syncfifo_replace = 1'd0; +reg [2:0] ethcore_mac_liteethmaccrc32checker_syncfifo_produce = 3'd0; +reg [2:0] ethcore_mac_liteethmaccrc32checker_syncfifo_consume = 3'd0; +reg [2:0] ethcore_mac_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; +wire [11:0] ethcore_mac_liteethmaccrc32checker_syncfifo_wrport_dat_r; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_wrport_we; +wire [11:0] ethcore_mac_liteethmaccrc32checker_syncfifo_wrport_dat_w; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_do_read; +wire [2:0] ethcore_mac_liteethmaccrc32checker_syncfifo_rdport_adr; +wire [11:0] ethcore_mac_liteethmaccrc32checker_syncfifo_rdport_dat_r; +wire [7:0] ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_in_first; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_in_last; +wire [7:0] ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_out_first; +wire ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_out_last; +reg ethcore_mac_liteethmaccrc32checker_fifo_reset = 1'd0; +wire ethcore_mac_liteethmaccrc32checker_fifo_in; +wire ethcore_mac_liteethmaccrc32checker_fifo_out; +wire ethcore_mac_liteethmaccrc32checker_fifo_full; +wire ethcore_mac_crc32_checker_sink_valid; +wire ethcore_mac_crc32_checker_sink_ready; +wire ethcore_mac_crc32_checker_sink_first; +wire ethcore_mac_crc32_checker_sink_last; +wire [7:0] ethcore_mac_crc32_checker_sink_payload_data; +wire ethcore_mac_crc32_checker_sink_payload_last_be; +wire ethcore_mac_crc32_checker_sink_payload_error; +reg ethcore_mac_crc32_checker_source_valid = 1'd0; +wire ethcore_mac_crc32_checker_source_ready; +reg ethcore_mac_crc32_checker_source_first = 1'd0; +reg ethcore_mac_crc32_checker_source_last = 1'd0; +reg [7:0] ethcore_mac_crc32_checker_source_payload_data = 8'd0; +reg ethcore_mac_crc32_checker_source_payload_last_be = 1'd0; +reg ethcore_mac_crc32_checker_source_payload_error = 1'd0; +wire ethcore_mac_ps_preamble_error_i; +wire ethcore_mac_ps_preamble_error_o; +reg ethcore_mac_ps_preamble_error_toggle_i = 1'd0; +wire ethcore_mac_ps_preamble_error_toggle_o; +reg ethcore_mac_ps_preamble_error_toggle_o_r = 1'd0; +wire ethcore_mac_ps_crc_error_i; +wire ethcore_mac_ps_crc_error_o; +reg ethcore_mac_ps_crc_error_toggle_i = 1'd0; +wire ethcore_mac_ps_crc_error_toggle_o; +reg ethcore_mac_ps_crc_error_toggle_o_r = 1'd0; +wire ethcore_mac_padding_inserter_sink_valid; +reg ethcore_mac_padding_inserter_sink_ready = 1'd0; +wire ethcore_mac_padding_inserter_sink_first; +wire ethcore_mac_padding_inserter_sink_last; +wire [7:0] ethcore_mac_padding_inserter_sink_payload_data; +wire ethcore_mac_padding_inserter_sink_payload_last_be; +wire ethcore_mac_padding_inserter_sink_payload_error; +reg ethcore_mac_padding_inserter_source_valid = 1'd0; +wire ethcore_mac_padding_inserter_source_ready; +reg ethcore_mac_padding_inserter_source_first = 1'd0; +reg ethcore_mac_padding_inserter_source_last = 1'd0; +reg [7:0] ethcore_mac_padding_inserter_source_payload_data = 8'd0; +reg ethcore_mac_padding_inserter_source_payload_last_be = 1'd0; +reg ethcore_mac_padding_inserter_source_payload_error = 1'd0; +reg [15:0] ethcore_mac_padding_inserter_counter = 16'd0; +wire ethcore_mac_padding_inserter_counter_done; +wire ethcore_mac_padding_checker_sink_valid; +wire ethcore_mac_padding_checker_sink_ready; +wire ethcore_mac_padding_checker_sink_first; +wire ethcore_mac_padding_checker_sink_last; +wire [7:0] ethcore_mac_padding_checker_sink_payload_data; +wire ethcore_mac_padding_checker_sink_payload_last_be; +wire ethcore_mac_padding_checker_sink_payload_error; +wire ethcore_mac_padding_checker_source_valid; +wire ethcore_mac_padding_checker_source_ready; +wire ethcore_mac_padding_checker_source_first; +wire ethcore_mac_padding_checker_source_last; +wire [7:0] ethcore_mac_padding_checker_source_payload_data; +wire ethcore_mac_padding_checker_source_payload_last_be; +wire ethcore_mac_padding_checker_source_payload_error; +wire ethcore_mac_tx_cdc_sink_valid; +wire ethcore_mac_tx_cdc_sink_ready; +wire ethcore_mac_tx_cdc_sink_first; +wire ethcore_mac_tx_cdc_sink_last; +wire [7:0] ethcore_mac_tx_cdc_sink_payload_data; +wire ethcore_mac_tx_cdc_sink_payload_last_be; +wire ethcore_mac_tx_cdc_sink_payload_error; +wire ethcore_mac_tx_cdc_source_valid; +wire ethcore_mac_tx_cdc_source_ready; +wire ethcore_mac_tx_cdc_source_first; +wire ethcore_mac_tx_cdc_source_last; +wire [7:0] ethcore_mac_tx_cdc_source_payload_data; +wire ethcore_mac_tx_cdc_source_payload_last_be; +wire ethcore_mac_tx_cdc_source_payload_error; +wire ethcore_mac_tx_cdc_asyncfifo_we; +wire ethcore_mac_tx_cdc_asyncfifo_writable; +wire ethcore_mac_tx_cdc_asyncfifo_re; +wire ethcore_mac_tx_cdc_asyncfifo_readable; +wire [11:0] ethcore_mac_tx_cdc_asyncfifo_din; +wire [11:0] ethcore_mac_tx_cdc_asyncfifo_dout; +wire ethcore_mac_tx_cdc_graycounter0_ce; +(* dont_touch = "true" *) reg [6:0] ethcore_mac_tx_cdc_graycounter0_q = 7'd0; +wire [6:0] ethcore_mac_tx_cdc_graycounter0_q_next; +reg [6:0] ethcore_mac_tx_cdc_graycounter0_q_binary = 7'd0; +reg [6:0] ethcore_mac_tx_cdc_graycounter0_q_next_binary = 7'd0; +wire ethcore_mac_tx_cdc_graycounter1_ce; +(* dont_touch = "true" *) reg [6:0] ethcore_mac_tx_cdc_graycounter1_q = 7'd0; +wire [6:0] ethcore_mac_tx_cdc_graycounter1_q_next; +reg [6:0] ethcore_mac_tx_cdc_graycounter1_q_binary = 7'd0; +reg [6:0] ethcore_mac_tx_cdc_graycounter1_q_next_binary = 7'd0; +wire [6:0] ethcore_mac_tx_cdc_produce_rdomain; +wire [6:0] ethcore_mac_tx_cdc_consume_wdomain; +wire [5:0] ethcore_mac_tx_cdc_wrport_adr; +wire [11:0] ethcore_mac_tx_cdc_wrport_dat_r; +wire ethcore_mac_tx_cdc_wrport_we; +wire [11:0] ethcore_mac_tx_cdc_wrport_dat_w; +wire [5:0] ethcore_mac_tx_cdc_rdport_adr; +wire [11:0] ethcore_mac_tx_cdc_rdport_dat_r; +wire [7:0] ethcore_mac_tx_cdc_fifo_in_payload_data; +wire ethcore_mac_tx_cdc_fifo_in_payload_last_be; +wire ethcore_mac_tx_cdc_fifo_in_payload_error; +wire ethcore_mac_tx_cdc_fifo_in_first; +wire ethcore_mac_tx_cdc_fifo_in_last; +wire [7:0] ethcore_mac_tx_cdc_fifo_out_payload_data; +wire ethcore_mac_tx_cdc_fifo_out_payload_last_be; +wire ethcore_mac_tx_cdc_fifo_out_payload_error; +wire ethcore_mac_tx_cdc_fifo_out_first; +wire ethcore_mac_tx_cdc_fifo_out_last; +wire ethcore_mac_rx_cdc_sink_valid; +wire ethcore_mac_rx_cdc_sink_ready; +wire ethcore_mac_rx_cdc_sink_first; +wire ethcore_mac_rx_cdc_sink_last; +wire [7:0] ethcore_mac_rx_cdc_sink_payload_data; +wire ethcore_mac_rx_cdc_sink_payload_last_be; +wire ethcore_mac_rx_cdc_sink_payload_error; +wire ethcore_mac_rx_cdc_source_valid; +wire ethcore_mac_rx_cdc_source_ready; +wire ethcore_mac_rx_cdc_source_first; +wire ethcore_mac_rx_cdc_source_last; +wire [7:0] ethcore_mac_rx_cdc_source_payload_data; +wire ethcore_mac_rx_cdc_source_payload_last_be; +wire ethcore_mac_rx_cdc_source_payload_error; +wire ethcore_mac_rx_cdc_asyncfifo_we; +wire ethcore_mac_rx_cdc_asyncfifo_writable; +wire ethcore_mac_rx_cdc_asyncfifo_re; +wire ethcore_mac_rx_cdc_asyncfifo_readable; +wire [11:0] ethcore_mac_rx_cdc_asyncfifo_din; +wire [11:0] ethcore_mac_rx_cdc_asyncfifo_dout; +wire ethcore_mac_rx_cdc_graycounter0_ce; +(* dont_touch = "true" *) reg [6:0] ethcore_mac_rx_cdc_graycounter0_q = 7'd0; +wire [6:0] ethcore_mac_rx_cdc_graycounter0_q_next; +reg [6:0] ethcore_mac_rx_cdc_graycounter0_q_binary = 7'd0; +reg [6:0] ethcore_mac_rx_cdc_graycounter0_q_next_binary = 7'd0; +wire ethcore_mac_rx_cdc_graycounter1_ce; +(* dont_touch = "true" *) reg [6:0] ethcore_mac_rx_cdc_graycounter1_q = 7'd0; +wire [6:0] ethcore_mac_rx_cdc_graycounter1_q_next; +reg [6:0] ethcore_mac_rx_cdc_graycounter1_q_binary = 7'd0; +reg [6:0] ethcore_mac_rx_cdc_graycounter1_q_next_binary = 7'd0; +wire [6:0] ethcore_mac_rx_cdc_produce_rdomain; +wire [6:0] ethcore_mac_rx_cdc_consume_wdomain; +wire [5:0] ethcore_mac_rx_cdc_wrport_adr; +wire [11:0] ethcore_mac_rx_cdc_wrport_dat_r; +wire ethcore_mac_rx_cdc_wrport_we; +wire [11:0] ethcore_mac_rx_cdc_wrport_dat_w; +wire [5:0] ethcore_mac_rx_cdc_rdport_adr; +wire [11:0] ethcore_mac_rx_cdc_rdport_dat_r; +wire [7:0] ethcore_mac_rx_cdc_fifo_in_payload_data; +wire ethcore_mac_rx_cdc_fifo_in_payload_last_be; +wire ethcore_mac_rx_cdc_fifo_in_payload_error; +wire ethcore_mac_rx_cdc_fifo_in_first; +wire ethcore_mac_rx_cdc_fifo_in_last; +wire [7:0] ethcore_mac_rx_cdc_fifo_out_payload_data; +wire ethcore_mac_rx_cdc_fifo_out_payload_last_be; +wire ethcore_mac_rx_cdc_fifo_out_payload_error; +wire ethcore_mac_rx_cdc_fifo_out_first; +wire ethcore_mac_rx_cdc_fifo_out_last; +reg ethcore_mac_crossbar_source_valid = 1'd0; +wire ethcore_mac_crossbar_source_ready; +reg ethcore_mac_crossbar_source_first = 1'd0; +reg ethcore_mac_crossbar_source_last = 1'd0; +reg [15:0] ethcore_mac_crossbar_source_payload_ethernet_type = 16'd0; +reg [47:0] ethcore_mac_crossbar_source_payload_sender_mac = 48'd0; +reg [47:0] ethcore_mac_crossbar_source_payload_target_mac = 48'd0; +reg [7:0] ethcore_mac_crossbar_source_payload_data = 8'd0; +reg ethcore_mac_crossbar_source_payload_last_be = 1'd0; +reg ethcore_mac_crossbar_source_payload_error = 1'd0; +wire ethcore_mac_crossbar_sink_valid; +reg ethcore_mac_crossbar_sink_ready = 1'd0; +wire ethcore_mac_crossbar_sink_first; +wire ethcore_mac_crossbar_sink_last; +wire [15:0] ethcore_mac_crossbar_sink_payload_ethernet_type; +wire [47:0] ethcore_mac_crossbar_sink_payload_sender_mac; +wire [47:0] ethcore_mac_crossbar_sink_payload_target_mac; +wire [7:0] ethcore_mac_crossbar_sink_payload_data; +wire ethcore_mac_crossbar_sink_payload_last_be; +wire ethcore_mac_crossbar_sink_payload_error; +wire ethcore_mac_packetizer_sink_valid; +reg ethcore_mac_packetizer_sink_ready = 1'd0; +wire ethcore_mac_packetizer_sink_first; +wire ethcore_mac_packetizer_sink_last; +wire [15:0] ethcore_mac_packetizer_sink_payload_ethernet_type; +wire [47:0] ethcore_mac_packetizer_sink_payload_sender_mac; +wire [47:0] ethcore_mac_packetizer_sink_payload_target_mac; +wire [7:0] ethcore_mac_packetizer_sink_payload_data; +wire ethcore_mac_packetizer_sink_payload_last_be; +wire ethcore_mac_packetizer_sink_payload_error; +reg ethcore_mac_packetizer_source_valid = 1'd0; +wire ethcore_mac_packetizer_source_ready; +reg ethcore_mac_packetizer_source_first = 1'd0; +reg ethcore_mac_packetizer_source_last = 1'd0; +reg [7:0] ethcore_mac_packetizer_source_payload_data = 8'd0; +wire ethcore_mac_packetizer_source_payload_last_be; +wire ethcore_mac_packetizer_source_payload_error; +reg [111:0] ethcore_mac_packetizer_header = 112'd0; +reg [111:0] ethcore_mac_packetizer_sr = 112'd0; +reg ethcore_mac_packetizer_sr_load = 1'd0; +reg ethcore_mac_packetizer_sr_shift = 1'd0; +reg [3:0] ethcore_mac_packetizer_count = 4'd0; +reg ethcore_mac_packetizer_sink_d_valid = 1'd0; +reg ethcore_mac_packetizer_sink_d_ready = 1'd0; +reg ethcore_mac_packetizer_sink_d_first = 1'd0; +reg ethcore_mac_packetizer_sink_d_last = 1'd0; +reg [15:0] ethcore_mac_packetizer_sink_d_payload_ethernet_type = 16'd0; +reg [47:0] ethcore_mac_packetizer_sink_d_payload_sender_mac = 48'd0; +reg [47:0] ethcore_mac_packetizer_sink_d_payload_target_mac = 48'd0; +reg [7:0] ethcore_mac_packetizer_sink_d_payload_data = 8'd0; +reg ethcore_mac_packetizer_sink_d_payload_last_be = 1'd0; +reg ethcore_mac_packetizer_sink_d_payload_error = 1'd0; +reg ethcore_mac_packetizer_fsm_from_idle = 1'd0; +wire ethcore_mac_depacketizer_sink_valid; +reg ethcore_mac_depacketizer_sink_ready = 1'd0; +wire ethcore_mac_depacketizer_sink_first; +wire ethcore_mac_depacketizer_sink_last; +wire [7:0] ethcore_mac_depacketizer_sink_payload_data; +wire ethcore_mac_depacketizer_sink_payload_last_be; +wire ethcore_mac_depacketizer_sink_payload_error; +reg ethcore_mac_depacketizer_source_valid = 1'd0; +wire ethcore_mac_depacketizer_source_ready; +reg ethcore_mac_depacketizer_source_first = 1'd0; +reg ethcore_mac_depacketizer_source_last = 1'd0; +wire [15:0] ethcore_mac_depacketizer_source_payload_ethernet_type; +wire [47:0] ethcore_mac_depacketizer_source_payload_sender_mac; +wire [47:0] ethcore_mac_depacketizer_source_payload_target_mac; +reg [7:0] ethcore_mac_depacketizer_source_payload_data = 8'd0; +wire ethcore_mac_depacketizer_source_payload_last_be; +wire ethcore_mac_depacketizer_source_payload_error; +wire [111:0] ethcore_mac_depacketizer_header; +reg [111:0] ethcore_mac_depacketizer_sr = 112'd0; +reg ethcore_mac_depacketizer_sr_shift = 1'd0; +reg ethcore_mac_depacketizer_sr_shift_leftover = 1'd0; +reg [3:0] ethcore_mac_depacketizer_count = 4'd0; +reg ethcore_mac_depacketizer_sink_d_valid = 1'd0; +reg ethcore_mac_depacketizer_sink_d_ready = 1'd0; +reg ethcore_mac_depacketizer_sink_d_first = 1'd0; +reg ethcore_mac_depacketizer_sink_d_last = 1'd0; +reg [7:0] ethcore_mac_depacketizer_sink_d_payload_data = 8'd0; +reg ethcore_mac_depacketizer_sink_d_payload_last_be = 1'd0; +reg ethcore_mac_depacketizer_sink_d_payload_error = 1'd0; +reg ethcore_mac_depacketizer_fsm_from_idle = 1'd0; +wire ethcore_arp_tx_sink_sink_valid; +reg ethcore_arp_tx_sink_sink_ready = 1'd0; +wire ethcore_arp_tx_sink_sink_first; +wire ethcore_arp_tx_sink_sink_last; +wire ethcore_arp_tx_sink_sink_payload_reply; +wire ethcore_arp_tx_sink_sink_payload_request; +wire [31:0] ethcore_arp_tx_sink_sink_payload_ip_address; +wire [47:0] ethcore_arp_tx_sink_sink_payload_mac_address; +reg ethcore_arp_tx_source_source_valid = 1'd0; +wire ethcore_arp_tx_source_source_ready; +reg ethcore_arp_tx_source_source_first = 1'd0; +reg ethcore_arp_tx_source_source_last = 1'd0; +reg [15:0] ethcore_arp_tx_source_source_payload_ethernet_type = 16'd0; +reg [47:0] ethcore_arp_tx_source_source_payload_sender_mac = 48'd0; +reg [47:0] ethcore_arp_tx_source_source_payload_target_mac = 48'd0; +reg [7:0] ethcore_arp_tx_source_source_payload_data = 8'd0; +reg ethcore_arp_tx_source_source_payload_last_be = 1'd0; +reg ethcore_arp_tx_source_source_payload_error = 1'd0; +reg [5:0] ethcore_arp_tx_counter = 6'd0; +reg ethcore_arp_tx_packetizer_sink_valid = 1'd0; +reg ethcore_arp_tx_packetizer_sink_ready = 1'd0; +reg ethcore_arp_tx_packetizer_sink_first = 1'd0; +wire ethcore_arp_tx_packetizer_sink_last; +reg [7:0] ethcore_arp_tx_packetizer_sink_payload_data = 8'd0; +reg ethcore_arp_tx_packetizer_sink_payload_error = 1'd0; +wire [7:0] ethcore_arp_tx_packetizer_sink_param_hwsize; +wire [15:0] ethcore_arp_tx_packetizer_sink_param_hwtype; +reg [15:0] ethcore_arp_tx_packetizer_sink_param_opcode = 16'd0; +wire [15:0] ethcore_arp_tx_packetizer_sink_param_proto; +wire [7:0] ethcore_arp_tx_packetizer_sink_param_protosize; +wire [31:0] ethcore_arp_tx_packetizer_sink_param_sender_ip; +wire [47:0] ethcore_arp_tx_packetizer_sink_param_sender_mac; +reg [31:0] ethcore_arp_tx_packetizer_sink_param_target_ip = 32'd0; +reg [47:0] ethcore_arp_tx_packetizer_sink_param_target_mac = 48'd0; +reg ethcore_arp_tx_packetizer_source_valid = 1'd0; +reg ethcore_arp_tx_packetizer_source_ready = 1'd0; +reg ethcore_arp_tx_packetizer_source_first = 1'd0; +reg ethcore_arp_tx_packetizer_source_last = 1'd0; +reg [15:0] ethcore_arp_tx_packetizer_source_payload_ethernet_type = 16'd0; +reg [47:0] ethcore_arp_tx_packetizer_source_payload_sender_mac = 48'd0; +reg [47:0] ethcore_arp_tx_packetizer_source_payload_target_mac = 48'd0; +reg [7:0] ethcore_arp_tx_packetizer_source_payload_data = 8'd0; +reg ethcore_arp_tx_packetizer_source_payload_last_be = 1'd0; +wire ethcore_arp_tx_packetizer_source_payload_error; +reg [223:0] ethcore_arp_tx_packetizer_header = 224'd0; +reg [223:0] ethcore_arp_tx_packetizer_sr = 224'd0; +reg ethcore_arp_tx_packetizer_sr_load = 1'd0; +reg ethcore_arp_tx_packetizer_sr_shift = 1'd0; +reg [4:0] ethcore_arp_tx_packetizer_count = 5'd0; +reg ethcore_arp_tx_packetizer_sink_d_valid = 1'd0; +reg ethcore_arp_tx_packetizer_sink_d_ready = 1'd0; +reg ethcore_arp_tx_packetizer_sink_d_first = 1'd0; +reg ethcore_arp_tx_packetizer_sink_d_last = 1'd0; +reg [7:0] ethcore_arp_tx_packetizer_sink_d_payload_data = 8'd0; +reg ethcore_arp_tx_packetizer_sink_d_payload_error = 1'd0; +reg [7:0] ethcore_arp_tx_packetizer_sink_d_param_hwsize = 8'd0; +reg [15:0] ethcore_arp_tx_packetizer_sink_d_param_hwtype = 16'd0; +reg [15:0] ethcore_arp_tx_packetizer_sink_d_param_opcode = 16'd0; +reg [15:0] ethcore_arp_tx_packetizer_sink_d_param_proto = 16'd0; +reg [7:0] ethcore_arp_tx_packetizer_sink_d_param_protosize = 8'd0; +reg [31:0] ethcore_arp_tx_packetizer_sink_d_param_sender_ip = 32'd0; +reg [47:0] ethcore_arp_tx_packetizer_sink_d_param_sender_mac = 48'd0; +reg [31:0] ethcore_arp_tx_packetizer_sink_d_param_target_ip = 32'd0; +reg [47:0] ethcore_arp_tx_packetizer_sink_d_param_target_mac = 48'd0; +reg ethcore_arp_tx_packetizer_fsm_from_idle = 1'd0; +wire ethcore_arp_rx_sink_sink_valid; +wire ethcore_arp_rx_sink_sink_ready; +wire ethcore_arp_rx_sink_sink_first; +wire ethcore_arp_rx_sink_sink_last; +wire [15:0] ethcore_arp_rx_sink_sink_payload_ethernet_type; +wire [47:0] ethcore_arp_rx_sink_sink_payload_sender_mac; +wire [47:0] ethcore_arp_rx_sink_sink_payload_target_mac; +wire [7:0] ethcore_arp_rx_sink_sink_payload_data; +wire ethcore_arp_rx_sink_sink_payload_last_be; +wire ethcore_arp_rx_sink_sink_payload_error; +reg ethcore_arp_rx_source_source_valid = 1'd0; +wire ethcore_arp_rx_source_source_ready; +reg ethcore_arp_rx_source_source_first = 1'd0; +reg ethcore_arp_rx_source_source_last = 1'd0; +reg ethcore_arp_rx_source_source_payload_reply = 1'd0; +reg ethcore_arp_rx_source_source_payload_request = 1'd0; +wire [31:0] ethcore_arp_rx_source_source_payload_ip_address; +wire [47:0] ethcore_arp_rx_source_source_payload_mac_address; +wire ethcore_arp_rx_depacketizer_sink_valid; +reg ethcore_arp_rx_depacketizer_sink_ready = 1'd0; +wire ethcore_arp_rx_depacketizer_sink_first; +wire ethcore_arp_rx_depacketizer_sink_last; +wire [15:0] ethcore_arp_rx_depacketizer_sink_payload_ethernet_type; +wire [47:0] ethcore_arp_rx_depacketizer_sink_payload_sender_mac; +wire [47:0] ethcore_arp_rx_depacketizer_sink_payload_target_mac; +wire [7:0] ethcore_arp_rx_depacketizer_sink_payload_data; +wire ethcore_arp_rx_depacketizer_sink_payload_last_be; +wire ethcore_arp_rx_depacketizer_sink_payload_error; +reg ethcore_arp_rx_depacketizer_source_valid = 1'd0; +reg ethcore_arp_rx_depacketizer_source_ready = 1'd0; +reg ethcore_arp_rx_depacketizer_source_last = 1'd0; +reg [7:0] ethcore_arp_rx_depacketizer_source_payload_data = 8'd0; +wire ethcore_arp_rx_depacketizer_source_payload_error; +wire [7:0] ethcore_arp_rx_depacketizer_source_param_hwsize; +wire [15:0] ethcore_arp_rx_depacketizer_source_param_hwtype; +wire [15:0] ethcore_arp_rx_depacketizer_source_param_opcode; +wire [15:0] ethcore_arp_rx_depacketizer_source_param_proto; +wire [7:0] ethcore_arp_rx_depacketizer_source_param_protosize; +wire [31:0] ethcore_arp_rx_depacketizer_source_param_sender_ip; +wire [47:0] ethcore_arp_rx_depacketizer_source_param_sender_mac; +wire [31:0] ethcore_arp_rx_depacketizer_source_param_target_ip; +wire [47:0] ethcore_arp_rx_depacketizer_source_param_target_mac; +wire [223:0] ethcore_arp_rx_depacketizer_header; +reg [223:0] ethcore_arp_rx_depacketizer_sr = 224'd0; +reg ethcore_arp_rx_depacketizer_sr_shift = 1'd0; +reg ethcore_arp_rx_depacketizer_sr_shift_leftover = 1'd0; +reg [4:0] ethcore_arp_rx_depacketizer_count = 5'd0; +reg ethcore_arp_rx_depacketizer_sink_d_valid = 1'd0; +reg ethcore_arp_rx_depacketizer_sink_d_ready = 1'd0; +reg ethcore_arp_rx_depacketizer_sink_d_first = 1'd0; +reg ethcore_arp_rx_depacketizer_sink_d_last = 1'd0; +reg [15:0] ethcore_arp_rx_depacketizer_sink_d_payload_ethernet_type = 16'd0; +reg [47:0] ethcore_arp_rx_depacketizer_sink_d_payload_sender_mac = 48'd0; +reg [47:0] ethcore_arp_rx_depacketizer_sink_d_payload_target_mac = 48'd0; +reg [7:0] ethcore_arp_rx_depacketizer_sink_d_payload_data = 8'd0; +reg ethcore_arp_rx_depacketizer_sink_d_payload_last_be = 1'd0; +reg ethcore_arp_rx_depacketizer_sink_d_payload_error = 1'd0; +reg ethcore_arp_rx_depacketizer_fsm_from_idle = 1'd0; +reg ethcore_arp_rx_valid = 1'd0; +reg ethcore_arp_rx_reply = 1'd0; +reg ethcore_arp_rx_request = 1'd0; +wire ethcore_arp_table_sink_valid; +reg ethcore_arp_table_sink_ready = 1'd0; +wire ethcore_arp_table_sink_first; +wire ethcore_arp_table_sink_last; +wire ethcore_arp_table_sink_payload_reply; +wire ethcore_arp_table_sink_payload_request; +wire [31:0] ethcore_arp_table_sink_payload_ip_address; +wire [47:0] ethcore_arp_table_sink_payload_mac_address; +reg ethcore_arp_table_source_valid = 1'd0; +wire ethcore_arp_table_source_ready; +reg ethcore_arp_table_source_first = 1'd0; +reg ethcore_arp_table_source_last = 1'd0; +reg ethcore_arp_table_source_payload_reply = 1'd0; +reg ethcore_arp_table_source_payload_request = 1'd0; +reg [31:0] ethcore_arp_table_source_payload_ip_address = 32'd0; +reg [47:0] ethcore_arp_table_source_payload_mac_address = 48'd0; +reg ethcore_arp_table_request_valid = 1'd0; +reg ethcore_arp_table_request_ready = 1'd0; +wire [31:0] ethcore_arp_table_request_payload_ip_address; +reg ethcore_arp_table_response_valid = 1'd0; +reg ethcore_arp_table_response_ready = 1'd0; +reg ethcore_arp_table_response_payload_failed = 1'd0; +wire [47:0] ethcore_arp_table_response_payload_mac_address; +reg ethcore_arp_table_request_pending = 1'd0; +reg ethcore_arp_table_request_pending_clr = 1'd0; +reg ethcore_arp_table_request_pending_set = 1'd0; +reg [31:0] ethcore_arp_table_request_ip_address = 32'd0; +reg ethcore_arp_table_request_ip_address_reset = 1'd0; +reg ethcore_arp_table_request_ip_address_update = 1'd0; +wire ethcore_arp_table_request_timer_wait; +wire ethcore_arp_table_request_timer_done; +reg [23:0] ethcore_arp_table_request_timer_count = 24'd10000000; +reg [2:0] ethcore_arp_table_request_counter = 3'd0; +reg ethcore_arp_table_request_counter_reset = 1'd0; +reg ethcore_arp_table_request_counter_ce = 1'd0; +reg ethcore_arp_table_update = 1'd0; +reg ethcore_arp_table_cached_valid = 1'd0; +reg [31:0] ethcore_arp_table_cached_ip_address = 32'd0; +reg [47:0] ethcore_arp_table_cached_mac_address = 48'd0; +wire ethcore_arp_table_cached_timer_wait; +wire ethcore_arp_table_cached_timer_done; +reg [29:0] ethcore_arp_table_cached_timer_count = 30'd1000000000; +wire ethcore_arp_mac_port_sink_valid; +reg ethcore_arp_mac_port_sink_ready = 1'd0; +wire ethcore_arp_mac_port_sink_first; +wire ethcore_arp_mac_port_sink_last; +wire [15:0] ethcore_arp_mac_port_sink_payload_ethernet_type; +wire [47:0] ethcore_arp_mac_port_sink_payload_sender_mac; +wire [47:0] ethcore_arp_mac_port_sink_payload_target_mac; +wire [7:0] ethcore_arp_mac_port_sink_payload_data; +wire ethcore_arp_mac_port_sink_payload_last_be; +wire ethcore_arp_mac_port_sink_payload_error; +reg ethcore_arp_mac_port_source_valid = 1'd0; +wire ethcore_arp_mac_port_source_ready; +reg ethcore_arp_mac_port_source_first = 1'd0; +reg ethcore_arp_mac_port_source_last = 1'd0; +reg [15:0] ethcore_arp_mac_port_source_payload_ethernet_type = 16'd0; +reg [47:0] ethcore_arp_mac_port_source_payload_sender_mac = 48'd0; +reg [47:0] ethcore_arp_mac_port_source_payload_target_mac = 48'd0; +reg [7:0] ethcore_arp_mac_port_source_payload_data = 8'd0; +reg ethcore_arp_mac_port_source_payload_last_be = 1'd0; +reg ethcore_arp_mac_port_source_payload_error = 1'd0; +wire ethcore_ip_tx_sink_sink_valid; +wire ethcore_ip_tx_sink_sink_ready; +wire ethcore_ip_tx_sink_sink_first; +wire ethcore_ip_tx_sink_sink_last; +wire [7:0] ethcore_ip_tx_sink_sink_payload_data; +wire ethcore_ip_tx_sink_sink_payload_error; +wire [15:0] ethcore_ip_tx_sink_sink_param_length; +wire [7:0] ethcore_ip_tx_sink_sink_param_protocol; +wire [31:0] ethcore_ip_tx_sink_sink_param_ip_address; +reg ethcore_ip_tx_source_source_valid = 1'd0; +wire ethcore_ip_tx_source_source_ready; +reg ethcore_ip_tx_source_source_first = 1'd0; +reg ethcore_ip_tx_source_source_last = 1'd0; +reg [15:0] ethcore_ip_tx_source_source_payload_ethernet_type = 16'd0; +reg [47:0] ethcore_ip_tx_source_source_payload_sender_mac = 48'd0; +reg [47:0] ethcore_ip_tx_source_source_payload_target_mac = 48'd0; +reg [7:0] ethcore_ip_tx_source_source_payload_data = 8'd0; +reg ethcore_ip_tx_source_source_payload_last_be = 1'd0; +reg ethcore_ip_tx_source_source_payload_error = 1'd0; +reg ethcore_ip_tx_target_unreachable = 1'd0; +wire [159:0] ethcore_ip_tx_liteethipv4checksum_header; +wire [15:0] ethcore_ip_tx_liteethipv4checksum_value; +wire ethcore_ip_tx_liteethipv4checksum_done; +reg [16:0] ethcore_ip_tx_liteethipv4checksum_r = 17'd0; +wire [16:0] ethcore_ip_tx_liteethipv4checksum_s_next0; +reg [16:0] ethcore_ip_tx_liteethipv4checksum_r_next0 = 17'd0; +reg ethcore_ip_tx_liteethipv4checksum0 = 1'd0; +wire [16:0] ethcore_ip_tx_liteethipv4checksum_s_next1; +reg [16:0] ethcore_ip_tx_liteethipv4checksum_r_next1 = 17'd0; +reg ethcore_ip_tx_liteethipv4checksum1 = 1'd0; +wire [16:0] ethcore_ip_tx_liteethipv4checksum_s_next2; +reg [16:0] ethcore_ip_tx_liteethipv4checksum_r_next2 = 17'd0; +reg ethcore_ip_tx_liteethipv4checksum2 = 1'd0; +wire [16:0] ethcore_ip_tx_liteethipv4checksum_s_next3; +reg [16:0] ethcore_ip_tx_liteethipv4checksum_r_next3 = 17'd0; +reg ethcore_ip_tx_liteethipv4checksum3 = 1'd0; +wire [16:0] ethcore_ip_tx_liteethipv4checksum_s_next4; +reg [16:0] ethcore_ip_tx_liteethipv4checksum_r_next4 = 17'd0; +reg ethcore_ip_tx_liteethipv4checksum4 = 1'd0; +wire [16:0] ethcore_ip_tx_liteethipv4checksum_s_next5; +reg [16:0] ethcore_ip_tx_liteethipv4checksum_r_next5 = 17'd0; +reg ethcore_ip_tx_liteethipv4checksum5 = 1'd0; +wire [16:0] ethcore_ip_tx_liteethipv4checksum_s_next6; +reg [16:0] ethcore_ip_tx_liteethipv4checksum_r_next6 = 17'd0; +reg ethcore_ip_tx_liteethipv4checksum6 = 1'd0; +wire [16:0] ethcore_ip_tx_liteethipv4checksum_s_next7; +reg [16:0] ethcore_ip_tx_liteethipv4checksum_r_next7 = 17'd0; +reg ethcore_ip_tx_liteethipv4checksum7 = 1'd0; +wire [16:0] ethcore_ip_tx_liteethipv4checksum_s_next8; +reg [16:0] ethcore_ip_tx_liteethipv4checksum_r_next8 = 17'd0; +reg ethcore_ip_tx_liteethipv4checksum8 = 1'd0; +reg [3:0] ethcore_ip_tx_liteethipv4checksum_counter = 4'd0; +wire ethcore_ip_tx_liteethipv4checksum_counter_ce; +wire ethcore_ip_tx_ce; +wire ethcore_ip_tx_reset; +wire ethcore_ip_tx_packetizer_sink_valid; +reg ethcore_ip_tx_packetizer_sink_ready = 1'd0; +reg ethcore_ip_tx_packetizer_sink_first = 1'd0; +wire ethcore_ip_tx_packetizer_sink_last; +wire [7:0] ethcore_ip_tx_packetizer_sink_payload_data; +reg ethcore_ip_tx_packetizer_sink_payload_error = 1'd0; +wire [15:0] ethcore_ip_tx_packetizer_sink_param_checksum; +wire [15:0] ethcore_ip_tx_packetizer_sink_param_identification; +wire [3:0] ethcore_ip_tx_packetizer_sink_param_ihl; +wire [7:0] ethcore_ip_tx_packetizer_sink_param_protocol; +wire [31:0] ethcore_ip_tx_packetizer_sink_param_sender_ip; +wire [31:0] ethcore_ip_tx_packetizer_sink_param_target_ip; +wire [15:0] ethcore_ip_tx_packetizer_sink_param_total_length; +wire [7:0] ethcore_ip_tx_packetizer_sink_param_ttl; +wire [3:0] ethcore_ip_tx_packetizer_sink_param_version; +reg ethcore_ip_tx_packetizer_source_valid = 1'd0; +reg ethcore_ip_tx_packetizer_source_ready = 1'd0; +reg ethcore_ip_tx_packetizer_source_first = 1'd0; +reg ethcore_ip_tx_packetizer_source_last = 1'd0; +reg [15:0] ethcore_ip_tx_packetizer_source_payload_ethernet_type = 16'd0; +reg [47:0] ethcore_ip_tx_packetizer_source_payload_sender_mac = 48'd0; +reg [47:0] ethcore_ip_tx_packetizer_source_payload_target_mac = 48'd0; +reg [7:0] ethcore_ip_tx_packetizer_source_payload_data = 8'd0; +reg ethcore_ip_tx_packetizer_source_payload_last_be = 1'd0; +wire ethcore_ip_tx_packetizer_source_payload_error; +reg [159:0] ethcore_ip_tx_packetizer_header = 160'd0; +reg [159:0] ethcore_ip_tx_packetizer_sr = 160'd0; +reg ethcore_ip_tx_packetizer_sr_load = 1'd0; +reg ethcore_ip_tx_packetizer_sr_shift = 1'd0; +reg [4:0] ethcore_ip_tx_packetizer_count = 5'd0; +reg ethcore_ip_tx_packetizer_sink_d_valid = 1'd0; +reg ethcore_ip_tx_packetizer_sink_d_ready = 1'd0; +reg ethcore_ip_tx_packetizer_sink_d_first = 1'd0; +reg ethcore_ip_tx_packetizer_sink_d_last = 1'd0; +reg [7:0] ethcore_ip_tx_packetizer_sink_d_payload_data = 8'd0; +reg ethcore_ip_tx_packetizer_sink_d_payload_error = 1'd0; +reg [15:0] ethcore_ip_tx_packetizer_sink_d_param_checksum = 16'd0; +reg [15:0] ethcore_ip_tx_packetizer_sink_d_param_identification = 16'd0; +reg [3:0] ethcore_ip_tx_packetizer_sink_d_param_ihl = 4'd0; +reg [7:0] ethcore_ip_tx_packetizer_sink_d_param_protocol = 8'd0; +reg [31:0] ethcore_ip_tx_packetizer_sink_d_param_sender_ip = 32'd0; +reg [31:0] ethcore_ip_tx_packetizer_sink_d_param_target_ip = 32'd0; +reg [15:0] ethcore_ip_tx_packetizer_sink_d_param_total_length = 16'd0; +reg [7:0] ethcore_ip_tx_packetizer_sink_d_param_ttl = 8'd0; +reg [3:0] ethcore_ip_tx_packetizer_sink_d_param_version = 4'd0; +reg ethcore_ip_tx_packetizer_fsm_from_idle = 1'd0; +reg [47:0] ethcore_ip_tx_target_mac = 48'd0; +wire ethcore_ip_rx_sink_sink_valid; +wire ethcore_ip_rx_sink_sink_ready; +wire ethcore_ip_rx_sink_sink_first; +wire ethcore_ip_rx_sink_sink_last; +wire [15:0] ethcore_ip_rx_sink_sink_payload_ethernet_type; +wire [47:0] ethcore_ip_rx_sink_sink_payload_sender_mac; +wire [47:0] ethcore_ip_rx_sink_sink_payload_target_mac; +wire [7:0] ethcore_ip_rx_sink_sink_payload_data; +wire ethcore_ip_rx_sink_sink_payload_last_be; +wire ethcore_ip_rx_sink_sink_payload_error; +reg ethcore_ip_rx_source_source_valid = 1'd0; +wire ethcore_ip_rx_source_source_ready; +reg ethcore_ip_rx_source_source_first = 1'd0; +wire ethcore_ip_rx_source_source_last; +wire [7:0] ethcore_ip_rx_source_source_payload_data; +wire ethcore_ip_rx_source_source_payload_error; +wire [15:0] ethcore_ip_rx_source_source_param_length; +wire [7:0] ethcore_ip_rx_source_source_param_protocol; +wire [31:0] ethcore_ip_rx_source_source_param_ip_address; +wire ethcore_ip_rx_depacketizer_sink_valid; +reg ethcore_ip_rx_depacketizer_sink_ready = 1'd0; +wire ethcore_ip_rx_depacketizer_sink_first; +wire ethcore_ip_rx_depacketizer_sink_last; +wire [15:0] ethcore_ip_rx_depacketizer_sink_payload_ethernet_type; +wire [47:0] ethcore_ip_rx_depacketizer_sink_payload_sender_mac; +wire [47:0] ethcore_ip_rx_depacketizer_sink_payload_target_mac; +wire [7:0] ethcore_ip_rx_depacketizer_sink_payload_data; +wire ethcore_ip_rx_depacketizer_sink_payload_last_be; +wire ethcore_ip_rx_depacketizer_sink_payload_error; +reg ethcore_ip_rx_depacketizer_source_valid = 1'd0; +reg ethcore_ip_rx_depacketizer_source_ready = 1'd0; +reg ethcore_ip_rx_depacketizer_source_last = 1'd0; +reg [7:0] ethcore_ip_rx_depacketizer_source_payload_data = 8'd0; +wire ethcore_ip_rx_depacketizer_source_payload_error; +wire [15:0] ethcore_ip_rx_depacketizer_source_param_checksum; +wire [15:0] ethcore_ip_rx_depacketizer_source_param_identification; +wire [3:0] ethcore_ip_rx_depacketizer_source_param_ihl; +wire [7:0] ethcore_ip_rx_depacketizer_source_param_protocol; +wire [31:0] ethcore_ip_rx_depacketizer_source_param_sender_ip; +wire [31:0] ethcore_ip_rx_depacketizer_source_param_target_ip; +wire [15:0] ethcore_ip_rx_depacketizer_source_param_total_length; +wire [7:0] ethcore_ip_rx_depacketizer_source_param_ttl; +wire [3:0] ethcore_ip_rx_depacketizer_source_param_version; +wire [159:0] ethcore_ip_rx_depacketizer_header; +reg [159:0] ethcore_ip_rx_depacketizer_sr = 160'd0; +reg ethcore_ip_rx_depacketizer_sr_shift = 1'd0; +reg ethcore_ip_rx_depacketizer_sr_shift_leftover = 1'd0; +reg [4:0] ethcore_ip_rx_depacketizer_count = 5'd0; +reg ethcore_ip_rx_depacketizer_sink_d_valid = 1'd0; +reg ethcore_ip_rx_depacketizer_sink_d_ready = 1'd0; +reg ethcore_ip_rx_depacketizer_sink_d_first = 1'd0; +reg ethcore_ip_rx_depacketizer_sink_d_last = 1'd0; +reg [15:0] ethcore_ip_rx_depacketizer_sink_d_payload_ethernet_type = 16'd0; +reg [47:0] ethcore_ip_rx_depacketizer_sink_d_payload_sender_mac = 48'd0; +reg [47:0] ethcore_ip_rx_depacketizer_sink_d_payload_target_mac = 48'd0; +reg [7:0] ethcore_ip_rx_depacketizer_sink_d_payload_data = 8'd0; +reg ethcore_ip_rx_depacketizer_sink_d_payload_last_be = 1'd0; +reg ethcore_ip_rx_depacketizer_sink_d_payload_error = 1'd0; +reg ethcore_ip_rx_depacketizer_fsm_from_idle = 1'd0; +wire [159:0] ethcore_ip_rx_liteethipv4checksum_header; +wire [15:0] ethcore_ip_rx_liteethipv4checksum_value; +wire ethcore_ip_rx_liteethipv4checksum_done; +reg [16:0] ethcore_ip_rx_liteethipv4checksum_r = 17'd0; +wire [16:0] ethcore_ip_rx_liteethipv4checksum_s_next0; +reg [16:0] ethcore_ip_rx_liteethipv4checksum_r_next0 = 17'd0; +reg ethcore_ip_rx_liteethipv4checksum0 = 1'd0; +wire [16:0] ethcore_ip_rx_liteethipv4checksum_s_next1; +reg [16:0] ethcore_ip_rx_liteethipv4checksum_r_next1 = 17'd0; +reg ethcore_ip_rx_liteethipv4checksum1 = 1'd0; +wire [16:0] ethcore_ip_rx_liteethipv4checksum_s_next2; +reg [16:0] ethcore_ip_rx_liteethipv4checksum_r_next2 = 17'd0; +reg ethcore_ip_rx_liteethipv4checksum2 = 1'd0; +wire [16:0] ethcore_ip_rx_liteethipv4checksum_s_next3; +reg [16:0] ethcore_ip_rx_liteethipv4checksum_r_next3 = 17'd0; +reg ethcore_ip_rx_liteethipv4checksum3 = 1'd0; +wire [16:0] ethcore_ip_rx_liteethipv4checksum_s_next4; +reg [16:0] ethcore_ip_rx_liteethipv4checksum_r_next4 = 17'd0; +reg ethcore_ip_rx_liteethipv4checksum4 = 1'd0; +wire [16:0] ethcore_ip_rx_liteethipv4checksum_s_next5; +reg [16:0] ethcore_ip_rx_liteethipv4checksum_r_next5 = 17'd0; +reg ethcore_ip_rx_liteethipv4checksum5 = 1'd0; +wire [16:0] ethcore_ip_rx_liteethipv4checksum_s_next6; +reg [16:0] ethcore_ip_rx_liteethipv4checksum_r_next6 = 17'd0; +reg ethcore_ip_rx_liteethipv4checksum6 = 1'd0; +wire [16:0] ethcore_ip_rx_liteethipv4checksum_s_next7; +reg [16:0] ethcore_ip_rx_liteethipv4checksum_r_next7 = 17'd0; +reg ethcore_ip_rx_liteethipv4checksum7 = 1'd0; +wire [16:0] ethcore_ip_rx_liteethipv4checksum_s_next8; +reg [16:0] ethcore_ip_rx_liteethipv4checksum_r_next8 = 17'd0; +reg ethcore_ip_rx_liteethipv4checksum8 = 1'd0; +wire [16:0] ethcore_ip_rx_liteethipv4checksum_s_next9; +reg [16:0] ethcore_ip_rx_liteethipv4checksum_r_next9 = 17'd0; +reg ethcore_ip_rx_liteethipv4checksum9 = 1'd0; +reg [3:0] ethcore_ip_rx_liteethipv4checksum_counter = 4'd0; +wire ethcore_ip_rx_liteethipv4checksum_counter_ce; +wire ethcore_ip_rx_ce; +wire ethcore_ip_rx_reset; +reg ethcore_ip_rx_valid = 1'd0; +wire ethcore_ip_mac_port_sink_valid; +reg ethcore_ip_mac_port_sink_ready = 1'd0; +wire ethcore_ip_mac_port_sink_first; +wire ethcore_ip_mac_port_sink_last; +wire [15:0] ethcore_ip_mac_port_sink_payload_ethernet_type; +wire [47:0] ethcore_ip_mac_port_sink_payload_sender_mac; +wire [47:0] ethcore_ip_mac_port_sink_payload_target_mac; +wire [7:0] ethcore_ip_mac_port_sink_payload_data; +wire ethcore_ip_mac_port_sink_payload_last_be; +wire ethcore_ip_mac_port_sink_payload_error; +reg ethcore_ip_mac_port_source_valid = 1'd0; +wire ethcore_ip_mac_port_source_ready; +reg ethcore_ip_mac_port_source_first = 1'd0; +reg ethcore_ip_mac_port_source_last = 1'd0; +reg [15:0] ethcore_ip_mac_port_source_payload_ethernet_type = 16'd0; +reg [47:0] ethcore_ip_mac_port_source_payload_sender_mac = 48'd0; +reg [47:0] ethcore_ip_mac_port_source_payload_target_mac = 48'd0; +reg [7:0] ethcore_ip_mac_port_source_payload_data = 8'd0; +reg ethcore_ip_mac_port_source_payload_last_be = 1'd0; +reg ethcore_ip_mac_port_source_payload_error = 1'd0; +reg ethcore_ip_crossbar_source_valid = 1'd0; +wire ethcore_ip_crossbar_source_ready; +reg ethcore_ip_crossbar_source_first = 1'd0; +reg ethcore_ip_crossbar_source_last = 1'd0; +reg [7:0] ethcore_ip_crossbar_source_payload_data = 8'd0; +reg ethcore_ip_crossbar_source_payload_error = 1'd0; +reg [15:0] ethcore_ip_crossbar_source_param_length = 16'd0; +reg [7:0] ethcore_ip_crossbar_source_param_protocol = 8'd0; +reg [31:0] ethcore_ip_crossbar_source_param_ip_address = 32'd0; +wire ethcore_ip_crossbar_sink_valid; +reg ethcore_ip_crossbar_sink_ready = 1'd0; +wire ethcore_ip_crossbar_sink_first; +wire ethcore_ip_crossbar_sink_last; +wire [7:0] ethcore_ip_crossbar_sink_payload_data; +wire ethcore_ip_crossbar_sink_payload_error; +wire [15:0] ethcore_ip_crossbar_sink_param_length; +wire [7:0] ethcore_ip_crossbar_sink_param_protocol; +wire [31:0] ethcore_ip_crossbar_sink_param_ip_address; +wire ethcore_icmp_tx_sink_sink_valid; +wire ethcore_icmp_tx_sink_sink_ready; +wire ethcore_icmp_tx_sink_sink_first; +wire ethcore_icmp_tx_sink_sink_last; +wire [7:0] ethcore_icmp_tx_sink_sink_payload_data; +wire ethcore_icmp_tx_sink_sink_payload_error; +wire [15:0] ethcore_icmp_tx_sink_sink_param_checksum; +wire [7:0] ethcore_icmp_tx_sink_sink_param_code; +wire [7:0] ethcore_icmp_tx_sink_sink_param_msgtype; +wire [31:0] ethcore_icmp_tx_sink_sink_param_quench; +wire [31:0] ethcore_icmp_tx_sink_sink_param_ip_address; +wire [15:0] ethcore_icmp_tx_sink_sink_param_length; +reg ethcore_icmp_tx_source_source_valid = 1'd0; +wire ethcore_icmp_tx_source_source_ready; +reg ethcore_icmp_tx_source_source_first = 1'd0; +reg ethcore_icmp_tx_source_source_last = 1'd0; +reg [7:0] ethcore_icmp_tx_source_source_payload_data = 8'd0; +reg ethcore_icmp_tx_source_source_payload_error = 1'd0; +reg [15:0] ethcore_icmp_tx_source_source_param_length = 16'd0; +reg [7:0] ethcore_icmp_tx_source_source_param_protocol = 8'd0; +reg [31:0] ethcore_icmp_tx_source_source_param_ip_address = 32'd0; +wire ethcore_icmp_tx_packetizer_sink_valid; +reg ethcore_icmp_tx_packetizer_sink_ready = 1'd0; +reg ethcore_icmp_tx_packetizer_sink_first = 1'd0; +wire ethcore_icmp_tx_packetizer_sink_last; +wire [7:0] ethcore_icmp_tx_packetizer_sink_payload_data; +reg ethcore_icmp_tx_packetizer_sink_payload_error = 1'd0; +wire [15:0] ethcore_icmp_tx_packetizer_sink_param_checksum; +wire [7:0] ethcore_icmp_tx_packetizer_sink_param_code; +wire [7:0] ethcore_icmp_tx_packetizer_sink_param_msgtype; +wire [31:0] ethcore_icmp_tx_packetizer_sink_param_quench; +reg ethcore_icmp_tx_packetizer_source_valid = 1'd0; +reg ethcore_icmp_tx_packetizer_source_ready = 1'd0; +reg ethcore_icmp_tx_packetizer_source_first = 1'd0; +reg ethcore_icmp_tx_packetizer_source_last = 1'd0; +reg [7:0] ethcore_icmp_tx_packetizer_source_payload_data = 8'd0; +wire ethcore_icmp_tx_packetizer_source_payload_error; +reg [15:0] ethcore_icmp_tx_packetizer_source_param_length = 16'd0; +reg [7:0] ethcore_icmp_tx_packetizer_source_param_protocol = 8'd0; +reg [31:0] ethcore_icmp_tx_packetizer_source_param_ip_address = 32'd0; +reg [63:0] ethcore_icmp_tx_packetizer_header = 64'd0; +reg [63:0] ethcore_icmp_tx_packetizer_sr = 64'd0; +reg ethcore_icmp_tx_packetizer_sr_load = 1'd0; +reg ethcore_icmp_tx_packetizer_sr_shift = 1'd0; +reg [2:0] ethcore_icmp_tx_packetizer_count = 3'd0; +reg ethcore_icmp_tx_packetizer_sink_d_valid = 1'd0; +reg ethcore_icmp_tx_packetizer_sink_d_ready = 1'd0; +reg ethcore_icmp_tx_packetizer_sink_d_first = 1'd0; +reg ethcore_icmp_tx_packetizer_sink_d_last = 1'd0; +reg [7:0] ethcore_icmp_tx_packetizer_sink_d_payload_data = 8'd0; +reg ethcore_icmp_tx_packetizer_sink_d_payload_error = 1'd0; +reg [15:0] ethcore_icmp_tx_packetizer_sink_d_param_checksum = 16'd0; +reg [7:0] ethcore_icmp_tx_packetizer_sink_d_param_code = 8'd0; +reg [7:0] ethcore_icmp_tx_packetizer_sink_d_param_msgtype = 8'd0; +reg [31:0] ethcore_icmp_tx_packetizer_sink_d_param_quench = 32'd0; +reg ethcore_icmp_tx_packetizer_fsm_from_idle = 1'd0; +wire ethcore_icmp_rx_sink_sink_valid; +wire ethcore_icmp_rx_sink_sink_ready; +wire ethcore_icmp_rx_sink_sink_first; +wire ethcore_icmp_rx_sink_sink_last; +wire [7:0] ethcore_icmp_rx_sink_sink_payload_data; +wire ethcore_icmp_rx_sink_sink_payload_error; +wire [15:0] ethcore_icmp_rx_sink_sink_param_length; +wire [7:0] ethcore_icmp_rx_sink_sink_param_protocol; +wire [31:0] ethcore_icmp_rx_sink_sink_param_ip_address; +reg ethcore_icmp_rx_source_source_valid = 1'd0; +wire ethcore_icmp_rx_source_source_ready; +reg ethcore_icmp_rx_source_source_first = 1'd0; +wire ethcore_icmp_rx_source_source_last; +wire [7:0] ethcore_icmp_rx_source_source_payload_data; +wire ethcore_icmp_rx_source_source_payload_error; +wire [15:0] ethcore_icmp_rx_source_source_param_checksum; +wire [7:0] ethcore_icmp_rx_source_source_param_code; +wire [7:0] ethcore_icmp_rx_source_source_param_msgtype; +wire [31:0] ethcore_icmp_rx_source_source_param_quench; +wire [31:0] ethcore_icmp_rx_source_source_param_ip_address; +wire [15:0] ethcore_icmp_rx_source_source_param_length; +wire ethcore_icmp_rx_depacketizer_sink_valid; +reg ethcore_icmp_rx_depacketizer_sink_ready = 1'd0; +wire ethcore_icmp_rx_depacketizer_sink_first; +wire ethcore_icmp_rx_depacketizer_sink_last; +wire [7:0] ethcore_icmp_rx_depacketizer_sink_payload_data; +wire ethcore_icmp_rx_depacketizer_sink_payload_error; +wire [15:0] ethcore_icmp_rx_depacketizer_sink_param_length; +wire [7:0] ethcore_icmp_rx_depacketizer_sink_param_protocol; +wire [31:0] ethcore_icmp_rx_depacketizer_sink_param_ip_address; +reg ethcore_icmp_rx_depacketizer_source_valid = 1'd0; +reg ethcore_icmp_rx_depacketizer_source_ready = 1'd0; +reg ethcore_icmp_rx_depacketizer_source_last = 1'd0; +reg [7:0] ethcore_icmp_rx_depacketizer_source_payload_data = 8'd0; +wire ethcore_icmp_rx_depacketizer_source_payload_error; +wire [15:0] ethcore_icmp_rx_depacketizer_source_param_checksum; +wire [7:0] ethcore_icmp_rx_depacketizer_source_param_code; +wire [7:0] ethcore_icmp_rx_depacketizer_source_param_msgtype; +wire [31:0] ethcore_icmp_rx_depacketizer_source_param_quench; +wire [63:0] ethcore_icmp_rx_depacketizer_header; +reg [63:0] ethcore_icmp_rx_depacketizer_sr = 64'd0; +reg ethcore_icmp_rx_depacketizer_sr_shift = 1'd0; +reg ethcore_icmp_rx_depacketizer_sr_shift_leftover = 1'd0; +reg [2:0] ethcore_icmp_rx_depacketizer_count = 3'd0; +reg ethcore_icmp_rx_depacketizer_sink_d_valid = 1'd0; +reg ethcore_icmp_rx_depacketizer_sink_d_ready = 1'd0; +reg ethcore_icmp_rx_depacketizer_sink_d_first = 1'd0; +reg ethcore_icmp_rx_depacketizer_sink_d_last = 1'd0; +reg [7:0] ethcore_icmp_rx_depacketizer_sink_d_payload_data = 8'd0; +reg ethcore_icmp_rx_depacketizer_sink_d_payload_error = 1'd0; +reg [15:0] ethcore_icmp_rx_depacketizer_sink_d_param_length = 16'd0; +reg [7:0] ethcore_icmp_rx_depacketizer_sink_d_param_protocol = 8'd0; +reg [31:0] ethcore_icmp_rx_depacketizer_sink_d_param_ip_address = 32'd0; +reg ethcore_icmp_rx_depacketizer_fsm_from_idle = 1'd0; +reg ethcore_icmp_rx_valid = 1'd0; +wire ethcore_icmp_echo_sink_sink_valid; +wire ethcore_icmp_echo_sink_sink_ready; +wire ethcore_icmp_echo_sink_sink_first; +wire ethcore_icmp_echo_sink_sink_last; +wire [7:0] ethcore_icmp_echo_sink_sink_payload_data; +wire ethcore_icmp_echo_sink_sink_payload_error; +wire [15:0] ethcore_icmp_echo_sink_sink_param_checksum; +wire [7:0] ethcore_icmp_echo_sink_sink_param_code; +wire [7:0] ethcore_icmp_echo_sink_sink_param_msgtype; +wire [31:0] ethcore_icmp_echo_sink_sink_param_quench; +wire [31:0] ethcore_icmp_echo_sink_sink_param_ip_address; +wire [15:0] ethcore_icmp_echo_sink_sink_param_length; +wire ethcore_icmp_echo_source_source_valid; +wire ethcore_icmp_echo_source_source_ready; +wire ethcore_icmp_echo_source_source_first; +wire ethcore_icmp_echo_source_source_last; +wire [7:0] ethcore_icmp_echo_source_source_payload_data; +wire ethcore_icmp_echo_source_source_payload_error; +reg [15:0] ethcore_icmp_echo_source_source_param_checksum = 16'd0; +wire [7:0] ethcore_icmp_echo_source_source_param_code; +reg [7:0] ethcore_icmp_echo_source_source_param_msgtype = 8'd0; +wire [31:0] ethcore_icmp_echo_source_source_param_quench; +wire [31:0] ethcore_icmp_echo_source_source_param_ip_address; +wire [15:0] ethcore_icmp_echo_source_source_param_length; +wire ethcore_icmp_echo_buffer_sink_valid; +wire ethcore_icmp_echo_buffer_sink_ready; +wire ethcore_icmp_echo_buffer_sink_first; +wire ethcore_icmp_echo_buffer_sink_last; +wire [7:0] ethcore_icmp_echo_buffer_sink_payload_data; +wire ethcore_icmp_echo_buffer_sink_payload_error; +wire [15:0] ethcore_icmp_echo_buffer_sink_param_checksum; +wire [7:0] ethcore_icmp_echo_buffer_sink_param_code; +wire [7:0] ethcore_icmp_echo_buffer_sink_param_msgtype; +wire [31:0] ethcore_icmp_echo_buffer_sink_param_quench; +wire [31:0] ethcore_icmp_echo_buffer_sink_param_ip_address; +wire [15:0] ethcore_icmp_echo_buffer_sink_param_length; +wire ethcore_icmp_echo_buffer_source_valid; +wire ethcore_icmp_echo_buffer_source_ready; +wire ethcore_icmp_echo_buffer_source_first; +wire ethcore_icmp_echo_buffer_source_last; +wire [7:0] ethcore_icmp_echo_buffer_source_payload_data; +wire ethcore_icmp_echo_buffer_source_payload_error; +wire [15:0] ethcore_icmp_echo_buffer_source_param_checksum; +wire [7:0] ethcore_icmp_echo_buffer_source_param_code; +wire [7:0] ethcore_icmp_echo_buffer_source_param_msgtype; +wire [31:0] ethcore_icmp_echo_buffer_source_param_quench; +wire [31:0] ethcore_icmp_echo_buffer_source_param_ip_address; +wire [15:0] ethcore_icmp_echo_buffer_source_param_length; +wire ethcore_icmp_echo_buffer_re; +reg ethcore_icmp_echo_buffer_readable = 1'd0; +wire ethcore_icmp_echo_buffer_syncfifo_we; +wire ethcore_icmp_echo_buffer_syncfifo_writable; +wire ethcore_icmp_echo_buffer_syncfifo_re; +wire ethcore_icmp_echo_buffer_syncfifo_readable; +wire [122:0] ethcore_icmp_echo_buffer_syncfifo_din; +wire [122:0] ethcore_icmp_echo_buffer_syncfifo_dout; +reg [7:0] ethcore_icmp_echo_buffer_level0 = 8'd0; +reg ethcore_icmp_echo_buffer_replace = 1'd0; +reg [6:0] ethcore_icmp_echo_buffer_produce = 7'd0; +reg [6:0] ethcore_icmp_echo_buffer_consume = 7'd0; +reg [6:0] ethcore_icmp_echo_buffer_wrport_adr = 7'd0; +wire [122:0] ethcore_icmp_echo_buffer_wrport_dat_r; +wire ethcore_icmp_echo_buffer_wrport_we; +wire [122:0] ethcore_icmp_echo_buffer_wrport_dat_w; +wire ethcore_icmp_echo_buffer_do_read; +wire [6:0] ethcore_icmp_echo_buffer_rdport_adr; +wire [122:0] ethcore_icmp_echo_buffer_rdport_dat_r; +wire ethcore_icmp_echo_buffer_rdport_re; +wire [7:0] ethcore_icmp_echo_buffer_level1; +wire [7:0] ethcore_icmp_echo_buffer_fifo_in_payload_data; +wire ethcore_icmp_echo_buffer_fifo_in_payload_error; +wire [15:0] ethcore_icmp_echo_buffer_fifo_in_param_checksum; +wire [7:0] ethcore_icmp_echo_buffer_fifo_in_param_code; +wire [7:0] ethcore_icmp_echo_buffer_fifo_in_param_msgtype; +wire [31:0] ethcore_icmp_echo_buffer_fifo_in_param_quench; +wire [31:0] ethcore_icmp_echo_buffer_fifo_in_param_ip_address; +wire [15:0] ethcore_icmp_echo_buffer_fifo_in_param_length; +wire ethcore_icmp_echo_buffer_fifo_in_first; +wire ethcore_icmp_echo_buffer_fifo_in_last; +wire [7:0] ethcore_icmp_echo_buffer_fifo_out_payload_data; +wire ethcore_icmp_echo_buffer_fifo_out_payload_error; +wire [15:0] ethcore_icmp_echo_buffer_fifo_out_param_checksum; +wire [7:0] ethcore_icmp_echo_buffer_fifo_out_param_code; +wire [7:0] ethcore_icmp_echo_buffer_fifo_out_param_msgtype; +wire [31:0] ethcore_icmp_echo_buffer_fifo_out_param_quench; +wire [31:0] ethcore_icmp_echo_buffer_fifo_out_param_ip_address; +wire [15:0] ethcore_icmp_echo_buffer_fifo_out_param_length; +wire ethcore_icmp_echo_buffer_fifo_out_first; +wire ethcore_icmp_echo_buffer_fifo_out_last; +wire ethcore_icmp_sink_valid; +reg ethcore_icmp_sink_ready = 1'd0; +wire ethcore_icmp_sink_first; +wire ethcore_icmp_sink_last; +wire [7:0] ethcore_icmp_sink_payload_data; +wire ethcore_icmp_sink_payload_error; +wire [15:0] ethcore_icmp_sink_param_length; +wire [7:0] ethcore_icmp_sink_param_protocol; +wire [31:0] ethcore_icmp_sink_param_ip_address; +reg ethcore_icmp_source_valid = 1'd0; +wire ethcore_icmp_source_ready; +reg ethcore_icmp_source_first = 1'd0; +reg ethcore_icmp_source_last = 1'd0; +reg [7:0] ethcore_icmp_source_payload_data = 8'd0; +reg ethcore_icmp_source_payload_error = 1'd0; +reg [15:0] ethcore_icmp_source_param_length = 16'd0; +reg [7:0] ethcore_icmp_source_param_protocol = 8'd0; +reg [31:0] ethcore_icmp_source_param_ip_address = 32'd0; +wire ethcore_tx_sink_sink_valid; +wire ethcore_tx_sink_sink_ready; +wire ethcore_tx_sink_sink_first; +wire ethcore_tx_sink_sink_last; +wire [7:0] ethcore_tx_sink_sink_payload_data; +wire ethcore_tx_sink_sink_payload_error; +wire [15:0] ethcore_tx_sink_sink_param_src_port; +wire [15:0] ethcore_tx_sink_sink_param_dst_port; +wire [31:0] ethcore_tx_sink_sink_param_ip_address; +wire [15:0] ethcore_tx_sink_sink_param_length; +reg ethcore_tx_source_source_valid = 1'd0; +wire ethcore_tx_source_source_ready; +reg ethcore_tx_source_source_first = 1'd0; +reg ethcore_tx_source_source_last = 1'd0; +reg [7:0] ethcore_tx_source_source_payload_data = 8'd0; +reg ethcore_tx_source_source_payload_error = 1'd0; +reg [15:0] ethcore_tx_source_source_param_length = 16'd0; +reg [7:0] ethcore_tx_source_source_param_protocol = 8'd0; +reg [31:0] ethcore_tx_source_source_param_ip_address = 32'd0; +wire ethcore_tx_packetizer_sink_valid; +reg ethcore_tx_packetizer_sink_ready = 1'd0; +reg ethcore_tx_packetizer_sink_first = 1'd0; +wire ethcore_tx_packetizer_sink_last; +wire [7:0] ethcore_tx_packetizer_sink_payload_data; +reg ethcore_tx_packetizer_sink_payload_error = 1'd0; +wire [15:0] ethcore_tx_packetizer_sink_param_checksum; +wire [15:0] ethcore_tx_packetizer_sink_param_dst_port; +wire [15:0] ethcore_tx_packetizer_sink_param_length; +wire [15:0] ethcore_tx_packetizer_sink_param_src_port; +reg ethcore_tx_packetizer_source_valid = 1'd0; +reg ethcore_tx_packetizer_source_ready = 1'd0; +reg ethcore_tx_packetizer_source_first = 1'd0; +reg ethcore_tx_packetizer_source_last = 1'd0; +reg [7:0] ethcore_tx_packetizer_source_payload_data = 8'd0; +wire ethcore_tx_packetizer_source_payload_error; +reg [15:0] ethcore_tx_packetizer_source_param_length = 16'd0; +reg [7:0] ethcore_tx_packetizer_source_param_protocol = 8'd0; +reg [31:0] ethcore_tx_packetizer_source_param_ip_address = 32'd0; +reg [63:0] ethcore_tx_packetizer_header = 64'd0; +reg [63:0] ethcore_tx_packetizer_sr = 64'd0; +reg ethcore_tx_packetizer_sr_load = 1'd0; +reg ethcore_tx_packetizer_sr_shift = 1'd0; +reg [2:0] ethcore_tx_packetizer_count = 3'd0; +reg ethcore_tx_packetizer_sink_d_valid = 1'd0; +reg ethcore_tx_packetizer_sink_d_ready = 1'd0; +reg ethcore_tx_packetizer_sink_d_first = 1'd0; +reg ethcore_tx_packetizer_sink_d_last = 1'd0; +reg [7:0] ethcore_tx_packetizer_sink_d_payload_data = 8'd0; +reg ethcore_tx_packetizer_sink_d_payload_error = 1'd0; +reg [15:0] ethcore_tx_packetizer_sink_d_param_checksum = 16'd0; +reg [15:0] ethcore_tx_packetizer_sink_d_param_dst_port = 16'd0; +reg [15:0] ethcore_tx_packetizer_sink_d_param_length = 16'd0; +reg [15:0] ethcore_tx_packetizer_sink_d_param_src_port = 16'd0; +reg ethcore_tx_packetizer_fsm_from_idle = 1'd0; +wire ethcore_rx_sink_sink_valid; +wire ethcore_rx_sink_sink_ready; +wire ethcore_rx_sink_sink_first; +wire ethcore_rx_sink_sink_last; +wire [7:0] ethcore_rx_sink_sink_payload_data; +wire ethcore_rx_sink_sink_payload_error; +wire [15:0] ethcore_rx_sink_sink_param_length; +wire [7:0] ethcore_rx_sink_sink_param_protocol; +wire [31:0] ethcore_rx_sink_sink_param_ip_address; +reg ethcore_rx_source_source_valid = 1'd0; +wire ethcore_rx_source_source_ready; +reg ethcore_rx_source_source_first = 1'd0; +wire ethcore_rx_source_source_last; +wire [7:0] ethcore_rx_source_source_payload_data; +wire ethcore_rx_source_source_payload_error; +wire [15:0] ethcore_rx_source_source_param_src_port; +wire [15:0] ethcore_rx_source_source_param_dst_port; +wire [31:0] ethcore_rx_source_source_param_ip_address; +wire [15:0] ethcore_rx_source_source_param_length; +wire ethcore_rx_depacketizer_sink_valid; +reg ethcore_rx_depacketizer_sink_ready = 1'd0; +wire ethcore_rx_depacketizer_sink_first; +wire ethcore_rx_depacketizer_sink_last; +wire [7:0] ethcore_rx_depacketizer_sink_payload_data; +wire ethcore_rx_depacketizer_sink_payload_error; +wire [15:0] ethcore_rx_depacketizer_sink_param_length; +wire [7:0] ethcore_rx_depacketizer_sink_param_protocol; +wire [31:0] ethcore_rx_depacketizer_sink_param_ip_address; +reg ethcore_rx_depacketizer_source_valid = 1'd0; +reg ethcore_rx_depacketizer_source_ready = 1'd0; +reg ethcore_rx_depacketizer_source_last = 1'd0; +reg [7:0] ethcore_rx_depacketizer_source_payload_data = 8'd0; +wire ethcore_rx_depacketizer_source_payload_error; +wire [15:0] ethcore_rx_depacketizer_source_param_checksum; +wire [15:0] ethcore_rx_depacketizer_source_param_dst_port; +wire [15:0] ethcore_rx_depacketizer_source_param_length; +wire [15:0] ethcore_rx_depacketizer_source_param_src_port; +wire [63:0] ethcore_rx_depacketizer_header; +reg [63:0] ethcore_rx_depacketizer_sr = 64'd0; +reg ethcore_rx_depacketizer_sr_shift = 1'd0; +reg ethcore_rx_depacketizer_sr_shift_leftover = 1'd0; +reg [2:0] ethcore_rx_depacketizer_count = 3'd0; +reg ethcore_rx_depacketizer_sink_d_valid = 1'd0; +reg ethcore_rx_depacketizer_sink_d_ready = 1'd0; +reg ethcore_rx_depacketizer_sink_d_first = 1'd0; +reg ethcore_rx_depacketizer_sink_d_last = 1'd0; +reg [7:0] ethcore_rx_depacketizer_sink_d_payload_data = 8'd0; +reg ethcore_rx_depacketizer_sink_d_payload_error = 1'd0; +reg [15:0] ethcore_rx_depacketizer_sink_d_param_length = 16'd0; +reg [7:0] ethcore_rx_depacketizer_sink_d_param_protocol = 8'd0; +reg [31:0] ethcore_rx_depacketizer_sink_d_param_ip_address = 32'd0; +reg ethcore_rx_depacketizer_fsm_from_idle = 1'd0; +reg ethcore_rx_valid = 1'd0; +wire ethcore_ip_port_sink_valid; +reg ethcore_ip_port_sink_ready = 1'd0; +wire ethcore_ip_port_sink_first; +wire ethcore_ip_port_sink_last; +wire [7:0] ethcore_ip_port_sink_payload_data; +wire ethcore_ip_port_sink_payload_error; +wire [15:0] ethcore_ip_port_sink_param_length; +wire [7:0] ethcore_ip_port_sink_param_protocol; +wire [31:0] ethcore_ip_port_sink_param_ip_address; +reg ethcore_ip_port_source_valid = 1'd0; +wire ethcore_ip_port_source_ready; +reg ethcore_ip_port_source_first = 1'd0; +reg ethcore_ip_port_source_last = 1'd0; +reg [7:0] ethcore_ip_port_source_payload_data = 8'd0; +reg ethcore_ip_port_source_payload_error = 1'd0; +reg [15:0] ethcore_ip_port_source_param_length = 16'd0; +reg [7:0] ethcore_ip_port_source_param_protocol = 8'd0; +reg [31:0] ethcore_ip_port_source_param_ip_address = 32'd0; +wire ethcore_crossbar_source_valid; +wire ethcore_crossbar_source_ready; +wire ethcore_crossbar_source_first; +wire ethcore_crossbar_source_last; +wire [7:0] ethcore_crossbar_source_payload_data; +wire ethcore_crossbar_source_payload_error; +wire [15:0] ethcore_crossbar_source_param_src_port; +wire [15:0] ethcore_crossbar_source_param_dst_port; +wire [31:0] ethcore_crossbar_source_param_ip_address; +wire [15:0] ethcore_crossbar_source_param_length; +wire ethcore_crossbar_sink_valid; +wire ethcore_crossbar_sink_ready; +wire ethcore_crossbar_sink_first; +wire ethcore_crossbar_sink_last; +wire [7:0] ethcore_crossbar_sink_payload_data; +wire ethcore_crossbar_sink_payload_error; +wire [15:0] ethcore_crossbar_sink_param_src_port; +wire [15:0] ethcore_crossbar_sink_param_dst_port; +wire [31:0] ethcore_crossbar_sink_param_ip_address; +wire [15:0] ethcore_crossbar_sink_param_length; +reg etherbone_tx_sink_sink_valid = 1'd0; +wire etherbone_tx_sink_sink_ready; +reg etherbone_tx_sink_sink_first = 1'd0; +reg etherbone_tx_sink_sink_last = 1'd0; +reg [31:0] etherbone_tx_sink_sink_payload_data = 32'd0; +reg [3:0] etherbone_tx_sink_sink_payload_error = 4'd0; +reg [3:0] etherbone_tx_sink_sink_param_addr_size = 4'd0; +reg etherbone_tx_sink_sink_param_nr = 1'd0; +reg etherbone_tx_sink_sink_param_pf = 1'd0; +reg [3:0] etherbone_tx_sink_sink_param_port_size = 4'd0; +reg etherbone_tx_sink_sink_param_pr = 1'd0; +reg [15:0] etherbone_tx_sink_sink_param_src_port = 16'd0; +reg [15:0] etherbone_tx_sink_sink_param_dst_port = 16'd0; +reg [31:0] etherbone_tx_sink_sink_param_ip_address = 32'd0; +reg [15:0] etherbone_tx_sink_sink_param_length = 16'd0; +reg etherbone_tx_source_source_valid = 1'd0; +wire etherbone_tx_source_source_ready; +reg etherbone_tx_source_source_first = 1'd0; +reg etherbone_tx_source_source_last = 1'd0; +reg [31:0] etherbone_tx_source_source_payload_data = 32'd0; +reg [3:0] etherbone_tx_source_source_payload_error = 4'd0; +reg [15:0] etherbone_tx_source_source_param_src_port = 16'd0; +reg [15:0] etherbone_tx_source_source_param_dst_port = 16'd0; +reg [31:0] etherbone_tx_source_source_param_ip_address = 32'd0; +reg [15:0] etherbone_tx_source_source_param_length = 16'd0; +wire etherbone_tx_packetizer_sink_valid; +reg etherbone_tx_packetizer_sink_ready = 1'd0; +reg etherbone_tx_packetizer_sink_first = 1'd0; +wire etherbone_tx_packetizer_sink_last; +wire [31:0] etherbone_tx_packetizer_sink_payload_data; +reg [3:0] etherbone_tx_packetizer_sink_payload_error = 4'd0; +wire [3:0] etherbone_tx_packetizer_sink_param_addr_size; +wire [15:0] etherbone_tx_packetizer_sink_param_magic; +wire etherbone_tx_packetizer_sink_param_nr; +wire etherbone_tx_packetizer_sink_param_pf; +wire [3:0] etherbone_tx_packetizer_sink_param_port_size; +wire etherbone_tx_packetizer_sink_param_pr; +wire [3:0] etherbone_tx_packetizer_sink_param_version; +reg etherbone_tx_packetizer_source_valid = 1'd0; +reg etherbone_tx_packetizer_source_ready = 1'd0; +reg etherbone_tx_packetizer_source_first = 1'd0; +reg etherbone_tx_packetizer_source_last = 1'd0; +reg [31:0] etherbone_tx_packetizer_source_payload_data = 32'd0; +wire [3:0] etherbone_tx_packetizer_source_payload_error; +reg [15:0] etherbone_tx_packetizer_source_param_src_port = 16'd0; +reg [15:0] etherbone_tx_packetizer_source_param_dst_port = 16'd0; +reg [31:0] etherbone_tx_packetizer_source_param_ip_address = 32'd0; +reg [15:0] etherbone_tx_packetizer_source_param_length = 16'd0; +reg [63:0] etherbone_tx_packetizer_header = 64'd0; +reg [63:0] etherbone_tx_packetizer_sr = 64'd0; +reg etherbone_tx_packetizer_sr_load = 1'd0; +reg etherbone_tx_packetizer_sr_shift = 1'd0; +reg etherbone_tx_packetizer_count = 1'd0; +reg etherbone_tx_packetizer_sink_d_valid = 1'd0; +reg etherbone_tx_packetizer_sink_d_ready = 1'd0; +reg etherbone_tx_packetizer_sink_d_first = 1'd0; +reg etherbone_tx_packetizer_sink_d_last = 1'd0; +reg [31:0] etherbone_tx_packetizer_sink_d_payload_data = 32'd0; +reg [3:0] etherbone_tx_packetizer_sink_d_payload_error = 4'd0; +reg [3:0] etherbone_tx_packetizer_sink_d_param_addr_size = 4'd0; +reg [15:0] etherbone_tx_packetizer_sink_d_param_magic = 16'd0; +reg etherbone_tx_packetizer_sink_d_param_nr = 1'd0; +reg etherbone_tx_packetizer_sink_d_param_pf = 1'd0; +reg [3:0] etherbone_tx_packetizer_sink_d_param_port_size = 4'd0; +reg etherbone_tx_packetizer_sink_d_param_pr = 1'd0; +reg [3:0] etherbone_tx_packetizer_sink_d_param_version = 4'd0; +reg etherbone_tx_packetizer_fsm_from_idle = 1'd0; +wire etherbone_rx_sink_sink_valid; +wire etherbone_rx_sink_sink_ready; +wire etherbone_rx_sink_sink_first; +wire etherbone_rx_sink_sink_last; +wire [31:0] etherbone_rx_sink_sink_payload_data; +wire [3:0] etherbone_rx_sink_sink_payload_error; +wire [15:0] etherbone_rx_sink_sink_param_src_port; +wire [15:0] etherbone_rx_sink_sink_param_dst_port; +wire [31:0] etherbone_rx_sink_sink_param_ip_address; +wire [15:0] etherbone_rx_sink_sink_param_length; +reg etherbone_rx_source_source_valid = 1'd0; +reg etherbone_rx_source_source_ready = 1'd0; +reg etherbone_rx_source_source_first = 1'd0; +wire etherbone_rx_source_source_last; +wire [31:0] etherbone_rx_source_source_payload_data; +reg [3:0] etherbone_rx_source_source_payload_error = 4'd0; +reg [3:0] etherbone_rx_source_source_param_addr_size = 4'd0; +wire etherbone_rx_source_source_param_nr; +wire etherbone_rx_source_source_param_pf; +reg [3:0] etherbone_rx_source_source_param_port_size = 4'd0; +wire etherbone_rx_source_source_param_pr; +wire [15:0] etherbone_rx_source_source_param_src_port; +wire [15:0] etherbone_rx_source_source_param_dst_port; +wire [31:0] etherbone_rx_source_source_param_ip_address; +wire [15:0] etherbone_rx_source_source_param_length; +wire etherbone_rx_depacketizer_sink_valid; +reg etherbone_rx_depacketizer_sink_ready = 1'd0; +wire etherbone_rx_depacketizer_sink_first; +wire etherbone_rx_depacketizer_sink_last; +wire [31:0] etherbone_rx_depacketizer_sink_payload_data; +wire [3:0] etherbone_rx_depacketizer_sink_payload_error; +wire [15:0] etherbone_rx_depacketizer_sink_param_src_port; +wire [15:0] etherbone_rx_depacketizer_sink_param_dst_port; +wire [31:0] etherbone_rx_depacketizer_sink_param_ip_address; +wire [15:0] etherbone_rx_depacketizer_sink_param_length; +reg etherbone_rx_depacketizer_source_valid = 1'd0; +reg etherbone_rx_depacketizer_source_ready = 1'd0; +reg etherbone_rx_depacketizer_source_last = 1'd0; +reg [31:0] etherbone_rx_depacketizer_source_payload_data = 32'd0; +wire [3:0] etherbone_rx_depacketizer_source_payload_error; +wire [3:0] etherbone_rx_depacketizer_source_param_addr_size; +wire [15:0] etherbone_rx_depacketizer_source_param_magic; +wire etherbone_rx_depacketizer_source_param_nr; +wire etherbone_rx_depacketizer_source_param_pf; +wire [3:0] etherbone_rx_depacketizer_source_param_port_size; +wire etherbone_rx_depacketizer_source_param_pr; +wire [3:0] etherbone_rx_depacketizer_source_param_version; +wire [63:0] etherbone_rx_depacketizer_header; +reg [63:0] etherbone_rx_depacketizer_sr = 64'd0; +reg etherbone_rx_depacketizer_sr_shift = 1'd0; +reg etherbone_rx_depacketizer_sr_shift_leftover = 1'd0; +reg etherbone_rx_depacketizer_count = 1'd0; +reg etherbone_rx_depacketizer_sink_d_valid = 1'd0; +reg etherbone_rx_depacketizer_sink_d_ready = 1'd0; +reg etherbone_rx_depacketizer_sink_d_first = 1'd0; +reg etherbone_rx_depacketizer_sink_d_last = 1'd0; +reg [31:0] etherbone_rx_depacketizer_sink_d_payload_data = 32'd0; +reg [3:0] etherbone_rx_depacketizer_sink_d_payload_error = 4'd0; +reg [15:0] etherbone_rx_depacketizer_sink_d_param_src_port = 16'd0; +reg [15:0] etherbone_rx_depacketizer_sink_d_param_dst_port = 16'd0; +reg [31:0] etherbone_rx_depacketizer_sink_d_param_ip_address = 32'd0; +reg [15:0] etherbone_rx_depacketizer_sink_d_param_length = 16'd0; +reg etherbone_rx_depacketizer_fsm_from_idle = 1'd0; +reg etherbone_rx_valid = 1'd0; +wire etherbone_user_port_sink_valid; +wire etherbone_user_port_sink_ready; +wire etherbone_user_port_sink_first; +wire etherbone_user_port_sink_last; +wire [31:0] etherbone_user_port_sink_payload_data; +wire [3:0] etherbone_user_port_sink_payload_error; +wire [15:0] etherbone_user_port_sink_param_src_port; +wire [15:0] etherbone_user_port_sink_param_dst_port; +wire [31:0] etherbone_user_port_sink_param_ip_address; +wire [15:0] etherbone_user_port_sink_param_length; +wire etherbone_user_port_source_valid; +wire etherbone_user_port_source_ready; +wire etherbone_user_port_source_first; +wire etherbone_user_port_source_last; +wire [31:0] etherbone_user_port_source_payload_data; +wire [3:0] etherbone_user_port_source_payload_error; +wire [15:0] etherbone_user_port_source_param_src_port; +wire [15:0] etherbone_user_port_source_param_dst_port; +wire [31:0] etherbone_user_port_source_param_ip_address; +wire [15:0] etherbone_user_port_source_param_length; +wire etherbone_internal_port_sink_valid; +wire etherbone_internal_port_sink_ready; +wire etherbone_internal_port_sink_first; +wire etherbone_internal_port_sink_last; +wire [7:0] etherbone_internal_port_sink_payload_data; +wire etherbone_internal_port_sink_payload_error; +wire [15:0] etherbone_internal_port_sink_param_src_port; +wire [15:0] etherbone_internal_port_sink_param_dst_port; +wire [31:0] etherbone_internal_port_sink_param_ip_address; +wire [15:0] etherbone_internal_port_sink_param_length; +wire etherbone_internal_port_source_valid; +wire etherbone_internal_port_source_ready; +wire etherbone_internal_port_source_first; +wire etherbone_internal_port_source_last; +wire [7:0] etherbone_internal_port_source_payload_data; +wire etherbone_internal_port_source_payload_error; +wire [15:0] etherbone_internal_port_source_param_src_port; +wire [15:0] etherbone_internal_port_source_param_dst_port; +wire [31:0] etherbone_internal_port_source_param_ip_address; +wire [15:0] etherbone_internal_port_source_param_length; +wire etherbone_tx_converter_sink_valid; +wire etherbone_tx_converter_sink_ready; +wire etherbone_tx_converter_sink_first; +wire etherbone_tx_converter_sink_last; +wire [31:0] etherbone_tx_converter_sink_payload_data; +wire [3:0] etherbone_tx_converter_sink_payload_error; +wire [15:0] etherbone_tx_converter_sink_param_src_port; +wire [15:0] etherbone_tx_converter_sink_param_dst_port; +wire [31:0] etherbone_tx_converter_sink_param_ip_address; +wire [15:0] etherbone_tx_converter_sink_param_length; +wire etherbone_tx_converter_source_valid; +wire etherbone_tx_converter_source_ready; +wire etherbone_tx_converter_source_first; +wire etherbone_tx_converter_source_last; +wire [7:0] etherbone_tx_converter_source_payload_data; +wire etherbone_tx_converter_source_payload_error; +wire [15:0] etherbone_tx_converter_source_param_src_port; +wire [15:0] etherbone_tx_converter_source_param_dst_port; +wire [31:0] etherbone_tx_converter_source_param_ip_address; +wire [15:0] etherbone_tx_converter_source_param_length; +wire etherbone_tx_converter_converter_sink_valid; +wire etherbone_tx_converter_converter_sink_ready; +wire etherbone_tx_converter_converter_sink_first; +wire etherbone_tx_converter_converter_sink_last; +reg [35:0] etherbone_tx_converter_converter_sink_payload_data = 36'd0; +wire etherbone_tx_converter_converter_source_valid; +wire etherbone_tx_converter_converter_source_ready; +wire etherbone_tx_converter_converter_source_first; +wire etherbone_tx_converter_converter_source_last; +reg [8:0] etherbone_tx_converter_converter_source_payload_data = 9'd0; +wire etherbone_tx_converter_converter_source_payload_valid_token_count; +reg [1:0] etherbone_tx_converter_converter_mux = 2'd0; +wire etherbone_tx_converter_converter_first; +wire etherbone_tx_converter_converter_last; +wire etherbone_tx_converter_source_source_valid; +wire etherbone_tx_converter_source_source_ready; +wire etherbone_tx_converter_source_source_first; +wire etherbone_tx_converter_source_source_last; +wire [8:0] etherbone_tx_converter_source_source_payload_data; +wire etherbone_rx_converter_sink_valid; +wire etherbone_rx_converter_sink_ready; +wire etherbone_rx_converter_sink_first; +wire etherbone_rx_converter_sink_last; +wire [7:0] etherbone_rx_converter_sink_payload_data; +wire etherbone_rx_converter_sink_payload_error; +wire [15:0] etherbone_rx_converter_sink_param_src_port; +wire [15:0] etherbone_rx_converter_sink_param_dst_port; +wire [31:0] etherbone_rx_converter_sink_param_ip_address; +wire [15:0] etherbone_rx_converter_sink_param_length; +wire etherbone_rx_converter_source_valid; +wire etherbone_rx_converter_source_ready; +wire etherbone_rx_converter_source_first; +wire etherbone_rx_converter_source_last; +reg [31:0] etherbone_rx_converter_source_payload_data = 32'd0; +reg [3:0] etherbone_rx_converter_source_payload_error = 4'd0; +reg [15:0] etherbone_rx_converter_source_param_src_port = 16'd0; +reg [15:0] etherbone_rx_converter_source_param_dst_port = 16'd0; +reg [31:0] etherbone_rx_converter_source_param_ip_address = 32'd0; +reg [15:0] etherbone_rx_converter_source_param_length = 16'd0; +wire etherbone_rx_converter_converter_sink_valid; +wire etherbone_rx_converter_converter_sink_ready; +wire etherbone_rx_converter_converter_sink_first; +wire etherbone_rx_converter_converter_sink_last; +wire [8:0] etherbone_rx_converter_converter_sink_payload_data; +wire etherbone_rx_converter_converter_source_valid; +wire etherbone_rx_converter_converter_source_ready; +reg etherbone_rx_converter_converter_source_first = 1'd0; +reg etherbone_rx_converter_converter_source_last = 1'd0; +reg [35:0] etherbone_rx_converter_converter_source_payload_data = 36'd0; +reg [2:0] etherbone_rx_converter_converter_source_payload_valid_token_count = 3'd0; +reg [1:0] etherbone_rx_converter_converter_demux = 2'd0; +wire etherbone_rx_converter_converter_load_part; +reg etherbone_rx_converter_converter_strobe_all = 1'd0; +wire etherbone_rx_converter_source_source_valid; +wire etherbone_rx_converter_source_source_ready; +wire etherbone_rx_converter_source_source_first; +wire etherbone_rx_converter_source_source_last; +wire [35:0] etherbone_rx_converter_source_source_payload_data; +reg etherbone_probe_sink_valid = 1'd0; +reg etherbone_probe_sink_ready = 1'd0; +reg etherbone_probe_sink_first = 1'd0; +reg etherbone_probe_sink_last = 1'd0; +reg [31:0] etherbone_probe_sink_payload_data = 32'd0; +reg [3:0] etherbone_probe_sink_payload_error = 4'd0; +reg [3:0] etherbone_probe_sink_param_addr_size = 4'd0; +reg etherbone_probe_sink_param_nr = 1'd0; +reg etherbone_probe_sink_param_pf = 1'd0; +reg [3:0] etherbone_probe_sink_param_port_size = 4'd0; +reg etherbone_probe_sink_param_pr = 1'd0; +reg [15:0] etherbone_probe_sink_param_src_port = 16'd0; +reg [15:0] etherbone_probe_sink_param_dst_port = 16'd0; +reg [31:0] etherbone_probe_sink_param_ip_address = 32'd0; +reg [15:0] etherbone_probe_sink_param_length = 16'd0; +reg etherbone_probe_source_valid = 1'd0; +reg etherbone_probe_source_ready = 1'd0; +reg etherbone_probe_source_first = 1'd0; +reg etherbone_probe_source_last = 1'd0; +reg [31:0] etherbone_probe_source_payload_data = 32'd0; +reg [3:0] etherbone_probe_source_payload_error = 4'd0; +reg [3:0] etherbone_probe_source_param_addr_size = 4'd0; +reg etherbone_probe_source_param_nr = 1'd0; +reg etherbone_probe_source_param_pf = 1'd0; +reg [3:0] etherbone_probe_source_param_port_size = 4'd0; +reg etherbone_probe_source_param_pr = 1'd0; +reg [15:0] etherbone_probe_source_param_src_port = 16'd0; +reg [15:0] etherbone_probe_source_param_dst_port = 16'd0; +reg [31:0] etherbone_probe_source_param_ip_address = 32'd0; +reg [15:0] etherbone_probe_source_param_length = 16'd0; +reg etherbone_record_sink_sink_valid = 1'd0; +wire etherbone_record_sink_sink_ready; +reg etherbone_record_sink_sink_first = 1'd0; +reg etherbone_record_sink_sink_last = 1'd0; +reg [31:0] etherbone_record_sink_sink_payload_data = 32'd0; +reg [3:0] etherbone_record_sink_sink_payload_error = 4'd0; +reg [3:0] etherbone_record_sink_sink_param_addr_size = 4'd0; +reg etherbone_record_sink_sink_param_nr = 1'd0; +reg etherbone_record_sink_sink_param_pf = 1'd0; +reg [3:0] etherbone_record_sink_sink_param_port_size = 4'd0; +reg etherbone_record_sink_sink_param_pr = 1'd0; +reg [15:0] etherbone_record_sink_sink_param_src_port = 16'd0; +reg [15:0] etherbone_record_sink_sink_param_dst_port = 16'd0; +reg [31:0] etherbone_record_sink_sink_param_ip_address = 32'd0; +reg [15:0] etherbone_record_sink_sink_param_length = 16'd0; +wire etherbone_record_source_source_valid; +reg etherbone_record_source_source_ready = 1'd0; +wire etherbone_record_source_source_first; +wire etherbone_record_source_source_last; +wire [31:0] etherbone_record_source_source_payload_data; +wire [3:0] etherbone_record_source_source_payload_error; +wire [3:0] etherbone_record_source_source_param_addr_size; +wire etherbone_record_source_source_param_nr; +wire etherbone_record_source_source_param_pf; +wire [3:0] etherbone_record_source_source_param_port_size; +wire etherbone_record_source_source_param_pr; +wire [15:0] etherbone_record_source_source_param_src_port; +wire [15:0] etherbone_record_source_source_param_dst_port; +reg [31:0] etherbone_record_source_source_param_ip_address = 32'd0; +reg [15:0] etherbone_record_source_source_param_length = 16'd0; +wire etherbone_record_depacketizer_sink_valid; +reg etherbone_record_depacketizer_sink_ready = 1'd0; +wire etherbone_record_depacketizer_sink_first; +wire etherbone_record_depacketizer_sink_last; +wire [31:0] etherbone_record_depacketizer_sink_payload_data; +wire [3:0] etherbone_record_depacketizer_sink_payload_error; +wire [3:0] etherbone_record_depacketizer_sink_param_addr_size; +wire etherbone_record_depacketizer_sink_param_nr; +wire etherbone_record_depacketizer_sink_param_pf; +wire [3:0] etherbone_record_depacketizer_sink_param_port_size; +wire etherbone_record_depacketizer_sink_param_pr; +wire [15:0] etherbone_record_depacketizer_sink_param_src_port; +wire [15:0] etherbone_record_depacketizer_sink_param_dst_port; +wire [31:0] etherbone_record_depacketizer_sink_param_ip_address; +wire [15:0] etherbone_record_depacketizer_sink_param_length; +reg etherbone_record_depacketizer_source_valid = 1'd0; +wire etherbone_record_depacketizer_source_ready; +reg etherbone_record_depacketizer_source_first = 1'd0; +reg etherbone_record_depacketizer_source_last = 1'd0; +reg [31:0] etherbone_record_depacketizer_source_payload_data = 32'd0; +wire [3:0] etherbone_record_depacketizer_source_payload_error; +wire etherbone_record_depacketizer_source_param_bca; +wire [7:0] etherbone_record_depacketizer_source_param_byte_enable; +wire etherbone_record_depacketizer_source_param_cyc; +wire etherbone_record_depacketizer_source_param_rca; +wire [7:0] etherbone_record_depacketizer_source_param_rcount; +wire etherbone_record_depacketizer_source_param_rff; +wire etherbone_record_depacketizer_source_param_wca; +wire [7:0] etherbone_record_depacketizer_source_param_wcount; +wire etherbone_record_depacketizer_source_param_wff; +wire [31:0] etherbone_record_depacketizer_header; +reg [31:0] etherbone_record_depacketizer_sr = 32'd0; +reg etherbone_record_depacketizer_sr_shift = 1'd0; +reg etherbone_record_depacketizer_sr_shift_leftover = 1'd0; +reg etherbone_record_depacketizer_count = 1'd0; +reg etherbone_record_depacketizer_sink_d_valid = 1'd0; +reg etherbone_record_depacketizer_sink_d_ready = 1'd0; +reg etherbone_record_depacketizer_sink_d_first = 1'd0; +reg etherbone_record_depacketizer_sink_d_last = 1'd0; +reg [31:0] etherbone_record_depacketizer_sink_d_payload_data = 32'd0; +reg [3:0] etherbone_record_depacketizer_sink_d_payload_error = 4'd0; +reg [3:0] etherbone_record_depacketizer_sink_d_param_addr_size = 4'd0; +reg etherbone_record_depacketizer_sink_d_param_nr = 1'd0; +reg etherbone_record_depacketizer_sink_d_param_pf = 1'd0; +reg [3:0] etherbone_record_depacketizer_sink_d_param_port_size = 4'd0; +reg etherbone_record_depacketizer_sink_d_param_pr = 1'd0; +reg [15:0] etherbone_record_depacketizer_sink_d_param_src_port = 16'd0; +reg [15:0] etherbone_record_depacketizer_sink_d_param_dst_port = 16'd0; +reg [31:0] etherbone_record_depacketizer_sink_d_param_ip_address = 32'd0; +reg [15:0] etherbone_record_depacketizer_sink_d_param_length = 16'd0; +reg etherbone_record_depacketizer_fsm_from_idle = 1'd0; +wire etherbone_record_receiver_sink_sink_valid; +wire etherbone_record_receiver_sink_sink_ready; +wire etherbone_record_receiver_sink_sink_first; +wire etherbone_record_receiver_sink_sink_last; +reg [31:0] etherbone_record_receiver_sink_sink_payload_data = 32'd0; +wire [3:0] etherbone_record_receiver_sink_sink_payload_error; +wire etherbone_record_receiver_sink_sink_param_bca; +wire [7:0] etherbone_record_receiver_sink_sink_param_byte_enable; +wire etherbone_record_receiver_sink_sink_param_cyc; +wire etherbone_record_receiver_sink_sink_param_rca; +wire [7:0] etherbone_record_receiver_sink_sink_param_rcount; +wire etherbone_record_receiver_sink_sink_param_rff; +wire etherbone_record_receiver_sink_sink_param_wca; +wire [7:0] etherbone_record_receiver_sink_sink_param_wcount; +wire etherbone_record_receiver_sink_sink_param_wff; +reg etherbone_record_receiver_source_source_valid = 1'd0; +wire etherbone_record_receiver_source_source_ready; +reg etherbone_record_receiver_source_source_first = 1'd0; +reg etherbone_record_receiver_source_source_last = 1'd0; +reg [31:0] etherbone_record_receiver_source_source_payload_addr = 32'd0; +reg [31:0] etherbone_record_receiver_source_source_payload_data = 32'd0; +reg etherbone_record_receiver_source_source_param_we = 1'd0; +reg [7:0] etherbone_record_receiver_source_source_param_count = 8'd0; +reg [31:0] etherbone_record_receiver_source_source_param_base_addr = 32'd0; +reg [3:0] etherbone_record_receiver_source_source_param_be = 4'd0; +wire etherbone_record_receiver_fifo_sink_valid; +wire etherbone_record_receiver_fifo_sink_ready; +wire etherbone_record_receiver_fifo_sink_first; +wire etherbone_record_receiver_fifo_sink_last; +wire [31:0] etherbone_record_receiver_fifo_sink_payload_data; +wire [3:0] etherbone_record_receiver_fifo_sink_payload_error; +wire etherbone_record_receiver_fifo_sink_param_bca; +wire [7:0] etherbone_record_receiver_fifo_sink_param_byte_enable; +wire etherbone_record_receiver_fifo_sink_param_cyc; +wire etherbone_record_receiver_fifo_sink_param_rca; +wire [7:0] etherbone_record_receiver_fifo_sink_param_rcount; +wire etherbone_record_receiver_fifo_sink_param_rff; +wire etherbone_record_receiver_fifo_sink_param_wca; +wire [7:0] etherbone_record_receiver_fifo_sink_param_wcount; +wire etherbone_record_receiver_fifo_sink_param_wff; +wire etherbone_record_receiver_fifo_source_valid; +reg etherbone_record_receiver_fifo_source_ready = 1'd0; +wire etherbone_record_receiver_fifo_source_first; +wire etherbone_record_receiver_fifo_source_last; +wire [31:0] etherbone_record_receiver_fifo_source_payload_data; +wire [3:0] etherbone_record_receiver_fifo_source_payload_error; +wire etherbone_record_receiver_fifo_source_param_bca; +wire [7:0] etherbone_record_receiver_fifo_source_param_byte_enable; +wire etherbone_record_receiver_fifo_source_param_cyc; +wire etherbone_record_receiver_fifo_source_param_rca; +wire [7:0] etherbone_record_receiver_fifo_source_param_rcount; +wire etherbone_record_receiver_fifo_source_param_rff; +wire etherbone_record_receiver_fifo_source_param_wca; +wire [7:0] etherbone_record_receiver_fifo_source_param_wcount; +wire etherbone_record_receiver_fifo_source_param_wff; +wire etherbone_record_receiver_fifo_re; +reg etherbone_record_receiver_fifo_readable = 1'd0; +wire etherbone_record_receiver_fifo_syncfifo_we; +wire etherbone_record_receiver_fifo_syncfifo_writable; +wire etherbone_record_receiver_fifo_syncfifo_re; +wire etherbone_record_receiver_fifo_syncfifo_readable; +wire [67:0] etherbone_record_receiver_fifo_syncfifo_din; +wire [67:0] etherbone_record_receiver_fifo_syncfifo_dout; +reg [2:0] etherbone_record_receiver_fifo_level0 = 3'd0; +reg etherbone_record_receiver_fifo_replace = 1'd0; +reg [1:0] etherbone_record_receiver_fifo_produce = 2'd0; +reg [1:0] etherbone_record_receiver_fifo_consume = 2'd0; +reg [1:0] etherbone_record_receiver_fifo_wrport_adr = 2'd0; +wire [67:0] etherbone_record_receiver_fifo_wrport_dat_r; +wire etherbone_record_receiver_fifo_wrport_we; +wire [67:0] etherbone_record_receiver_fifo_wrport_dat_w; +wire etherbone_record_receiver_fifo_do_read; +wire [1:0] etherbone_record_receiver_fifo_rdport_adr; +wire [67:0] etherbone_record_receiver_fifo_rdport_dat_r; +wire etherbone_record_receiver_fifo_rdport_re; +wire [2:0] etherbone_record_receiver_fifo_level1; +wire [31:0] etherbone_record_receiver_fifo_fifo_in_payload_data; +wire [3:0] etherbone_record_receiver_fifo_fifo_in_payload_error; +wire etherbone_record_receiver_fifo_fifo_in_param_bca; +wire [7:0] etherbone_record_receiver_fifo_fifo_in_param_byte_enable; +wire etherbone_record_receiver_fifo_fifo_in_param_cyc; +wire etherbone_record_receiver_fifo_fifo_in_param_rca; +wire [7:0] etherbone_record_receiver_fifo_fifo_in_param_rcount; +wire etherbone_record_receiver_fifo_fifo_in_param_rff; +wire etherbone_record_receiver_fifo_fifo_in_param_wca; +wire [7:0] etherbone_record_receiver_fifo_fifo_in_param_wcount; +wire etherbone_record_receiver_fifo_fifo_in_param_wff; +wire etherbone_record_receiver_fifo_fifo_in_first; +wire etherbone_record_receiver_fifo_fifo_in_last; +wire [31:0] etherbone_record_receiver_fifo_fifo_out_payload_data; +wire [3:0] etherbone_record_receiver_fifo_fifo_out_payload_error; +wire etherbone_record_receiver_fifo_fifo_out_param_bca; +wire [7:0] etherbone_record_receiver_fifo_fifo_out_param_byte_enable; +wire etherbone_record_receiver_fifo_fifo_out_param_cyc; +wire etherbone_record_receiver_fifo_fifo_out_param_rca; +wire [7:0] etherbone_record_receiver_fifo_fifo_out_param_rcount; +wire etherbone_record_receiver_fifo_fifo_out_param_rff; +wire etherbone_record_receiver_fifo_fifo_out_param_wca; +wire [7:0] etherbone_record_receiver_fifo_fifo_out_param_wcount; +wire etherbone_record_receiver_fifo_fifo_out_param_wff; +wire etherbone_record_receiver_fifo_fifo_out_first; +wire etherbone_record_receiver_fifo_fifo_out_last; +reg [31:0] etherbone_record_receiver_base_addr = 32'd0; +reg etherbone_record_receiver_base_addr_update = 1'd0; +reg [8:0] etherbone_record_receiver_counter = 9'd0; +reg etherbone_record_receiver_counter_reset = 1'd0; +reg etherbone_record_receiver_counter_ce = 1'd0; +reg etherbone_record_first = 1'd1; +reg [31:0] etherbone_record_last_ip_address = 32'd0; +wire etherbone_record_sender_sink_sink_valid; +wire etherbone_record_sender_sink_sink_ready; +wire etherbone_record_sender_sink_sink_first; +wire etherbone_record_sender_sink_sink_last; +wire [31:0] etherbone_record_sender_sink_sink_payload_addr; +wire [31:0] etherbone_record_sender_sink_sink_payload_data; +wire etherbone_record_sender_sink_sink_param_we; +wire [7:0] etherbone_record_sender_sink_sink_param_count; +wire [31:0] etherbone_record_sender_sink_sink_param_base_addr; +wire [3:0] etherbone_record_sender_sink_sink_param_be; +reg etherbone_record_sender_source_source_valid = 1'd0; +wire etherbone_record_sender_source_source_ready; +reg etherbone_record_sender_source_source_first = 1'd0; +reg etherbone_record_sender_source_source_last = 1'd0; +reg [31:0] etherbone_record_sender_source_source_payload_data = 32'd0; +reg [3:0] etherbone_record_sender_source_source_payload_error = 4'd0; +reg etherbone_record_sender_source_source_param_bca = 1'd0; +reg [7:0] etherbone_record_sender_source_source_param_byte_enable = 8'd0; +reg etherbone_record_sender_source_source_param_cyc = 1'd0; +reg etherbone_record_sender_source_source_param_rca = 1'd0; +reg [7:0] etherbone_record_sender_source_source_param_rcount = 8'd0; +reg etherbone_record_sender_source_source_param_rff = 1'd0; +reg etherbone_record_sender_source_source_param_wca = 1'd0; +reg [7:0] etherbone_record_sender_source_source_param_wcount = 8'd0; +reg etherbone_record_sender_source_source_param_wff = 1'd0; +wire etherbone_record_sender_fifo_sink_valid; +wire etherbone_record_sender_fifo_sink_ready; +wire etherbone_record_sender_fifo_sink_first; +wire etherbone_record_sender_fifo_sink_last; +wire [31:0] etherbone_record_sender_fifo_sink_payload_addr; +wire [31:0] etherbone_record_sender_fifo_sink_payload_data; +wire etherbone_record_sender_fifo_sink_param_we; +wire [7:0] etherbone_record_sender_fifo_sink_param_count; +wire [31:0] etherbone_record_sender_fifo_sink_param_base_addr; +wire [3:0] etherbone_record_sender_fifo_sink_param_be; +wire etherbone_record_sender_fifo_source_valid; +reg etherbone_record_sender_fifo_source_ready = 1'd0; +wire etherbone_record_sender_fifo_source_first; +wire etherbone_record_sender_fifo_source_last; +wire [31:0] etherbone_record_sender_fifo_source_payload_addr; +wire [31:0] etherbone_record_sender_fifo_source_payload_data; +wire etherbone_record_sender_fifo_source_param_we; +wire [7:0] etherbone_record_sender_fifo_source_param_count; +wire [31:0] etherbone_record_sender_fifo_source_param_base_addr; +wire [3:0] etherbone_record_sender_fifo_source_param_be; +wire etherbone_record_sender_fifo_re; +reg etherbone_record_sender_fifo_readable = 1'd0; +wire etherbone_record_sender_fifo_syncfifo_we; +wire etherbone_record_sender_fifo_syncfifo_writable; +wire etherbone_record_sender_fifo_syncfifo_re; +wire etherbone_record_sender_fifo_syncfifo_readable; +wire [110:0] etherbone_record_sender_fifo_syncfifo_din; +wire [110:0] etherbone_record_sender_fifo_syncfifo_dout; +reg [2:0] etherbone_record_sender_fifo_level0 = 3'd0; +reg etherbone_record_sender_fifo_replace = 1'd0; +reg [1:0] etherbone_record_sender_fifo_produce = 2'd0; +reg [1:0] etherbone_record_sender_fifo_consume = 2'd0; +reg [1:0] etherbone_record_sender_fifo_wrport_adr = 2'd0; +wire [110:0] etherbone_record_sender_fifo_wrport_dat_r; +wire etherbone_record_sender_fifo_wrport_we; +wire [110:0] etherbone_record_sender_fifo_wrport_dat_w; +wire etherbone_record_sender_fifo_do_read; +wire [1:0] etherbone_record_sender_fifo_rdport_adr; +wire [110:0] etherbone_record_sender_fifo_rdport_dat_r; +wire etherbone_record_sender_fifo_rdport_re; +wire [2:0] etherbone_record_sender_fifo_level1; +wire [31:0] etherbone_record_sender_fifo_fifo_in_payload_addr; +wire [31:0] etherbone_record_sender_fifo_fifo_in_payload_data; +wire etherbone_record_sender_fifo_fifo_in_param_we; +wire [7:0] etherbone_record_sender_fifo_fifo_in_param_count; +wire [31:0] etherbone_record_sender_fifo_fifo_in_param_base_addr; +wire [3:0] etherbone_record_sender_fifo_fifo_in_param_be; +wire etherbone_record_sender_fifo_fifo_in_first; +wire etherbone_record_sender_fifo_fifo_in_last; +wire [31:0] etherbone_record_sender_fifo_fifo_out_payload_addr; +wire [31:0] etherbone_record_sender_fifo_fifo_out_payload_data; +wire etherbone_record_sender_fifo_fifo_out_param_we; +wire [7:0] etherbone_record_sender_fifo_fifo_out_param_count; +wire [31:0] etherbone_record_sender_fifo_fifo_out_param_base_addr; +wire [3:0] etherbone_record_sender_fifo_fifo_out_param_be; +wire etherbone_record_sender_fifo_fifo_out_first; +wire etherbone_record_sender_fifo_fifo_out_last; +reg etherbone_record_sender_data_sel = 1'd0; +wire etherbone_record_packetizer_sink_valid; +reg etherbone_record_packetizer_sink_ready = 1'd0; +wire etherbone_record_packetizer_sink_first; +wire etherbone_record_packetizer_sink_last; +reg [31:0] etherbone_record_packetizer_sink_payload_data = 32'd0; +wire [3:0] etherbone_record_packetizer_sink_payload_error; +wire etherbone_record_packetizer_sink_param_bca; +wire [7:0] etherbone_record_packetizer_sink_param_byte_enable; +wire etherbone_record_packetizer_sink_param_cyc; +wire etherbone_record_packetizer_sink_param_rca; +wire [7:0] etherbone_record_packetizer_sink_param_rcount; +wire etherbone_record_packetizer_sink_param_rff; +wire etherbone_record_packetizer_sink_param_wca; +wire [7:0] etherbone_record_packetizer_sink_param_wcount; +wire etherbone_record_packetizer_sink_param_wff; +reg etherbone_record_packetizer_source_valid = 1'd0; +wire etherbone_record_packetizer_source_ready; +reg etherbone_record_packetizer_source_first = 1'd0; +reg etherbone_record_packetizer_source_last = 1'd0; +reg [31:0] etherbone_record_packetizer_source_payload_data = 32'd0; +wire [3:0] etherbone_record_packetizer_source_payload_error; +reg [3:0] etherbone_record_packetizer_source_param_addr_size = 4'd0; +reg etherbone_record_packetizer_source_param_nr = 1'd0; +reg etherbone_record_packetizer_source_param_pf = 1'd0; +reg [3:0] etherbone_record_packetizer_source_param_port_size = 4'd0; +reg etherbone_record_packetizer_source_param_pr = 1'd0; +reg [15:0] etherbone_record_packetizer_source_param_src_port = 16'd0; +reg [15:0] etherbone_record_packetizer_source_param_dst_port = 16'd0; +reg [31:0] etherbone_record_packetizer_source_param_ip_address = 32'd0; +reg [15:0] etherbone_record_packetizer_source_param_length = 16'd0; +reg [31:0] etherbone_record_packetizer_header = 32'd0; +reg [31:0] etherbone_record_packetizer_sr = 32'd0; +reg etherbone_record_packetizer_sr_load = 1'd0; +reg etherbone_record_packetizer_sr_shift = 1'd0; +reg etherbone_record_packetizer_count = 1'd0; +reg etherbone_record_packetizer_sink_d_valid = 1'd0; +reg etherbone_record_packetizer_sink_d_ready = 1'd0; +reg etherbone_record_packetizer_sink_d_first = 1'd0; +reg etherbone_record_packetizer_sink_d_last = 1'd0; +reg [31:0] etherbone_record_packetizer_sink_d_payload_data = 32'd0; +reg [3:0] etherbone_record_packetizer_sink_d_payload_error = 4'd0; +reg etherbone_record_packetizer_sink_d_param_bca = 1'd0; +reg [7:0] etherbone_record_packetizer_sink_d_param_byte_enable = 8'd0; +reg etherbone_record_packetizer_sink_d_param_cyc = 1'd0; +reg etherbone_record_packetizer_sink_d_param_rca = 1'd0; +reg [7:0] etherbone_record_packetizer_sink_d_param_rcount = 8'd0; +reg etherbone_record_packetizer_sink_d_param_rff = 1'd0; +reg etherbone_record_packetizer_sink_d_param_wca = 1'd0; +reg [7:0] etherbone_record_packetizer_sink_d_param_wcount = 8'd0; +reg etherbone_record_packetizer_sink_d_param_wff = 1'd0; +reg etherbone_record_packetizer_fsm_from_idle = 1'd0; +wire etherbone_dispatcher_sel0; +reg etherbone_dispatcher_first = 1'd1; +reg etherbone_dispatcher_last = 1'd0; +wire etherbone_dispatcher_ongoing0; +reg etherbone_dispatcher_ongoing1 = 1'd0; +reg etherbone_dispatcher_sel1 = 1'd0; +reg etherbone_dispatcher_sel_ongoing = 1'd0; +reg [1:0] etherbone_request = 2'd0; +reg etherbone_grant = 1'd0; +reg etherbone_status0_first = 1'd1; +reg etherbone_status0_last = 1'd0; +wire etherbone_status0_ongoing0; +reg etherbone_status0_ongoing1 = 1'd0; +reg etherbone_status1_first = 1'd1; +reg etherbone_status1_last = 1'd0; +wire etherbone_status1_ongoing0; +reg etherbone_status1_ongoing1 = 1'd0; +wire etherbone_liteethetherbonewishbonemaster_sink_valid; +reg etherbone_liteethetherbonewishbonemaster_sink_ready = 1'd0; +wire etherbone_liteethetherbonewishbonemaster_sink_first; +wire etherbone_liteethetherbonewishbonemaster_sink_last; +wire [31:0] etherbone_liteethetherbonewishbonemaster_sink_payload_addr; +wire [31:0] etherbone_liteethetherbonewishbonemaster_sink_payload_data; +wire etherbone_liteethetherbonewishbonemaster_sink_param_we; +wire [7:0] etherbone_liteethetherbonewishbonemaster_sink_param_count; +wire [31:0] etherbone_liteethetherbonewishbonemaster_sink_param_base_addr; +wire [3:0] etherbone_liteethetherbonewishbonemaster_sink_param_be; +reg etherbone_liteethetherbonewishbonemaster_source_valid = 1'd0; +wire etherbone_liteethetherbonewishbonemaster_source_ready; +reg etherbone_liteethetherbonewishbonemaster_source_first = 1'd0; +reg etherbone_liteethetherbonewishbonemaster_source_last = 1'd0; +reg [31:0] etherbone_liteethetherbonewishbonemaster_source_payload_addr = 32'd0; +reg [31:0] etherbone_liteethetherbonewishbonemaster_source_payload_data = 32'd0; +reg etherbone_liteethetherbonewishbonemaster_source_param_we = 1'd0; +reg [7:0] etherbone_liteethetherbonewishbonemaster_source_param_count = 8'd0; +reg [31:0] etherbone_liteethetherbonewishbonemaster_source_param_base_addr = 32'd0; +reg [3:0] etherbone_liteethetherbonewishbonemaster_source_param_be = 4'd0; +reg [29:0] etherbone_liteethetherbonewishbonemaster_bus_adr = 30'd0; +reg [31:0] etherbone_liteethetherbonewishbonemaster_bus_dat_w = 32'd0; +wire [31:0] etherbone_liteethetherbonewishbonemaster_bus_dat_r; +reg [3:0] etherbone_liteethetherbonewishbonemaster_bus_sel = 4'd0; +reg etherbone_liteethetherbonewishbonemaster_bus_cyc = 1'd0; +reg etherbone_liteethetherbonewishbonemaster_bus_stb = 1'd0; +wire etherbone_liteethetherbonewishbonemaster_bus_ack; +reg etherbone_liteethetherbonewishbonemaster_bus_we = 1'd0; +reg [2:0] etherbone_liteethetherbonewishbonemaster_bus_cti = 3'd0; +reg [1:0] etherbone_liteethetherbonewishbonemaster_bus_bte = 2'd0; +wire etherbone_liteethetherbonewishbonemaster_bus_err; +reg etherbone_liteethetherbonewishbonemaster_data_update = 1'd0; +wire s7pciephy_sink_sink_valid; +wire s7pciephy_sink_sink_ready; +wire s7pciephy_sink_sink_first; +wire s7pciephy_sink_sink_last; +wire [63:0] s7pciephy_sink_sink_payload_dat; +wire [7:0] s7pciephy_sink_sink_payload_be; +wire s7pciephy_source_source_valid; +wire s7pciephy_source_source_ready; +wire s7pciephy_source_source_first; +wire s7pciephy_source_source_last; +wire [63:0] s7pciephy_source_source_payload_dat; +wire [7:0] s7pciephy_source_source_payload_be; +wire s7pciephy_msi_valid; +wire s7pciephy_msi_ready; +wire s7pciephy_msi_first; +wire s7pciephy_msi_last; +wire [7:0] s7pciephy_msi_payload_dat; +wire s7pciephy_csrfield_status; +wire s7pciephy_csrfield_rate; +wire [1:0] s7pciephy_csrfield_width; +wire [5:0] s7pciephy_csrfield_ltssm; +reg [9:0] s7pciephy_link_status_status = 10'd0; +wire s7pciephy_link_status_we; +wire s7pciephy_link_status_re; +wire s7pciephy_msi_enable_status; +wire s7pciephy_msi_enable_we; +wire s7pciephy_msi_enable_re; +wire s7pciephy_msix_enable_status; +wire s7pciephy_msix_enable_we; +wire s7pciephy_msix_enable_re; +wire s7pciephy_bus_master_enable_status; +wire s7pciephy_bus_master_enable_we; +wire s7pciephy_bus_master_enable_re; +wire [15:0] s7pciephy_max_request_size_status; +wire s7pciephy_max_request_size_we; +wire s7pciephy_max_request_size_re; +wire [15:0] s7pciephy_max_payload_size_status; +wire s7pciephy_max_payload_size_we; +wire s7pciephy_max_payload_size_re; +reg [15:0] s7pciephy_id = 16'd0; +reg [15:0] s7pciephy_max_request_size = 16'd0; +reg [15:0] s7pciephy_max_payload_size = 16'd0; +wire s7pciephy_pcie_refclk; +wire s7pciephy_pcie_rst_n; +(* dont_touch = "true" *) wire pcie_clk; +wire pcie_rst; +wire s7pciephy_tx_datapath_sink_sink_valid; +wire s7pciephy_tx_datapath_sink_sink_ready; +wire s7pciephy_tx_datapath_sink_sink_first; +wire s7pciephy_tx_datapath_sink_sink_last; +wire [63:0] s7pciephy_tx_datapath_sink_sink_payload_dat; +wire [7:0] s7pciephy_tx_datapath_sink_sink_payload_be; +wire s7pciephy_tx_datapath_source_source_valid; +wire s7pciephy_tx_datapath_source_source_ready; +wire s7pciephy_tx_datapath_source_source_first; +wire s7pciephy_tx_datapath_source_source_last; +wire [63:0] s7pciephy_tx_datapath_source_source_payload_dat; +wire [7:0] s7pciephy_tx_datapath_source_source_payload_be; +wire s7pciephy_tx_datapath_pipe_valid_sink_valid; +wire s7pciephy_tx_datapath_pipe_valid_sink_ready; +wire s7pciephy_tx_datapath_pipe_valid_sink_first; +wire s7pciephy_tx_datapath_pipe_valid_sink_last; +wire [63:0] s7pciephy_tx_datapath_pipe_valid_sink_payload_dat; +wire [7:0] s7pciephy_tx_datapath_pipe_valid_sink_payload_be; +reg s7pciephy_tx_datapath_pipe_valid_source_valid = 1'd0; +wire s7pciephy_tx_datapath_pipe_valid_source_ready; +reg s7pciephy_tx_datapath_pipe_valid_source_first = 1'd0; +reg s7pciephy_tx_datapath_pipe_valid_source_last = 1'd0; +reg [63:0] s7pciephy_tx_datapath_pipe_valid_source_payload_dat = 64'd0; +reg [7:0] s7pciephy_tx_datapath_pipe_valid_source_payload_be = 8'd0; +wire s7pciephy_tx_datapath_cdc_sink_valid; +wire s7pciephy_tx_datapath_cdc_sink_ready; +wire s7pciephy_tx_datapath_cdc_sink_first; +wire s7pciephy_tx_datapath_cdc_sink_last; +wire [63:0] s7pciephy_tx_datapath_cdc_sink_payload_dat; +wire [7:0] s7pciephy_tx_datapath_cdc_sink_payload_be; +wire s7pciephy_tx_datapath_cdc_source_valid; +wire s7pciephy_tx_datapath_cdc_source_ready; +wire s7pciephy_tx_datapath_cdc_source_first; +wire s7pciephy_tx_datapath_cdc_source_last; +wire [63:0] s7pciephy_tx_datapath_cdc_source_payload_dat; +wire [7:0] s7pciephy_tx_datapath_cdc_source_payload_be; +wire s7pciephy_tx_datapath_cdc_asyncfifo_we; +wire s7pciephy_tx_datapath_cdc_asyncfifo_writable; +wire s7pciephy_tx_datapath_cdc_asyncfifo_re; +wire s7pciephy_tx_datapath_cdc_asyncfifo_readable; +wire [73:0] s7pciephy_tx_datapath_cdc_asyncfifo_din; +wire [73:0] s7pciephy_tx_datapath_cdc_asyncfifo_dout; +wire s7pciephy_tx_datapath_cdc_graycounter0_ce; +(* dont_touch = "true" *) reg [2:0] s7pciephy_tx_datapath_cdc_graycounter0_q = 3'd0; +wire [2:0] s7pciephy_tx_datapath_cdc_graycounter0_q_next; +reg [2:0] s7pciephy_tx_datapath_cdc_graycounter0_q_binary = 3'd0; +reg [2:0] s7pciephy_tx_datapath_cdc_graycounter0_q_next_binary = 3'd0; +wire s7pciephy_tx_datapath_cdc_graycounter1_ce; +(* dont_touch = "true" *) reg [2:0] s7pciephy_tx_datapath_cdc_graycounter1_q = 3'd0; +wire [2:0] s7pciephy_tx_datapath_cdc_graycounter1_q_next; +reg [2:0] s7pciephy_tx_datapath_cdc_graycounter1_q_binary = 3'd0; +reg [2:0] s7pciephy_tx_datapath_cdc_graycounter1_q_next_binary = 3'd0; +wire [2:0] s7pciephy_tx_datapath_cdc_produce_rdomain; +wire [2:0] s7pciephy_tx_datapath_cdc_consume_wdomain; +wire [1:0] s7pciephy_tx_datapath_cdc_wrport_adr; +wire [73:0] s7pciephy_tx_datapath_cdc_wrport_dat_r; +wire s7pciephy_tx_datapath_cdc_wrport_we; +wire [73:0] s7pciephy_tx_datapath_cdc_wrport_dat_w; +wire [1:0] s7pciephy_tx_datapath_cdc_rdport_adr; +wire [73:0] s7pciephy_tx_datapath_cdc_rdport_dat_r; +wire [63:0] s7pciephy_tx_datapath_cdc_fifo_in_payload_dat; +wire [7:0] s7pciephy_tx_datapath_cdc_fifo_in_payload_be; +wire s7pciephy_tx_datapath_cdc_fifo_in_first; +wire s7pciephy_tx_datapath_cdc_fifo_in_last; +wire [63:0] s7pciephy_tx_datapath_cdc_fifo_out_payload_dat; +wire [7:0] s7pciephy_tx_datapath_cdc_fifo_out_payload_be; +wire s7pciephy_tx_datapath_cdc_fifo_out_first; +wire s7pciephy_tx_datapath_cdc_fifo_out_last; +wire s7pciephy_tx_datapath_converter_sink_valid; +wire s7pciephy_tx_datapath_converter_sink_ready; +wire s7pciephy_tx_datapath_converter_sink_first; +wire s7pciephy_tx_datapath_converter_sink_last; +wire [63:0] s7pciephy_tx_datapath_converter_sink_payload_dat; +wire [7:0] s7pciephy_tx_datapath_converter_sink_payload_be; +wire s7pciephy_tx_datapath_converter_source_valid; +wire s7pciephy_tx_datapath_converter_source_ready; +wire s7pciephy_tx_datapath_converter_source_first; +wire s7pciephy_tx_datapath_converter_source_last; +wire [63:0] s7pciephy_tx_datapath_converter_source_payload_dat; +wire [7:0] s7pciephy_tx_datapath_converter_source_payload_be; +wire s7pciephy_tx_datapath_converter_converter_sink_valid; +wire s7pciephy_tx_datapath_converter_converter_sink_ready; +wire s7pciephy_tx_datapath_converter_converter_sink_first; +wire s7pciephy_tx_datapath_converter_converter_sink_last; +wire [71:0] s7pciephy_tx_datapath_converter_converter_sink_payload_data; +wire s7pciephy_tx_datapath_converter_converter_source_valid; +wire s7pciephy_tx_datapath_converter_converter_source_ready; +wire s7pciephy_tx_datapath_converter_converter_source_first; +wire s7pciephy_tx_datapath_converter_converter_source_last; +wire [71:0] s7pciephy_tx_datapath_converter_converter_source_payload_data; +wire s7pciephy_tx_datapath_converter_converter_source_payload_valid_token_count; +wire s7pciephy_tx_datapath_converter_source_source_valid; +wire s7pciephy_tx_datapath_converter_source_source_ready; +wire s7pciephy_tx_datapath_converter_source_source_first; +wire s7pciephy_tx_datapath_converter_source_source_last; +wire [71:0] s7pciephy_tx_datapath_converter_source_source_payload_data; +wire s7pciephy_tx_datapath_pipe_ready_sink_valid; +wire s7pciephy_tx_datapath_pipe_ready_sink_ready; +wire s7pciephy_tx_datapath_pipe_ready_sink_first; +wire s7pciephy_tx_datapath_pipe_ready_sink_last; +wire [63:0] s7pciephy_tx_datapath_pipe_ready_sink_payload_dat; +wire [7:0] s7pciephy_tx_datapath_pipe_ready_sink_payload_be; +reg s7pciephy_tx_datapath_pipe_ready_source_valid = 1'd0; +wire s7pciephy_tx_datapath_pipe_ready_source_ready; +reg s7pciephy_tx_datapath_pipe_ready_source_first = 1'd0; +reg s7pciephy_tx_datapath_pipe_ready_source_last = 1'd0; +reg [63:0] s7pciephy_tx_datapath_pipe_ready_source_payload_dat = 64'd0; +reg [7:0] s7pciephy_tx_datapath_pipe_ready_source_payload_be = 8'd0; +reg s7pciephy_tx_datapath_pipe_ready_valid = 1'd0; +reg s7pciephy_tx_datapath_pipe_ready_sink_d_valid = 1'd0; +reg s7pciephy_tx_datapath_pipe_ready_sink_d_ready = 1'd0; +reg s7pciephy_tx_datapath_pipe_ready_sink_d_first = 1'd0; +reg s7pciephy_tx_datapath_pipe_ready_sink_d_last = 1'd0; +reg [63:0] s7pciephy_tx_datapath_pipe_ready_sink_d_payload_dat = 64'd0; +reg [7:0] s7pciephy_tx_datapath_pipe_ready_sink_d_payload_be = 8'd0; +wire s7pciephy_rx_datapath_sink_sink_valid; +wire s7pciephy_rx_datapath_sink_sink_ready; +wire s7pciephy_rx_datapath_sink_sink_first; +wire s7pciephy_rx_datapath_sink_sink_last; +wire [63:0] s7pciephy_rx_datapath_sink_sink_payload_dat; +wire [7:0] s7pciephy_rx_datapath_sink_sink_payload_be; +wire s7pciephy_rx_datapath_source_source_valid; +wire s7pciephy_rx_datapath_source_source_ready; +wire s7pciephy_rx_datapath_source_source_first; +wire s7pciephy_rx_datapath_source_source_last; +wire [63:0] s7pciephy_rx_datapath_source_source_payload_dat; +wire [7:0] s7pciephy_rx_datapath_source_source_payload_be; +wire s7pciephy_rx_datapath_pipe_ready_sink_valid; +wire s7pciephy_rx_datapath_pipe_ready_sink_ready; +wire s7pciephy_rx_datapath_pipe_ready_sink_first; +wire s7pciephy_rx_datapath_pipe_ready_sink_last; +wire [63:0] s7pciephy_rx_datapath_pipe_ready_sink_payload_dat; +wire [7:0] s7pciephy_rx_datapath_pipe_ready_sink_payload_be; +reg s7pciephy_rx_datapath_pipe_ready_source_valid = 1'd0; +wire s7pciephy_rx_datapath_pipe_ready_source_ready; +reg s7pciephy_rx_datapath_pipe_ready_source_first = 1'd0; +reg s7pciephy_rx_datapath_pipe_ready_source_last = 1'd0; +reg [63:0] s7pciephy_rx_datapath_pipe_ready_source_payload_dat = 64'd0; +reg [7:0] s7pciephy_rx_datapath_pipe_ready_source_payload_be = 8'd0; +reg s7pciephy_rx_datapath_pipe_ready_valid = 1'd0; +reg s7pciephy_rx_datapath_pipe_ready_sink_d_valid = 1'd0; +reg s7pciephy_rx_datapath_pipe_ready_sink_d_ready = 1'd0; +reg s7pciephy_rx_datapath_pipe_ready_sink_d_first = 1'd0; +reg s7pciephy_rx_datapath_pipe_ready_sink_d_last = 1'd0; +reg [63:0] s7pciephy_rx_datapath_pipe_ready_sink_d_payload_dat = 64'd0; +reg [7:0] s7pciephy_rx_datapath_pipe_ready_sink_d_payload_be = 8'd0; +wire s7pciephy_rx_datapath_converter_sink_valid; +wire s7pciephy_rx_datapath_converter_sink_ready; +wire s7pciephy_rx_datapath_converter_sink_first; +wire s7pciephy_rx_datapath_converter_sink_last; +wire [63:0] s7pciephy_rx_datapath_converter_sink_payload_dat; +wire [7:0] s7pciephy_rx_datapath_converter_sink_payload_be; +wire s7pciephy_rx_datapath_converter_source_valid; +wire s7pciephy_rx_datapath_converter_source_ready; +wire s7pciephy_rx_datapath_converter_source_first; +wire s7pciephy_rx_datapath_converter_source_last; +wire [63:0] s7pciephy_rx_datapath_converter_source_payload_dat; +wire [7:0] s7pciephy_rx_datapath_converter_source_payload_be; +wire s7pciephy_rx_datapath_converter_converter_sink_valid; +wire s7pciephy_rx_datapath_converter_converter_sink_ready; +wire s7pciephy_rx_datapath_converter_converter_sink_first; +wire s7pciephy_rx_datapath_converter_converter_sink_last; +wire [71:0] s7pciephy_rx_datapath_converter_converter_sink_payload_data; +wire s7pciephy_rx_datapath_converter_converter_source_valid; +wire s7pciephy_rx_datapath_converter_converter_source_ready; +wire s7pciephy_rx_datapath_converter_converter_source_first; +wire s7pciephy_rx_datapath_converter_converter_source_last; +wire [71:0] s7pciephy_rx_datapath_converter_converter_source_payload_data; +wire s7pciephy_rx_datapath_converter_converter_source_payload_valid_token_count; +wire s7pciephy_rx_datapath_converter_source_source_valid; +wire s7pciephy_rx_datapath_converter_source_source_ready; +wire s7pciephy_rx_datapath_converter_source_source_first; +wire s7pciephy_rx_datapath_converter_source_source_last; +wire [71:0] s7pciephy_rx_datapath_converter_source_source_payload_data; +wire s7pciephy_rx_datapath_cdc_sink_valid; +wire s7pciephy_rx_datapath_cdc_sink_ready; +wire s7pciephy_rx_datapath_cdc_sink_first; +wire s7pciephy_rx_datapath_cdc_sink_last; +wire [63:0] s7pciephy_rx_datapath_cdc_sink_payload_dat; +wire [7:0] s7pciephy_rx_datapath_cdc_sink_payload_be; +wire s7pciephy_rx_datapath_cdc_source_valid; +wire s7pciephy_rx_datapath_cdc_source_ready; +wire s7pciephy_rx_datapath_cdc_source_first; +wire s7pciephy_rx_datapath_cdc_source_last; +wire [63:0] s7pciephy_rx_datapath_cdc_source_payload_dat; +wire [7:0] s7pciephy_rx_datapath_cdc_source_payload_be; +wire s7pciephy_rx_datapath_cdc_asyncfifo_we; +wire s7pciephy_rx_datapath_cdc_asyncfifo_writable; +wire s7pciephy_rx_datapath_cdc_asyncfifo_re; +wire s7pciephy_rx_datapath_cdc_asyncfifo_readable; +wire [73:0] s7pciephy_rx_datapath_cdc_asyncfifo_din; +wire [73:0] s7pciephy_rx_datapath_cdc_asyncfifo_dout; +wire s7pciephy_rx_datapath_cdc_graycounter0_ce; +(* dont_touch = "true" *) reg [2:0] s7pciephy_rx_datapath_cdc_graycounter0_q = 3'd0; +wire [2:0] s7pciephy_rx_datapath_cdc_graycounter0_q_next; +reg [2:0] s7pciephy_rx_datapath_cdc_graycounter0_q_binary = 3'd0; +reg [2:0] s7pciephy_rx_datapath_cdc_graycounter0_q_next_binary = 3'd0; +wire s7pciephy_rx_datapath_cdc_graycounter1_ce; +(* dont_touch = "true" *) reg [2:0] s7pciephy_rx_datapath_cdc_graycounter1_q = 3'd0; +wire [2:0] s7pciephy_rx_datapath_cdc_graycounter1_q_next; +reg [2:0] s7pciephy_rx_datapath_cdc_graycounter1_q_binary = 3'd0; +reg [2:0] s7pciephy_rx_datapath_cdc_graycounter1_q_next_binary = 3'd0; +wire [2:0] s7pciephy_rx_datapath_cdc_produce_rdomain; +wire [2:0] s7pciephy_rx_datapath_cdc_consume_wdomain; +wire [1:0] s7pciephy_rx_datapath_cdc_wrport_adr; +wire [73:0] s7pciephy_rx_datapath_cdc_wrport_dat_r; +wire s7pciephy_rx_datapath_cdc_wrport_we; +wire [73:0] s7pciephy_rx_datapath_cdc_wrport_dat_w; +wire [1:0] s7pciephy_rx_datapath_cdc_rdport_adr; +wire [73:0] s7pciephy_rx_datapath_cdc_rdport_dat_r; +wire [63:0] s7pciephy_rx_datapath_cdc_fifo_in_payload_dat; +wire [7:0] s7pciephy_rx_datapath_cdc_fifo_in_payload_be; +wire s7pciephy_rx_datapath_cdc_fifo_in_first; +wire s7pciephy_rx_datapath_cdc_fifo_in_last; +wire [63:0] s7pciephy_rx_datapath_cdc_fifo_out_payload_dat; +wire [7:0] s7pciephy_rx_datapath_cdc_fifo_out_payload_be; +wire s7pciephy_rx_datapath_cdc_fifo_out_first; +wire s7pciephy_rx_datapath_cdc_fifo_out_last; +wire s7pciephy_rx_datapath_pipe_valid_sink_valid; +wire s7pciephy_rx_datapath_pipe_valid_sink_ready; +wire s7pciephy_rx_datapath_pipe_valid_sink_first; +wire s7pciephy_rx_datapath_pipe_valid_sink_last; +wire [63:0] s7pciephy_rx_datapath_pipe_valid_sink_payload_dat; +wire [7:0] s7pciephy_rx_datapath_pipe_valid_sink_payload_be; +reg s7pciephy_rx_datapath_pipe_valid_source_valid = 1'd0; +wire s7pciephy_rx_datapath_pipe_valid_source_ready; +reg s7pciephy_rx_datapath_pipe_valid_source_first = 1'd0; +reg s7pciephy_rx_datapath_pipe_valid_source_last = 1'd0; +reg [63:0] s7pciephy_rx_datapath_pipe_valid_source_payload_dat = 64'd0; +reg [7:0] s7pciephy_rx_datapath_pipe_valid_source_payload_be = 8'd0; +wire s7pciephy_msi_cdc_sink_valid; +wire s7pciephy_msi_cdc_sink_ready; +wire s7pciephy_msi_cdc_sink_first; +wire s7pciephy_msi_cdc_sink_last; +wire [7:0] s7pciephy_msi_cdc_sink_payload_dat; +wire s7pciephy_msi_cdc_source_valid; +wire s7pciephy_msi_cdc_source_ready; +wire s7pciephy_msi_cdc_source_first; +wire s7pciephy_msi_cdc_source_last; +wire [7:0] s7pciephy_msi_cdc_source_payload_dat; +wire s7pciephy_msi_cdc_asyncfifo_we; +wire s7pciephy_msi_cdc_asyncfifo_writable; +wire s7pciephy_msi_cdc_asyncfifo_re; +wire s7pciephy_msi_cdc_asyncfifo_readable; +wire [9:0] s7pciephy_msi_cdc_asyncfifo_din; +wire [9:0] s7pciephy_msi_cdc_asyncfifo_dout; +wire s7pciephy_msi_cdc_graycounter0_ce; +(* dont_touch = "true" *) reg [2:0] s7pciephy_msi_cdc_graycounter0_q = 3'd0; +wire [2:0] s7pciephy_msi_cdc_graycounter0_q_next; +reg [2:0] s7pciephy_msi_cdc_graycounter0_q_binary = 3'd0; +reg [2:0] s7pciephy_msi_cdc_graycounter0_q_next_binary = 3'd0; +wire s7pciephy_msi_cdc_graycounter1_ce; +(* dont_touch = "true" *) reg [2:0] s7pciephy_msi_cdc_graycounter1_q = 3'd0; +wire [2:0] s7pciephy_msi_cdc_graycounter1_q_next; +reg [2:0] s7pciephy_msi_cdc_graycounter1_q_binary = 3'd0; +reg [2:0] s7pciephy_msi_cdc_graycounter1_q_next_binary = 3'd0; +wire [2:0] s7pciephy_msi_cdc_produce_rdomain; +wire [2:0] s7pciephy_msi_cdc_consume_wdomain; +wire [1:0] s7pciephy_msi_cdc_wrport_adr; +wire [9:0] s7pciephy_msi_cdc_wrport_dat_r; +wire s7pciephy_msi_cdc_wrport_we; +wire [9:0] s7pciephy_msi_cdc_wrport_dat_w; +wire [1:0] s7pciephy_msi_cdc_rdport_adr; +wire [9:0] s7pciephy_msi_cdc_rdport_dat_r; +wire [7:0] s7pciephy_msi_cdc_fifo_in_payload_dat; +wire s7pciephy_msi_cdc_fifo_in_first; +wire s7pciephy_msi_cdc_fifo_in_last; +wire [7:0] s7pciephy_msi_cdc_fifo_out_payload_dat; +wire s7pciephy_msi_cdc_fifo_out_first; +wire s7pciephy_msi_cdc_fifo_out_last; +wire [7:0] s7pciephy_bus_number; +wire [4:0] s7pciephy_device_number; +wire [2:0] s7pciephy_function_number; +wire [15:0] s7pciephy_command; +wire [15:0] s7pciephy_dcommand; +wire s7pciephy_m_axis_rx_tlast; +wire [31:0] s7pciephy_m_axis_rx_tuser; +wire s7pciephy0; +wire s7pciephy1; +wire s7pciephy2; +wire s7pciephy3; +wire s7pciephy4; +wire s7pciephy5; +wire s7pciephy6; +wire s7pciephy7; +wire s7pciephy8; +wire s7pciephy9; +wire s7pciephy10; +wire s7pciephy11; +wire s7pciephy12; +wire s7pciephy13; +wire s7pciephy14; +wire s7pciephy15; +wire s7pciephy16; +wire s7pciephy17; +wire s7pciephy18; +wire s7pciephy19; +wire s7pciephy20; +wire s7pciephy21; +wire s7pciephy22; +wire s7pciephy23; +wire s7pciephy24; +wire s7pciephy25; +wire s7pciephy26; +wire s7pciephy27; +wire s7pciephy28; +wire s7pciephy29; +wire s7pciephy30; +wire s7pciephy31; +wire s7pciephy32; +wire s7pciephy33; +wire s7pciephy34; +wire s7pciephy35; +wire s7pciephy36; +wire s7pciephy37; +wire s7pciephy38; +wire s7pciephy39; +wire s7pciephy40; +wire s7pciephy41; +wire s7pciephy42; +wire s7pciephy43; +wire s7pciephy44; +wire s7pciephy45; +wire s7pciephy46; +wire s7pciephy47; +wire s7pciephy48; +wire s7pciephy49; +wire s7pciephy50; +wire s7pciephy51; +wire s7pciephy52; +wire s7pciephy53; +wire s7pciephy54; +wire s7pciephy55; +wire s7pciephy56; +wire s7pciephy57; +wire s7pciephy58; +wire s7pciephy59; +wire s7pciephy60; +wire s7pciephy61; +wire s7pciephy62; +wire s7pciephy63; +wire s7pciephy64; +wire s7pciephy65; +wire s7pciephy66; +wire s7pciephy67; +wire s7pciephy68; +wire s7pciephy69; +wire s7pciephy70; +wire s7pciephy71; +wire s7pciephy72; +wire s7pciephy73; +wire s7pciephy74; +wire s7pciephy75; +wire s7pciephy76; +wire s7pciephy77; +wire s7pciephy78; +wire s7pciephy79; +wire depacketizer_sink_sink_valid; +wire depacketizer_sink_sink_ready; +wire depacketizer_sink_sink_first; +wire depacketizer_sink_sink_last; +wire [63:0] depacketizer_sink_sink_payload_dat; +wire [7:0] depacketizer_sink_sink_payload_be; +wire depacketizer_req_source_valid; +wire depacketizer_req_source_ready; +wire depacketizer_req_source_first; +wire depacketizer_req_source_last; +wire depacketizer_req_source_payload_we; +wire [31:0] depacketizer_req_source_payload_adr; +wire [9:0] depacketizer_req_source_payload_len; +wire [15:0] depacketizer_req_source_payload_req_id; +wire [7:0] depacketizer_req_source_payload_tag; +wire [63:0] depacketizer_req_source_payload_dat; +reg [7:0] depacketizer_req_source_payload_channel = 8'd0; +reg [7:0] depacketizer_req_source_payload_user_id = 8'd0; +wire depacketizer_cmp_source_valid; +wire depacketizer_cmp_source_ready; +wire depacketizer_cmp_source_first; +wire depacketizer_cmp_source_last; +wire [31:0] depacketizer_cmp_source_payload_adr; +wire [9:0] depacketizer_cmp_source_payload_len; +wire depacketizer_cmp_source_payload_end; +wire [15:0] depacketizer_cmp_source_payload_req_id; +wire [15:0] depacketizer_cmp_source_payload_cmp_id; +wire depacketizer_cmp_source_payload_err; +wire [7:0] depacketizer_cmp_source_payload_tag; +wire [63:0] depacketizer_cmp_source_payload_dat; +reg [7:0] depacketizer_cmp_source_payload_channel = 8'd0; +reg [7:0] depacketizer_cmp_source_payload_user_id = 8'd0; +wire depacketizer_header_extracter_sink_valid; +reg depacketizer_header_extracter_sink_ready = 1'd0; +wire depacketizer_header_extracter_sink_first; +wire depacketizer_header_extracter_sink_last; +wire [63:0] depacketizer_header_extracter_sink_payload_dat; +wire [7:0] depacketizer_header_extracter_sink_payload_be; +reg depacketizer_header_extracter_source_valid = 1'd0; +wire depacketizer_header_extracter_source_ready; +reg depacketizer_header_extracter_source_first = 1'd0; +reg depacketizer_header_extracter_source_last = 1'd0; +reg [127:0] depacketizer_header_extracter_source_payload_header = 128'd0; +reg [63:0] depacketizer_header_extracter_source_payload_dat = 64'd0; +reg [7:0] depacketizer_header_extracter_source_payload_be = 8'd0; +reg depacketizer_header_extracter_first = 1'd0; +reg depacketizer_header_extracter_last = 1'd0; +reg depacketizer_header_extracter_count = 1'd0; +reg [63:0] depacketizer_header_extracter_dat = 64'd0; +reg [7:0] depacketizer_header_extracter_be = 8'd0; +wire depacketizer_dispatch_source_valid; +reg depacketizer_dispatch_source_ready = 1'd0; +wire depacketizer_dispatch_source_first; +wire depacketizer_dispatch_source_last; +wire [1:0] depacketizer_dispatch_source_payload_fmt; +wire [4:0] depacketizer_dispatch_source_payload_type; +wire [63:0] depacketizer_dispatch_source_payload_dat; +wire [7:0] depacketizer_dispatch_source_payload_be; +reg depacketizer_endpoint0_valid = 1'd0; +wire depacketizer_endpoint0_ready; +reg depacketizer_endpoint0_first = 1'd0; +reg depacketizer_endpoint0_last = 1'd0; +reg [1:0] depacketizer_endpoint0_payload_fmt = 2'd0; +reg [4:0] depacketizer_endpoint0_payload_type = 5'd0; +reg [63:0] depacketizer_endpoint0_payload_dat = 64'd0; +reg [7:0] depacketizer_endpoint0_payload_be = 8'd0; +reg depacketizer_endpoint1_valid = 1'd0; +wire depacketizer_endpoint1_ready; +reg depacketizer_endpoint1_first = 1'd0; +reg depacketizer_endpoint1_last = 1'd0; +reg [1:0] depacketizer_endpoint1_payload_fmt = 2'd0; +reg [4:0] depacketizer_endpoint1_payload_type = 5'd0; +reg [63:0] depacketizer_endpoint1_payload_dat = 64'd0; +reg [7:0] depacketizer_endpoint1_payload_be = 8'd0; +reg depacketizer_dispatcher_sel0 = 1'd0; +reg depacketizer_dispatcher_first = 1'd1; +reg depacketizer_dispatcher_last = 1'd0; +wire depacketizer_dispatcher_ongoing0; +reg depacketizer_dispatcher_ongoing1 = 1'd0; +reg depacketizer_dispatcher_sel1 = 1'd0; +reg depacketizer_dispatcher_sel_ongoing = 1'd0; +wire depacketizer_tlp_req_valid; +wire depacketizer_tlp_req_ready; +wire depacketizer_tlp_req_first; +wire depacketizer_tlp_req_last; +wire [31:0] depacketizer_tlp_req_payload_address; +wire [1:0] depacketizer_tlp_req_payload_attr; +wire depacketizer_tlp_req_payload_ep; +wire [3:0] depacketizer_tlp_req_payload_first_be; +reg [1:0] depacketizer_tlp_req_payload_fmt = 2'd0; +wire [3:0] depacketizer_tlp_req_payload_last_be; +wire [9:0] depacketizer_tlp_req_payload_length; +wire [15:0] depacketizer_tlp_req_payload_requester_id; +wire [7:0] depacketizer_tlp_req_payload_tag; +wire [2:0] depacketizer_tlp_req_payload_tc; +wire depacketizer_tlp_req_payload_td; +reg [4:0] depacketizer_tlp_req_payload_type = 5'd0; +wire [63:0] depacketizer_tlp_req_payload_dat; +wire [7:0] depacketizer_tlp_req_payload_be; +wire depacketizer_tlp_cmp_valid; +wire depacketizer_tlp_cmp_ready; +wire depacketizer_tlp_cmp_first; +wire depacketizer_tlp_cmp_last; +wire [1:0] depacketizer_tlp_cmp_payload_attr; +wire depacketizer_tlp_cmp_payload_bcm; +wire [11:0] depacketizer_tlp_cmp_payload_byte_count; +wire [15:0] depacketizer_tlp_cmp_payload_completer_id; +wire depacketizer_tlp_cmp_payload_ep; +reg [1:0] depacketizer_tlp_cmp_payload_fmt = 2'd0; +wire [9:0] depacketizer_tlp_cmp_payload_length; +wire [6:0] depacketizer_tlp_cmp_payload_lower_address; +wire [15:0] depacketizer_tlp_cmp_payload_requester_id; +wire [2:0] depacketizer_tlp_cmp_payload_status; +wire [7:0] depacketizer_tlp_cmp_payload_tag; +wire [2:0] depacketizer_tlp_cmp_payload_tc; +wire depacketizer_tlp_cmp_payload_td; +reg [4:0] depacketizer_tlp_cmp_payload_type = 5'd0; +wire [63:0] depacketizer_tlp_cmp_payload_dat; +wire [7:0] depacketizer_tlp_cmp_payload_be; +wire packetizer_req_sink_valid; +wire packetizer_req_sink_ready; +wire packetizer_req_sink_first; +wire packetizer_req_sink_last; +wire packetizer_req_sink_payload_we; +wire [31:0] packetizer_req_sink_payload_adr; +wire [9:0] packetizer_req_sink_payload_len; +wire [15:0] packetizer_req_sink_payload_req_id; +wire [7:0] packetizer_req_sink_payload_tag; +wire [63:0] packetizer_req_sink_payload_dat; +wire [7:0] packetizer_req_sink_payload_channel; +wire [7:0] packetizer_req_sink_payload_user_id; +wire packetizer_cmp_sink_valid; +wire packetizer_cmp_sink_ready; +wire packetizer_cmp_sink_first; +wire packetizer_cmp_sink_last; +wire [31:0] packetizer_cmp_sink_payload_adr; +wire [9:0] packetizer_cmp_sink_payload_len; +wire packetizer_cmp_sink_payload_end; +wire [15:0] packetizer_cmp_sink_payload_req_id; +wire [15:0] packetizer_cmp_sink_payload_cmp_id; +wire packetizer_cmp_sink_payload_err; +wire [7:0] packetizer_cmp_sink_payload_tag; +wire [63:0] packetizer_cmp_sink_payload_dat; +wire [7:0] packetizer_cmp_sink_payload_channel; +wire [7:0] packetizer_cmp_sink_payload_user_id; +wire packetizer_source_source_valid; +wire packetizer_source_source_ready; +wire packetizer_source_source_first; +wire packetizer_source_source_last; +wire [63:0] packetizer_source_source_payload_dat; +wire [7:0] packetizer_source_source_payload_be; +wire packetizer_tlp_req_valid; +wire packetizer_tlp_req_ready; +wire packetizer_tlp_req_first; +wire packetizer_tlp_req_last; +wire [31:0] packetizer_tlp_req_payload_address; +wire [1:0] packetizer_tlp_req_payload_attr; +wire packetizer_tlp_req_payload_ep; +wire [3:0] packetizer_tlp_req_payload_first_be; +reg [1:0] packetizer_tlp_req_payload_fmt = 2'd0; +reg [3:0] packetizer_tlp_req_payload_last_be = 4'd0; +wire [9:0] packetizer_tlp_req_payload_length; +wire [15:0] packetizer_tlp_req_payload_requester_id; +wire [7:0] packetizer_tlp_req_payload_tag; +wire [2:0] packetizer_tlp_req_payload_tc; +wire packetizer_tlp_req_payload_td; +reg [4:0] packetizer_tlp_req_payload_type = 5'd0; +wire [63:0] packetizer_tlp_req_payload_dat; +reg [7:0] packetizer_tlp_req_payload_be = 8'd0; +wire packetizer_tlp_raw_req_valid; +reg packetizer_tlp_raw_req_ready = 1'd0; +wire packetizer_tlp_raw_req_first; +wire packetizer_tlp_raw_req_last; +reg [127:0] packetizer_tlp_raw_req_payload_header = 128'd0; +wire [63:0] packetizer_tlp_raw_req_payload_dat; +wire [7:0] packetizer_tlp_raw_req_payload_be; +wire packetizer_tlp_cmp_valid; +wire packetizer_tlp_cmp_ready; +wire packetizer_tlp_cmp_first; +wire packetizer_tlp_cmp_last; +wire [1:0] packetizer_tlp_cmp_payload_attr; +wire packetizer_tlp_cmp_payload_bcm; +wire [11:0] packetizer_tlp_cmp_payload_byte_count; +wire [15:0] packetizer_tlp_cmp_payload_completer_id; +wire packetizer_tlp_cmp_payload_ep; +reg [1:0] packetizer_tlp_cmp_payload_fmt = 2'd0; +wire [9:0] packetizer_tlp_cmp_payload_length; +wire [6:0] packetizer_tlp_cmp_payload_lower_address; +wire [15:0] packetizer_tlp_cmp_payload_requester_id; +reg [2:0] packetizer_tlp_cmp_payload_status = 3'd0; +wire [7:0] packetizer_tlp_cmp_payload_tag; +wire [2:0] packetizer_tlp_cmp_payload_tc; +wire packetizer_tlp_cmp_payload_td; +reg [4:0] packetizer_tlp_cmp_payload_type = 5'd0; +wire [63:0] packetizer_tlp_cmp_payload_dat; +reg [7:0] packetizer_tlp_cmp_payload_be = 8'd0; +wire packetizer_tlp_raw_cmp_valid; +reg packetizer_tlp_raw_cmp_ready = 1'd0; +wire packetizer_tlp_raw_cmp_first; +wire packetizer_tlp_raw_cmp_last; +reg [127:0] packetizer_tlp_raw_cmp_payload_header = 128'd0; +wire [63:0] packetizer_tlp_raw_cmp_payload_dat; +wire [7:0] packetizer_tlp_raw_cmp_payload_be; +reg packetizer_tlp_raw_valid = 1'd0; +wire packetizer_tlp_raw_ready; +reg packetizer_tlp_raw_first = 1'd0; +reg packetizer_tlp_raw_last = 1'd0; +reg [127:0] packetizer_tlp_raw_payload_header = 128'd0; +reg [63:0] packetizer_tlp_raw_payload_dat = 64'd0; +reg [7:0] packetizer_tlp_raw_payload_be = 8'd0; +reg [1:0] packetizer_request = 2'd0; +reg packetizer_grant = 1'd0; +reg packetizer_status0_first = 1'd1; +reg packetizer_status0_last = 1'd0; +wire packetizer_status0_ongoing0; +reg packetizer_status0_ongoing1 = 1'd0; +reg packetizer_status1_first = 1'd1; +reg packetizer_status1_last = 1'd0; +wire packetizer_status1_ongoing0; +reg packetizer_status1_ongoing1 = 1'd0; +wire packetizer_header_inserter_sink_valid; +reg packetizer_header_inserter_sink_ready = 1'd0; +wire packetizer_header_inserter_sink_first; +wire packetizer_header_inserter_sink_last; +wire [127:0] packetizer_header_inserter_sink_payload_header; +wire [63:0] packetizer_header_inserter_sink_payload_dat; +wire [7:0] packetizer_header_inserter_sink_payload_be; +reg packetizer_header_inserter_source_valid = 1'd0; +wire packetizer_header_inserter_source_ready; +reg packetizer_header_inserter_source_first = 1'd0; +reg packetizer_header_inserter_source_last = 1'd0; +reg [63:0] packetizer_header_inserter_source_payload_dat = 64'd0; +reg [7:0] packetizer_header_inserter_source_payload_be = 8'd0; +reg [63:0] packetizer_header_inserter_dat = 64'd0; +reg packetizer_header_inserter_last = 1'd0; +reg master_sink_valid = 1'd0; +wire master_sink_ready; +reg master_sink_first = 1'd0; +reg master_sink_last = 1'd0; +reg master_sink_payload_we = 1'd0; +reg [31:0] master_sink_payload_adr = 32'd0; +reg [9:0] master_sink_payload_len = 10'd0; +reg [15:0] master_sink_payload_req_id = 16'd0; +reg [7:0] master_sink_payload_tag = 8'd0; +reg [63:0] master_sink_payload_dat = 64'd0; +reg [7:0] master_sink_payload_channel = 8'd0; +reg [7:0] master_sink_payload_user_id = 8'd0; +wire master_source_valid; +wire master_source_ready; +wire master_source_first; +wire master_source_last; +wire [31:0] master_source_payload_adr; +wire [9:0] master_source_payload_len; +wire master_source_payload_end; +wire [15:0] master_source_payload_req_id; +wire [15:0] master_source_payload_cmp_id; +wire master_source_payload_err; +wire [7:0] master_source_payload_tag; +wire [63:0] master_source_payload_dat; +wire [7:0] master_source_payload_channel; +wire [7:0] master_source_payload_user_id; +wire slave_sink_valid; +wire slave_sink_ready; +wire slave_sink_first; +wire slave_sink_last; +wire [31:0] slave_sink_payload_adr; +wire [9:0] slave_sink_payload_len; +wire slave_sink_payload_end; +wire [15:0] slave_sink_payload_req_id; +wire [15:0] slave_sink_payload_cmp_id; +wire slave_sink_payload_err; +wire [7:0] slave_sink_payload_tag; +wire [63:0] slave_sink_payload_dat; +wire [7:0] slave_sink_payload_channel; +wire [7:0] slave_sink_payload_user_id; +wire slave_source_valid; +wire slave_source_ready; +wire slave_source_first; +wire slave_source_last; +wire slave_source_payload_we; +wire [31:0] slave_source_payload_adr; +wire [9:0] slave_source_payload_len; +wire [15:0] slave_source_payload_req_id; +wire [7:0] slave_source_payload_tag; +wire [63:0] slave_source_payload_dat; +wire [7:0] slave_source_payload_channel; +wire [7:0] slave_source_payload_user_id; +reg [29:0] pcie_bridge_wishbone_adr = 30'd0; +reg [31:0] pcie_bridge_wishbone_dat_w = 32'd0; +wire [31:0] pcie_bridge_wishbone_dat_r; +reg [3:0] pcie_bridge_wishbone_sel = 4'd0; +reg pcie_bridge_wishbone_cyc = 1'd0; +reg pcie_bridge_wishbone_stb = 1'd0; +wire pcie_bridge_wishbone_ack; +reg pcie_bridge_wishbone_we = 1'd0; +reg [2:0] pcie_bridge_wishbone_cti = 3'd0; +reg [1:0] pcie_bridge_wishbone_bte = 2'd0; +wire pcie_bridge_wishbone_err; +reg pcie_bridge_sink_valid = 1'd0; +wire pcie_bridge_sink_ready; +reg pcie_bridge_sink_first = 1'd0; +reg pcie_bridge_sink_last = 1'd0; +reg [31:0] pcie_bridge_sink_payload_adr = 32'd0; +reg [9:0] pcie_bridge_sink_payload_len = 10'd0; +reg pcie_bridge_sink_payload_end = 1'd0; +reg [15:0] pcie_bridge_sink_payload_req_id = 16'd0; +reg [15:0] pcie_bridge_sink_payload_cmp_id = 16'd0; +reg pcie_bridge_sink_payload_err = 1'd0; +reg [7:0] pcie_bridge_sink_payload_tag = 8'd0; +reg [63:0] pcie_bridge_sink_payload_dat = 64'd0; +reg [7:0] pcie_bridge_sink_payload_channel = 8'd0; +reg [7:0] pcie_bridge_sink_payload_user_id = 8'd0; +wire pcie_bridge_source_valid; +reg pcie_bridge_source_ready = 1'd0; +wire pcie_bridge_source_first; +wire pcie_bridge_source_last; +wire pcie_bridge_source_payload_we; +wire [31:0] pcie_bridge_source_payload_adr; +wire [9:0] pcie_bridge_source_payload_len; +wire [15:0] pcie_bridge_source_payload_req_id; +wire [7:0] pcie_bridge_source_payload_tag; +wire [63:0] pcie_bridge_source_payload_dat; +wire [7:0] pcie_bridge_source_payload_channel; +wire [7:0] pcie_bridge_source_payload_user_id; +reg pcie_bridge_update_dat = 1'd0; +reg pcie_dma0_litepciemasterinternalport0_sink_valid = 1'd0; +reg pcie_dma0_litepciemasterinternalport0_sink_ready = 1'd0; +wire pcie_dma0_litepciemasterinternalport0_sink_first; +wire pcie_dma0_litepciemasterinternalport0_sink_last; +wire pcie_dma0_litepciemasterinternalport0_sink_payload_we; +wire [31:0] pcie_dma0_litepciemasterinternalport0_sink_payload_adr; +wire [9:0] pcie_dma0_litepciemasterinternalport0_sink_payload_len; +wire [15:0] pcie_dma0_litepciemasterinternalport0_sink_payload_req_id; +wire [7:0] pcie_dma0_litepciemasterinternalport0_sink_payload_tag; +wire [63:0] pcie_dma0_litepciemasterinternalport0_sink_payload_dat; +wire [7:0] pcie_dma0_litepciemasterinternalport0_sink_payload_channel; +wire [7:0] pcie_dma0_litepciemasterinternalport0_sink_payload_user_id; +reg pcie_dma0_litepciemasterinternalport0_source_valid = 1'd0; +reg pcie_dma0_litepciemasterinternalport0_source_ready = 1'd0; +reg pcie_dma0_litepciemasterinternalport0_source_first = 1'd0; +reg pcie_dma0_litepciemasterinternalport0_source_last = 1'd0; +reg [31:0] pcie_dma0_litepciemasterinternalport0_source_payload_adr = 32'd0; +reg [9:0] pcie_dma0_litepciemasterinternalport0_source_payload_len = 10'd0; +reg pcie_dma0_litepciemasterinternalport0_source_payload_end = 1'd0; +reg [15:0] pcie_dma0_litepciemasterinternalport0_source_payload_req_id = 16'd0; +reg [15:0] pcie_dma0_litepciemasterinternalport0_source_payload_cmp_id = 16'd0; +reg pcie_dma0_litepciemasterinternalport0_source_payload_err = 1'd0; +reg [7:0] pcie_dma0_litepciemasterinternalport0_source_payload_tag = 8'd0; +reg [63:0] pcie_dma0_litepciemasterinternalport0_source_payload_dat = 64'd0; +reg [7:0] pcie_dma0_litepciemasterinternalport0_source_payload_channel = 8'd0; +reg [7:0] pcie_dma0_litepciemasterinternalport0_source_payload_user_id = 8'd0; +wire pcie_dma0_writer_sink_valid; +wire pcie_dma0_writer_sink_ready; +wire pcie_dma0_writer_sink_first; +wire pcie_dma0_writer_sink_last; +wire [63:0] pcie_dma0_writer_sink_payload_data; +wire pcie_dma0_writer_irq; +reg pcie_dma0_writer_enable_storage = 1'd0; +reg pcie_dma0_writer_enable_re = 1'd0; +reg [12:0] pcie_dma0_writer_counter = 13'd0; +wire pcie_dma0_writer_source_source_valid; +wire pcie_dma0_writer_source_source_ready; +wire pcie_dma0_writer_source_source_first; +reg pcie_dma0_writer_source_source_last = 1'd0; +wire [31:0] pcie_dma0_writer_source_source_payload_address; +wire [23:0] pcie_dma0_writer_source_source_payload_length; +wire [7:0] pcie_dma0_writer_source_source_payload_control; +wire [31:0] pcie_dma0_writer_address; +wire [23:0] pcie_dma0_writer_length; +wire pcie_dma0_writer_irq_disable; +wire pcie_dma0_writer_last_disable; +reg [57:0] pcie_dma0_writer_value_storage = 58'd0; +reg pcie_dma0_writer_value_re = 1'd0; +reg pcie_dma0_writer_we_storage = 1'd0; +reg pcie_dma0_writer_we_re = 1'd0; +reg pcie_dma0_writer_loop_prog_n_storage = 1'd0; +reg pcie_dma0_writer_loop_prog_n_re = 1'd0; +reg [15:0] pcie_dma0_writer_index = 16'd0; +reg [15:0] pcie_dma0_writer_count = 16'd0; +reg [31:0] pcie_dma0_writer_loop_status_status = 32'd0; +wire pcie_dma0_writer_loop_status_we; +wire pcie_dma0_writer_loop_status_re; +wire [8:0] pcie_dma0_writer_level_status; +wire pcie_dma0_writer_level_we; +wire pcie_dma0_writer_level_re; +reg pcie_dma0_writer_flush_storage = 1'd0; +reg pcie_dma0_writer_flush_re = 1'd0; +reg pcie_dma0_writer_fifo_sink_valid = 1'd0; +wire pcie_dma0_writer_fifo_sink_ready; +reg pcie_dma0_writer_fifo_sink_first = 1'd0; +reg pcie_dma0_writer_fifo_sink_last = 1'd0; +reg [31:0] pcie_dma0_writer_fifo_sink_payload_address = 32'd0; +reg [23:0] pcie_dma0_writer_fifo_sink_payload_length = 24'd0; +reg [7:0] pcie_dma0_writer_fifo_sink_payload_control = 8'd0; +wire pcie_dma0_writer_fifo_source_valid; +wire pcie_dma0_writer_fifo_source_ready; +wire pcie_dma0_writer_fifo_source_first; +wire pcie_dma0_writer_fifo_source_last; +wire [31:0] pcie_dma0_writer_fifo_source_payload_address; +wire [23:0] pcie_dma0_writer_fifo_source_payload_length; +wire [7:0] pcie_dma0_writer_fifo_source_payload_control; +wire pcie_dma0_writer_fifo_syncfifo_we0; +wire pcie_dma0_writer_fifo_syncfifo_writable0; +wire pcie_dma0_writer_fifo_syncfifo_re0; +wire pcie_dma0_writer_fifo_syncfifo_readable0; +wire [65:0] pcie_dma0_writer_fifo_syncfifo_din0; +wire [65:0] pcie_dma0_writer_fifo_syncfifo_dout0; +reg [8:0] pcie_dma0_writer_fifo_level0 = 9'd0; +reg pcie_dma0_writer_fifo_replace0 = 1'd0; +reg [7:0] pcie_dma0_writer_fifo_produce0 = 8'd0; +reg [7:0] pcie_dma0_writer_fifo_consume0 = 8'd0; +reg [7:0] pcie_dma0_writer_fifo_wrport_adr0 = 8'd0; +wire [65:0] pcie_dma0_writer_fifo_wrport_dat_r0; +wire pcie_dma0_writer_fifo_wrport_we0; +wire [65:0] pcie_dma0_writer_fifo_wrport_dat_w0; +wire pcie_dma0_writer_fifo_do_read0; +wire [7:0] pcie_dma0_writer_fifo_rdport_adr0; +wire [65:0] pcie_dma0_writer_fifo_rdport_dat_r0; +wire [31:0] pcie_dma0_writer_fifo_fifo_in_payload_address; +wire [23:0] pcie_dma0_writer_fifo_fifo_in_payload_length; +wire [7:0] pcie_dma0_writer_fifo_fifo_in_payload_control; +wire pcie_dma0_writer_fifo_fifo_in_first; +wire pcie_dma0_writer_fifo_fifo_in_last; +wire [31:0] pcie_dma0_writer_fifo_fifo_out_payload_address; +wire [23:0] pcie_dma0_writer_fifo_fifo_out_payload_length; +wire [7:0] pcie_dma0_writer_fifo_fifo_out_payload_control; +wire pcie_dma0_writer_fifo_fifo_out_first; +wire pcie_dma0_writer_fifo_fifo_out_last; +wire pcie_dma0_writer_fifo_reset; +reg pcie_dma0_writer_loop_first = 1'd1; +reg [7:0] pcie_dma0_writer_loop_index = 8'd0; +reg [15:0] pcie_dma0_writer_loop_count = 16'd0; +wire pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_valid; +reg pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_ready = 1'd0; +wire pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_first; +wire pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_last; +wire [31:0] pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_payload_address; +wire [23:0] pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_payload_length; +wire [7:0] pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_payload_control; +reg pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_valid = 1'd0; +wire pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_ready; +reg pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_first = 1'd0; +reg pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_last = 1'd0; +wire [31:0] pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_payload_address; +reg [23:0] pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_payload_length = 24'd0; +wire [7:0] pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_payload_control; +wire [7:0] pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_payload_user_id; +reg pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_end = 1'd0; +reg [31:0] pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_offset = 32'd0; +reg [31:0] pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_user_id = 32'd0; +wire pcie_dma0_writer_splitter_reset; +wire pcie_dma0_writer_splitter_bufferizeendpoints_sink_valid; +wire pcie_dma0_writer_splitter_bufferizeendpoints_sink_ready; +wire pcie_dma0_writer_splitter_bufferizeendpoints_sink_first; +wire pcie_dma0_writer_splitter_bufferizeendpoints_sink_last; +wire [31:0] pcie_dma0_writer_splitter_bufferizeendpoints_sink_payload_address; +wire [23:0] pcie_dma0_writer_splitter_bufferizeendpoints_sink_payload_length; +wire [7:0] pcie_dma0_writer_splitter_bufferizeendpoints_sink_payload_control; +wire [7:0] pcie_dma0_writer_splitter_bufferizeendpoints_sink_payload_user_id; +reg pcie_dma0_writer_splitter_bufferizeendpoints_source_valid = 1'd0; +reg pcie_dma0_writer_splitter_bufferizeendpoints_source_ready = 1'd0; +reg pcie_dma0_writer_splitter_bufferizeendpoints_source_first = 1'd0; +reg pcie_dma0_writer_splitter_bufferizeendpoints_source_last = 1'd0; +reg [31:0] pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_address = 32'd0; +reg [23:0] pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_length = 24'd0; +reg [7:0] pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_control = 8'd0; +reg [7:0] pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_user_id = 8'd0; +reg pcie_dma0_writer_fifo_re = 1'd0; +reg pcie_dma0_writer_fifo_readable = 1'd0; +wire pcie_dma0_writer_fifo_syncfifo_we1; +wire pcie_dma0_writer_fifo_syncfifo_writable1; +wire pcie_dma0_writer_fifo_syncfifo_re1; +wire pcie_dma0_writer_fifo_syncfifo_readable1; +wire [64:0] pcie_dma0_writer_fifo_syncfifo_din1; +wire [64:0] pcie_dma0_writer_fifo_syncfifo_dout1; +reg [8:0] pcie_dma0_writer_fifo_level1 = 9'd0; +reg pcie_dma0_writer_fifo_replace1 = 1'd0; +reg [7:0] pcie_dma0_writer_fifo_produce1 = 8'd0; +reg [7:0] pcie_dma0_writer_fifo_consume1 = 8'd0; +reg [7:0] pcie_dma0_writer_fifo_wrport_adr1 = 8'd0; +wire [64:0] pcie_dma0_writer_fifo_wrport_dat_r1; +wire pcie_dma0_writer_fifo_wrport_we1; +wire [64:0] pcie_dma0_writer_fifo_wrport_dat_w1; +wire pcie_dma0_writer_fifo_do_read1; +wire [7:0] pcie_dma0_writer_fifo_rdport_adr1; +wire [64:0] pcie_dma0_writer_fifo_rdport_dat_r1; +wire pcie_dma0_writer_fifo_rdport_re; +wire [8:0] pcie_dma0_writer_fifo_level2; +wire pcie_dma0_writer_resetinserter_reset; +reg pcie_dma0_litepciemasterinternalport1_sink_valid = 1'd0; +reg pcie_dma0_litepciemasterinternalport1_sink_ready = 1'd0; +wire pcie_dma0_litepciemasterinternalport1_sink_first; +wire pcie_dma0_litepciemasterinternalport1_sink_last; +wire pcie_dma0_litepciemasterinternalport1_sink_payload_we; +wire [31:0] pcie_dma0_litepciemasterinternalport1_sink_payload_adr; +wire [9:0] pcie_dma0_litepciemasterinternalport1_sink_payload_len; +wire [15:0] pcie_dma0_litepciemasterinternalport1_sink_payload_req_id; +reg [7:0] pcie_dma0_litepciemasterinternalport1_sink_payload_tag = 8'd0; +wire [63:0] pcie_dma0_litepciemasterinternalport1_sink_payload_dat; +wire [7:0] pcie_dma0_litepciemasterinternalport1_sink_payload_channel; +wire [7:0] pcie_dma0_litepciemasterinternalport1_sink_payload_user_id; +reg pcie_dma0_litepciemasterinternalport1_source_valid = 1'd0; +wire pcie_dma0_litepciemasterinternalport1_source_ready; +reg pcie_dma0_litepciemasterinternalport1_source_first = 1'd0; +reg pcie_dma0_litepciemasterinternalport1_source_last = 1'd0; +reg [31:0] pcie_dma0_litepciemasterinternalport1_source_payload_adr = 32'd0; +reg [9:0] pcie_dma0_litepciemasterinternalport1_source_payload_len = 10'd0; +reg pcie_dma0_litepciemasterinternalport1_source_payload_end = 1'd0; +reg [15:0] pcie_dma0_litepciemasterinternalport1_source_payload_req_id = 16'd0; +reg [15:0] pcie_dma0_litepciemasterinternalport1_source_payload_cmp_id = 16'd0; +reg pcie_dma0_litepciemasterinternalport1_source_payload_err = 1'd0; +reg [7:0] pcie_dma0_litepciemasterinternalport1_source_payload_tag = 8'd0; +reg [63:0] pcie_dma0_litepciemasterinternalport1_source_payload_dat = 64'd0; +reg [7:0] pcie_dma0_litepciemasterinternalport1_source_payload_channel = 8'd0; +reg [7:0] pcie_dma0_litepciemasterinternalport1_source_payload_user_id = 8'd0; +wire pcie_dma0_reader_source_source_valid0; +wire pcie_dma0_reader_source_source_ready0; +wire pcie_dma0_reader_source_source_first0; +wire pcie_dma0_reader_source_source_last0; +wire [63:0] pcie_dma0_reader_source_source_payload_data; +wire pcie_dma0_reader_irq; +reg pcie_dma0_reader_enable_storage = 1'd0; +reg pcie_dma0_reader_enable_re = 1'd0; +reg [10:0] pcie_dma0_reader_pending_words = 11'd0; +reg [10:0] pcie_dma0_reader_pending_words_queue = 11'd0; +reg [10:0] pcie_dma0_reader_pending_words_dequeue = 11'd0; +wire pcie_dma0_reader_source_source_valid1; +wire pcie_dma0_reader_source_source_ready1; +wire pcie_dma0_reader_source_source_first1; +reg pcie_dma0_reader_source_source_last1 = 1'd0; +wire [31:0] pcie_dma0_reader_source_source_payload_address; +wire [23:0] pcie_dma0_reader_source_source_payload_length; +wire [7:0] pcie_dma0_reader_source_source_payload_control; +wire [31:0] pcie_dma0_reader_address; +wire [23:0] pcie_dma0_reader_length; +wire pcie_dma0_reader_irq_disable; +wire pcie_dma0_reader_last_disable; +reg [57:0] pcie_dma0_reader_value_storage = 58'd0; +reg pcie_dma0_reader_value_re = 1'd0; +reg pcie_dma0_reader_we_storage = 1'd0; +reg pcie_dma0_reader_we_re = 1'd0; +reg pcie_dma0_reader_loop_prog_n_storage = 1'd0; +reg pcie_dma0_reader_loop_prog_n_re = 1'd0; +reg [15:0] pcie_dma0_reader_index = 16'd0; +reg [15:0] pcie_dma0_reader_count = 16'd0; +reg [31:0] pcie_dma0_reader_loop_status_status = 32'd0; +wire pcie_dma0_reader_loop_status_we; +wire pcie_dma0_reader_loop_status_re; +wire [8:0] pcie_dma0_reader_level_status; +wire pcie_dma0_reader_level_we; +wire pcie_dma0_reader_level_re; +reg pcie_dma0_reader_flush_storage = 1'd0; +reg pcie_dma0_reader_flush_re = 1'd0; +reg pcie_dma0_reader_fifo_sink_valid0 = 1'd0; +wire pcie_dma0_reader_fifo_sink_ready0; +reg pcie_dma0_reader_fifo_sink_first0 = 1'd0; +reg pcie_dma0_reader_fifo_sink_last0 = 1'd0; +reg [31:0] pcie_dma0_reader_fifo_sink_payload_address = 32'd0; +reg [23:0] pcie_dma0_reader_fifo_sink_payload_length = 24'd0; +reg [7:0] pcie_dma0_reader_fifo_sink_payload_control = 8'd0; +wire pcie_dma0_reader_fifo_source_valid0; +wire pcie_dma0_reader_fifo_source_ready0; +wire pcie_dma0_reader_fifo_source_first0; +wire pcie_dma0_reader_fifo_source_last0; +wire [31:0] pcie_dma0_reader_fifo_source_payload_address; +wire [23:0] pcie_dma0_reader_fifo_source_payload_length; +wire [7:0] pcie_dma0_reader_fifo_source_payload_control; +wire pcie_dma0_reader_fifo_syncfifo_we0; +wire pcie_dma0_reader_fifo_syncfifo_writable0; +wire pcie_dma0_reader_fifo_syncfifo_re0; +wire pcie_dma0_reader_fifo_syncfifo_readable0; +wire [65:0] pcie_dma0_reader_fifo_syncfifo_din0; +wire [65:0] pcie_dma0_reader_fifo_syncfifo_dout0; +reg [8:0] pcie_dma0_reader_fifo_level0 = 9'd0; +reg pcie_dma0_reader_fifo_replace0 = 1'd0; +reg [7:0] pcie_dma0_reader_fifo_produce0 = 8'd0; +reg [7:0] pcie_dma0_reader_fifo_consume0 = 8'd0; +reg [7:0] pcie_dma0_reader_fifo_wrport_adr0 = 8'd0; +wire [65:0] pcie_dma0_reader_fifo_wrport_dat_r0; +wire pcie_dma0_reader_fifo_wrport_we0; +wire [65:0] pcie_dma0_reader_fifo_wrport_dat_w0; +wire pcie_dma0_reader_fifo_do_read0; +wire [7:0] pcie_dma0_reader_fifo_rdport_adr0; +wire [65:0] pcie_dma0_reader_fifo_rdport_dat_r0; +wire [31:0] pcie_dma0_reader_fifo_fifo_in_payload_address; +wire [23:0] pcie_dma0_reader_fifo_fifo_in_payload_length; +wire [7:0] pcie_dma0_reader_fifo_fifo_in_payload_control; +wire pcie_dma0_reader_fifo_fifo_in_first0; +wire pcie_dma0_reader_fifo_fifo_in_last0; +wire [31:0] pcie_dma0_reader_fifo_fifo_out_payload_address; +wire [23:0] pcie_dma0_reader_fifo_fifo_out_payload_length; +wire [7:0] pcie_dma0_reader_fifo_fifo_out_payload_control; +wire pcie_dma0_reader_fifo_fifo_out_first0; +wire pcie_dma0_reader_fifo_fifo_out_last0; +wire pcie_dma0_reader_fifo_reset0; +reg pcie_dma0_reader_loop_first = 1'd1; +reg [7:0] pcie_dma0_reader_loop_index = 8'd0; +reg [15:0] pcie_dma0_reader_loop_count = 16'd0; +wire pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_valid; +reg pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_ready = 1'd0; +wire pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_first; +wire pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_last; +wire [31:0] pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_payload_address; +wire [23:0] pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_payload_length; +wire [7:0] pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_payload_control; +reg pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_valid = 1'd0; +wire pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_ready; +reg pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_first = 1'd0; +reg pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_last = 1'd0; +wire [31:0] pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_payload_address; +reg [23:0] pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_payload_length = 24'd0; +wire [7:0] pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_payload_control; +wire [7:0] pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_payload_user_id; +reg pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_end = 1'd0; +reg [31:0] pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_offset = 32'd0; +reg [31:0] pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_user_id = 32'd0; +wire pcie_dma0_reader_splitter_reset; +wire pcie_dma0_reader_splitter_bufferizeendpoints_sink_valid; +wire pcie_dma0_reader_splitter_bufferizeendpoints_sink_ready; +wire pcie_dma0_reader_splitter_bufferizeendpoints_sink_first; +wire pcie_dma0_reader_splitter_bufferizeendpoints_sink_last; +wire [31:0] pcie_dma0_reader_splitter_bufferizeendpoints_sink_payload_address; +wire [23:0] pcie_dma0_reader_splitter_bufferizeendpoints_sink_payload_length; +wire [7:0] pcie_dma0_reader_splitter_bufferizeendpoints_sink_payload_control; +wire [7:0] pcie_dma0_reader_splitter_bufferizeendpoints_sink_payload_user_id; +reg pcie_dma0_reader_splitter_bufferizeendpoints_source_valid = 1'd0; +reg pcie_dma0_reader_splitter_bufferizeendpoints_source_ready = 1'd0; +reg pcie_dma0_reader_splitter_bufferizeendpoints_source_first = 1'd0; +reg pcie_dma0_reader_splitter_bufferizeendpoints_source_last = 1'd0; +reg [31:0] pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_address = 32'd0; +reg [23:0] pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_length = 24'd0; +reg [7:0] pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_control = 8'd0; +reg [7:0] pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_user_id = 8'd0; +wire pcie_dma0_reader_fifo_sink_valid1; +wire pcie_dma0_reader_fifo_sink_ready1; +wire pcie_dma0_reader_fifo_sink_first1; +reg pcie_dma0_reader_fifo_sink_last1 = 1'd0; +wire [63:0] pcie_dma0_reader_fifo_sink_payload_data; +wire pcie_dma0_reader_fifo_source_valid1; +wire pcie_dma0_reader_fifo_source_ready1; +wire pcie_dma0_reader_fifo_source_first1; +wire pcie_dma0_reader_fifo_source_last1; +wire [63:0] pcie_dma0_reader_fifo_source_payload_data; +wire pcie_dma0_reader_fifo_re; +reg pcie_dma0_reader_fifo_readable = 1'd0; +wire pcie_dma0_reader_fifo_syncfifo_we1; +wire pcie_dma0_reader_fifo_syncfifo_writable1; +wire pcie_dma0_reader_fifo_syncfifo_re1; +wire pcie_dma0_reader_fifo_syncfifo_readable1; +wire [65:0] pcie_dma0_reader_fifo_syncfifo_din1; +wire [65:0] pcie_dma0_reader_fifo_syncfifo_dout1; +reg [10:0] pcie_dma0_reader_fifo_level1 = 11'd0; +reg pcie_dma0_reader_fifo_replace1 = 1'd0; +reg [9:0] pcie_dma0_reader_fifo_produce1 = 10'd0; +reg [9:0] pcie_dma0_reader_fifo_consume1 = 10'd0; +reg [9:0] pcie_dma0_reader_fifo_wrport_adr1 = 10'd0; +wire [65:0] pcie_dma0_reader_fifo_wrport_dat_r1; +wire pcie_dma0_reader_fifo_wrport_we1; +wire [65:0] pcie_dma0_reader_fifo_wrport_dat_w1; +wire pcie_dma0_reader_fifo_do_read1; +wire [9:0] pcie_dma0_reader_fifo_rdport_adr1; +wire [65:0] pcie_dma0_reader_fifo_rdport_dat_r1; +wire pcie_dma0_reader_fifo_rdport_re; +wire [10:0] pcie_dma0_reader_fifo_level2; +wire [63:0] pcie_dma0_reader_fifo_fifo_in_payload_data; +wire pcie_dma0_reader_fifo_fifo_in_first1; +wire pcie_dma0_reader_fifo_fifo_in_last1; +wire [63:0] pcie_dma0_reader_fifo_fifo_out_payload_data; +wire pcie_dma0_reader_fifo_fifo_out_first1; +wire pcie_dma0_reader_fifo_fifo_out_last1; +wire pcie_dma0_reader_fifo_reset1; +reg [7:0] pcie_dma0_reader_last_user_id = 8'd255; +reg pcie_dma0_loopback_storage = 1'd0; +reg pcie_dma0_loopback_re = 1'd0; +wire pcie_dma0_loopback_sink_valid; +reg pcie_dma0_loopback_sink_ready = 1'd0; +wire pcie_dma0_loopback_sink_first; +wire pcie_dma0_loopback_sink_last; +wire [63:0] pcie_dma0_loopback_sink_payload_data; +reg pcie_dma0_loopback_source_valid = 1'd0; +wire pcie_dma0_loopback_source_ready; +reg pcie_dma0_loopback_source_first = 1'd0; +reg pcie_dma0_loopback_source_last = 1'd0; +reg [63:0] pcie_dma0_loopback_source_payload_data = 64'd0; +reg pcie_dma0_loopback_next_source_valid = 1'd0; +wire pcie_dma0_loopback_next_source_ready; +reg pcie_dma0_loopback_next_source_first = 1'd0; +reg pcie_dma0_loopback_next_source_last = 1'd0; +reg [63:0] pcie_dma0_loopback_next_source_payload_data = 64'd0; +wire pcie_dma0_loopback_next_sink_valid; +reg pcie_dma0_loopback_next_sink_ready = 1'd0; +wire pcie_dma0_loopback_next_sink_first; +wire pcie_dma0_loopback_next_sink_last; +wire [63:0] pcie_dma0_loopback_next_sink_payload_data; +wire pcie_dma0_buffering_sink_sink_valid; +reg pcie_dma0_buffering_sink_sink_ready = 1'd0; +wire pcie_dma0_buffering_sink_sink_first; +wire pcie_dma0_buffering_sink_sink_last; +wire [63:0] pcie_dma0_buffering_sink_sink_payload_data; +wire pcie_dma0_buffering_source_source_valid; +wire pcie_dma0_buffering_source_source_ready; +wire pcie_dma0_buffering_source_source_first; +wire pcie_dma0_buffering_source_source_last; +wire [63:0] pcie_dma0_buffering_source_source_payload_data; +wire pcie_dma0_buffering_next_source_valid; +reg pcie_dma0_buffering_next_source_ready = 1'd0; +wire pcie_dma0_buffering_next_source_first; +wire pcie_dma0_buffering_next_source_last; +wire [63:0] pcie_dma0_buffering_next_source_payload_data; +reg pcie_dma0_buffering_next_sink_valid = 1'd0; +reg pcie_dma0_buffering_next_sink_ready = 1'd0; +reg pcie_dma0_buffering_next_sink_first = 1'd0; +reg pcie_dma0_buffering_next_sink_last = 1'd0; +reg [63:0] pcie_dma0_buffering_next_sink_payload_data = 64'd0; +reg [10:0] pcie_dma0_buffering_reader_fifo_depth_storage = 11'd1024; +reg pcie_dma0_buffering_reader_fifo_depth_re = 1'd0; +wire [10:0] pcie_dma0_buffering_reader_fifo_level_status; +wire pcie_dma0_buffering_reader_fifo_level_we; +wire pcie_dma0_buffering_reader_fifo_level_re; +reg [10:0] pcie_dma0_buffering_writer_fifo_depth_storage = 11'd1024; +reg pcie_dma0_buffering_writer_fifo_depth_re = 1'd0; +wire [10:0] pcie_dma0_buffering_writer_fifo_level_status; +wire pcie_dma0_buffering_writer_fifo_level_we; +wire pcie_dma0_buffering_writer_fifo_level_re; +reg pcie_dma0_buffering_reader_fifo_sink_valid = 1'd0; +wire pcie_dma0_buffering_reader_fifo_sink_ready; +wire pcie_dma0_buffering_reader_fifo_sink_first; +wire pcie_dma0_buffering_reader_fifo_sink_last; +wire [63:0] pcie_dma0_buffering_reader_fifo_sink_payload_data; +wire pcie_dma0_buffering_reader_fifo_source_valid; +wire pcie_dma0_buffering_reader_fifo_source_ready; +wire pcie_dma0_buffering_reader_fifo_source_first; +wire pcie_dma0_buffering_reader_fifo_source_last; +wire [63:0] pcie_dma0_buffering_reader_fifo_source_payload_data; +wire pcie_dma0_buffering_reader_fifo_re; +reg pcie_dma0_buffering_reader_fifo_readable = 1'd0; +wire pcie_dma0_buffering_reader_fifo_syncfifo_we; +wire pcie_dma0_buffering_reader_fifo_syncfifo_writable; +wire pcie_dma0_buffering_reader_fifo_syncfifo_re; +wire pcie_dma0_buffering_reader_fifo_syncfifo_readable; +wire [65:0] pcie_dma0_buffering_reader_fifo_syncfifo_din; +wire [65:0] pcie_dma0_buffering_reader_fifo_syncfifo_dout; +reg [7:0] pcie_dma0_buffering_reader_fifo_level0 = 8'd0; +reg pcie_dma0_buffering_reader_fifo_replace = 1'd0; +reg [6:0] pcie_dma0_buffering_reader_fifo_produce = 7'd0; +reg [6:0] pcie_dma0_buffering_reader_fifo_consume = 7'd0; +reg [6:0] pcie_dma0_buffering_reader_fifo_wrport_adr = 7'd0; +wire [65:0] pcie_dma0_buffering_reader_fifo_wrport_dat_r; +wire pcie_dma0_buffering_reader_fifo_wrport_we; +wire [65:0] pcie_dma0_buffering_reader_fifo_wrport_dat_w; +wire pcie_dma0_buffering_reader_fifo_do_read; +wire [6:0] pcie_dma0_buffering_reader_fifo_rdport_adr; +wire [65:0] pcie_dma0_buffering_reader_fifo_rdport_dat_r; +wire pcie_dma0_buffering_reader_fifo_rdport_re; +wire [7:0] pcie_dma0_buffering_reader_fifo_level1; +wire [63:0] pcie_dma0_buffering_reader_fifo_fifo_in_payload_data; +wire pcie_dma0_buffering_reader_fifo_fifo_in_first; +wire pcie_dma0_buffering_reader_fifo_fifo_in_last; +wire [63:0] pcie_dma0_buffering_reader_fifo_fifo_out_payload_data; +wire pcie_dma0_buffering_reader_fifo_fifo_out_first; +wire pcie_dma0_buffering_reader_fifo_fifo_out_last; +reg pcie_dma0_buffering_writer_fifo_sink_valid = 1'd0; +wire pcie_dma0_buffering_writer_fifo_sink_ready; +wire pcie_dma0_buffering_writer_fifo_sink_first; +wire pcie_dma0_buffering_writer_fifo_sink_last; +wire [63:0] pcie_dma0_buffering_writer_fifo_sink_payload_data; +wire pcie_dma0_buffering_writer_fifo_source_valid; +wire pcie_dma0_buffering_writer_fifo_source_ready; +wire pcie_dma0_buffering_writer_fifo_source_first; +wire pcie_dma0_buffering_writer_fifo_source_last; +wire [63:0] pcie_dma0_buffering_writer_fifo_source_payload_data; +wire pcie_dma0_buffering_writer_fifo_re; +reg pcie_dma0_buffering_writer_fifo_readable = 1'd0; +wire pcie_dma0_buffering_writer_fifo_syncfifo_we; +wire pcie_dma0_buffering_writer_fifo_syncfifo_writable; +wire pcie_dma0_buffering_writer_fifo_syncfifo_re; +wire pcie_dma0_buffering_writer_fifo_syncfifo_readable; +wire [65:0] pcie_dma0_buffering_writer_fifo_syncfifo_din; +wire [65:0] pcie_dma0_buffering_writer_fifo_syncfifo_dout; +reg [7:0] pcie_dma0_buffering_writer_fifo_level0 = 8'd0; +reg pcie_dma0_buffering_writer_fifo_replace = 1'd0; +reg [6:0] pcie_dma0_buffering_writer_fifo_produce = 7'd0; +reg [6:0] pcie_dma0_buffering_writer_fifo_consume = 7'd0; +reg [6:0] pcie_dma0_buffering_writer_fifo_wrport_adr = 7'd0; +wire [65:0] pcie_dma0_buffering_writer_fifo_wrport_dat_r; +wire pcie_dma0_buffering_writer_fifo_wrport_we; +wire [65:0] pcie_dma0_buffering_writer_fifo_wrport_dat_w; +wire pcie_dma0_buffering_writer_fifo_do_read; +wire [6:0] pcie_dma0_buffering_writer_fifo_rdport_adr; +wire [65:0] pcie_dma0_buffering_writer_fifo_rdport_dat_r; +wire pcie_dma0_buffering_writer_fifo_rdport_re; +wire [7:0] pcie_dma0_buffering_writer_fifo_level1; +wire [63:0] pcie_dma0_buffering_writer_fifo_fifo_in_payload_data; +wire pcie_dma0_buffering_writer_fifo_fifo_in_first; +wire pcie_dma0_buffering_writer_fifo_fifo_in_last; +wire [63:0] pcie_dma0_buffering_writer_fifo_fifo_out_payload_data; +wire pcie_dma0_buffering_writer_fifo_fifo_out_first; +wire pcie_dma0_buffering_writer_fifo_fifo_out_last; +reg pcie_dma1_litepciemasterinternalport0_sink_valid = 1'd0; +reg pcie_dma1_litepciemasterinternalport0_sink_ready = 1'd0; +wire pcie_dma1_litepciemasterinternalport0_sink_first; +wire pcie_dma1_litepciemasterinternalport0_sink_last; +wire pcie_dma1_litepciemasterinternalport0_sink_payload_we; +wire [31:0] pcie_dma1_litepciemasterinternalport0_sink_payload_adr; +wire [9:0] pcie_dma1_litepciemasterinternalport0_sink_payload_len; +wire [15:0] pcie_dma1_litepciemasterinternalport0_sink_payload_req_id; +wire [7:0] pcie_dma1_litepciemasterinternalport0_sink_payload_tag; +wire [63:0] pcie_dma1_litepciemasterinternalport0_sink_payload_dat; +wire [7:0] pcie_dma1_litepciemasterinternalport0_sink_payload_channel; +wire [7:0] pcie_dma1_litepciemasterinternalport0_sink_payload_user_id; +reg pcie_dma1_litepciemasterinternalport0_source_valid = 1'd0; +reg pcie_dma1_litepciemasterinternalport0_source_ready = 1'd0; +reg pcie_dma1_litepciemasterinternalport0_source_first = 1'd0; +reg pcie_dma1_litepciemasterinternalport0_source_last = 1'd0; +reg [31:0] pcie_dma1_litepciemasterinternalport0_source_payload_adr = 32'd0; +reg [9:0] pcie_dma1_litepciemasterinternalport0_source_payload_len = 10'd0; +reg pcie_dma1_litepciemasterinternalport0_source_payload_end = 1'd0; +reg [15:0] pcie_dma1_litepciemasterinternalport0_source_payload_req_id = 16'd0; +reg [15:0] pcie_dma1_litepciemasterinternalport0_source_payload_cmp_id = 16'd0; +reg pcie_dma1_litepciemasterinternalport0_source_payload_err = 1'd0; +reg [7:0] pcie_dma1_litepciemasterinternalport0_source_payload_tag = 8'd0; +reg [63:0] pcie_dma1_litepciemasterinternalport0_source_payload_dat = 64'd0; +reg [7:0] pcie_dma1_litepciemasterinternalport0_source_payload_channel = 8'd0; +reg [7:0] pcie_dma1_litepciemasterinternalport0_source_payload_user_id = 8'd0; +wire pcie_dma1_writer_sink_valid; +wire pcie_dma1_writer_sink_ready; +wire pcie_dma1_writer_sink_first; +wire pcie_dma1_writer_sink_last; +wire [63:0] pcie_dma1_writer_sink_payload_data; +wire pcie_dma1_writer_irq; +reg pcie_dma1_writer_enable_storage = 1'd0; +reg pcie_dma1_writer_enable_re = 1'd0; +reg [12:0] pcie_dma1_writer_counter = 13'd0; +wire pcie_dma1_writer_source_source_valid; +wire pcie_dma1_writer_source_source_ready; +wire pcie_dma1_writer_source_source_first; +reg pcie_dma1_writer_source_source_last = 1'd0; +wire [31:0] pcie_dma1_writer_source_source_payload_address; +wire [23:0] pcie_dma1_writer_source_source_payload_length; +wire [7:0] pcie_dma1_writer_source_source_payload_control; +wire [31:0] pcie_dma1_writer_address; +wire [23:0] pcie_dma1_writer_length; +wire pcie_dma1_writer_irq_disable; +wire pcie_dma1_writer_last_disable; +reg [57:0] pcie_dma1_writer_value_storage = 58'd0; +reg pcie_dma1_writer_value_re = 1'd0; +reg pcie_dma1_writer_we_storage = 1'd0; +reg pcie_dma1_writer_we_re = 1'd0; +reg pcie_dma1_writer_loop_prog_n_storage = 1'd0; +reg pcie_dma1_writer_loop_prog_n_re = 1'd0; +reg [15:0] pcie_dma1_writer_index = 16'd0; +reg [15:0] pcie_dma1_writer_count = 16'd0; +reg [31:0] pcie_dma1_writer_loop_status_status = 32'd0; +wire pcie_dma1_writer_loop_status_we; +wire pcie_dma1_writer_loop_status_re; +wire [8:0] pcie_dma1_writer_level_status; +wire pcie_dma1_writer_level_we; +wire pcie_dma1_writer_level_re; +reg pcie_dma1_writer_flush_storage = 1'd0; +reg pcie_dma1_writer_flush_re = 1'd0; +reg pcie_dma1_writer_fifo_sink_valid = 1'd0; +wire pcie_dma1_writer_fifo_sink_ready; +reg pcie_dma1_writer_fifo_sink_first = 1'd0; +reg pcie_dma1_writer_fifo_sink_last = 1'd0; +reg [31:0] pcie_dma1_writer_fifo_sink_payload_address = 32'd0; +reg [23:0] pcie_dma1_writer_fifo_sink_payload_length = 24'd0; +reg [7:0] pcie_dma1_writer_fifo_sink_payload_control = 8'd0; +wire pcie_dma1_writer_fifo_source_valid; +wire pcie_dma1_writer_fifo_source_ready; +wire pcie_dma1_writer_fifo_source_first; +wire pcie_dma1_writer_fifo_source_last; +wire [31:0] pcie_dma1_writer_fifo_source_payload_address; +wire [23:0] pcie_dma1_writer_fifo_source_payload_length; +wire [7:0] pcie_dma1_writer_fifo_source_payload_control; +wire pcie_dma1_writer_fifo_syncfifo_we0; +wire pcie_dma1_writer_fifo_syncfifo_writable0; +wire pcie_dma1_writer_fifo_syncfifo_re0; +wire pcie_dma1_writer_fifo_syncfifo_readable0; +wire [65:0] pcie_dma1_writer_fifo_syncfifo_din0; +wire [65:0] pcie_dma1_writer_fifo_syncfifo_dout0; +reg [8:0] pcie_dma1_writer_fifo_level0 = 9'd0; +reg pcie_dma1_writer_fifo_replace0 = 1'd0; +reg [7:0] pcie_dma1_writer_fifo_produce0 = 8'd0; +reg [7:0] pcie_dma1_writer_fifo_consume0 = 8'd0; +reg [7:0] pcie_dma1_writer_fifo_wrport_adr0 = 8'd0; +wire [65:0] pcie_dma1_writer_fifo_wrport_dat_r0; +wire pcie_dma1_writer_fifo_wrport_we0; +wire [65:0] pcie_dma1_writer_fifo_wrport_dat_w0; +wire pcie_dma1_writer_fifo_do_read0; +wire [7:0] pcie_dma1_writer_fifo_rdport_adr0; +wire [65:0] pcie_dma1_writer_fifo_rdport_dat_r0; +wire [31:0] pcie_dma1_writer_fifo_fifo_in_payload_address; +wire [23:0] pcie_dma1_writer_fifo_fifo_in_payload_length; +wire [7:0] pcie_dma1_writer_fifo_fifo_in_payload_control; +wire pcie_dma1_writer_fifo_fifo_in_first; +wire pcie_dma1_writer_fifo_fifo_in_last; +wire [31:0] pcie_dma1_writer_fifo_fifo_out_payload_address; +wire [23:0] pcie_dma1_writer_fifo_fifo_out_payload_length; +wire [7:0] pcie_dma1_writer_fifo_fifo_out_payload_control; +wire pcie_dma1_writer_fifo_fifo_out_first; +wire pcie_dma1_writer_fifo_fifo_out_last; +wire pcie_dma1_writer_fifo_reset; +reg pcie_dma1_writer_loop_first = 1'd1; +reg [7:0] pcie_dma1_writer_loop_index = 8'd0; +reg [15:0] pcie_dma1_writer_loop_count = 16'd0; +wire pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_valid; +reg pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_ready = 1'd0; +wire pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_first; +wire pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_last; +wire [31:0] pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_payload_address; +wire [23:0] pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_payload_length; +wire [7:0] pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_payload_control; +reg pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_valid = 1'd0; +wire pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_ready; +reg pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_first = 1'd0; +reg pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_last = 1'd0; +wire [31:0] pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_payload_address; +reg [23:0] pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_payload_length = 24'd0; +wire [7:0] pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_payload_control; +wire [7:0] pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_payload_user_id; +reg pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_end = 1'd0; +reg [31:0] pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_offset = 32'd0; +reg [31:0] pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_user_id = 32'd0; +wire pcie_dma1_writer_splitter_reset; +wire pcie_dma1_writer_splitter_bufferizeendpoints_sink_valid; +wire pcie_dma1_writer_splitter_bufferizeendpoints_sink_ready; +wire pcie_dma1_writer_splitter_bufferizeendpoints_sink_first; +wire pcie_dma1_writer_splitter_bufferizeendpoints_sink_last; +wire [31:0] pcie_dma1_writer_splitter_bufferizeendpoints_sink_payload_address; +wire [23:0] pcie_dma1_writer_splitter_bufferizeendpoints_sink_payload_length; +wire [7:0] pcie_dma1_writer_splitter_bufferizeendpoints_sink_payload_control; +wire [7:0] pcie_dma1_writer_splitter_bufferizeendpoints_sink_payload_user_id; +reg pcie_dma1_writer_splitter_bufferizeendpoints_source_valid = 1'd0; +reg pcie_dma1_writer_splitter_bufferizeendpoints_source_ready = 1'd0; +reg pcie_dma1_writer_splitter_bufferizeendpoints_source_first = 1'd0; +reg pcie_dma1_writer_splitter_bufferizeendpoints_source_last = 1'd0; +reg [31:0] pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_address = 32'd0; +reg [23:0] pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_length = 24'd0; +reg [7:0] pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_control = 8'd0; +reg [7:0] pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_user_id = 8'd0; +reg pcie_dma1_writer_fifo_re = 1'd0; +reg pcie_dma1_writer_fifo_readable = 1'd0; +wire pcie_dma1_writer_fifo_syncfifo_we1; +wire pcie_dma1_writer_fifo_syncfifo_writable1; +wire pcie_dma1_writer_fifo_syncfifo_re1; +wire pcie_dma1_writer_fifo_syncfifo_readable1; +wire [64:0] pcie_dma1_writer_fifo_syncfifo_din1; +wire [64:0] pcie_dma1_writer_fifo_syncfifo_dout1; +reg [8:0] pcie_dma1_writer_fifo_level1 = 9'd0; +reg pcie_dma1_writer_fifo_replace1 = 1'd0; +reg [7:0] pcie_dma1_writer_fifo_produce1 = 8'd0; +reg [7:0] pcie_dma1_writer_fifo_consume1 = 8'd0; +reg [7:0] pcie_dma1_writer_fifo_wrport_adr1 = 8'd0; +wire [64:0] pcie_dma1_writer_fifo_wrport_dat_r1; +wire pcie_dma1_writer_fifo_wrport_we1; +wire [64:0] pcie_dma1_writer_fifo_wrport_dat_w1; +wire pcie_dma1_writer_fifo_do_read1; +wire [7:0] pcie_dma1_writer_fifo_rdport_adr1; +wire [64:0] pcie_dma1_writer_fifo_rdport_dat_r1; +wire pcie_dma1_writer_fifo_rdport_re; +wire [8:0] pcie_dma1_writer_fifo_level2; +wire pcie_dma1_writer_resetinserter_reset; +reg pcie_dma1_litepciemasterinternalport1_sink_valid = 1'd0; +reg pcie_dma1_litepciemasterinternalport1_sink_ready = 1'd0; +wire pcie_dma1_litepciemasterinternalport1_sink_first; +wire pcie_dma1_litepciemasterinternalport1_sink_last; +wire pcie_dma1_litepciemasterinternalport1_sink_payload_we; +wire [31:0] pcie_dma1_litepciemasterinternalport1_sink_payload_adr; +wire [9:0] pcie_dma1_litepciemasterinternalport1_sink_payload_len; +wire [15:0] pcie_dma1_litepciemasterinternalport1_sink_payload_req_id; +reg [7:0] pcie_dma1_litepciemasterinternalport1_sink_payload_tag = 8'd0; +wire [63:0] pcie_dma1_litepciemasterinternalport1_sink_payload_dat; +wire [7:0] pcie_dma1_litepciemasterinternalport1_sink_payload_channel; +wire [7:0] pcie_dma1_litepciemasterinternalport1_sink_payload_user_id; +reg pcie_dma1_litepciemasterinternalport1_source_valid = 1'd0; +wire pcie_dma1_litepciemasterinternalport1_source_ready; +reg pcie_dma1_litepciemasterinternalport1_source_first = 1'd0; +reg pcie_dma1_litepciemasterinternalport1_source_last = 1'd0; +reg [31:0] pcie_dma1_litepciemasterinternalport1_source_payload_adr = 32'd0; +reg [9:0] pcie_dma1_litepciemasterinternalport1_source_payload_len = 10'd0; +reg pcie_dma1_litepciemasterinternalport1_source_payload_end = 1'd0; +reg [15:0] pcie_dma1_litepciemasterinternalport1_source_payload_req_id = 16'd0; +reg [15:0] pcie_dma1_litepciemasterinternalport1_source_payload_cmp_id = 16'd0; +reg pcie_dma1_litepciemasterinternalport1_source_payload_err = 1'd0; +reg [7:0] pcie_dma1_litepciemasterinternalport1_source_payload_tag = 8'd0; +reg [63:0] pcie_dma1_litepciemasterinternalport1_source_payload_dat = 64'd0; +reg [7:0] pcie_dma1_litepciemasterinternalport1_source_payload_channel = 8'd0; +reg [7:0] pcie_dma1_litepciemasterinternalport1_source_payload_user_id = 8'd0; +wire pcie_dma1_reader_source_source_valid0; +wire pcie_dma1_reader_source_source_ready0; +wire pcie_dma1_reader_source_source_first0; +wire pcie_dma1_reader_source_source_last0; +wire [63:0] pcie_dma1_reader_source_source_payload_data; +wire pcie_dma1_reader_irq; +reg pcie_dma1_reader_enable_storage = 1'd0; +reg pcie_dma1_reader_enable_re = 1'd0; +reg [10:0] pcie_dma1_reader_pending_words = 11'd0; +reg [10:0] pcie_dma1_reader_pending_words_queue = 11'd0; +reg [10:0] pcie_dma1_reader_pending_words_dequeue = 11'd0; +wire pcie_dma1_reader_source_source_valid1; +wire pcie_dma1_reader_source_source_ready1; +wire pcie_dma1_reader_source_source_first1; +reg pcie_dma1_reader_source_source_last1 = 1'd0; +wire [31:0] pcie_dma1_reader_source_source_payload_address; +wire [23:0] pcie_dma1_reader_source_source_payload_length; +wire [7:0] pcie_dma1_reader_source_source_payload_control; +wire [31:0] pcie_dma1_reader_address; +wire [23:0] pcie_dma1_reader_length; +wire pcie_dma1_reader_irq_disable; +wire pcie_dma1_reader_last_disable; +reg [57:0] pcie_dma1_reader_value_storage = 58'd0; +reg pcie_dma1_reader_value_re = 1'd0; +reg pcie_dma1_reader_we_storage = 1'd0; +reg pcie_dma1_reader_we_re = 1'd0; +reg pcie_dma1_reader_loop_prog_n_storage = 1'd0; +reg pcie_dma1_reader_loop_prog_n_re = 1'd0; +reg [15:0] pcie_dma1_reader_index = 16'd0; +reg [15:0] pcie_dma1_reader_count = 16'd0; +reg [31:0] pcie_dma1_reader_loop_status_status = 32'd0; +wire pcie_dma1_reader_loop_status_we; +wire pcie_dma1_reader_loop_status_re; +wire [8:0] pcie_dma1_reader_level_status; +wire pcie_dma1_reader_level_we; +wire pcie_dma1_reader_level_re; +reg pcie_dma1_reader_flush_storage = 1'd0; +reg pcie_dma1_reader_flush_re = 1'd0; +reg pcie_dma1_reader_fifo_sink_valid0 = 1'd0; +wire pcie_dma1_reader_fifo_sink_ready0; +reg pcie_dma1_reader_fifo_sink_first0 = 1'd0; +reg pcie_dma1_reader_fifo_sink_last0 = 1'd0; +reg [31:0] pcie_dma1_reader_fifo_sink_payload_address = 32'd0; +reg [23:0] pcie_dma1_reader_fifo_sink_payload_length = 24'd0; +reg [7:0] pcie_dma1_reader_fifo_sink_payload_control = 8'd0; +wire pcie_dma1_reader_fifo_source_valid0; +wire pcie_dma1_reader_fifo_source_ready0; +wire pcie_dma1_reader_fifo_source_first0; +wire pcie_dma1_reader_fifo_source_last0; +wire [31:0] pcie_dma1_reader_fifo_source_payload_address; +wire [23:0] pcie_dma1_reader_fifo_source_payload_length; +wire [7:0] pcie_dma1_reader_fifo_source_payload_control; +wire pcie_dma1_reader_fifo_syncfifo_we0; +wire pcie_dma1_reader_fifo_syncfifo_writable0; +wire pcie_dma1_reader_fifo_syncfifo_re0; +wire pcie_dma1_reader_fifo_syncfifo_readable0; +wire [65:0] pcie_dma1_reader_fifo_syncfifo_din0; +wire [65:0] pcie_dma1_reader_fifo_syncfifo_dout0; +reg [8:0] pcie_dma1_reader_fifo_level0 = 9'd0; +reg pcie_dma1_reader_fifo_replace0 = 1'd0; +reg [7:0] pcie_dma1_reader_fifo_produce0 = 8'd0; +reg [7:0] pcie_dma1_reader_fifo_consume0 = 8'd0; +reg [7:0] pcie_dma1_reader_fifo_wrport_adr0 = 8'd0; +wire [65:0] pcie_dma1_reader_fifo_wrport_dat_r0; +wire pcie_dma1_reader_fifo_wrport_we0; +wire [65:0] pcie_dma1_reader_fifo_wrport_dat_w0; +wire pcie_dma1_reader_fifo_do_read0; +wire [7:0] pcie_dma1_reader_fifo_rdport_adr0; +wire [65:0] pcie_dma1_reader_fifo_rdport_dat_r0; +wire [31:0] pcie_dma1_reader_fifo_fifo_in_payload_address; +wire [23:0] pcie_dma1_reader_fifo_fifo_in_payload_length; +wire [7:0] pcie_dma1_reader_fifo_fifo_in_payload_control; +wire pcie_dma1_reader_fifo_fifo_in_first0; +wire pcie_dma1_reader_fifo_fifo_in_last0; +wire [31:0] pcie_dma1_reader_fifo_fifo_out_payload_address; +wire [23:0] pcie_dma1_reader_fifo_fifo_out_payload_length; +wire [7:0] pcie_dma1_reader_fifo_fifo_out_payload_control; +wire pcie_dma1_reader_fifo_fifo_out_first0; +wire pcie_dma1_reader_fifo_fifo_out_last0; +wire pcie_dma1_reader_fifo_reset0; +reg pcie_dma1_reader_loop_first = 1'd1; +reg [7:0] pcie_dma1_reader_loop_index = 8'd0; +reg [15:0] pcie_dma1_reader_loop_count = 16'd0; +wire pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_valid; +reg pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_ready = 1'd0; +wire pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_first; +wire pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_last; +wire [31:0] pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_payload_address; +wire [23:0] pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_payload_length; +wire [7:0] pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_payload_control; +reg pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_valid = 1'd0; +wire pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_ready; +reg pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_first = 1'd0; +reg pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_last = 1'd0; +wire [31:0] pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_payload_address; +reg [23:0] pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_payload_length = 24'd0; +wire [7:0] pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_payload_control; +wire [7:0] pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_payload_user_id; +reg pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_end = 1'd0; +reg [31:0] pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_offset = 32'd0; +reg [31:0] pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_user_id = 32'd0; +wire pcie_dma1_reader_splitter_reset; +wire pcie_dma1_reader_splitter_bufferizeendpoints_sink_valid; +wire pcie_dma1_reader_splitter_bufferizeendpoints_sink_ready; +wire pcie_dma1_reader_splitter_bufferizeendpoints_sink_first; +wire pcie_dma1_reader_splitter_bufferizeendpoints_sink_last; +wire [31:0] pcie_dma1_reader_splitter_bufferizeendpoints_sink_payload_address; +wire [23:0] pcie_dma1_reader_splitter_bufferizeendpoints_sink_payload_length; +wire [7:0] pcie_dma1_reader_splitter_bufferizeendpoints_sink_payload_control; +wire [7:0] pcie_dma1_reader_splitter_bufferizeendpoints_sink_payload_user_id; +reg pcie_dma1_reader_splitter_bufferizeendpoints_source_valid = 1'd0; +reg pcie_dma1_reader_splitter_bufferizeendpoints_source_ready = 1'd0; +reg pcie_dma1_reader_splitter_bufferizeendpoints_source_first = 1'd0; +reg pcie_dma1_reader_splitter_bufferizeendpoints_source_last = 1'd0; +reg [31:0] pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_address = 32'd0; +reg [23:0] pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_length = 24'd0; +reg [7:0] pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_control = 8'd0; +reg [7:0] pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_user_id = 8'd0; +wire pcie_dma1_reader_fifo_sink_valid1; +wire pcie_dma1_reader_fifo_sink_ready1; +wire pcie_dma1_reader_fifo_sink_first1; +reg pcie_dma1_reader_fifo_sink_last1 = 1'd0; +wire [63:0] pcie_dma1_reader_fifo_sink_payload_data; +wire pcie_dma1_reader_fifo_source_valid1; +wire pcie_dma1_reader_fifo_source_ready1; +wire pcie_dma1_reader_fifo_source_first1; +wire pcie_dma1_reader_fifo_source_last1; +wire [63:0] pcie_dma1_reader_fifo_source_payload_data; +wire pcie_dma1_reader_fifo_re; +reg pcie_dma1_reader_fifo_readable = 1'd0; +wire pcie_dma1_reader_fifo_syncfifo_we1; +wire pcie_dma1_reader_fifo_syncfifo_writable1; +wire pcie_dma1_reader_fifo_syncfifo_re1; +wire pcie_dma1_reader_fifo_syncfifo_readable1; +wire [65:0] pcie_dma1_reader_fifo_syncfifo_din1; +wire [65:0] pcie_dma1_reader_fifo_syncfifo_dout1; +reg [10:0] pcie_dma1_reader_fifo_level1 = 11'd0; +reg pcie_dma1_reader_fifo_replace1 = 1'd0; +reg [9:0] pcie_dma1_reader_fifo_produce1 = 10'd0; +reg [9:0] pcie_dma1_reader_fifo_consume1 = 10'd0; +reg [9:0] pcie_dma1_reader_fifo_wrport_adr1 = 10'd0; +wire [65:0] pcie_dma1_reader_fifo_wrport_dat_r1; +wire pcie_dma1_reader_fifo_wrport_we1; +wire [65:0] pcie_dma1_reader_fifo_wrport_dat_w1; +wire pcie_dma1_reader_fifo_do_read1; +wire [9:0] pcie_dma1_reader_fifo_rdport_adr1; +wire [65:0] pcie_dma1_reader_fifo_rdport_dat_r1; +wire pcie_dma1_reader_fifo_rdport_re; +wire [10:0] pcie_dma1_reader_fifo_level2; +wire [63:0] pcie_dma1_reader_fifo_fifo_in_payload_data; +wire pcie_dma1_reader_fifo_fifo_in_first1; +wire pcie_dma1_reader_fifo_fifo_in_last1; +wire [63:0] pcie_dma1_reader_fifo_fifo_out_payload_data; +wire pcie_dma1_reader_fifo_fifo_out_first1; +wire pcie_dma1_reader_fifo_fifo_out_last1; +wire pcie_dma1_reader_fifo_reset1; +reg [7:0] pcie_dma1_reader_last_user_id = 8'd255; +reg pcie_dma1_loopback_storage = 1'd0; +reg pcie_dma1_loopback_re = 1'd0; +wire pcie_dma1_loopback_sink_valid; +reg pcie_dma1_loopback_sink_ready = 1'd0; +wire pcie_dma1_loopback_sink_first; +wire pcie_dma1_loopback_sink_last; +wire [63:0] pcie_dma1_loopback_sink_payload_data; +reg pcie_dma1_loopback_source_valid = 1'd0; +wire pcie_dma1_loopback_source_ready; +reg pcie_dma1_loopback_source_first = 1'd0; +reg pcie_dma1_loopback_source_last = 1'd0; +reg [63:0] pcie_dma1_loopback_source_payload_data = 64'd0; +reg pcie_dma1_loopback_next_source_valid = 1'd0; +wire pcie_dma1_loopback_next_source_ready; +reg pcie_dma1_loopback_next_source_first = 1'd0; +reg pcie_dma1_loopback_next_source_last = 1'd0; +reg [63:0] pcie_dma1_loopback_next_source_payload_data = 64'd0; +wire pcie_dma1_loopback_next_sink_valid; +reg pcie_dma1_loopback_next_sink_ready = 1'd0; +wire pcie_dma1_loopback_next_sink_first; +wire pcie_dma1_loopback_next_sink_last; +wire [63:0] pcie_dma1_loopback_next_sink_payload_data; +wire pcie_dma1_buffering_sink_sink_valid; +reg pcie_dma1_buffering_sink_sink_ready = 1'd0; +wire pcie_dma1_buffering_sink_sink_first; +wire pcie_dma1_buffering_sink_sink_last; +wire [63:0] pcie_dma1_buffering_sink_sink_payload_data; +wire pcie_dma1_buffering_source_source_valid; +wire pcie_dma1_buffering_source_source_ready; +wire pcie_dma1_buffering_source_source_first; +wire pcie_dma1_buffering_source_source_last; +wire [63:0] pcie_dma1_buffering_source_source_payload_data; +wire pcie_dma1_buffering_next_source_valid; +reg pcie_dma1_buffering_next_source_ready = 1'd0; +wire pcie_dma1_buffering_next_source_first; +wire pcie_dma1_buffering_next_source_last; +wire [63:0] pcie_dma1_buffering_next_source_payload_data; +reg pcie_dma1_buffering_next_sink_valid = 1'd0; +reg pcie_dma1_buffering_next_sink_ready = 1'd0; +reg pcie_dma1_buffering_next_sink_first = 1'd0; +reg pcie_dma1_buffering_next_sink_last = 1'd0; +reg [63:0] pcie_dma1_buffering_next_sink_payload_data = 64'd0; +reg [10:0] pcie_dma1_buffering_reader_fifo_depth_storage = 11'd1024; +reg pcie_dma1_buffering_reader_fifo_depth_re = 1'd0; +wire [10:0] pcie_dma1_buffering_reader_fifo_level_status; +wire pcie_dma1_buffering_reader_fifo_level_we; +wire pcie_dma1_buffering_reader_fifo_level_re; +reg [10:0] pcie_dma1_buffering_writer_fifo_depth_storage = 11'd1024; +reg pcie_dma1_buffering_writer_fifo_depth_re = 1'd0; +wire [10:0] pcie_dma1_buffering_writer_fifo_level_status; +wire pcie_dma1_buffering_writer_fifo_level_we; +wire pcie_dma1_buffering_writer_fifo_level_re; +reg pcie_dma1_buffering_reader_fifo_sink_valid = 1'd0; +wire pcie_dma1_buffering_reader_fifo_sink_ready; +wire pcie_dma1_buffering_reader_fifo_sink_first; +wire pcie_dma1_buffering_reader_fifo_sink_last; +wire [63:0] pcie_dma1_buffering_reader_fifo_sink_payload_data; +wire pcie_dma1_buffering_reader_fifo_source_valid; +wire pcie_dma1_buffering_reader_fifo_source_ready; +wire pcie_dma1_buffering_reader_fifo_source_first; +wire pcie_dma1_buffering_reader_fifo_source_last; +wire [63:0] pcie_dma1_buffering_reader_fifo_source_payload_data; +wire pcie_dma1_buffering_reader_fifo_re; +reg pcie_dma1_buffering_reader_fifo_readable = 1'd0; +wire pcie_dma1_buffering_reader_fifo_syncfifo_we; +wire pcie_dma1_buffering_reader_fifo_syncfifo_writable; +wire pcie_dma1_buffering_reader_fifo_syncfifo_re; +wire pcie_dma1_buffering_reader_fifo_syncfifo_readable; +wire [65:0] pcie_dma1_buffering_reader_fifo_syncfifo_din; +wire [65:0] pcie_dma1_buffering_reader_fifo_syncfifo_dout; +reg [7:0] pcie_dma1_buffering_reader_fifo_level0 = 8'd0; +reg pcie_dma1_buffering_reader_fifo_replace = 1'd0; +reg [6:0] pcie_dma1_buffering_reader_fifo_produce = 7'd0; +reg [6:0] pcie_dma1_buffering_reader_fifo_consume = 7'd0; +reg [6:0] pcie_dma1_buffering_reader_fifo_wrport_adr = 7'd0; +wire [65:0] pcie_dma1_buffering_reader_fifo_wrport_dat_r; +wire pcie_dma1_buffering_reader_fifo_wrport_we; +wire [65:0] pcie_dma1_buffering_reader_fifo_wrport_dat_w; +wire pcie_dma1_buffering_reader_fifo_do_read; +wire [6:0] pcie_dma1_buffering_reader_fifo_rdport_adr; +wire [65:0] pcie_dma1_buffering_reader_fifo_rdport_dat_r; +wire pcie_dma1_buffering_reader_fifo_rdport_re; +wire [7:0] pcie_dma1_buffering_reader_fifo_level1; +wire [63:0] pcie_dma1_buffering_reader_fifo_fifo_in_payload_data; +wire pcie_dma1_buffering_reader_fifo_fifo_in_first; +wire pcie_dma1_buffering_reader_fifo_fifo_in_last; +wire [63:0] pcie_dma1_buffering_reader_fifo_fifo_out_payload_data; +wire pcie_dma1_buffering_reader_fifo_fifo_out_first; +wire pcie_dma1_buffering_reader_fifo_fifo_out_last; +reg pcie_dma1_buffering_writer_fifo_sink_valid = 1'd0; +wire pcie_dma1_buffering_writer_fifo_sink_ready; +wire pcie_dma1_buffering_writer_fifo_sink_first; +wire pcie_dma1_buffering_writer_fifo_sink_last; +wire [63:0] pcie_dma1_buffering_writer_fifo_sink_payload_data; +wire pcie_dma1_buffering_writer_fifo_source_valid; +wire pcie_dma1_buffering_writer_fifo_source_ready; +wire pcie_dma1_buffering_writer_fifo_source_first; +wire pcie_dma1_buffering_writer_fifo_source_last; +wire [63:0] pcie_dma1_buffering_writer_fifo_source_payload_data; +wire pcie_dma1_buffering_writer_fifo_re; +reg pcie_dma1_buffering_writer_fifo_readable = 1'd0; +wire pcie_dma1_buffering_writer_fifo_syncfifo_we; +wire pcie_dma1_buffering_writer_fifo_syncfifo_writable; +wire pcie_dma1_buffering_writer_fifo_syncfifo_re; +wire pcie_dma1_buffering_writer_fifo_syncfifo_readable; +wire [65:0] pcie_dma1_buffering_writer_fifo_syncfifo_din; +wire [65:0] pcie_dma1_buffering_writer_fifo_syncfifo_dout; +reg [7:0] pcie_dma1_buffering_writer_fifo_level0 = 8'd0; +reg pcie_dma1_buffering_writer_fifo_replace = 1'd0; +reg [6:0] pcie_dma1_buffering_writer_fifo_produce = 7'd0; +reg [6:0] pcie_dma1_buffering_writer_fifo_consume = 7'd0; +reg [6:0] pcie_dma1_buffering_writer_fifo_wrport_adr = 7'd0; +wire [65:0] pcie_dma1_buffering_writer_fifo_wrport_dat_r; +wire pcie_dma1_buffering_writer_fifo_wrport_we; +wire [65:0] pcie_dma1_buffering_writer_fifo_wrport_dat_w; +wire pcie_dma1_buffering_writer_fifo_do_read; +wire [6:0] pcie_dma1_buffering_writer_fifo_rdport_adr; +wire [65:0] pcie_dma1_buffering_writer_fifo_rdport_dat_r; +wire pcie_dma1_buffering_writer_fifo_rdport_re; +wire [7:0] pcie_dma1_buffering_writer_fifo_level1; +wire [63:0] pcie_dma1_buffering_writer_fifo_fifo_in_payload_data; +wire pcie_dma1_buffering_writer_fifo_fifo_in_first; +wire pcie_dma1_buffering_writer_fifo_fifo_in_last; +wire [63:0] pcie_dma1_buffering_writer_fifo_fifo_out_payload_data; +wire pcie_dma1_buffering_writer_fifo_fifo_out_first; +wire pcie_dma1_buffering_writer_fifo_fifo_out_last; +reg [31:0] pcie_msi_irqs = 32'd0; +wire pcie_msi_source_valid; +wire pcie_msi_source_ready; +reg pcie_msi_source_first = 1'd0; +reg pcie_msi_source_last = 1'd0; +reg [7:0] pcie_msi_source_payload_dat = 8'd0; +reg [31:0] pcie_msi_enable_storage = 32'd0; +reg pcie_msi_enable_re = 1'd0; +reg [31:0] pcie_msi_clear_storage = 32'd0; +reg pcie_msi_clear_re = 1'd0; +wire [31:0] pcie_msi_vector_status; +wire pcie_msi_vector_we; +wire pcie_msi_vector_re; +wire [31:0] pcie_msi_enable; +reg [31:0] pcie_msi_clear = 32'd0; +reg [31:0] pcie_msi_vector = 32'd0; +reg [31:0] pcie_msi_msi = 32'd0; +reg [31:0] pcie_dma0_counter = 32'd0; +reg [31:0] pcie_dma1_counter = 32'd0; +wire freqmeter; +wire [31:0] freqmeter_status; +wire freqmeter_we; +wire freqmeter_re; +wire fmeter_clk; +wire freqmeter_period_done; +reg [31:0] freqmeter_period_counter = 32'd0; +wire freqmeter_ce; +reg [5:0] freqmeter_q = 6'd0; +wire [5:0] freqmeter_q_next; +reg [5:0] freqmeter_q_binary = 6'd0; +reg [5:0] freqmeter_q_next_binary = 6'd0; +wire [5:0] freqmeter_gray_decoder_i; +reg [5:0] freqmeter_gray_decoder_o = 6'd0; +reg [5:0] freqmeter_gray_decoder_o_comb = 6'd0; +wire freqmeter_sampler_latch; +wire [5:0] freqmeter_sampler_i; +reg [31:0] freqmeter_sampler_o = 32'd0; +wire [5:0] freqmeter_sampler_inc; +reg [31:0] freqmeter_sampler_counter = 32'd0; +reg [5:0] freqmeter_sampler_i_d = 6'd0; +wire litedramcrossbar_litedramnativeport0_cmd_valid0; +wire litedramcrossbar_litedramnativeport0_cmd_ready0; +wire litedramcrossbar_litedramnativeport0_cmd_payload_we0; +wire [23:0] litedramcrossbar_litedramnativeport0_cmd_payload_addr0; +wire litedramcrossbar_litedramnativeport0_wdata_valid; +wire litedramcrossbar_litedramnativeport0_wdata_ready; +wire [255:0] litedramcrossbar_litedramnativeport0_wdata_payload_data; +wire [31:0] litedramcrossbar_litedramnativeport0_wdata_payload_we; +wire litedramcrossbar_litedramnativeport0_rdata_valid0; +wire [255:0] litedramcrossbar_litedramnativeport0_rdata_payload_data0; +wire hdmi_in0_hpd_notif_status; +wire hdmi_in0_hpd_notif_we; +wire hdmi_in0_hpd_notif_re; +reg hdmi_in0_hpd_en_storage = 1'd0; +reg hdmi_in0_hpd_en_re = 1'd0; +wire hdmi_in0_scl_raw; +reg hdmi_in0_sda_i = 1'd0; +wire hdmi_in0_sda_raw; +reg hdmi_in0_sda_drv = 1'd0; +reg hdmi_in0_sda_drv_reg = 1'd0; +wire hdmi_in0_sda_o; +reg hdmi_in0_scl_i = 1'd0; +reg [5:0] hdmi_in0_samp_count = 6'd0; +reg hdmi_in0_samp_carry = 1'd0; +reg hdmi_in0_scl_r = 1'd0; +reg hdmi_in0_sda_r = 1'd0; +wire hdmi_in0_scl_rising; +wire hdmi_in0_sda_rising; +wire hdmi_in0_sda_falling; +wire hdmi_in0_start; +reg [7:0] hdmi_in0_din = 8'd0; +reg [3:0] hdmi_in0_counter = 4'd0; +reg hdmi_in0_is_read = 1'd0; +reg hdmi_in0_update_is_read = 1'd0; +reg [7:0] hdmi_in0_offset_counter = 8'd0; +reg hdmi_in0_oc_load = 1'd0; +reg hdmi_in0_oc_inc = 1'd0; +wire [7:0] hdmi_in0_adr; +wire [7:0] hdmi_in0_dat_r; +reg hdmi_in0_data_bit = 1'd0; +reg hdmi_in0_zero_drv = 1'd0; +reg hdmi_in0_data_drv = 1'd0; +reg hdmi_in0_data_drv_en = 1'd0; +reg hdmi_in0_data_drv_stop = 1'd0; +reg hdmi_in0_mmcm_reset_storage = 1'd1; +reg hdmi_in0_mmcm_reset_re = 1'd0; +wire hdmi_in0_locked_status; +wire hdmi_in0_locked_we; +wire hdmi_in0_locked_re; +wire hdmi_in0_mmcm_read_re; +wire hdmi_in0_mmcm_read_r; +wire hdmi_in0_mmcm_read_we; +reg hdmi_in0_mmcm_read_w = 1'd0; +wire hdmi_in0_mmcm_write_re; +wire hdmi_in0_mmcm_write_r; +wire hdmi_in0_mmcm_write_we; +reg hdmi_in0_mmcm_write_w = 1'd0; +reg hdmi_in0_mmcm_drdy_status = 1'd0; +wire hdmi_in0_mmcm_drdy_we; +wire hdmi_in0_mmcm_drdy_re; +reg [6:0] hdmi_in0_mmcm_adr_storage = 7'd0; +reg hdmi_in0_mmcm_adr_re = 1'd0; +reg [15:0] hdmi_in0_mmcm_dat_w_storage = 16'd0; +reg hdmi_in0_mmcm_dat_w_re = 1'd0; +wire [15:0] hdmi_in0_mmcm_dat_r_status; +wire hdmi_in0_mmcm_dat_r_we; +wire hdmi_in0_mmcm_dat_r_re; +wire hdmi_in0_locked; +(* dont_touch = "true" *) wire hdmi_in0_pix_clk; +wire hdmi_in0_pix_rst; +wire pix_o_clk; +wire pix_o_rst; +(* dont_touch = "true" *) wire pix1p25x_clk; +wire pix1p25x_rst; +(* dont_touch = "true" *) wire hdmi_in0_pix5x_clk; +wire pix5x_o_clk; +wire hdmi_in0_mmcm_write_o_re; +wire hdmi_in0_mmcm_write_o_r; +wire hdmi_in0_mmcm_write_o_we; +reg hdmi_in0_mmcm_write_o_w = 1'd0; +wire hdmi_in0_mmcm_read_o_re; +wire hdmi_in0_mmcm_read_o_r; +wire hdmi_in0_mmcm_read_o_we; +reg hdmi_in0_mmcm_read_o_w = 1'd0; +wire [15:0] hdmi_in0_mmcm_dat_o_r_status; +wire hdmi_in0_mmcm_dat_o_r_we; +wire hdmi_in0_mmcm_dat_o_r_re; +reg hdmi_in0_mmcm_drdy_o_status = 1'd0; +wire hdmi_in0_mmcm_drdy_o_we; +wire hdmi_in0_mmcm_drdy_o_re; +wire hdmi_in0_clk_input; +wire hdmi_in0_clk_input_bufr; +wire hdmi_in0_mmcm_fb; +wire hdmi_in0_mmcm_locked; +wire hdmi_in0_mmcm_clk0; +wire hdmi_in0_mmcm_clk1; +wire hdmi_in0_mmcm_clk2; +wire hdmi_in0_mmcm_drdy; +wire hdmi_in0_mmcm_fb_o; +wire hdmi_in0_mmcm_fb2_o; +wire hdmi_in0_mmcm_locked_o; +wire hdmi_in0_mmcm_clk0_o; +wire hdmi_in0_mmcm_clk2_o; +wire hdmi_in0_mmcm_drdy_o; +wire [9:0] hdmi_in0_s7datacapture0_d; +wire hdmi_in0_s7datacapture0_dly_ctl_re; +wire [4:0] hdmi_in0_s7datacapture0_dly_ctl_r; +wire hdmi_in0_s7datacapture0_dly_ctl_we; +reg [4:0] hdmi_in0_s7datacapture0_dly_ctl_w = 5'd0; +wire [1:0] hdmi_in0_s7datacapture0_phase_status; +wire hdmi_in0_s7datacapture0_phase_we; +wire hdmi_in0_s7datacapture0_phase_re; +wire hdmi_in0_s7datacapture0_phase_reset_re; +wire hdmi_in0_s7datacapture0_phase_reset_r; +wire hdmi_in0_s7datacapture0_phase_reset_we; +reg hdmi_in0_s7datacapture0_phase_reset_w = 1'd0; +wire [4:0] hdmi_in0_s7datacapture0_cntvalueout_m_status; +wire hdmi_in0_s7datacapture0_cntvalueout_m_we; +wire hdmi_in0_s7datacapture0_cntvalueout_m_re; +wire [4:0] hdmi_in0_s7datacapture0_cntvalueout_s_status; +wire hdmi_in0_s7datacapture0_cntvalueout_s_we; +wire hdmi_in0_s7datacapture0_cntvalueout_s_re; +wire hdmi_in0_s7datacapture0_serdes_m_i_nodelay; +wire hdmi_in0_s7datacapture0_serdes_s_i_nodelay; +wire hdmi_in0_s7datacapture0_delay_rst; +wire hdmi_in0_s7datacapture0_delay_master_inc; +wire hdmi_in0_s7datacapture0_delay_master_ce; +wire hdmi_in0_s7datacapture0_delay_slave_inc; +wire hdmi_in0_s7datacapture0_delay_slave_ce; +wire hdmi_in0_s7datacapture0_serdes_m_i_delayed; +wire [7:0] hdmi_in0_s7datacapture0_serdes_m_q; +wire [7:0] hdmi_in0_s7datacapture0_serdes_m_d; +wire [4:0] hdmi_in0_s7datacapture0_serdes_m_cntvalue; +wire hdmi_in0_s7datacapture0_serdes_s_i_delayed; +wire [7:0] hdmi_in0_s7datacapture0_serdes_s_q; +wire [7:0] hdmi_in0_s7datacapture0_serdes_s_d; +wire [4:0] hdmi_in0_s7datacapture0_serdes_s_cntvalue; +wire [4:0] hdmi_in0_s7datacapture0_sync_mcntvalue_i; +reg [4:0] hdmi_in0_s7datacapture0_sync_mcntvalue_o = 5'd0; +reg hdmi_in0_s7datacapture0_sync_mcntvalue_starter = 1'd1; +wire hdmi_in0_s7datacapture0_sync_mcntvalue_ping_i; +wire hdmi_in0_s7datacapture0_sync_mcntvalue_ping_o0; +reg hdmi_in0_s7datacapture0_sync_mcntvalue_ping_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture0_sync_mcntvalue_ping_toggle_o; +reg hdmi_in0_s7datacapture0_sync_mcntvalue_ping_toggle_o_r = 1'd0; +reg hdmi_in0_s7datacapture0_sync_mcntvalue_ping_o1 = 1'd0; +wire hdmi_in0_s7datacapture0_sync_mcntvalue_pong_i; +wire hdmi_in0_s7datacapture0_sync_mcntvalue_pong_o; +reg hdmi_in0_s7datacapture0_sync_mcntvalue_pong_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture0_sync_mcntvalue_pong_toggle_o; +reg hdmi_in0_s7datacapture0_sync_mcntvalue_pong_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture0_sync_mcntvalue_wait; +wire hdmi_in0_s7datacapture0_sync_mcntvalue_done; +reg [7:0] hdmi_in0_s7datacapture0_sync_mcntvalue_count = 8'd128; +(* dont_touch = "true" *) reg [4:0] hdmi_in0_s7datacapture0_sync_mcntvalue_ibuffer = 5'd0; +wire [4:0] hdmi_in0_s7datacapture0_sync_mcntvalue_obuffer; +wire [4:0] hdmi_in0_s7datacapture0_sync_scntvalue_i; +reg [4:0] hdmi_in0_s7datacapture0_sync_scntvalue_o = 5'd0; +reg hdmi_in0_s7datacapture0_sync_scntvalue_starter = 1'd1; +wire hdmi_in0_s7datacapture0_sync_scntvalue_ping_i; +wire hdmi_in0_s7datacapture0_sync_scntvalue_ping_o0; +reg hdmi_in0_s7datacapture0_sync_scntvalue_ping_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture0_sync_scntvalue_ping_toggle_o; +reg hdmi_in0_s7datacapture0_sync_scntvalue_ping_toggle_o_r = 1'd0; +reg hdmi_in0_s7datacapture0_sync_scntvalue_ping_o1 = 1'd0; +wire hdmi_in0_s7datacapture0_sync_scntvalue_pong_i; +wire hdmi_in0_s7datacapture0_sync_scntvalue_pong_o; +reg hdmi_in0_s7datacapture0_sync_scntvalue_pong_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture0_sync_scntvalue_pong_toggle_o; +reg hdmi_in0_s7datacapture0_sync_scntvalue_pong_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture0_sync_scntvalue_wait; +wire hdmi_in0_s7datacapture0_sync_scntvalue_done; +reg [7:0] hdmi_in0_s7datacapture0_sync_scntvalue_count = 8'd128; +(* dont_touch = "true" *) reg [4:0] hdmi_in0_s7datacapture0_sync_scntvalue_ibuffer = 5'd0; +wire [4:0] hdmi_in0_s7datacapture0_sync_scntvalue_obuffer; +wire [7:0] hdmi_in0_s7datacapture0_gearbox_i; +reg [9:0] hdmi_in0_s7datacapture0_gearbox_o = 10'd0; +wire hdmi_in0_s7datacapture0_gearbox_rst; +wire data0_cap_write_clk; +wire data0_cap_write_rst; +wire data0_cap_read_clk; +wire data0_cap_read_rst; +reg [79:0] hdmi_in0_s7datacapture0_gearbox_storage = 80'd0; +reg [3:0] hdmi_in0_s7datacapture0_gearbox_wrpointer = 4'd5; +reg [2:0] hdmi_in0_s7datacapture0_gearbox_rdpointer = 3'd0; +wire [7:0] hdmi_in0_s7datacapture0_mdata; +wire [7:0] hdmi_in0_s7datacapture0_sdata; +wire hdmi_in0_s7datacapture0_inc; +wire hdmi_in0_s7datacapture0_dec; +wire hdmi_in0_s7datacapture0_transition; +reg [7:0] hdmi_in0_s7datacapture0_mdata_d = 8'd0; +reg [7:0] hdmi_in0_s7datacapture0_lateness = 8'd128; +wire hdmi_in0_s7datacapture0_too_late; +wire hdmi_in0_s7datacapture0_too_early; +wire hdmi_in0_s7datacapture0_reset_lateness; +wire hdmi_in0_s7datacapture0_do_delay_rst_i; +wire hdmi_in0_s7datacapture0_do_delay_rst_o; +reg hdmi_in0_s7datacapture0_do_delay_rst_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture0_do_delay_rst_toggle_o; +reg hdmi_in0_s7datacapture0_do_delay_rst_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture0_do_delay_master_inc_i; +wire hdmi_in0_s7datacapture0_do_delay_master_inc_o; +reg hdmi_in0_s7datacapture0_do_delay_master_inc_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture0_do_delay_master_inc_toggle_o; +reg hdmi_in0_s7datacapture0_do_delay_master_inc_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture0_do_delay_master_dec_i; +wire hdmi_in0_s7datacapture0_do_delay_master_dec_o; +reg hdmi_in0_s7datacapture0_do_delay_master_dec_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture0_do_delay_master_dec_toggle_o; +reg hdmi_in0_s7datacapture0_do_delay_master_dec_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture0_do_delay_slave_inc_i; +wire hdmi_in0_s7datacapture0_do_delay_slave_inc_o; +reg hdmi_in0_s7datacapture0_do_delay_slave_inc_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture0_do_delay_slave_inc_toggle_o; +reg hdmi_in0_s7datacapture0_do_delay_slave_inc_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture0_do_delay_slave_dec_i; +wire hdmi_in0_s7datacapture0_do_delay_slave_dec_o; +reg hdmi_in0_s7datacapture0_do_delay_slave_dec_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture0_do_delay_slave_dec_toggle_o; +reg hdmi_in0_s7datacapture0_do_delay_slave_dec_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture0_do_reset_lateness_i; +wire hdmi_in0_s7datacapture0_do_reset_lateness_o; +reg hdmi_in0_s7datacapture0_do_reset_lateness_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture0_do_reset_lateness_toggle_o; +reg hdmi_in0_s7datacapture0_do_reset_lateness_toggle_o_r = 1'd0; +wire [9:0] hdmi_in0_charsync0_raw_data; +reg hdmi_in0_charsync0_synced = 1'd0; +reg [9:0] hdmi_in0_charsync0_data = 10'd0; +wire hdmi_in0_charsync0_char_synced_status; +wire hdmi_in0_charsync0_char_synced_we; +wire hdmi_in0_charsync0_char_synced_re; +wire [3:0] hdmi_in0_charsync0_ctl_pos_status; +wire hdmi_in0_charsync0_ctl_pos_we; +wire hdmi_in0_charsync0_ctl_pos_re; +reg [9:0] hdmi_in0_charsync0_raw_data1 = 10'd0; +wire [19:0] hdmi_in0_charsync0_raw; +reg hdmi_in0_charsync0_found_control = 1'd0; +reg [3:0] hdmi_in0_charsync0_control_position = 4'd0; +reg [2:0] hdmi_in0_charsync0_control_counter = 3'd0; +reg [3:0] hdmi_in0_charsync0_previous_control_position = 4'd0; +reg [3:0] hdmi_in0_charsync0_word_sel = 4'd0; +wire [9:0] hdmi_in0_wer0_data; +wire hdmi_in0_wer0_update_re; +wire hdmi_in0_wer0_update_r; +wire hdmi_in0_wer0_update_we; +reg hdmi_in0_wer0_update_w = 1'd0; +reg [23:0] hdmi_in0_wer0_status = 24'd0; +wire hdmi_in0_wer0_we; +wire hdmi_in0_wer0_re; +reg [8:0] hdmi_in0_wer0_data_r = 9'd0; +reg [7:0] hdmi_in0_wer0_transitions = 8'd0; +reg [3:0] hdmi_in0_wer0_transition_count = 4'd0; +reg hdmi_in0_wer0_is_control = 1'd0; +reg hdmi_in0_wer0_is_error = 1'd0; +reg [23:0] hdmi_in0_wer0_period_counter = 24'd0; +reg hdmi_in0_wer0_period_done = 1'd0; +reg [23:0] hdmi_in0_wer0_wer_counter = 24'd0; +reg [23:0] hdmi_in0_wer0_wer_counter_r = 24'd0; +reg hdmi_in0_wer0_wer_counter_r_updated = 1'd0; +reg [23:0] hdmi_in0_wer0_wer_counter_sys = 24'd0; +wire hdmi_in0_wer0_i; +wire hdmi_in0_wer0_o; +reg hdmi_in0_wer0_toggle_i = 1'd0; +wire hdmi_in0_wer0_toggle_o; +reg hdmi_in0_wer0_toggle_o_r = 1'd0; +wire hdmi_in0_decoding0_valid_i; +wire [9:0] hdmi_in0_decoding0_input; +reg hdmi_in0_decoding0_valid_o = 1'd0; +reg [9:0] hdmi_in0_decoding0_output_raw = 10'd0; +reg [7:0] hdmi_in0_decoding0_output_d = 8'd0; +reg [1:0] hdmi_in0_decoding0_output_c = 2'd0; +reg hdmi_in0_decoding0_output_de = 1'd0; +wire [9:0] hdmi_in0_s7datacapture1_d; +wire hdmi_in0_s7datacapture1_dly_ctl_re; +wire [4:0] hdmi_in0_s7datacapture1_dly_ctl_r; +wire hdmi_in0_s7datacapture1_dly_ctl_we; +reg [4:0] hdmi_in0_s7datacapture1_dly_ctl_w = 5'd0; +wire [1:0] hdmi_in0_s7datacapture1_phase_status; +wire hdmi_in0_s7datacapture1_phase_we; +wire hdmi_in0_s7datacapture1_phase_re; +wire hdmi_in0_s7datacapture1_phase_reset_re; +wire hdmi_in0_s7datacapture1_phase_reset_r; +wire hdmi_in0_s7datacapture1_phase_reset_we; +reg hdmi_in0_s7datacapture1_phase_reset_w = 1'd0; +wire [4:0] hdmi_in0_s7datacapture1_cntvalueout_m_status; +wire hdmi_in0_s7datacapture1_cntvalueout_m_we; +wire hdmi_in0_s7datacapture1_cntvalueout_m_re; +wire [4:0] hdmi_in0_s7datacapture1_cntvalueout_s_status; +wire hdmi_in0_s7datacapture1_cntvalueout_s_we; +wire hdmi_in0_s7datacapture1_cntvalueout_s_re; +wire hdmi_in0_s7datacapture1_serdes_m_i_nodelay; +wire hdmi_in0_s7datacapture1_serdes_s_i_nodelay; +wire hdmi_in0_s7datacapture1_delay_rst; +wire hdmi_in0_s7datacapture1_delay_master_inc; +wire hdmi_in0_s7datacapture1_delay_master_ce; +wire hdmi_in0_s7datacapture1_delay_slave_inc; +wire hdmi_in0_s7datacapture1_delay_slave_ce; +wire hdmi_in0_s7datacapture1_serdes_m_i_delayed; +wire [7:0] hdmi_in0_s7datacapture1_serdes_m_q; +wire [7:0] hdmi_in0_s7datacapture1_serdes_m_d; +wire [4:0] hdmi_in0_s7datacapture1_serdes_m_cntvalue; +wire hdmi_in0_s7datacapture1_serdes_s_i_delayed; +wire [7:0] hdmi_in0_s7datacapture1_serdes_s_q; +wire [7:0] hdmi_in0_s7datacapture1_serdes_s_d; +wire [4:0] hdmi_in0_s7datacapture1_serdes_s_cntvalue; +wire [4:0] hdmi_in0_s7datacapture1_sync_mcntvalue_i; +reg [4:0] hdmi_in0_s7datacapture1_sync_mcntvalue_o = 5'd0; +reg hdmi_in0_s7datacapture1_sync_mcntvalue_starter = 1'd1; +wire hdmi_in0_s7datacapture1_sync_mcntvalue_ping_i; +wire hdmi_in0_s7datacapture1_sync_mcntvalue_ping_o0; +reg hdmi_in0_s7datacapture1_sync_mcntvalue_ping_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture1_sync_mcntvalue_ping_toggle_o; +reg hdmi_in0_s7datacapture1_sync_mcntvalue_ping_toggle_o_r = 1'd0; +reg hdmi_in0_s7datacapture1_sync_mcntvalue_ping_o1 = 1'd0; +wire hdmi_in0_s7datacapture1_sync_mcntvalue_pong_i; +wire hdmi_in0_s7datacapture1_sync_mcntvalue_pong_o; +reg hdmi_in0_s7datacapture1_sync_mcntvalue_pong_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture1_sync_mcntvalue_pong_toggle_o; +reg hdmi_in0_s7datacapture1_sync_mcntvalue_pong_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture1_sync_mcntvalue_wait; +wire hdmi_in0_s7datacapture1_sync_mcntvalue_done; +reg [7:0] hdmi_in0_s7datacapture1_sync_mcntvalue_count = 8'd128; +(* dont_touch = "true" *) reg [4:0] hdmi_in0_s7datacapture1_sync_mcntvalue_ibuffer = 5'd0; +wire [4:0] hdmi_in0_s7datacapture1_sync_mcntvalue_obuffer; +wire [4:0] hdmi_in0_s7datacapture1_sync_scntvalue_i; +reg [4:0] hdmi_in0_s7datacapture1_sync_scntvalue_o = 5'd0; +reg hdmi_in0_s7datacapture1_sync_scntvalue_starter = 1'd1; +wire hdmi_in0_s7datacapture1_sync_scntvalue_ping_i; +wire hdmi_in0_s7datacapture1_sync_scntvalue_ping_o0; +reg hdmi_in0_s7datacapture1_sync_scntvalue_ping_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture1_sync_scntvalue_ping_toggle_o; +reg hdmi_in0_s7datacapture1_sync_scntvalue_ping_toggle_o_r = 1'd0; +reg hdmi_in0_s7datacapture1_sync_scntvalue_ping_o1 = 1'd0; +wire hdmi_in0_s7datacapture1_sync_scntvalue_pong_i; +wire hdmi_in0_s7datacapture1_sync_scntvalue_pong_o; +reg hdmi_in0_s7datacapture1_sync_scntvalue_pong_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture1_sync_scntvalue_pong_toggle_o; +reg hdmi_in0_s7datacapture1_sync_scntvalue_pong_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture1_sync_scntvalue_wait; +wire hdmi_in0_s7datacapture1_sync_scntvalue_done; +reg [7:0] hdmi_in0_s7datacapture1_sync_scntvalue_count = 8'd128; +(* dont_touch = "true" *) reg [4:0] hdmi_in0_s7datacapture1_sync_scntvalue_ibuffer = 5'd0; +wire [4:0] hdmi_in0_s7datacapture1_sync_scntvalue_obuffer; +wire [7:0] hdmi_in0_s7datacapture1_gearbox_i; +reg [9:0] hdmi_in0_s7datacapture1_gearbox_o = 10'd0; +wire hdmi_in0_s7datacapture1_gearbox_rst; +wire data1_cap_write_clk; +wire data1_cap_write_rst; +wire data1_cap_read_clk; +wire data1_cap_read_rst; +reg [79:0] hdmi_in0_s7datacapture1_gearbox_storage = 80'd0; +reg [3:0] hdmi_in0_s7datacapture1_gearbox_wrpointer = 4'd5; +reg [2:0] hdmi_in0_s7datacapture1_gearbox_rdpointer = 3'd0; +wire [7:0] hdmi_in0_s7datacapture1_mdata; +wire [7:0] hdmi_in0_s7datacapture1_sdata; +wire hdmi_in0_s7datacapture1_inc; +wire hdmi_in0_s7datacapture1_dec; +wire hdmi_in0_s7datacapture1_transition; +reg [7:0] hdmi_in0_s7datacapture1_mdata_d = 8'd0; +reg [7:0] hdmi_in0_s7datacapture1_lateness = 8'd128; +wire hdmi_in0_s7datacapture1_too_late; +wire hdmi_in0_s7datacapture1_too_early; +wire hdmi_in0_s7datacapture1_reset_lateness; +wire hdmi_in0_s7datacapture1_do_delay_rst_i; +wire hdmi_in0_s7datacapture1_do_delay_rst_o; +reg hdmi_in0_s7datacapture1_do_delay_rst_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture1_do_delay_rst_toggle_o; +reg hdmi_in0_s7datacapture1_do_delay_rst_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture1_do_delay_master_inc_i; +wire hdmi_in0_s7datacapture1_do_delay_master_inc_o; +reg hdmi_in0_s7datacapture1_do_delay_master_inc_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture1_do_delay_master_inc_toggle_o; +reg hdmi_in0_s7datacapture1_do_delay_master_inc_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture1_do_delay_master_dec_i; +wire hdmi_in0_s7datacapture1_do_delay_master_dec_o; +reg hdmi_in0_s7datacapture1_do_delay_master_dec_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture1_do_delay_master_dec_toggle_o; +reg hdmi_in0_s7datacapture1_do_delay_master_dec_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture1_do_delay_slave_inc_i; +wire hdmi_in0_s7datacapture1_do_delay_slave_inc_o; +reg hdmi_in0_s7datacapture1_do_delay_slave_inc_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture1_do_delay_slave_inc_toggle_o; +reg hdmi_in0_s7datacapture1_do_delay_slave_inc_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture1_do_delay_slave_dec_i; +wire hdmi_in0_s7datacapture1_do_delay_slave_dec_o; +reg hdmi_in0_s7datacapture1_do_delay_slave_dec_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture1_do_delay_slave_dec_toggle_o; +reg hdmi_in0_s7datacapture1_do_delay_slave_dec_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture1_do_reset_lateness_i; +wire hdmi_in0_s7datacapture1_do_reset_lateness_o; +reg hdmi_in0_s7datacapture1_do_reset_lateness_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture1_do_reset_lateness_toggle_o; +reg hdmi_in0_s7datacapture1_do_reset_lateness_toggle_o_r = 1'd0; +wire [9:0] hdmi_in0_charsync1_raw_data; +reg hdmi_in0_charsync1_synced = 1'd0; +reg [9:0] hdmi_in0_charsync1_data = 10'd0; +wire hdmi_in0_charsync1_char_synced_status; +wire hdmi_in0_charsync1_char_synced_we; +wire hdmi_in0_charsync1_char_synced_re; +wire [3:0] hdmi_in0_charsync1_ctl_pos_status; +wire hdmi_in0_charsync1_ctl_pos_we; +wire hdmi_in0_charsync1_ctl_pos_re; +reg [9:0] hdmi_in0_charsync1_raw_data1 = 10'd0; +wire [19:0] hdmi_in0_charsync1_raw; +reg hdmi_in0_charsync1_found_control = 1'd0; +reg [3:0] hdmi_in0_charsync1_control_position = 4'd0; +reg [2:0] hdmi_in0_charsync1_control_counter = 3'd0; +reg [3:0] hdmi_in0_charsync1_previous_control_position = 4'd0; +reg [3:0] hdmi_in0_charsync1_word_sel = 4'd0; +wire [9:0] hdmi_in0_wer1_data; +wire hdmi_in0_wer1_update_re; +wire hdmi_in0_wer1_update_r; +wire hdmi_in0_wer1_update_we; +reg hdmi_in0_wer1_update_w = 1'd0; +reg [23:0] hdmi_in0_wer1_status = 24'd0; +wire hdmi_in0_wer1_we; +wire hdmi_in0_wer1_re; +reg [8:0] hdmi_in0_wer1_data_r = 9'd0; +reg [7:0] hdmi_in0_wer1_transitions = 8'd0; +reg [3:0] hdmi_in0_wer1_transition_count = 4'd0; +reg hdmi_in0_wer1_is_control = 1'd0; +reg hdmi_in0_wer1_is_error = 1'd0; +reg [23:0] hdmi_in0_wer1_period_counter = 24'd0; +reg hdmi_in0_wer1_period_done = 1'd0; +reg [23:0] hdmi_in0_wer1_wer_counter = 24'd0; +reg [23:0] hdmi_in0_wer1_wer_counter_r = 24'd0; +reg hdmi_in0_wer1_wer_counter_r_updated = 1'd0; +reg [23:0] hdmi_in0_wer1_wer_counter_sys = 24'd0; +wire hdmi_in0_wer1_i; +wire hdmi_in0_wer1_o; +reg hdmi_in0_wer1_toggle_i = 1'd0; +wire hdmi_in0_wer1_toggle_o; +reg hdmi_in0_wer1_toggle_o_r = 1'd0; +wire hdmi_in0_decoding1_valid_i; +wire [9:0] hdmi_in0_decoding1_input; +reg hdmi_in0_decoding1_valid_o = 1'd0; +reg [9:0] hdmi_in0_decoding1_output_raw = 10'd0; +reg [7:0] hdmi_in0_decoding1_output_d = 8'd0; +reg [1:0] hdmi_in0_decoding1_output_c = 2'd0; +reg hdmi_in0_decoding1_output_de = 1'd0; +wire [9:0] hdmi_in0_s7datacapture2_d; +wire hdmi_in0_s7datacapture2_dly_ctl_re; +wire [4:0] hdmi_in0_s7datacapture2_dly_ctl_r; +wire hdmi_in0_s7datacapture2_dly_ctl_we; +reg [4:0] hdmi_in0_s7datacapture2_dly_ctl_w = 5'd0; +wire [1:0] hdmi_in0_s7datacapture2_phase_status; +wire hdmi_in0_s7datacapture2_phase_we; +wire hdmi_in0_s7datacapture2_phase_re; +wire hdmi_in0_s7datacapture2_phase_reset_re; +wire hdmi_in0_s7datacapture2_phase_reset_r; +wire hdmi_in0_s7datacapture2_phase_reset_we; +reg hdmi_in0_s7datacapture2_phase_reset_w = 1'd0; +wire [4:0] hdmi_in0_s7datacapture2_cntvalueout_m_status; +wire hdmi_in0_s7datacapture2_cntvalueout_m_we; +wire hdmi_in0_s7datacapture2_cntvalueout_m_re; +wire [4:0] hdmi_in0_s7datacapture2_cntvalueout_s_status; +wire hdmi_in0_s7datacapture2_cntvalueout_s_we; +wire hdmi_in0_s7datacapture2_cntvalueout_s_re; +wire hdmi_in0_s7datacapture2_serdes_m_i_nodelay; +wire hdmi_in0_s7datacapture2_serdes_s_i_nodelay; +wire hdmi_in0_s7datacapture2_delay_rst; +wire hdmi_in0_s7datacapture2_delay_master_inc; +wire hdmi_in0_s7datacapture2_delay_master_ce; +wire hdmi_in0_s7datacapture2_delay_slave_inc; +wire hdmi_in0_s7datacapture2_delay_slave_ce; +wire hdmi_in0_s7datacapture2_serdes_m_i_delayed; +wire [7:0] hdmi_in0_s7datacapture2_serdes_m_q; +wire [7:0] hdmi_in0_s7datacapture2_serdes_m_d; +wire [4:0] hdmi_in0_s7datacapture2_serdes_m_cntvalue; +wire hdmi_in0_s7datacapture2_serdes_s_i_delayed; +wire [7:0] hdmi_in0_s7datacapture2_serdes_s_q; +wire [7:0] hdmi_in0_s7datacapture2_serdes_s_d; +wire [4:0] hdmi_in0_s7datacapture2_serdes_s_cntvalue; +wire [4:0] hdmi_in0_s7datacapture2_sync_mcntvalue_i; +reg [4:0] hdmi_in0_s7datacapture2_sync_mcntvalue_o = 5'd0; +reg hdmi_in0_s7datacapture2_sync_mcntvalue_starter = 1'd1; +wire hdmi_in0_s7datacapture2_sync_mcntvalue_ping_i; +wire hdmi_in0_s7datacapture2_sync_mcntvalue_ping_o0; +reg hdmi_in0_s7datacapture2_sync_mcntvalue_ping_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture2_sync_mcntvalue_ping_toggle_o; +reg hdmi_in0_s7datacapture2_sync_mcntvalue_ping_toggle_o_r = 1'd0; +reg hdmi_in0_s7datacapture2_sync_mcntvalue_ping_o1 = 1'd0; +wire hdmi_in0_s7datacapture2_sync_mcntvalue_pong_i; +wire hdmi_in0_s7datacapture2_sync_mcntvalue_pong_o; +reg hdmi_in0_s7datacapture2_sync_mcntvalue_pong_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture2_sync_mcntvalue_pong_toggle_o; +reg hdmi_in0_s7datacapture2_sync_mcntvalue_pong_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture2_sync_mcntvalue_wait; +wire hdmi_in0_s7datacapture2_sync_mcntvalue_done; +reg [7:0] hdmi_in0_s7datacapture2_sync_mcntvalue_count = 8'd128; +(* dont_touch = "true" *) reg [4:0] hdmi_in0_s7datacapture2_sync_mcntvalue_ibuffer = 5'd0; +wire [4:0] hdmi_in0_s7datacapture2_sync_mcntvalue_obuffer; +wire [4:0] hdmi_in0_s7datacapture2_sync_scntvalue_i; +reg [4:0] hdmi_in0_s7datacapture2_sync_scntvalue_o = 5'd0; +reg hdmi_in0_s7datacapture2_sync_scntvalue_starter = 1'd1; +wire hdmi_in0_s7datacapture2_sync_scntvalue_ping_i; +wire hdmi_in0_s7datacapture2_sync_scntvalue_ping_o0; +reg hdmi_in0_s7datacapture2_sync_scntvalue_ping_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture2_sync_scntvalue_ping_toggle_o; +reg hdmi_in0_s7datacapture2_sync_scntvalue_ping_toggle_o_r = 1'd0; +reg hdmi_in0_s7datacapture2_sync_scntvalue_ping_o1 = 1'd0; +wire hdmi_in0_s7datacapture2_sync_scntvalue_pong_i; +wire hdmi_in0_s7datacapture2_sync_scntvalue_pong_o; +reg hdmi_in0_s7datacapture2_sync_scntvalue_pong_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture2_sync_scntvalue_pong_toggle_o; +reg hdmi_in0_s7datacapture2_sync_scntvalue_pong_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture2_sync_scntvalue_wait; +wire hdmi_in0_s7datacapture2_sync_scntvalue_done; +reg [7:0] hdmi_in0_s7datacapture2_sync_scntvalue_count = 8'd128; +(* dont_touch = "true" *) reg [4:0] hdmi_in0_s7datacapture2_sync_scntvalue_ibuffer = 5'd0; +wire [4:0] hdmi_in0_s7datacapture2_sync_scntvalue_obuffer; +wire [7:0] hdmi_in0_s7datacapture2_gearbox_i; +reg [9:0] hdmi_in0_s7datacapture2_gearbox_o = 10'd0; +wire hdmi_in0_s7datacapture2_gearbox_rst; +wire data2_cap_write_clk; +wire data2_cap_write_rst; +wire data2_cap_read_clk; +wire data2_cap_read_rst; +reg [79:0] hdmi_in0_s7datacapture2_gearbox_storage = 80'd0; +reg [3:0] hdmi_in0_s7datacapture2_gearbox_wrpointer = 4'd5; +reg [2:0] hdmi_in0_s7datacapture2_gearbox_rdpointer = 3'd0; +wire [7:0] hdmi_in0_s7datacapture2_mdata; +wire [7:0] hdmi_in0_s7datacapture2_sdata; +wire hdmi_in0_s7datacapture2_inc; +wire hdmi_in0_s7datacapture2_dec; +wire hdmi_in0_s7datacapture2_transition; +reg [7:0] hdmi_in0_s7datacapture2_mdata_d = 8'd0; +reg [7:0] hdmi_in0_s7datacapture2_lateness = 8'd128; +wire hdmi_in0_s7datacapture2_too_late; +wire hdmi_in0_s7datacapture2_too_early; +wire hdmi_in0_s7datacapture2_reset_lateness; +wire hdmi_in0_s7datacapture2_do_delay_rst_i; +wire hdmi_in0_s7datacapture2_do_delay_rst_o; +reg hdmi_in0_s7datacapture2_do_delay_rst_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture2_do_delay_rst_toggle_o; +reg hdmi_in0_s7datacapture2_do_delay_rst_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture2_do_delay_master_inc_i; +wire hdmi_in0_s7datacapture2_do_delay_master_inc_o; +reg hdmi_in0_s7datacapture2_do_delay_master_inc_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture2_do_delay_master_inc_toggle_o; +reg hdmi_in0_s7datacapture2_do_delay_master_inc_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture2_do_delay_master_dec_i; +wire hdmi_in0_s7datacapture2_do_delay_master_dec_o; +reg hdmi_in0_s7datacapture2_do_delay_master_dec_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture2_do_delay_master_dec_toggle_o; +reg hdmi_in0_s7datacapture2_do_delay_master_dec_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture2_do_delay_slave_inc_i; +wire hdmi_in0_s7datacapture2_do_delay_slave_inc_o; +reg hdmi_in0_s7datacapture2_do_delay_slave_inc_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture2_do_delay_slave_inc_toggle_o; +reg hdmi_in0_s7datacapture2_do_delay_slave_inc_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture2_do_delay_slave_dec_i; +wire hdmi_in0_s7datacapture2_do_delay_slave_dec_o; +reg hdmi_in0_s7datacapture2_do_delay_slave_dec_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture2_do_delay_slave_dec_toggle_o; +reg hdmi_in0_s7datacapture2_do_delay_slave_dec_toggle_o_r = 1'd0; +wire hdmi_in0_s7datacapture2_do_reset_lateness_i; +wire hdmi_in0_s7datacapture2_do_reset_lateness_o; +reg hdmi_in0_s7datacapture2_do_reset_lateness_toggle_i = 1'd0; +wire hdmi_in0_s7datacapture2_do_reset_lateness_toggle_o; +reg hdmi_in0_s7datacapture2_do_reset_lateness_toggle_o_r = 1'd0; +wire [9:0] hdmi_in0_charsync2_raw_data; +reg hdmi_in0_charsync2_synced = 1'd0; +reg [9:0] hdmi_in0_charsync2_data = 10'd0; +wire hdmi_in0_charsync2_char_synced_status; +wire hdmi_in0_charsync2_char_synced_we; +wire hdmi_in0_charsync2_char_synced_re; +wire [3:0] hdmi_in0_charsync2_ctl_pos_status; +wire hdmi_in0_charsync2_ctl_pos_we; +wire hdmi_in0_charsync2_ctl_pos_re; +reg [9:0] hdmi_in0_charsync2_raw_data1 = 10'd0; +wire [19:0] hdmi_in0_charsync2_raw; +reg hdmi_in0_charsync2_found_control = 1'd0; +reg [3:0] hdmi_in0_charsync2_control_position = 4'd0; +reg [2:0] hdmi_in0_charsync2_control_counter = 3'd0; +reg [3:0] hdmi_in0_charsync2_previous_control_position = 4'd0; +reg [3:0] hdmi_in0_charsync2_word_sel = 4'd0; +wire [9:0] hdmi_in0_wer2_data; +wire hdmi_in0_wer2_update_re; +wire hdmi_in0_wer2_update_r; +wire hdmi_in0_wer2_update_we; +reg hdmi_in0_wer2_update_w = 1'd0; +reg [23:0] hdmi_in0_wer2_status = 24'd0; +wire hdmi_in0_wer2_we; +wire hdmi_in0_wer2_re; +reg [8:0] hdmi_in0_wer2_data_r = 9'd0; +reg [7:0] hdmi_in0_wer2_transitions = 8'd0; +reg [3:0] hdmi_in0_wer2_transition_count = 4'd0; +reg hdmi_in0_wer2_is_control = 1'd0; +reg hdmi_in0_wer2_is_error = 1'd0; +reg [23:0] hdmi_in0_wer2_period_counter = 24'd0; +reg hdmi_in0_wer2_period_done = 1'd0; +reg [23:0] hdmi_in0_wer2_wer_counter = 24'd0; +reg [23:0] hdmi_in0_wer2_wer_counter_r = 24'd0; +reg hdmi_in0_wer2_wer_counter_r_updated = 1'd0; +reg [23:0] hdmi_in0_wer2_wer_counter_sys = 24'd0; +wire hdmi_in0_wer2_i; +wire hdmi_in0_wer2_o; +reg hdmi_in0_wer2_toggle_i = 1'd0; +wire hdmi_in0_wer2_toggle_o; +reg hdmi_in0_wer2_toggle_o_r = 1'd0; +wire hdmi_in0_decoding2_valid_i; +wire [9:0] hdmi_in0_decoding2_input; +reg hdmi_in0_decoding2_valid_o = 1'd0; +reg [9:0] hdmi_in0_decoding2_output_raw = 10'd0; +reg [7:0] hdmi_in0_decoding2_output_d = 8'd0; +reg [1:0] hdmi_in0_decoding2_output_c = 2'd0; +reg hdmi_in0_decoding2_output_de = 1'd0; +wire hdmi_in0_chansync_valid_i; +reg hdmi_in0_chansync_chan_synced = 1'd0; +wire hdmi_in0_chansync_status; +wire hdmi_in0_chansync_we; +wire hdmi_in0_chansync_re; +wire hdmi_in0_chansync_all_control; +wire [9:0] hdmi_in0_chansync_data_in0_raw; +wire [7:0] hdmi_in0_chansync_data_in0_d; +wire [1:0] hdmi_in0_chansync_data_in0_c; +wire hdmi_in0_chansync_data_in0_de; +wire [9:0] hdmi_in0_chansync_data_out0_raw; +wire [7:0] hdmi_in0_chansync_data_out0_d; +wire [1:0] hdmi_in0_chansync_data_out0_c; +wire hdmi_in0_chansync_data_out0_de; +wire [20:0] hdmi_in0_chansync_syncbuffer0_din; +wire [20:0] hdmi_in0_chansync_syncbuffer0_dout; +wire hdmi_in0_chansync_syncbuffer0_re; +reg [2:0] hdmi_in0_chansync_syncbuffer0_produce = 3'd0; +reg [2:0] hdmi_in0_chansync_syncbuffer0_consume = 3'd0; +wire [2:0] hdmi_in0_chansync_syncbuffer0_wrport_adr; +wire [20:0] hdmi_in0_chansync_syncbuffer0_wrport_dat_r; +wire hdmi_in0_chansync_syncbuffer0_wrport_we; +wire [20:0] hdmi_in0_chansync_syncbuffer0_wrport_dat_w; +wire [2:0] hdmi_in0_chansync_syncbuffer0_rdport_adr; +wire [20:0] hdmi_in0_chansync_syncbuffer0_rdport_dat_r; +wire hdmi_in0_chansync_is_control0; +wire [9:0] hdmi_in0_chansync_data_in1_raw; +wire [7:0] hdmi_in0_chansync_data_in1_d; +wire [1:0] hdmi_in0_chansync_data_in1_c; +wire hdmi_in0_chansync_data_in1_de; +wire [9:0] hdmi_in0_chansync_data_out1_raw; +wire [7:0] hdmi_in0_chansync_data_out1_d; +wire [1:0] hdmi_in0_chansync_data_out1_c; +wire hdmi_in0_chansync_data_out1_de; +wire [20:0] hdmi_in0_chansync_syncbuffer1_din; +wire [20:0] hdmi_in0_chansync_syncbuffer1_dout; +wire hdmi_in0_chansync_syncbuffer1_re; +reg [2:0] hdmi_in0_chansync_syncbuffer1_produce = 3'd0; +reg [2:0] hdmi_in0_chansync_syncbuffer1_consume = 3'd0; +wire [2:0] hdmi_in0_chansync_syncbuffer1_wrport_adr; +wire [20:0] hdmi_in0_chansync_syncbuffer1_wrport_dat_r; +wire hdmi_in0_chansync_syncbuffer1_wrport_we; +wire [20:0] hdmi_in0_chansync_syncbuffer1_wrport_dat_w; +wire [2:0] hdmi_in0_chansync_syncbuffer1_rdport_adr; +wire [20:0] hdmi_in0_chansync_syncbuffer1_rdport_dat_r; +wire hdmi_in0_chansync_is_control1; +wire [9:0] hdmi_in0_chansync_data_in2_raw; +wire [7:0] hdmi_in0_chansync_data_in2_d; +wire [1:0] hdmi_in0_chansync_data_in2_c; +wire hdmi_in0_chansync_data_in2_de; +wire [9:0] hdmi_in0_chansync_data_out2_raw; +wire [7:0] hdmi_in0_chansync_data_out2_d; +wire [1:0] hdmi_in0_chansync_data_out2_c; +wire hdmi_in0_chansync_data_out2_de; +wire [20:0] hdmi_in0_chansync_syncbuffer2_din; +wire [20:0] hdmi_in0_chansync_syncbuffer2_dout; +wire hdmi_in0_chansync_syncbuffer2_re; +reg [2:0] hdmi_in0_chansync_syncbuffer2_produce = 3'd0; +reg [2:0] hdmi_in0_chansync_syncbuffer2_consume = 3'd0; +wire [2:0] hdmi_in0_chansync_syncbuffer2_wrport_adr; +wire [20:0] hdmi_in0_chansync_syncbuffer2_wrport_dat_r; +wire hdmi_in0_chansync_syncbuffer2_wrport_we; +wire [20:0] hdmi_in0_chansync_syncbuffer2_wrport_dat_w; +wire [2:0] hdmi_in0_chansync_syncbuffer2_rdport_adr; +wire [20:0] hdmi_in0_chansync_syncbuffer2_rdport_dat_r; +wire hdmi_in0_chansync_is_control2; +wire hdmi_in0_chansync_some_control; +wire hdmi_in0_syncpol_valid_i; +wire [9:0] hdmi_in0_syncpol_data_in0_raw; +wire [7:0] hdmi_in0_syncpol_data_in0_d; +wire [1:0] hdmi_in0_syncpol_data_in0_c; +wire hdmi_in0_syncpol_data_in0_de; +wire [9:0] hdmi_in0_syncpol_data_in1_raw; +wire [7:0] hdmi_in0_syncpol_data_in1_d; +wire [1:0] hdmi_in0_syncpol_data_in1_c; +wire hdmi_in0_syncpol_data_in1_de; +wire [9:0] hdmi_in0_syncpol_data_in2_raw; +wire [7:0] hdmi_in0_syncpol_data_in2_d; +wire [1:0] hdmi_in0_syncpol_data_in2_c; +wire hdmi_in0_syncpol_data_in2_de; +reg hdmi_in0_syncpol_valid_o = 1'd0; +wire hdmi_in0_syncpol_de; +wire hdmi_in0_syncpol_hsync; +wire hdmi_in0_syncpol_vsync; +reg [7:0] hdmi_in0_syncpol_r = 8'd0; +reg [7:0] hdmi_in0_syncpol_g = 8'd0; +reg [7:0] hdmi_in0_syncpol_b = 8'd0; +reg [9:0] hdmi_in0_syncpol_c0 = 10'd0; +reg [9:0] hdmi_in0_syncpol_c1 = 10'd0; +reg [9:0] hdmi_in0_syncpol_c2 = 10'd0; +wire hdmi_in0_syncpol_de_rising; +reg hdmi_in0_syncpol_de_r = 1'd0; +reg [1:0] hdmi_in0_syncpol_c_polarity = 2'd0; +reg [1:0] hdmi_in0_syncpol_c_out = 2'd0; +wire hdmi_in0_resdetection_valid_i; +wire hdmi_in0_resdetection_vsync; +wire hdmi_in0_resdetection_de; +wire [10:0] hdmi_in0_resdetection_hres_status; +wire hdmi_in0_resdetection_hres_we; +wire hdmi_in0_resdetection_hres_re; +wire [10:0] hdmi_in0_resdetection_vres_status; +wire hdmi_in0_resdetection_vres_we; +wire hdmi_in0_resdetection_vres_re; +reg hdmi_in0_resdetection_de_r = 1'd0; +wire hdmi_in0_resdetection_pn_de; +reg [10:0] hdmi_in0_resdetection_hcounter = 11'd0; +reg [10:0] hdmi_in0_resdetection_hcounter_st = 11'd0; +reg hdmi_in0_resdetection_vsync_r = 1'd0; +wire hdmi_in0_resdetection_p_vsync; +reg [10:0] hdmi_in0_resdetection_vcounter = 11'd0; +reg [10:0] hdmi_in0_resdetection_vcounter_st = 11'd0; +wire hdmi_in0_frame_valid_i; +wire hdmi_in0_frame_vsync; +wire hdmi_in0_frame_de; +wire [7:0] hdmi_in0_frame_r; +wire [7:0] hdmi_in0_frame_g; +wire [7:0] hdmi_in0_frame_b; +wire hdmi_in0_frame_frame_valid; +wire hdmi_in0_frame_frame_ready; +wire hdmi_in0_frame_frame_first; +wire hdmi_in0_frame_frame_last; +wire hdmi_in0_frame_frame_payload_sof; +wire [255:0] hdmi_in0_frame_frame_payload_pixels; +wire hdmi_in0_frame_busy; +wire hdmi_in0_frame_overflow_re; +wire hdmi_in0_frame_overflow_r; +wire hdmi_in0_frame_overflow_we; +wire hdmi_in0_frame_overflow_w; +reg hdmi_in0_frame_vsync_r = 1'd0; +wire hdmi_in0_frame_new_frame; +reg hdmi_in0_frame_de_r = 1'd0; +wire hdmi_in0_frame_rgb2ycbcr_sink_valid; +wire hdmi_in0_frame_rgb2ycbcr_sink_ready; +reg hdmi_in0_frame_rgb2ycbcr_sink_first = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_sink_last = 1'd0; +wire [7:0] hdmi_in0_frame_rgb2ycbcr_sink_payload_r; +wire [7:0] hdmi_in0_frame_rgb2ycbcr_sink_payload_g; +wire [7:0] hdmi_in0_frame_rgb2ycbcr_sink_payload_b; +wire hdmi_in0_frame_rgb2ycbcr_source_valid; +wire hdmi_in0_frame_rgb2ycbcr_source_ready; +wire hdmi_in0_frame_rgb2ycbcr_source_first; +wire hdmi_in0_frame_rgb2ycbcr_source_last; +wire [7:0] hdmi_in0_frame_rgb2ycbcr_source_payload_y; +wire [7:0] hdmi_in0_frame_rgb2ycbcr_source_payload_cb; +wire [7:0] hdmi_in0_frame_rgb2ycbcr_source_payload_cr; +wire [7:0] hdmi_in0_frame_rgb2ycbcr_sink_r; +wire [7:0] hdmi_in0_frame_rgb2ycbcr_sink_g; +wire [7:0] hdmi_in0_frame_rgb2ycbcr_sink_b; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_source_y = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_source_cb = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_source_cr = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record0_rgb_n_r = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record0_rgb_n_g = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record0_rgb_n_b = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record1_rgb_n_r = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record1_rgb_n_g = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record1_rgb_n_b = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record2_rgb_n_r = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record2_rgb_n_g = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record2_rgb_n_b = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record3_rgb_n_r = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record3_rgb_n_g = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record3_rgb_n_b = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record4_rgb_n_r = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record4_rgb_n_g = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record4_rgb_n_b = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record5_rgb_n_r = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record5_rgb_n_g = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record5_rgb_n_b = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record6_rgb_n_r = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record6_rgb_n_g = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record6_rgb_n_b = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record7_rgb_n_r = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record7_rgb_n_g = 8'd0; +reg [7:0] hdmi_in0_frame_rgb2ycbcr_record7_rgb_n_b = 8'd0; +reg signed [8:0] hdmi_in0_frame_rgb2ycbcr_r_minus_g = 9'd0; +reg signed [8:0] hdmi_in0_frame_rgb2ycbcr_b_minus_g = 9'd0; +reg signed [16:0] hdmi_in0_frame_rgb2ycbcr_ca_mult_rg = 17'd0; +reg signed [16:0] hdmi_in0_frame_rgb2ycbcr_cb_mult_bg = 17'd0; +reg signed [24:0] hdmi_in0_frame_rgb2ycbcr_carg_plus_cbbg = 25'd0; +reg signed [10:0] hdmi_in0_frame_rgb2ycbcr_yraw = 11'd0; +reg signed [11:0] hdmi_in0_frame_rgb2ycbcr_b_minus_yraw = 12'd0; +reg signed [11:0] hdmi_in0_frame_rgb2ycbcr_r_minus_yraw = 12'd0; +reg signed [10:0] hdmi_in0_frame_rgb2ycbcr_yraw_r0 = 11'd0; +reg signed [19:0] hdmi_in0_frame_rgb2ycbcr_cc_mult_ryraw = 20'd0; +reg signed [19:0] hdmi_in0_frame_rgb2ycbcr_cd_mult_byraw = 20'd0; +reg signed [10:0] hdmi_in0_frame_rgb2ycbcr_yraw_r1 = 11'd0; +reg signed [10:0] hdmi_in0_frame_rgb2ycbcr_y = 11'd0; +reg signed [11:0] hdmi_in0_frame_rgb2ycbcr_cb = 12'd0; +reg signed [11:0] hdmi_in0_frame_rgb2ycbcr_cr = 12'd0; +wire hdmi_in0_frame_rgb2ycbcr_ce; +wire hdmi_in0_frame_rgb2ycbcr_pipe_ce; +wire hdmi_in0_frame_rgb2ycbcr_busy; +reg hdmi_in0_frame_rgb2ycbcr_valid_n0 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_valid_n1 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_valid_n2 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_valid_n3 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_valid_n4 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_valid_n5 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_valid_n6 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_valid_n7 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_first_n0 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_last_n0 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_first_n1 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_last_n1 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_first_n2 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_last_n2 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_first_n3 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_last_n3 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_first_n4 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_last_n4 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_first_n5 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_last_n5 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_first_n6 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_last_n6 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_first_n7 = 1'd0; +reg hdmi_in0_frame_rgb2ycbcr_last_n7 = 1'd0; +wire hdmi_in0_frame_chroma_downsampler_sink_valid; +wire hdmi_in0_frame_chroma_downsampler_sink_ready; +wire hdmi_in0_frame_chroma_downsampler_sink_first; +wire hdmi_in0_frame_chroma_downsampler_sink_last; +wire [7:0] hdmi_in0_frame_chroma_downsampler_sink_payload_y; +wire [7:0] hdmi_in0_frame_chroma_downsampler_sink_payload_cb; +wire [7:0] hdmi_in0_frame_chroma_downsampler_sink_payload_cr; +wire hdmi_in0_frame_chroma_downsampler_source_valid; +wire hdmi_in0_frame_chroma_downsampler_source_ready; +wire hdmi_in0_frame_chroma_downsampler_source_first; +wire hdmi_in0_frame_chroma_downsampler_source_last; +wire [7:0] hdmi_in0_frame_chroma_downsampler_source_payload_y; +wire [7:0] hdmi_in0_frame_chroma_downsampler_source_payload_cb_cr; +wire [7:0] hdmi_in0_frame_chroma_downsampler_sink_y; +wire [7:0] hdmi_in0_frame_chroma_downsampler_sink_cb; +wire [7:0] hdmi_in0_frame_chroma_downsampler_sink_cr; +reg [7:0] hdmi_in0_frame_chroma_downsampler_source_y = 8'd0; +reg [7:0] hdmi_in0_frame_chroma_downsampler_source_cb_cr = 8'd0; +wire hdmi_in0_frame_chroma_downsampler_first; +reg [7:0] hdmi_in0_frame_chroma_downsampler_record0_ycbcr_n_y = 8'd0; +reg [7:0] hdmi_in0_frame_chroma_downsampler_record0_ycbcr_n_cb = 8'd0; +reg [7:0] hdmi_in0_frame_chroma_downsampler_record0_ycbcr_n_cr = 8'd0; +reg [7:0] hdmi_in0_frame_chroma_downsampler_record1_ycbcr_n_y = 8'd0; +reg [7:0] hdmi_in0_frame_chroma_downsampler_record1_ycbcr_n_cb = 8'd0; +reg [7:0] hdmi_in0_frame_chroma_downsampler_record1_ycbcr_n_cr = 8'd0; +reg [7:0] hdmi_in0_frame_chroma_downsampler_record2_ycbcr_n_y = 8'd0; +reg [7:0] hdmi_in0_frame_chroma_downsampler_record2_ycbcr_n_cb = 8'd0; +reg [7:0] hdmi_in0_frame_chroma_downsampler_record2_ycbcr_n_cr = 8'd0; +reg hdmi_in0_frame_chroma_downsampler_parity = 1'd0; +reg [8:0] hdmi_in0_frame_chroma_downsampler_cb_sum = 9'd0; +reg [8:0] hdmi_in0_frame_chroma_downsampler_cr_sum = 9'd0; +wire [7:0] hdmi_in0_frame_chroma_downsampler_cb_mean; +wire [7:0] hdmi_in0_frame_chroma_downsampler_cr_mean; +wire hdmi_in0_frame_chroma_downsampler_ce; +wire hdmi_in0_frame_chroma_downsampler_pipe_ce; +wire hdmi_in0_frame_chroma_downsampler_busy; +reg hdmi_in0_frame_chroma_downsampler_valid_n0 = 1'd0; +reg hdmi_in0_frame_chroma_downsampler_valid_n1 = 1'd0; +reg hdmi_in0_frame_chroma_downsampler_valid_n2 = 1'd0; +reg hdmi_in0_frame_chroma_downsampler_first_n0 = 1'd0; +reg hdmi_in0_frame_chroma_downsampler_last_n0 = 1'd0; +reg hdmi_in0_frame_chroma_downsampler_first_n1 = 1'd0; +reg hdmi_in0_frame_chroma_downsampler_last_n1 = 1'd0; +reg hdmi_in0_frame_chroma_downsampler_first_n2 = 1'd0; +reg hdmi_in0_frame_chroma_downsampler_last_n2 = 1'd0; +reg hdmi_in0_frame_next_de0 = 1'd0; +reg hdmi_in0_frame_next_vsync0 = 1'd0; +reg hdmi_in0_frame_next_de1 = 1'd0; +reg hdmi_in0_frame_next_vsync1 = 1'd0; +reg hdmi_in0_frame_next_de2 = 1'd0; +reg hdmi_in0_frame_next_vsync2 = 1'd0; +reg hdmi_in0_frame_next_de3 = 1'd0; +reg hdmi_in0_frame_next_vsync3 = 1'd0; +reg hdmi_in0_frame_next_de4 = 1'd0; +reg hdmi_in0_frame_next_vsync4 = 1'd0; +reg hdmi_in0_frame_next_de5 = 1'd0; +reg hdmi_in0_frame_next_vsync5 = 1'd0; +reg hdmi_in0_frame_next_de6 = 1'd0; +reg hdmi_in0_frame_next_vsync6 = 1'd0; +reg hdmi_in0_frame_next_de7 = 1'd0; +reg hdmi_in0_frame_next_vsync7 = 1'd0; +reg hdmi_in0_frame_next_de8 = 1'd0; +reg hdmi_in0_frame_next_vsync8 = 1'd0; +reg hdmi_in0_frame_next_de9 = 1'd0; +reg hdmi_in0_frame_next_vsync9 = 1'd0; +reg hdmi_in0_frame_next_de10 = 1'd0; +reg hdmi_in0_frame_next_vsync10 = 1'd0; +reg [255:0] hdmi_in0_frame_cur_word = 256'd0; +reg hdmi_in0_frame_cur_word_valid = 1'd0; +wire [15:0] hdmi_in0_frame_encoded_pixel; +reg [3:0] hdmi_in0_frame_pack_counter = 4'd0; +wire hdmi_in0_frame_fifo_sink_valid; +wire hdmi_in0_frame_fifo_sink_ready; +reg hdmi_in0_frame_fifo_sink_first = 1'd0; +reg hdmi_in0_frame_fifo_sink_last = 1'd0; +reg hdmi_in0_frame_fifo_sink_payload_sof = 1'd0; +wire [255:0] hdmi_in0_frame_fifo_sink_payload_pixels; +wire hdmi_in0_frame_fifo_source_valid; +wire hdmi_in0_frame_fifo_source_ready; +wire hdmi_in0_frame_fifo_source_first; +wire hdmi_in0_frame_fifo_source_last; +wire hdmi_in0_frame_fifo_source_payload_sof; +wire [255:0] hdmi_in0_frame_fifo_source_payload_pixels; +wire hdmi_in0_frame_fifo_asyncfifo_we; +wire hdmi_in0_frame_fifo_asyncfifo_writable; +wire hdmi_in0_frame_fifo_asyncfifo_re; +wire hdmi_in0_frame_fifo_asyncfifo_readable; +wire [258:0] hdmi_in0_frame_fifo_asyncfifo_din; +wire [258:0] hdmi_in0_frame_fifo_asyncfifo_dout; +wire hdmi_in0_frame_fifo_graycounter0_ce; +(* dont_touch = "true" *) reg [9:0] hdmi_in0_frame_fifo_graycounter0_q = 10'd0; +wire [9:0] hdmi_in0_frame_fifo_graycounter0_q_next; +reg [9:0] hdmi_in0_frame_fifo_graycounter0_q_binary = 10'd0; +reg [9:0] hdmi_in0_frame_fifo_graycounter0_q_next_binary = 10'd0; +wire hdmi_in0_frame_fifo_graycounter1_ce; +(* dont_touch = "true" *) reg [9:0] hdmi_in0_frame_fifo_graycounter1_q = 10'd0; +wire [9:0] hdmi_in0_frame_fifo_graycounter1_q_next; +reg [9:0] hdmi_in0_frame_fifo_graycounter1_q_binary = 10'd0; +reg [9:0] hdmi_in0_frame_fifo_graycounter1_q_next_binary = 10'd0; +wire [9:0] hdmi_in0_frame_fifo_produce_rdomain; +wire [9:0] hdmi_in0_frame_fifo_consume_wdomain; +wire [8:0] hdmi_in0_frame_fifo_wrport_adr; +wire [258:0] hdmi_in0_frame_fifo_wrport_dat_r; +wire hdmi_in0_frame_fifo_wrport_we; +wire [258:0] hdmi_in0_frame_fifo_wrport_dat_w; +wire [8:0] hdmi_in0_frame_fifo_rdport_adr; +wire [258:0] hdmi_in0_frame_fifo_rdport_dat_r; +wire hdmi_in0_frame_fifo_fifo_in_payload_sof; +wire [255:0] hdmi_in0_frame_fifo_fifo_in_payload_pixels; +wire hdmi_in0_frame_fifo_fifo_in_first; +wire hdmi_in0_frame_fifo_fifo_in_last; +wire hdmi_in0_frame_fifo_fifo_out_payload_sof; +wire [255:0] hdmi_in0_frame_fifo_fifo_out_payload_pixels; +wire hdmi_in0_frame_fifo_fifo_out_first; +wire hdmi_in0_frame_fifo_fifo_out_last; +reg hdmi_in0_frame_pix_overflow = 1'd0; +wire hdmi_in0_frame_pix_overflow_reset; +wire hdmi_in0_frame_sys_overflow; +wire hdmi_in0_frame_overflow_reset_i; +wire hdmi_in0_frame_overflow_reset_o; +reg hdmi_in0_frame_overflow_reset_toggle_i = 1'd0; +wire hdmi_in0_frame_overflow_reset_toggle_o; +reg hdmi_in0_frame_overflow_reset_toggle_o_r = 1'd0; +wire hdmi_in0_frame_overflow_reset_ack_i; +wire hdmi_in0_frame_overflow_reset_ack_o; +reg hdmi_in0_frame_overflow_reset_ack_toggle_i = 1'd0; +wire hdmi_in0_frame_overflow_reset_ack_toggle_o; +reg hdmi_in0_frame_overflow_reset_ack_toggle_o_r = 1'd0; +reg hdmi_in0_frame_overflow_mask = 1'd0; +wire hdmi_in0_dma_frame_valid; +reg hdmi_in0_dma_frame_ready = 1'd0; +wire hdmi_in0_dma_frame_first; +wire hdmi_in0_dma_frame_last; +wire hdmi_in0_dma_frame_payload_sof; +wire [255:0] hdmi_in0_dma_frame_payload_pixels; +reg [28:0] hdmi_in0_dma_frame_size_storage = 29'd0; +reg hdmi_in0_dma_frame_size_re = 1'd0; +wire hdmi_in0_dma_slot_array_irq; +wire [23:0] hdmi_in0_dma_slot_array_address; +wire [23:0] hdmi_in0_dma_slot_array_address_reached; +wire hdmi_in0_dma_slot_array_address_valid; +reg hdmi_in0_dma_slot_array_address_done = 1'd0; +wire hdmi_in0_dma_slot_array_slot0_status; +wire hdmi_in0_dma_slot_array_slot0_pending; +wire hdmi_in0_dma_slot_array_slot0_trigger; +reg hdmi_in0_dma_slot_array_slot0_clear = 1'd0; +wire [23:0] hdmi_in0_dma_slot_array_slot0_address; +wire [23:0] hdmi_in0_dma_slot_array_slot0_address_reached; +wire hdmi_in0_dma_slot_array_slot0_address_valid; +wire hdmi_in0_dma_slot_array_slot0_address_done; +reg [1:0] hdmi_in0_dma_slot_array_slot0_status_storage = 2'd0; +reg hdmi_in0_dma_slot_array_slot0_status_re = 1'd0; +wire hdmi_in0_dma_slot_array_slot0_status_we; +wire [1:0] hdmi_in0_dma_slot_array_slot0_status_dat_w; +reg [28:0] hdmi_in0_dma_slot_array_slot0_address_storage = 29'd0; +reg hdmi_in0_dma_slot_array_slot0_address_re = 1'd0; +wire hdmi_in0_dma_slot_array_slot0_address_we; +wire [28:0] hdmi_in0_dma_slot_array_slot0_address_dat_w; +wire hdmi_in0_dma_slot_array_slot1_status; +wire hdmi_in0_dma_slot_array_slot1_pending; +wire hdmi_in0_dma_slot_array_slot1_trigger; +reg hdmi_in0_dma_slot_array_slot1_clear = 1'd0; +wire [23:0] hdmi_in0_dma_slot_array_slot1_address; +wire [23:0] hdmi_in0_dma_slot_array_slot1_address_reached; +wire hdmi_in0_dma_slot_array_slot1_address_valid; +wire hdmi_in0_dma_slot_array_slot1_address_done; +reg [1:0] hdmi_in0_dma_slot_array_slot1_status_storage = 2'd0; +reg hdmi_in0_dma_slot_array_slot1_status_re = 1'd0; +wire hdmi_in0_dma_slot_array_slot1_status_we; +wire [1:0] hdmi_in0_dma_slot_array_slot1_status_dat_w; +reg [28:0] hdmi_in0_dma_slot_array_slot1_address_storage = 29'd0; +reg hdmi_in0_dma_slot_array_slot1_address_re = 1'd0; +wire hdmi_in0_dma_slot_array_slot1_address_we; +wire [28:0] hdmi_in0_dma_slot_array_slot1_address_dat_w; +wire hdmi_in0_dma_slot_array_status_re; +wire [1:0] hdmi_in0_dma_slot_array_status_r; +wire hdmi_in0_dma_slot_array_status_we; +reg [1:0] hdmi_in0_dma_slot_array_status_w = 2'd0; +wire hdmi_in0_dma_slot_array_pending_re; +wire [1:0] hdmi_in0_dma_slot_array_pending_r; +wire hdmi_in0_dma_slot_array_pending_we; +reg [1:0] hdmi_in0_dma_slot_array_pending_w = 2'd0; +reg [1:0] hdmi_in0_dma_slot_array_storage = 2'd0; +reg hdmi_in0_dma_slot_array_re = 1'd0; +wire hdmi_in0_dma_slot_array_change_slot; +reg hdmi_in0_dma_slot_array_current_slot = 1'd0; +reg hdmi_in0_dma_reset_words = 1'd0; +reg hdmi_in0_dma_count_word = 1'd0; +wire hdmi_in0_dma_last_word; +reg [23:0] hdmi_in0_dma_current_address = 24'd0; +reg [23:0] hdmi_in0_dma_mwords_remaining = 24'd0; +wire [255:0] hdmi_in0_dma_memory_word; +reg hdmi_in0_dma_sink_sink_valid = 1'd0; +wire hdmi_in0_dma_sink_sink_ready; +wire [23:0] hdmi_in0_dma_sink_sink_payload_address; +wire [255:0] hdmi_in0_dma_sink_sink_payload_data; +wire hdmi_in0_dma_fifo_sink_valid; +wire hdmi_in0_dma_fifo_sink_ready; +reg hdmi_in0_dma_fifo_sink_first = 1'd0; +reg hdmi_in0_dma_fifo_sink_last = 1'd0; +wire [255:0] hdmi_in0_dma_fifo_sink_payload_data; +wire hdmi_in0_dma_fifo_source_valid; +wire hdmi_in0_dma_fifo_source_ready; +wire hdmi_in0_dma_fifo_source_first; +wire hdmi_in0_dma_fifo_source_last; +wire [255:0] hdmi_in0_dma_fifo_source_payload_data; +wire hdmi_in0_dma_fifo_syncfifo_we; +wire hdmi_in0_dma_fifo_syncfifo_writable; +wire hdmi_in0_dma_fifo_syncfifo_re; +wire hdmi_in0_dma_fifo_syncfifo_readable; +wire [257:0] hdmi_in0_dma_fifo_syncfifo_din; +wire [257:0] hdmi_in0_dma_fifo_syncfifo_dout; +reg [4:0] hdmi_in0_dma_fifo_level = 5'd0; +reg hdmi_in0_dma_fifo_replace = 1'd0; +reg [3:0] hdmi_in0_dma_fifo_produce = 4'd0; +reg [3:0] hdmi_in0_dma_fifo_consume = 4'd0; +reg [3:0] hdmi_in0_dma_fifo_wrport_adr = 4'd0; +wire [257:0] hdmi_in0_dma_fifo_wrport_dat_r; +wire hdmi_in0_dma_fifo_wrport_we; +wire [257:0] hdmi_in0_dma_fifo_wrport_dat_w; +wire hdmi_in0_dma_fifo_do_read; +wire [3:0] hdmi_in0_dma_fifo_rdport_adr; +wire [257:0] hdmi_in0_dma_fifo_rdport_dat_r; +wire [255:0] hdmi_in0_dma_fifo_fifo_in_payload_data; +wire hdmi_in0_dma_fifo_fifo_in_first; +wire hdmi_in0_dma_fifo_fifo_in_last; +wire [255:0] hdmi_in0_dma_fifo_fifo_out_payload_data; +wire hdmi_in0_dma_fifo_fifo_out_first; +wire hdmi_in0_dma_fifo_fifo_out_last; +wire litedramcrossbar_litedramnativeport1_cmd_valid0; +wire litedramcrossbar_litedramnativeport1_cmd_ready0; +wire litedramcrossbar_litedramnativeport1_cmd_first; +wire litedramcrossbar_litedramnativeport1_cmd_last0; +wire litedramcrossbar_litedramnativeport1_cmd_payload_we0; +wire [23:0] litedramcrossbar_litedramnativeport1_cmd_payload_addr0; +wire litedramcrossbar_litedramnativeport1_wdata_ready; +reg [255:0] litedramcrossbar_litedramnativeport1_wdata_payload_data = 256'd0; +reg [31:0] litedramcrossbar_litedramnativeport1_wdata_payload_we = 32'd0; +wire litedramcrossbar_litedramnativeport1_rdata_valid0; +wire litedramcrossbar_litedramnativeport1_rdata_ready0; +reg litedramcrossbar_litedramnativeport1_rdata_first0 = 1'd0; +reg litedramcrossbar_litedramnativeport1_rdata_last0 = 1'd0; +wire [255:0] litedramcrossbar_litedramnativeport1_rdata_payload_data0; +reg litedramcrossbar_litedramnativeport0_cmd_valid1 = 1'd0; +wire litedramcrossbar_litedramnativeport0_cmd_ready1; +reg litedramcrossbar_litedramnativeport0_cmd_first = 1'd0; +reg litedramcrossbar_litedramnativeport0_cmd_last = 1'd0; +reg litedramcrossbar_litedramnativeport0_cmd_payload_we1 = 1'd0; +reg [23:0] litedramcrossbar_litedramnativeport0_cmd_payload_addr1 = 24'd0; +wire litedramcrossbar_litedramnativeport0_rdata_valid1; +wire litedramcrossbar_litedramnativeport0_rdata_ready; +wire litedramcrossbar_litedramnativeport0_rdata_first; +wire litedramcrossbar_litedramnativeport0_rdata_last; +wire [255:0] litedramcrossbar_litedramnativeport0_rdata_payload_data1; +wire litedramcrossbar_cmd_cdc_sink_sink_valid; +wire litedramcrossbar_cmd_cdc_sink_sink_ready; +wire litedramcrossbar_cmd_cdc_sink_sink_first; +wire litedramcrossbar_cmd_cdc_sink_sink_last; +wire litedramcrossbar_cmd_cdc_sink_sink_payload_we; +wire [23:0] litedramcrossbar_cmd_cdc_sink_sink_payload_addr; +wire litedramcrossbar_cmd_cdc_source_source_valid; +wire litedramcrossbar_cmd_cdc_source_source_ready; +wire litedramcrossbar_cmd_cdc_source_source_first; +wire litedramcrossbar_cmd_cdc_source_source_last; +wire litedramcrossbar_cmd_cdc_source_source_payload_we; +wire [23:0] litedramcrossbar_cmd_cdc_source_source_payload_addr; +wire litedramcrossbar_cmd_cdc_cdc_sink_valid; +wire litedramcrossbar_cmd_cdc_cdc_sink_ready; +wire litedramcrossbar_cmd_cdc_cdc_sink_first; +wire litedramcrossbar_cmd_cdc_cdc_sink_last; +wire litedramcrossbar_cmd_cdc_cdc_sink_payload_we; +wire [23:0] litedramcrossbar_cmd_cdc_cdc_sink_payload_addr; +wire litedramcrossbar_cmd_cdc_cdc_source_valid; +wire litedramcrossbar_cmd_cdc_cdc_source_ready; +wire litedramcrossbar_cmd_cdc_cdc_source_first; +wire litedramcrossbar_cmd_cdc_cdc_source_last; +wire litedramcrossbar_cmd_cdc_cdc_source_payload_we; +wire [23:0] litedramcrossbar_cmd_cdc_cdc_source_payload_addr; +wire litedramcrossbar_cmd_cdc_cdc_asyncfifo_we; +wire litedramcrossbar_cmd_cdc_cdc_asyncfifo_writable; +wire litedramcrossbar_cmd_cdc_cdc_asyncfifo_re; +wire litedramcrossbar_cmd_cdc_cdc_asyncfifo_readable; +wire [26:0] litedramcrossbar_cmd_cdc_cdc_asyncfifo_din; +wire [26:0] litedramcrossbar_cmd_cdc_cdc_asyncfifo_dout; +wire litedramcrossbar_cmd_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) reg [2:0] litedramcrossbar_cmd_cdc_cdc_graycounter0_q = 3'd0; +wire [2:0] litedramcrossbar_cmd_cdc_cdc_graycounter0_q_next; +reg [2:0] litedramcrossbar_cmd_cdc_cdc_graycounter0_q_binary = 3'd0; +reg [2:0] litedramcrossbar_cmd_cdc_cdc_graycounter0_q_next_binary = 3'd0; +wire litedramcrossbar_cmd_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) reg [2:0] litedramcrossbar_cmd_cdc_cdc_graycounter1_q = 3'd0; +wire [2:0] litedramcrossbar_cmd_cdc_cdc_graycounter1_q_next; +reg [2:0] litedramcrossbar_cmd_cdc_cdc_graycounter1_q_binary = 3'd0; +reg [2:0] litedramcrossbar_cmd_cdc_cdc_graycounter1_q_next_binary = 3'd0; +wire [2:0] litedramcrossbar_cmd_cdc_cdc_produce_rdomain; +wire [2:0] litedramcrossbar_cmd_cdc_cdc_consume_wdomain; +wire [1:0] litedramcrossbar_cmd_cdc_cdc_wrport_adr; +wire [26:0] litedramcrossbar_cmd_cdc_cdc_wrport_dat_r; +wire litedramcrossbar_cmd_cdc_cdc_wrport_we; +wire [26:0] litedramcrossbar_cmd_cdc_cdc_wrport_dat_w; +wire [1:0] litedramcrossbar_cmd_cdc_cdc_rdport_adr; +wire [26:0] litedramcrossbar_cmd_cdc_cdc_rdport_dat_r; +wire litedramcrossbar_cmd_cdc_cdc_fifo_in_payload_we; +wire [23:0] litedramcrossbar_cmd_cdc_cdc_fifo_in_payload_addr; +wire litedramcrossbar_cmd_cdc_cdc_fifo_in_first; +wire litedramcrossbar_cmd_cdc_cdc_fifo_in_last; +wire litedramcrossbar_cmd_cdc_cdc_fifo_out_payload_we; +wire [23:0] litedramcrossbar_cmd_cdc_cdc_fifo_out_payload_addr; +wire litedramcrossbar_cmd_cdc_cdc_fifo_out_first; +wire litedramcrossbar_cmd_cdc_cdc_fifo_out_last; +wire litedramcrossbar_rdata_cdc_sink_sink_valid; +wire litedramcrossbar_rdata_cdc_sink_sink_ready; +wire litedramcrossbar_rdata_cdc_sink_sink_first; +wire litedramcrossbar_rdata_cdc_sink_sink_last; +wire [255:0] litedramcrossbar_rdata_cdc_sink_sink_payload_data; +wire litedramcrossbar_rdata_cdc_source_source_valid; +wire litedramcrossbar_rdata_cdc_source_source_ready; +wire litedramcrossbar_rdata_cdc_source_source_first; +wire litedramcrossbar_rdata_cdc_source_source_last; +wire [255:0] litedramcrossbar_rdata_cdc_source_source_payload_data; +wire litedramcrossbar_rdata_cdc_cdc_sink_valid; +wire litedramcrossbar_rdata_cdc_cdc_sink_ready; +wire litedramcrossbar_rdata_cdc_cdc_sink_first; +wire litedramcrossbar_rdata_cdc_cdc_sink_last; +wire [255:0] litedramcrossbar_rdata_cdc_cdc_sink_payload_data; +wire litedramcrossbar_rdata_cdc_cdc_source_valid; +wire litedramcrossbar_rdata_cdc_cdc_source_ready; +wire litedramcrossbar_rdata_cdc_cdc_source_first; +wire litedramcrossbar_rdata_cdc_cdc_source_last; +wire [255:0] litedramcrossbar_rdata_cdc_cdc_source_payload_data; +wire litedramcrossbar_rdata_cdc_cdc_asyncfifo_we; +wire litedramcrossbar_rdata_cdc_cdc_asyncfifo_writable; +wire litedramcrossbar_rdata_cdc_cdc_asyncfifo_re; +wire litedramcrossbar_rdata_cdc_cdc_asyncfifo_readable; +wire [257:0] litedramcrossbar_rdata_cdc_cdc_asyncfifo_din; +wire [257:0] litedramcrossbar_rdata_cdc_cdc_asyncfifo_dout; +wire litedramcrossbar_rdata_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) reg [4:0] litedramcrossbar_rdata_cdc_cdc_graycounter0_q = 5'd0; +wire [4:0] litedramcrossbar_rdata_cdc_cdc_graycounter0_q_next; +reg [4:0] litedramcrossbar_rdata_cdc_cdc_graycounter0_q_binary = 5'd0; +reg [4:0] litedramcrossbar_rdata_cdc_cdc_graycounter0_q_next_binary = 5'd0; +wire litedramcrossbar_rdata_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) reg [4:0] litedramcrossbar_rdata_cdc_cdc_graycounter1_q = 5'd0; +wire [4:0] litedramcrossbar_rdata_cdc_cdc_graycounter1_q_next; +reg [4:0] litedramcrossbar_rdata_cdc_cdc_graycounter1_q_binary = 5'd0; +reg [4:0] litedramcrossbar_rdata_cdc_cdc_graycounter1_q_next_binary = 5'd0; +wire [4:0] litedramcrossbar_rdata_cdc_cdc_produce_rdomain; +wire [4:0] litedramcrossbar_rdata_cdc_cdc_consume_wdomain; +wire [3:0] litedramcrossbar_rdata_cdc_cdc_wrport_adr; +wire [257:0] litedramcrossbar_rdata_cdc_cdc_wrport_dat_r; +wire litedramcrossbar_rdata_cdc_cdc_wrport_we; +wire [257:0] litedramcrossbar_rdata_cdc_cdc_wrport_dat_w; +wire [3:0] litedramcrossbar_rdata_cdc_cdc_rdport_adr; +wire [257:0] litedramcrossbar_rdata_cdc_cdc_rdport_dat_r; +wire [255:0] litedramcrossbar_rdata_cdc_cdc_fifo_in_payload_data; +wire litedramcrossbar_rdata_cdc_cdc_fifo_in_first; +wire litedramcrossbar_rdata_cdc_cdc_fifo_in_last; +wire [255:0] litedramcrossbar_rdata_cdc_cdc_fifo_out_payload_data; +wire litedramcrossbar_rdata_cdc_cdc_fifo_out_first; +wire litedramcrossbar_rdata_cdc_cdc_fifo_out_last; +reg litedramcrossbar_litedramnativeport1_flush = 1'd0; +wire litedramcrossbar_litedramnativeport1_cmd_valid1; +reg litedramcrossbar_litedramnativeport1_cmd_ready1 = 1'd0; +reg litedramcrossbar_litedramnativeport1_cmd_last1 = 1'd0; +wire litedramcrossbar_litedramnativeport1_cmd_payload_we1; +wire [27:0] litedramcrossbar_litedramnativeport1_cmd_payload_addr1; +reg litedramcrossbar_litedramnativeport1_rdata_valid1 = 1'd0; +wire litedramcrossbar_litedramnativeport1_rdata_ready1; +reg litedramcrossbar_litedramnativeport1_rdata_first1 = 1'd0; +reg litedramcrossbar_litedramnativeport1_rdata_last1 = 1'd0; +reg [15:0] litedramcrossbar_litedramnativeport1_rdata_payload_data1 = 16'd0; +reg [15:0] litedramcrossbar_sel = 16'd0; +reg litedramcrossbar_cmd_buffer_sink_valid = 1'd0; +wire litedramcrossbar_cmd_buffer_sink_ready; +reg litedramcrossbar_cmd_buffer_sink_first = 1'd0; +reg litedramcrossbar_cmd_buffer_sink_last = 1'd0; +reg [15:0] litedramcrossbar_cmd_buffer_sink_payload_sel = 16'd0; +reg litedramcrossbar_cmd_buffer_sink_payload_we = 1'd0; +wire litedramcrossbar_cmd_buffer_source_valid; +wire litedramcrossbar_cmd_buffer_source_ready; +wire litedramcrossbar_cmd_buffer_source_first; +wire litedramcrossbar_cmd_buffer_source_last; +wire [15:0] litedramcrossbar_cmd_buffer_source_payload_sel; +wire litedramcrossbar_cmd_buffer_source_payload_we; +reg [27:0] litedramcrossbar_cmd_addr = 28'd0; +reg litedramcrossbar_cmd_we = 1'd0; +reg litedramcrossbar_cmd_last = 1'd0; +wire litedramcrossbar_next_cmd; +wire litedramcrossbar_addr_changed; +reg litedramcrossbar_wdata_finished = 1'd0; +reg litedramcrossbar_rdata_finished = 1'd0; +reg litedramcrossbar_read_lock = 1'd0; +reg litedramcrossbar_read_unlocked = 1'd0; +wire litedramcrossbar_rw_collision; +wire litedramcrossbar_rdata_fifo_sink_valid; +wire litedramcrossbar_rdata_fifo_sink_ready; +wire litedramcrossbar_rdata_fifo_sink_first; +wire litedramcrossbar_rdata_fifo_sink_last; +wire [255:0] litedramcrossbar_rdata_fifo_sink_payload_data; +wire litedramcrossbar_rdata_fifo_source_valid; +wire litedramcrossbar_rdata_fifo_source_ready; +wire litedramcrossbar_rdata_fifo_source_first; +wire litedramcrossbar_rdata_fifo_source_last; +wire [255:0] litedramcrossbar_rdata_fifo_source_payload_data; +wire litedramcrossbar_rdata_fifo_syncfifo_we; +wire litedramcrossbar_rdata_fifo_syncfifo_writable; +wire litedramcrossbar_rdata_fifo_syncfifo_re; +wire litedramcrossbar_rdata_fifo_syncfifo_readable; +wire [257:0] litedramcrossbar_rdata_fifo_syncfifo_din; +wire [257:0] litedramcrossbar_rdata_fifo_syncfifo_dout; +reg [3:0] litedramcrossbar_rdata_fifo_level = 4'd0; +reg litedramcrossbar_rdata_fifo_replace = 1'd0; +reg [3:0] litedramcrossbar_rdata_fifo_produce = 4'd0; +reg [3:0] litedramcrossbar_rdata_fifo_consume = 4'd0; +reg [3:0] litedramcrossbar_rdata_fifo_wrport_adr = 4'd0; +wire [257:0] litedramcrossbar_rdata_fifo_wrport_dat_r; +wire litedramcrossbar_rdata_fifo_wrport_we; +wire [257:0] litedramcrossbar_rdata_fifo_wrport_dat_w; +wire litedramcrossbar_rdata_fifo_do_read; +wire [3:0] litedramcrossbar_rdata_fifo_rdport_adr; +wire [257:0] litedramcrossbar_rdata_fifo_rdport_dat_r; +wire [255:0] litedramcrossbar_rdata_fifo_fifo_in_payload_data; +wire litedramcrossbar_rdata_fifo_fifo_in_first; +wire litedramcrossbar_rdata_fifo_fifo_in_last; +wire [255:0] litedramcrossbar_rdata_fifo_fifo_out_payload_data; +wire litedramcrossbar_rdata_fifo_fifo_out_first; +wire litedramcrossbar_rdata_fifo_fifo_out_last; +wire litedramcrossbar_rdata_converter_sink_valid; +wire litedramcrossbar_rdata_converter_sink_ready; +wire litedramcrossbar_rdata_converter_sink_first; +wire litedramcrossbar_rdata_converter_sink_last; +wire [255:0] litedramcrossbar_rdata_converter_sink_payload_data; +wire litedramcrossbar_rdata_converter_source_valid; +reg litedramcrossbar_rdata_converter_source_ready = 1'd0; +wire litedramcrossbar_rdata_converter_source_first; +wire litedramcrossbar_rdata_converter_source_last; +wire [15:0] litedramcrossbar_rdata_converter_source_payload_data; +wire litedramcrossbar_rdata_converter_converter_sink_valid; +wire litedramcrossbar_rdata_converter_converter_sink_ready; +wire litedramcrossbar_rdata_converter_converter_sink_first; +wire litedramcrossbar_rdata_converter_converter_sink_last; +reg [255:0] litedramcrossbar_rdata_converter_converter_sink_payload_data = 256'd0; +wire litedramcrossbar_rdata_converter_converter_source_valid; +wire litedramcrossbar_rdata_converter_converter_source_ready; +wire litedramcrossbar_rdata_converter_converter_source_first; +wire litedramcrossbar_rdata_converter_converter_source_last; +reg [15:0] litedramcrossbar_rdata_converter_converter_source_payload_data = 16'd0; +wire litedramcrossbar_rdata_converter_converter_source_payload_valid_token_count; +reg [3:0] litedramcrossbar_rdata_converter_converter_mux = 4'd0; +wire litedramcrossbar_rdata_converter_converter_first; +wire litedramcrossbar_rdata_converter_converter_last; +wire litedramcrossbar_rdata_converter_source_source_valid; +wire litedramcrossbar_rdata_converter_source_source_ready; +wire litedramcrossbar_rdata_converter_source_source_first; +wire litedramcrossbar_rdata_converter_source_source_last; +wire [15:0] litedramcrossbar_rdata_converter_source_source_payload_data; +reg [15:0] litedramcrossbar_rdata_chunk = 16'd1; +wire litedramcrossbar_rdata_chunk_valid; +wire hdmi_out0_core_source_source_valid; +wire hdmi_out0_core_source_source_ready; +wire [15:0] hdmi_out0_core_source_source_payload_data; +wire hdmi_out0_core_source_source_param_hsync; +wire hdmi_out0_core_source_source_param_vsync; +wire hdmi_out0_core_source_source_param_de; +reg hdmi_out0_core_underflow_enable_storage = 1'd0; +reg hdmi_out0_core_underflow_enable_re = 1'd0; +wire hdmi_out0_core_underflow_update_underflow_update_re; +wire hdmi_out0_core_underflow_update_underflow_update_r; +wire hdmi_out0_core_underflow_update_underflow_update_we; +reg hdmi_out0_core_underflow_update_underflow_update_w = 1'd0; +reg [31:0] hdmi_out0_core_underflow_counter_status = 32'd0; +wire hdmi_out0_core_underflow_counter_we; +wire hdmi_out0_core_underflow_counter_re; +wire hdmi_out0_core_initiator_source_source_valid; +wire hdmi_out0_core_initiator_source_source_ready; +wire hdmi_out0_core_initiator_source_source_first; +wire hdmi_out0_core_initiator_source_source_last; +wire [11:0] hdmi_out0_core_initiator_source_source_payload_hres; +wire [11:0] hdmi_out0_core_initiator_source_source_payload_hsync_start; +wire [11:0] hdmi_out0_core_initiator_source_source_payload_hsync_end; +wire [11:0] hdmi_out0_core_initiator_source_source_payload_hscan; +wire [11:0] hdmi_out0_core_initiator_source_source_payload_vres; +wire [11:0] hdmi_out0_core_initiator_source_source_payload_vsync_start; +wire [11:0] hdmi_out0_core_initiator_source_source_payload_vsync_end; +wire [11:0] hdmi_out0_core_initiator_source_source_payload_vscan; +wire [31:0] hdmi_out0_core_initiator_source_source_payload_base; +wire [31:0] hdmi_out0_core_initiator_source_source_payload_length; +wire hdmi_out0_core_initiator_cdc_sink_valid; +wire hdmi_out0_core_initiator_cdc_sink_ready; +reg hdmi_out0_core_initiator_cdc_sink_first = 1'd0; +reg hdmi_out0_core_initiator_cdc_sink_last = 1'd0; +wire [11:0] hdmi_out0_core_initiator_cdc_sink_payload_hres; +wire [11:0] hdmi_out0_core_initiator_cdc_sink_payload_hsync_start; +wire [11:0] hdmi_out0_core_initiator_cdc_sink_payload_hsync_end; +wire [11:0] hdmi_out0_core_initiator_cdc_sink_payload_hscan; +wire [11:0] hdmi_out0_core_initiator_cdc_sink_payload_vres; +wire [11:0] hdmi_out0_core_initiator_cdc_sink_payload_vsync_start; +wire [11:0] hdmi_out0_core_initiator_cdc_sink_payload_vsync_end; +wire [11:0] hdmi_out0_core_initiator_cdc_sink_payload_vscan; +wire [31:0] hdmi_out0_core_initiator_cdc_sink_payload_base; +wire [31:0] hdmi_out0_core_initiator_cdc_sink_payload_length; +wire hdmi_out0_core_initiator_cdc_source_valid; +wire hdmi_out0_core_initiator_cdc_source_ready; +wire hdmi_out0_core_initiator_cdc_source_first; +wire hdmi_out0_core_initiator_cdc_source_last; +wire [11:0] hdmi_out0_core_initiator_cdc_source_payload_hres; +wire [11:0] hdmi_out0_core_initiator_cdc_source_payload_hsync_start; +wire [11:0] hdmi_out0_core_initiator_cdc_source_payload_hsync_end; +wire [11:0] hdmi_out0_core_initiator_cdc_source_payload_hscan; +wire [11:0] hdmi_out0_core_initiator_cdc_source_payload_vres; +wire [11:0] hdmi_out0_core_initiator_cdc_source_payload_vsync_start; +wire [11:0] hdmi_out0_core_initiator_cdc_source_payload_vsync_end; +wire [11:0] hdmi_out0_core_initiator_cdc_source_payload_vscan; +wire [31:0] hdmi_out0_core_initiator_cdc_source_payload_base; +wire [31:0] hdmi_out0_core_initiator_cdc_source_payload_length; +wire hdmi_out0_core_initiator_cdc_asyncfifo_we; +wire hdmi_out0_core_initiator_cdc_asyncfifo_writable; +wire hdmi_out0_core_initiator_cdc_asyncfifo_re; +wire hdmi_out0_core_initiator_cdc_asyncfifo_readable; +wire [161:0] hdmi_out0_core_initiator_cdc_asyncfifo_din; +wire [161:0] hdmi_out0_core_initiator_cdc_asyncfifo_dout; +wire hdmi_out0_core_initiator_cdc_graycounter0_ce; +(* dont_touch = "true" *) reg [2:0] hdmi_out0_core_initiator_cdc_graycounter0_q = 3'd0; +wire [2:0] hdmi_out0_core_initiator_cdc_graycounter0_q_next; +reg [2:0] hdmi_out0_core_initiator_cdc_graycounter0_q_binary = 3'd0; +reg [2:0] hdmi_out0_core_initiator_cdc_graycounter0_q_next_binary = 3'd0; +wire hdmi_out0_core_initiator_cdc_graycounter1_ce; +(* dont_touch = "true" *) reg [2:0] hdmi_out0_core_initiator_cdc_graycounter1_q = 3'd0; +wire [2:0] hdmi_out0_core_initiator_cdc_graycounter1_q_next; +reg [2:0] hdmi_out0_core_initiator_cdc_graycounter1_q_binary = 3'd0; +reg [2:0] hdmi_out0_core_initiator_cdc_graycounter1_q_next_binary = 3'd0; +wire [2:0] hdmi_out0_core_initiator_cdc_produce_rdomain; +wire [2:0] hdmi_out0_core_initiator_cdc_consume_wdomain; +wire [1:0] hdmi_out0_core_initiator_cdc_wrport_adr; +wire [161:0] hdmi_out0_core_initiator_cdc_wrport_dat_r; +wire hdmi_out0_core_initiator_cdc_wrport_we; +wire [161:0] hdmi_out0_core_initiator_cdc_wrport_dat_w; +wire [1:0] hdmi_out0_core_initiator_cdc_rdport_adr; +wire [161:0] hdmi_out0_core_initiator_cdc_rdport_dat_r; +wire [11:0] hdmi_out0_core_initiator_cdc_fifo_in_payload_hres; +wire [11:0] hdmi_out0_core_initiator_cdc_fifo_in_payload_hsync_start; +wire [11:0] hdmi_out0_core_initiator_cdc_fifo_in_payload_hsync_end; +wire [11:0] hdmi_out0_core_initiator_cdc_fifo_in_payload_hscan; +wire [11:0] hdmi_out0_core_initiator_cdc_fifo_in_payload_vres; +wire [11:0] hdmi_out0_core_initiator_cdc_fifo_in_payload_vsync_start; +wire [11:0] hdmi_out0_core_initiator_cdc_fifo_in_payload_vsync_end; +wire [11:0] hdmi_out0_core_initiator_cdc_fifo_in_payload_vscan; +wire [31:0] hdmi_out0_core_initiator_cdc_fifo_in_payload_base; +wire [31:0] hdmi_out0_core_initiator_cdc_fifo_in_payload_length; +wire hdmi_out0_core_initiator_cdc_fifo_in_first; +wire hdmi_out0_core_initiator_cdc_fifo_in_last; +wire [11:0] hdmi_out0_core_initiator_cdc_fifo_out_payload_hres; +wire [11:0] hdmi_out0_core_initiator_cdc_fifo_out_payload_hsync_start; +wire [11:0] hdmi_out0_core_initiator_cdc_fifo_out_payload_hsync_end; +wire [11:0] hdmi_out0_core_initiator_cdc_fifo_out_payload_hscan; +wire [11:0] hdmi_out0_core_initiator_cdc_fifo_out_payload_vres; +wire [11:0] hdmi_out0_core_initiator_cdc_fifo_out_payload_vsync_start; +wire [11:0] hdmi_out0_core_initiator_cdc_fifo_out_payload_vsync_end; +wire [11:0] hdmi_out0_core_initiator_cdc_fifo_out_payload_vscan; +wire [31:0] hdmi_out0_core_initiator_cdc_fifo_out_payload_base; +wire [31:0] hdmi_out0_core_initiator_cdc_fifo_out_payload_length; +wire hdmi_out0_core_initiator_cdc_fifo_out_first; +wire hdmi_out0_core_initiator_cdc_fifo_out_last; +reg hdmi_out0_core_initiator_enable_storage = 1'd0; +reg hdmi_out0_core_initiator_enable_re = 1'd0; +reg [11:0] hdmi_out0_core_initiator_csrstorage0_storage = 12'd0; +reg hdmi_out0_core_initiator_csrstorage0_re = 1'd0; +reg [11:0] hdmi_out0_core_initiator_csrstorage1_storage = 12'd0; +reg hdmi_out0_core_initiator_csrstorage1_re = 1'd0; +reg [11:0] hdmi_out0_core_initiator_csrstorage2_storage = 12'd0; +reg hdmi_out0_core_initiator_csrstorage2_re = 1'd0; +reg [11:0] hdmi_out0_core_initiator_csrstorage3_storage = 12'd0; +reg hdmi_out0_core_initiator_csrstorage3_re = 1'd0; +reg [11:0] hdmi_out0_core_initiator_csrstorage4_storage = 12'd0; +reg hdmi_out0_core_initiator_csrstorage4_re = 1'd0; +reg [11:0] hdmi_out0_core_initiator_csrstorage5_storage = 12'd0; +reg hdmi_out0_core_initiator_csrstorage5_re = 1'd0; +reg [11:0] hdmi_out0_core_initiator_csrstorage6_storage = 12'd0; +reg hdmi_out0_core_initiator_csrstorage6_re = 1'd0; +reg [11:0] hdmi_out0_core_initiator_csrstorage7_storage = 12'd0; +reg hdmi_out0_core_initiator_csrstorage7_re = 1'd0; +reg [31:0] hdmi_out0_core_initiator_csrstorage8_storage = 32'd0; +reg hdmi_out0_core_initiator_csrstorage8_re = 1'd0; +reg [31:0] hdmi_out0_core_initiator_csrstorage9_storage = 32'd0; +reg hdmi_out0_core_initiator_csrstorage9_re = 1'd0; +wire hdmi_out0_core_timinggenerator_sink_valid; +wire hdmi_out0_core_timinggenerator_sink_ready; +wire [11:0] hdmi_out0_core_timinggenerator_sink_payload_hres; +wire [11:0] hdmi_out0_core_timinggenerator_sink_payload_hsync_start; +wire [11:0] hdmi_out0_core_timinggenerator_sink_payload_hsync_end; +wire [11:0] hdmi_out0_core_timinggenerator_sink_payload_hscan; +wire [11:0] hdmi_out0_core_timinggenerator_sink_payload_vres; +wire [11:0] hdmi_out0_core_timinggenerator_sink_payload_vsync_start; +wire [11:0] hdmi_out0_core_timinggenerator_sink_payload_vsync_end; +wire [11:0] hdmi_out0_core_timinggenerator_sink_payload_vscan; +reg hdmi_out0_core_timinggenerator_source_valid = 1'd0; +reg hdmi_out0_core_timinggenerator_source_ready = 1'd0; +reg hdmi_out0_core_timinggenerator_source_last = 1'd0; +reg hdmi_out0_core_timinggenerator_source_payload_hsync = 1'd0; +reg hdmi_out0_core_timinggenerator_source_payload_vsync = 1'd0; +reg hdmi_out0_core_timinggenerator_source_payload_de = 1'd0; +reg hdmi_out0_core_timinggenerator_hactive = 1'd0; +reg hdmi_out0_core_timinggenerator_vactive = 1'd0; +reg hdmi_out0_core_timinggenerator_active = 1'd0; +reg [11:0] hdmi_out0_core_timinggenerator_hcounter = 12'd0; +reg [11:0] hdmi_out0_core_timinggenerator_vcounter = 12'd0; +wire hdmi_out0_core_dmareader_sink_valid; +reg hdmi_out0_core_dmareader_sink_ready = 1'd0; +wire [31:0] hdmi_out0_core_dmareader_sink_payload_base; +wire [31:0] hdmi_out0_core_dmareader_sink_payload_length; +wire hdmi_out0_core_dmareader_source_valid; +reg hdmi_out0_core_dmareader_source_ready = 1'd0; +wire hdmi_out0_core_dmareader_source_first; +wire hdmi_out0_core_dmareader_source_last; +wire [15:0] hdmi_out0_core_dmareader_source_payload_data; +reg hdmi_out0_core_dmareader_sink_sink_valid = 1'd0; +wire hdmi_out0_core_dmareader_sink_sink_ready; +wire [27:0] hdmi_out0_core_dmareader_sink_sink_payload_address; +wire hdmi_out0_core_dmareader_source_source_valid; +wire hdmi_out0_core_dmareader_source_source_ready; +wire hdmi_out0_core_dmareader_source_source_first; +wire hdmi_out0_core_dmareader_source_source_last; +wire [15:0] hdmi_out0_core_dmareader_source_source_payload_data; +wire hdmi_out0_core_dmareader_request_enable; +wire hdmi_out0_core_dmareader_request_issued; +wire hdmi_out0_core_dmareader_data_dequeued; +reg [9:0] hdmi_out0_core_dmareader_rsv_level = 10'd0; +wire hdmi_out0_core_dmareader_fifo_sink_valid; +wire hdmi_out0_core_dmareader_fifo_sink_ready; +wire hdmi_out0_core_dmareader_fifo_sink_first; +wire hdmi_out0_core_dmareader_fifo_sink_last; +wire [15:0] hdmi_out0_core_dmareader_fifo_sink_payload_data; +wire hdmi_out0_core_dmareader_fifo_source_valid; +wire hdmi_out0_core_dmareader_fifo_source_ready; +wire hdmi_out0_core_dmareader_fifo_source_first; +wire hdmi_out0_core_dmareader_fifo_source_last; +wire [15:0] hdmi_out0_core_dmareader_fifo_source_payload_data; +wire hdmi_out0_core_dmareader_fifo_re; +reg hdmi_out0_core_dmareader_fifo_readable = 1'd0; +wire hdmi_out0_core_dmareader_fifo_syncfifo_we; +wire hdmi_out0_core_dmareader_fifo_syncfifo_writable; +wire hdmi_out0_core_dmareader_fifo_syncfifo_re; +wire hdmi_out0_core_dmareader_fifo_syncfifo_readable; +wire [17:0] hdmi_out0_core_dmareader_fifo_syncfifo_din; +wire [17:0] hdmi_out0_core_dmareader_fifo_syncfifo_dout; +reg [9:0] hdmi_out0_core_dmareader_fifo_level0 = 10'd0; +reg hdmi_out0_core_dmareader_fifo_replace = 1'd0; +reg [8:0] hdmi_out0_core_dmareader_fifo_produce = 9'd0; +reg [8:0] hdmi_out0_core_dmareader_fifo_consume = 9'd0; +reg [8:0] hdmi_out0_core_dmareader_fifo_wrport_adr = 9'd0; +wire [17:0] hdmi_out0_core_dmareader_fifo_wrport_dat_r; +wire hdmi_out0_core_dmareader_fifo_wrport_we; +wire [17:0] hdmi_out0_core_dmareader_fifo_wrport_dat_w; +wire hdmi_out0_core_dmareader_fifo_do_read; +wire [8:0] hdmi_out0_core_dmareader_fifo_rdport_adr; +wire [17:0] hdmi_out0_core_dmareader_fifo_rdport_dat_r; +wire hdmi_out0_core_dmareader_fifo_rdport_re; +wire [9:0] hdmi_out0_core_dmareader_fifo_level1; +wire [15:0] hdmi_out0_core_dmareader_fifo_fifo_in_payload_data; +wire hdmi_out0_core_dmareader_fifo_fifo_in_first; +wire hdmi_out0_core_dmareader_fifo_fifo_in_last; +wire [15:0] hdmi_out0_core_dmareader_fifo_fifo_out_payload_data; +wire hdmi_out0_core_dmareader_fifo_fifo_out_first; +wire hdmi_out0_core_dmareader_fifo_fifo_out_last; +wire [27:0] hdmi_out0_core_dmareader_base; +wire [27:0] hdmi_out0_core_dmareader_length; +reg [27:0] hdmi_out0_core_dmareader_offset = 28'd0; +reg [31:0] hdmi_out0_core_dmareader_storage = 32'd0; +reg hdmi_out0_core_dmareader_re = 1'd0; +wire hdmi_out0_core_underflow_enable; +wire hdmi_out0_core_underflow_update; +reg [31:0] hdmi_out0_core_underflow_counter = 32'd0; +wire hdmi_out0_core_i; +wire hdmi_out0_core_o; +reg hdmi_out0_core_toggle_i = 1'd0; +wire hdmi_out0_core_toggle_o; +reg hdmi_out0_core_toggle_o_r = 1'd0; +wire hdmi_out0_driver_sink_sink_valid; +wire hdmi_out0_driver_sink_sink_ready; +wire hdmi_out0_driver_sink_sink_first; +wire hdmi_out0_driver_sink_sink_last; +wire [7:0] hdmi_out0_driver_sink_sink_payload_r; +wire [7:0] hdmi_out0_driver_sink_sink_payload_g; +wire [7:0] hdmi_out0_driver_sink_sink_payload_b; +wire hdmi_out0_driver_sink_sink_param_hsync; +wire hdmi_out0_driver_sink_sink_param_vsync; +wire hdmi_out0_driver_sink_sink_param_de; +(* dont_touch = "true" *) wire hdmi_out0_pix_clk; +wire hdmi_out0_pix_rst; +(* dont_touch = "true" *) wire hdmi_out0_pix5x_clk; +reg hdmi_out0_driver_s7hdmioutclocking_mmcm_reset_storage = 1'd0; +reg hdmi_out0_driver_s7hdmioutclocking_mmcm_reset_re = 1'd0; +wire hdmi_out0_driver_s7hdmioutclocking_mmcm_read_re; +wire hdmi_out0_driver_s7hdmioutclocking_mmcm_read_r; +wire hdmi_out0_driver_s7hdmioutclocking_mmcm_read_we; +reg hdmi_out0_driver_s7hdmioutclocking_mmcm_read_w = 1'd0; +wire hdmi_out0_driver_s7hdmioutclocking_mmcm_write_re; +wire hdmi_out0_driver_s7hdmioutclocking_mmcm_write_r; +wire hdmi_out0_driver_s7hdmioutclocking_mmcm_write_we; +reg hdmi_out0_driver_s7hdmioutclocking_mmcm_write_w = 1'd0; +reg hdmi_out0_driver_s7hdmioutclocking_mmcm_drdy_status = 1'd0; +wire hdmi_out0_driver_s7hdmioutclocking_mmcm_drdy_we; +wire hdmi_out0_driver_s7hdmioutclocking_mmcm_drdy_re; +reg [6:0] hdmi_out0_driver_s7hdmioutclocking_mmcm_adr_storage = 7'd0; +reg hdmi_out0_driver_s7hdmioutclocking_mmcm_adr_re = 1'd0; +reg [15:0] hdmi_out0_driver_s7hdmioutclocking_mmcm_dat_w_storage = 16'd0; +reg hdmi_out0_driver_s7hdmioutclocking_mmcm_dat_w_re = 1'd0; +wire [15:0] hdmi_out0_driver_s7hdmioutclocking_mmcm_dat_r_status; +wire hdmi_out0_driver_s7hdmioutclocking_mmcm_dat_r_we; +wire hdmi_out0_driver_s7hdmioutclocking_mmcm_dat_r_re; +wire hdmi_out0_driver_s7hdmioutclocking_mmcm_locked; +wire hdmi_out0_driver_s7hdmioutclocking_mmcm_fb; +wire hdmi_out0_driver_s7hdmioutclocking_mmcm_clk0; +wire hdmi_out0_driver_s7hdmioutclocking_mmcm_clk1; +wire hdmi_out0_driver_s7hdmioutclocking_mmcm_drdy; +wire [9:0] hdmi_out0_driver_s7hdmioutclocking_data0; +wire [9:0] hdmi_out0_driver_s7hdmioutclocking_data1; +reg hdmi_out0_driver_s7hdmioutclocking_ce = 1'd0; +wire [1:0] hdmi_out0_driver_s7hdmioutclocking_shift; +wire hdmi_out0_driver_s7hdmioutclocking_pad_se; +reg [9:0] hdmi_out0_driver_s7hdmioutclocking = 10'd31; +wire hdmi_out0_driver_hdmi_phy_sink_valid; +wire hdmi_out0_driver_hdmi_phy_sink_ready; +wire hdmi_out0_driver_hdmi_phy_sink_first; +wire hdmi_out0_driver_hdmi_phy_sink_last; +wire [7:0] hdmi_out0_driver_hdmi_phy_sink_payload_r; +wire [7:0] hdmi_out0_driver_hdmi_phy_sink_payload_g; +wire [7:0] hdmi_out0_driver_hdmi_phy_sink_payload_b; +wire hdmi_out0_driver_hdmi_phy_sink_param_hsync; +wire hdmi_out0_driver_hdmi_phy_sink_param_vsync; +wire hdmi_out0_driver_hdmi_phy_sink_param_de; +wire [7:0] hdmi_out0_driver_hdmi_phy_es0_d0; +wire [1:0] hdmi_out0_driver_hdmi_phy_es0_c; +wire hdmi_out0_driver_hdmi_phy_es0_de; +reg [9:0] hdmi_out0_driver_hdmi_phy_es0_out = 10'd0; +reg [7:0] hdmi_out0_driver_hdmi_phy_es0_d1 = 8'd0; +reg [3:0] hdmi_out0_driver_hdmi_phy_es0_n1d = 4'd0; +reg [8:0] hdmi_out0_driver_hdmi_phy_es0_q_m = 9'd0; +wire hdmi_out0_driver_hdmi_phy_es0_q_m8_n; +reg [8:0] hdmi_out0_driver_hdmi_phy_es0_q_m_r = 9'd0; +reg [3:0] hdmi_out0_driver_hdmi_phy_es0_n0q_m = 4'd0; +reg [3:0] hdmi_out0_driver_hdmi_phy_es0_n1q_m = 4'd0; +reg signed [5:0] hdmi_out0_driver_hdmi_phy_es0_cnt = 6'd0; +reg [1:0] hdmi_out0_driver_hdmi_phy_es0_new_c0 = 2'd0; +reg hdmi_out0_driver_hdmi_phy_es0_new_de0 = 1'd0; +reg [1:0] hdmi_out0_driver_hdmi_phy_es0_new_c1 = 2'd0; +reg hdmi_out0_driver_hdmi_phy_es0_new_de1 = 1'd0; +reg [1:0] hdmi_out0_driver_hdmi_phy_es0_new_c2 = 2'd0; +reg hdmi_out0_driver_hdmi_phy_es0_new_de2 = 1'd0; +wire [9:0] hdmi_out0_driver_hdmi_phy_es0_data; +reg hdmi_out0_driver_hdmi_phy_es0_ce = 1'd0; +wire [1:0] hdmi_out0_driver_hdmi_phy_es0_shift; +wire hdmi_out0_driver_hdmi_phy_es0_pad_se; +wire [7:0] hdmi_out0_driver_hdmi_phy_es1_d0; +wire [1:0] hdmi_out0_driver_hdmi_phy_es1_c; +wire hdmi_out0_driver_hdmi_phy_es1_de; +reg [9:0] hdmi_out0_driver_hdmi_phy_es1_out = 10'd0; +reg [7:0] hdmi_out0_driver_hdmi_phy_es1_d1 = 8'd0; +reg [3:0] hdmi_out0_driver_hdmi_phy_es1_n1d = 4'd0; +reg [8:0] hdmi_out0_driver_hdmi_phy_es1_q_m = 9'd0; +wire hdmi_out0_driver_hdmi_phy_es1_q_m8_n; +reg [8:0] hdmi_out0_driver_hdmi_phy_es1_q_m_r = 9'd0; +reg [3:0] hdmi_out0_driver_hdmi_phy_es1_n0q_m = 4'd0; +reg [3:0] hdmi_out0_driver_hdmi_phy_es1_n1q_m = 4'd0; +reg signed [5:0] hdmi_out0_driver_hdmi_phy_es1_cnt = 6'd0; +reg [1:0] hdmi_out0_driver_hdmi_phy_es1_new_c0 = 2'd0; +reg hdmi_out0_driver_hdmi_phy_es1_new_de0 = 1'd0; +reg [1:0] hdmi_out0_driver_hdmi_phy_es1_new_c1 = 2'd0; +reg hdmi_out0_driver_hdmi_phy_es1_new_de1 = 1'd0; +reg [1:0] hdmi_out0_driver_hdmi_phy_es1_new_c2 = 2'd0; +reg hdmi_out0_driver_hdmi_phy_es1_new_de2 = 1'd0; +wire [9:0] hdmi_out0_driver_hdmi_phy_es1_data; +reg hdmi_out0_driver_hdmi_phy_es1_ce = 1'd0; +wire [1:0] hdmi_out0_driver_hdmi_phy_es1_shift; +wire hdmi_out0_driver_hdmi_phy_es1_pad_se; +wire [7:0] hdmi_out0_driver_hdmi_phy_es2_d0; +wire [1:0] hdmi_out0_driver_hdmi_phy_es2_c; +wire hdmi_out0_driver_hdmi_phy_es2_de; +reg [9:0] hdmi_out0_driver_hdmi_phy_es2_out = 10'd0; +reg [7:0] hdmi_out0_driver_hdmi_phy_es2_d1 = 8'd0; +reg [3:0] hdmi_out0_driver_hdmi_phy_es2_n1d = 4'd0; +reg [8:0] hdmi_out0_driver_hdmi_phy_es2_q_m = 9'd0; +wire hdmi_out0_driver_hdmi_phy_es2_q_m8_n; +reg [8:0] hdmi_out0_driver_hdmi_phy_es2_q_m_r = 9'd0; +reg [3:0] hdmi_out0_driver_hdmi_phy_es2_n0q_m = 4'd0; +reg [3:0] hdmi_out0_driver_hdmi_phy_es2_n1q_m = 4'd0; +reg signed [5:0] hdmi_out0_driver_hdmi_phy_es2_cnt = 6'd0; +reg [1:0] hdmi_out0_driver_hdmi_phy_es2_new_c0 = 2'd0; +reg hdmi_out0_driver_hdmi_phy_es2_new_de0 = 1'd0; +reg [1:0] hdmi_out0_driver_hdmi_phy_es2_new_c1 = 2'd0; +reg hdmi_out0_driver_hdmi_phy_es2_new_de1 = 1'd0; +reg [1:0] hdmi_out0_driver_hdmi_phy_es2_new_c2 = 2'd0; +reg hdmi_out0_driver_hdmi_phy_es2_new_de2 = 1'd0; +wire [9:0] hdmi_out0_driver_hdmi_phy_es2_data; +reg hdmi_out0_driver_hdmi_phy_es2_ce = 1'd0; +wire [1:0] hdmi_out0_driver_hdmi_phy_es2_shift; +wire hdmi_out0_driver_hdmi_phy_es2_pad_se; +wire hdmi_out0_resetinserter_sink_sink_valid; +reg hdmi_out0_resetinserter_sink_sink_ready = 1'd0; +wire [7:0] hdmi_out0_resetinserter_sink_sink_payload_y; +wire [7:0] hdmi_out0_resetinserter_sink_sink_payload_cb_cr; +wire hdmi_out0_resetinserter_source_source_valid; +wire hdmi_out0_resetinserter_source_source_ready; +reg hdmi_out0_resetinserter_source_source_first = 1'd0; +reg hdmi_out0_resetinserter_source_source_last = 1'd0; +wire [7:0] hdmi_out0_resetinserter_source_source_payload_y; +wire [7:0] hdmi_out0_resetinserter_source_source_payload_cb; +wire [7:0] hdmi_out0_resetinserter_source_source_payload_cr; +reg hdmi_out0_resetinserter_y_fifo_sink_valid = 1'd0; +wire hdmi_out0_resetinserter_y_fifo_sink_ready; +reg hdmi_out0_resetinserter_y_fifo_sink_first = 1'd0; +reg hdmi_out0_resetinserter_y_fifo_sink_last = 1'd0; +reg [7:0] hdmi_out0_resetinserter_y_fifo_sink_payload_data = 8'd0; +wire hdmi_out0_resetinserter_y_fifo_source_valid; +wire hdmi_out0_resetinserter_y_fifo_source_ready; +wire hdmi_out0_resetinserter_y_fifo_source_first; +wire hdmi_out0_resetinserter_y_fifo_source_last; +wire [7:0] hdmi_out0_resetinserter_y_fifo_source_payload_data; +wire hdmi_out0_resetinserter_y_fifo_syncfifo_we; +wire hdmi_out0_resetinserter_y_fifo_syncfifo_writable; +wire hdmi_out0_resetinserter_y_fifo_syncfifo_re; +wire hdmi_out0_resetinserter_y_fifo_syncfifo_readable; +wire [9:0] hdmi_out0_resetinserter_y_fifo_syncfifo_din; +wire [9:0] hdmi_out0_resetinserter_y_fifo_syncfifo_dout; +reg [2:0] hdmi_out0_resetinserter_y_fifo_level = 3'd0; +reg hdmi_out0_resetinserter_y_fifo_replace = 1'd0; +reg [1:0] hdmi_out0_resetinserter_y_fifo_produce = 2'd0; +reg [1:0] hdmi_out0_resetinserter_y_fifo_consume = 2'd0; +reg [1:0] hdmi_out0_resetinserter_y_fifo_wrport_adr = 2'd0; +wire [9:0] hdmi_out0_resetinserter_y_fifo_wrport_dat_r; +wire hdmi_out0_resetinserter_y_fifo_wrport_we; +wire [9:0] hdmi_out0_resetinserter_y_fifo_wrport_dat_w; +wire hdmi_out0_resetinserter_y_fifo_do_read; +wire [1:0] hdmi_out0_resetinserter_y_fifo_rdport_adr; +wire [9:0] hdmi_out0_resetinserter_y_fifo_rdport_dat_r; +wire [7:0] hdmi_out0_resetinserter_y_fifo_fifo_in_payload_data; +wire hdmi_out0_resetinserter_y_fifo_fifo_in_first; +wire hdmi_out0_resetinserter_y_fifo_fifo_in_last; +wire [7:0] hdmi_out0_resetinserter_y_fifo_fifo_out_payload_data; +wire hdmi_out0_resetinserter_y_fifo_fifo_out_first; +wire hdmi_out0_resetinserter_y_fifo_fifo_out_last; +reg hdmi_out0_resetinserter_cb_fifo_sink_valid = 1'd0; +wire hdmi_out0_resetinserter_cb_fifo_sink_ready; +reg hdmi_out0_resetinserter_cb_fifo_sink_first = 1'd0; +reg hdmi_out0_resetinserter_cb_fifo_sink_last = 1'd0; +reg [7:0] hdmi_out0_resetinserter_cb_fifo_sink_payload_data = 8'd0; +wire hdmi_out0_resetinserter_cb_fifo_source_valid; +wire hdmi_out0_resetinserter_cb_fifo_source_ready; +wire hdmi_out0_resetinserter_cb_fifo_source_first; +wire hdmi_out0_resetinserter_cb_fifo_source_last; +wire [7:0] hdmi_out0_resetinserter_cb_fifo_source_payload_data; +wire hdmi_out0_resetinserter_cb_fifo_syncfifo_we; +wire hdmi_out0_resetinserter_cb_fifo_syncfifo_writable; +wire hdmi_out0_resetinserter_cb_fifo_syncfifo_re; +wire hdmi_out0_resetinserter_cb_fifo_syncfifo_readable; +wire [9:0] hdmi_out0_resetinserter_cb_fifo_syncfifo_din; +wire [9:0] hdmi_out0_resetinserter_cb_fifo_syncfifo_dout; +reg [2:0] hdmi_out0_resetinserter_cb_fifo_level = 3'd0; +reg hdmi_out0_resetinserter_cb_fifo_replace = 1'd0; +reg [1:0] hdmi_out0_resetinserter_cb_fifo_produce = 2'd0; +reg [1:0] hdmi_out0_resetinserter_cb_fifo_consume = 2'd0; +reg [1:0] hdmi_out0_resetinserter_cb_fifo_wrport_adr = 2'd0; +wire [9:0] hdmi_out0_resetinserter_cb_fifo_wrport_dat_r; +wire hdmi_out0_resetinserter_cb_fifo_wrport_we; +wire [9:0] hdmi_out0_resetinserter_cb_fifo_wrport_dat_w; +wire hdmi_out0_resetinserter_cb_fifo_do_read; +wire [1:0] hdmi_out0_resetinserter_cb_fifo_rdport_adr; +wire [9:0] hdmi_out0_resetinserter_cb_fifo_rdport_dat_r; +wire [7:0] hdmi_out0_resetinserter_cb_fifo_fifo_in_payload_data; +wire hdmi_out0_resetinserter_cb_fifo_fifo_in_first; +wire hdmi_out0_resetinserter_cb_fifo_fifo_in_last; +wire [7:0] hdmi_out0_resetinserter_cb_fifo_fifo_out_payload_data; +wire hdmi_out0_resetinserter_cb_fifo_fifo_out_first; +wire hdmi_out0_resetinserter_cb_fifo_fifo_out_last; +reg hdmi_out0_resetinserter_cr_fifo_sink_valid = 1'd0; +wire hdmi_out0_resetinserter_cr_fifo_sink_ready; +reg hdmi_out0_resetinserter_cr_fifo_sink_first = 1'd0; +reg hdmi_out0_resetinserter_cr_fifo_sink_last = 1'd0; +reg [7:0] hdmi_out0_resetinserter_cr_fifo_sink_payload_data = 8'd0; +wire hdmi_out0_resetinserter_cr_fifo_source_valid; +wire hdmi_out0_resetinserter_cr_fifo_source_ready; +wire hdmi_out0_resetinserter_cr_fifo_source_first; +wire hdmi_out0_resetinserter_cr_fifo_source_last; +wire [7:0] hdmi_out0_resetinserter_cr_fifo_source_payload_data; +wire hdmi_out0_resetinserter_cr_fifo_syncfifo_we; +wire hdmi_out0_resetinserter_cr_fifo_syncfifo_writable; +wire hdmi_out0_resetinserter_cr_fifo_syncfifo_re; +wire hdmi_out0_resetinserter_cr_fifo_syncfifo_readable; +wire [9:0] hdmi_out0_resetinserter_cr_fifo_syncfifo_din; +wire [9:0] hdmi_out0_resetinserter_cr_fifo_syncfifo_dout; +reg [2:0] hdmi_out0_resetinserter_cr_fifo_level = 3'd0; +reg hdmi_out0_resetinserter_cr_fifo_replace = 1'd0; +reg [1:0] hdmi_out0_resetinserter_cr_fifo_produce = 2'd0; +reg [1:0] hdmi_out0_resetinserter_cr_fifo_consume = 2'd0; +reg [1:0] hdmi_out0_resetinserter_cr_fifo_wrport_adr = 2'd0; +wire [9:0] hdmi_out0_resetinserter_cr_fifo_wrport_dat_r; +wire hdmi_out0_resetinserter_cr_fifo_wrport_we; +wire [9:0] hdmi_out0_resetinserter_cr_fifo_wrport_dat_w; +wire hdmi_out0_resetinserter_cr_fifo_do_read; +wire [1:0] hdmi_out0_resetinserter_cr_fifo_rdport_adr; +wire [9:0] hdmi_out0_resetinserter_cr_fifo_rdport_dat_r; +wire [7:0] hdmi_out0_resetinserter_cr_fifo_fifo_in_payload_data; +wire hdmi_out0_resetinserter_cr_fifo_fifo_in_first; +wire hdmi_out0_resetinserter_cr_fifo_fifo_in_last; +wire [7:0] hdmi_out0_resetinserter_cr_fifo_fifo_out_payload_data; +wire hdmi_out0_resetinserter_cr_fifo_fifo_out_first; +wire hdmi_out0_resetinserter_cr_fifo_fifo_out_last; +reg hdmi_out0_resetinserter_parity_in = 1'd0; +reg hdmi_out0_resetinserter_parity_out = 1'd0; +wire hdmi_out0_resetinserter_reset; +wire hdmi_out0_sink_valid; +wire hdmi_out0_sink_ready; +wire hdmi_out0_sink_first; +wire hdmi_out0_sink_last; +wire [7:0] hdmi_out0_sink_payload_y; +wire [7:0] hdmi_out0_sink_payload_cb; +wire [7:0] hdmi_out0_sink_payload_cr; +wire hdmi_out0_source_valid; +wire hdmi_out0_source_ready; +wire hdmi_out0_source_first; +wire hdmi_out0_source_last; +wire [7:0] hdmi_out0_source_payload_r; +wire [7:0] hdmi_out0_source_payload_g; +wire [7:0] hdmi_out0_source_payload_b; +wire [7:0] hdmi_out0_sink_y; +wire [7:0] hdmi_out0_sink_cb; +wire [7:0] hdmi_out0_sink_cr; +reg [7:0] hdmi_out0_source_r = 8'd0; +reg [7:0] hdmi_out0_source_g = 8'd0; +reg [7:0] hdmi_out0_source_b = 8'd0; +reg [7:0] hdmi_out0_record0_ycbcr_n_y = 8'd0; +reg [7:0] hdmi_out0_record0_ycbcr_n_cb = 8'd0; +reg [7:0] hdmi_out0_record0_ycbcr_n_cr = 8'd0; +reg [7:0] hdmi_out0_record1_ycbcr_n_y = 8'd0; +reg [7:0] hdmi_out0_record1_ycbcr_n_cb = 8'd0; +reg [7:0] hdmi_out0_record1_ycbcr_n_cr = 8'd0; +reg [7:0] hdmi_out0_record2_ycbcr_n_y = 8'd0; +reg [7:0] hdmi_out0_record2_ycbcr_n_cb = 8'd0; +reg [7:0] hdmi_out0_record2_ycbcr_n_cr = 8'd0; +reg [7:0] hdmi_out0_record3_ycbcr_n_y = 8'd0; +reg [7:0] hdmi_out0_record3_ycbcr_n_cb = 8'd0; +reg [7:0] hdmi_out0_record3_ycbcr_n_cr = 8'd0; +reg signed [8:0] hdmi_out0_cb_minus_coffset = 9'd0; +reg signed [8:0] hdmi_out0_cr_minus_coffset = 9'd0; +reg signed [8:0] hdmi_out0_y_minus_yoffset = 9'd0; +reg signed [19:0] hdmi_out0_cr_minus_coffset_mult_acoef = 20'd0; +reg signed [19:0] hdmi_out0_cb_minus_coffset_mult_bcoef = 20'd0; +reg signed [19:0] hdmi_out0_cr_minus_coffset_mult_ccoef = 20'd0; +reg signed [19:0] hdmi_out0_cb_minus_coffset_mult_dcoef = 20'd0; +reg signed [11:0] hdmi_out0_r = 12'd0; +reg signed [11:0] hdmi_out0_g = 12'd0; +reg signed [11:0] hdmi_out0_b = 12'd0; +wire hdmi_out0_ce; +wire hdmi_out0_pipe_ce; +wire hdmi_out0_busy; +reg hdmi_out0_valid_n0 = 1'd0; +reg hdmi_out0_valid_n1 = 1'd0; +reg hdmi_out0_valid_n2 = 1'd0; +reg hdmi_out0_valid_n3 = 1'd0; +reg hdmi_out0_first_n0 = 1'd0; +reg hdmi_out0_last_n0 = 1'd0; +reg hdmi_out0_first_n1 = 1'd0; +reg hdmi_out0_last_n1 = 1'd0; +reg hdmi_out0_first_n2 = 1'd0; +reg hdmi_out0_last_n2 = 1'd0; +reg hdmi_out0_first_n3 = 1'd0; +reg hdmi_out0_last_n3 = 1'd0; +wire hdmi_out0_sink_payload_hsync; +wire hdmi_out0_sink_payload_vsync; +wire hdmi_out0_sink_payload_de; +wire hdmi_out0_source_payload_hsync; +wire hdmi_out0_source_payload_vsync; +wire hdmi_out0_source_payload_de; +reg hdmi_out0_next_s0 = 1'd0; +reg hdmi_out0_next_s1 = 1'd0; +reg hdmi_out0_next_s2 = 1'd0; +reg hdmi_out0_next_s3 = 1'd0; +reg hdmi_out0_next_s4 = 1'd0; +reg hdmi_out0_next_s5 = 1'd0; +reg hdmi_out0_next_s6 = 1'd0; +reg hdmi_out0_next_s7 = 1'd0; +reg hdmi_out0_next_s8 = 1'd0; +reg hdmi_out0_next_s9 = 1'd0; +reg hdmi_out0_next_s10 = 1'd0; +reg hdmi_out0_next_s11 = 1'd0; +reg hdmi_out0_next_s12 = 1'd0; +reg hdmi_out0_next_s13 = 1'd0; +reg hdmi_out0_next_s14 = 1'd0; +reg hdmi_out0_next_s15 = 1'd0; +reg hdmi_out0_next_s16 = 1'd0; +reg hdmi_out0_next_s17 = 1'd0; +reg hdmi_out0_de_r = 1'd0; +reg hdmi_out0_core_source_valid_d = 1'd0; +reg [15:0] hdmi_out0_core_source_data_d = 16'd0; +wire pll_fb; +reg [1:0] s7spiflash_state = 2'd0; +reg [1:0] s7spiflash_next_state = 2'd0; +reg [5:0] flash_count_s7spiflash_next_value = 6'd0; +reg flash_count_s7spiflash_next_value_ce = 1'd0; +reg [1:0] litedramcore_refresher_state = 2'd0; +reg [1:0] litedramcore_refresher_next_state = 2'd0; +reg [3:0] litedramcore_bankmachine0_state = 4'd0; +reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine1_state = 4'd0; +reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine2_state = 4'd0; +reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine3_state = 4'd0; +reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine4_state = 4'd0; +reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine5_state = 4'd0; +reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine6_state = 4'd0; +reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine7_state = 4'd0; +reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; +reg [3:0] litedramcore_multiplexer_state = 4'd0; +reg [3:0] litedramcore_multiplexer_next_state = 4'd0; +reg [1:0] litedramcore_state = 2'd0; +reg [1:0] litedramcore_next_state = 2'd0; +reg [27:0] litedramcrossbar_cmd_addr_litedramcore_next_value0 = 28'd0; +reg litedramcrossbar_cmd_addr_litedramcore_next_value_ce0 = 1'd0; +reg litedramcrossbar_cmd_we_litedramcore_next_value1 = 1'd0; +reg litedramcrossbar_cmd_we_litedramcore_next_value_ce1 = 1'd0; +reg litedramcrossbar_cmd_last_litedramcore_next_value2 = 1'd0; +reg litedramcrossbar_cmd_last_litedramcore_next_value_ce2 = 1'd0; +reg [15:0] litedramcrossbar_sel_litedramcore_next_value3 = 16'd0; +reg litedramcrossbar_sel_litedramcore_next_value_ce3 = 1'd0; +wire [2:0] litedramcore_roundrobin0_request; +reg [1:0] litedramcore_roundrobin0_grant = 2'd0; +wire litedramcore_roundrobin0_ce; +wire [2:0] litedramcore_roundrobin1_request; +reg [1:0] litedramcore_roundrobin1_grant = 2'd0; +wire litedramcore_roundrobin1_ce; +wire [2:0] litedramcore_roundrobin2_request; +reg [1:0] litedramcore_roundrobin2_grant = 2'd0; +wire litedramcore_roundrobin2_ce; +wire [2:0] litedramcore_roundrobin3_request; +reg [1:0] litedramcore_roundrobin3_grant = 2'd0; +wire litedramcore_roundrobin3_ce; +wire [2:0] litedramcore_roundrobin4_request; +reg [1:0] litedramcore_roundrobin4_grant = 2'd0; +wire litedramcore_roundrobin4_ce; +wire [2:0] litedramcore_roundrobin5_request; +reg [1:0] litedramcore_roundrobin5_grant = 2'd0; +wire litedramcore_roundrobin5_ce; +wire [2:0] litedramcore_roundrobin6_request; +reg [1:0] litedramcore_roundrobin6_grant = 2'd0; +wire litedramcore_roundrobin6_ce; +wire [2:0] litedramcore_roundrobin7_request; +reg [1:0] litedramcore_roundrobin7_grant = 2'd0; +wire litedramcore_roundrobin7_ce; +reg litedramcore_locked0 = 1'd0; +reg litedramcore_locked1 = 1'd0; +reg litedramcore_locked2 = 1'd0; +reg litedramcore_locked3 = 1'd0; +reg litedramcore_locked4 = 1'd0; +reg litedramcore_locked5 = 1'd0; +reg litedramcore_locked6 = 1'd0; +reg litedramcore_locked7 = 1'd0; +reg litedramcore_locked8 = 1'd0; +reg litedramcore_locked9 = 1'd0; +reg litedramcore_locked10 = 1'd0; +reg litedramcore_locked11 = 1'd0; +reg litedramcore_locked12 = 1'd0; +reg litedramcore_locked13 = 1'd0; +reg litedramcore_locked14 = 1'd0; +reg litedramcore_locked15 = 1'd0; +reg litedramcore_locked16 = 1'd0; +reg litedramcore_locked17 = 1'd0; +reg litedramcore_locked18 = 1'd0; +reg litedramcore_locked19 = 1'd0; +reg litedramcore_locked20 = 1'd0; +reg litedramcore_locked21 = 1'd0; +reg litedramcore_locked22 = 1'd0; +reg litedramcore_locked23 = 1'd0; +reg litedramcore_new_master_wdata_ready0 = 1'd0; +reg litedramcore_new_master_wdata_ready1 = 1'd0; +reg litedramcore_new_master_wdata_ready2 = 1'd0; +reg litedramcore_new_master_wdata_ready3 = 1'd0; +reg litedramcore_new_master_wdata_ready4 = 1'd0; +reg litedramcore_new_master_wdata_ready5 = 1'd0; +reg litedramcore_new_master_rdata_valid0 = 1'd0; +reg litedramcore_new_master_rdata_valid1 = 1'd0; +reg litedramcore_new_master_rdata_valid2 = 1'd0; +reg litedramcore_new_master_rdata_valid3 = 1'd0; +reg litedramcore_new_master_rdata_valid4 = 1'd0; +reg litedramcore_new_master_rdata_valid5 = 1'd0; +reg litedramcore_new_master_rdata_valid6 = 1'd0; +reg litedramcore_new_master_rdata_valid7 = 1'd0; +reg litedramcore_new_master_rdata_valid8 = 1'd0; +reg litedramcore_new_master_rdata_valid9 = 1'd0; +reg litedramcore_new_master_rdata_valid10 = 1'd0; +reg litedramcore_new_master_rdata_valid11 = 1'd0; +reg litedramcore_new_master_rdata_valid12 = 1'd0; +reg litedramcore_new_master_rdata_valid13 = 1'd0; +reg litedramcore_new_master_rdata_valid14 = 1'd0; +reg litedramcore_new_master_rdata_valid15 = 1'd0; +reg litedramcore_new_master_rdata_valid16 = 1'd0; +reg litedramcore_new_master_rdata_valid17 = 1'd0; +reg litedramcore_new_master_rdata_valid18 = 1'd0; +reg litedramcore_new_master_rdata_valid19 = 1'd0; +reg litedramcore_new_master_rdata_valid20 = 1'd0; +reg litedramcore_new_master_rdata_valid21 = 1'd0; +reg litedramcore_new_master_rdata_valid22 = 1'd0; +reg litedramcore_new_master_rdata_valid23 = 1'd0; +reg litedramcore_new_master_rdata_valid24 = 1'd0; +reg litedramcore_new_master_rdata_valid25 = 1'd0; +reg litedramcore_new_master_rdata_valid26 = 1'd0; +reg [1:0] fullmemorywe_state = 2'd0; +reg [1:0] fullmemorywe_next_state = 2'd0; +reg liteethphyrmii_state = 1'd0; +reg liteethphyrmii_next_state = 1'd0; +reg liteethudpipcore_liteethmac_liteethmacgap_state = 1'd0; +reg liteethudpipcore_liteethmac_liteethmacgap_next_state = 1'd0; +reg [3:0] ethcore_mac_tx_gap_inserter_counter_liteethmacgap_next_value = 4'd0; +reg ethcore_mac_tx_gap_inserter_counter_liteethmacgap_next_value_ce = 1'd0; +reg [1:0] liteethudpipcore_liteethmac_liteethmacpreambleinserter_state = 2'd0; +reg [1:0] liteethudpipcore_liteethmac_liteethmacpreambleinserter_next_state = 2'd0; +reg [2:0] ethcore_mac_preamble_inserter_count_liteethmacpreambleinserter_next_value = 3'd0; +reg ethcore_mac_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce = 1'd0; +reg liteethudpipcore_liteethmac_liteethmacpreamblechecker_state = 1'd0; +reg liteethudpipcore_liteethmac_liteethmacpreamblechecker_next_state = 1'd0; +reg [1:0] liteethudpipcore_liteethmac_liteethmaccrc32inserter_state = 2'd0; +reg [1:0] liteethudpipcore_liteethmac_liteethmaccrc32inserter_next_state = 2'd0; +reg [1:0] liteethudpipcore_liteethmac_liteethmaccrc32checker_state = 2'd0; +reg [1:0] liteethudpipcore_liteethmac_liteethmaccrc32checker_next_state = 2'd0; +reg liteethudpipcore_liteethmac_liteethmacpaddinginserter_state = 1'd0; +reg liteethudpipcore_liteethmac_liteethmacpaddinginserter_next_state = 1'd0; +reg [15:0] ethcore_mac_padding_inserter_counter_liteethmacpaddinginserter_next_value = 16'd0; +reg ethcore_mac_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce = 1'd0; +reg [1:0] liteethudpipcore_liteethmac_request = 2'd0; +reg liteethudpipcore_liteethmac_grant = 1'd0; +reg liteethudpipcore_liteethmac_status0_first = 1'd1; +reg liteethudpipcore_liteethmac_status0_last = 1'd0; +wire liteethudpipcore_liteethmac_status0_ongoing0; +reg liteethudpipcore_liteethmac_status0_ongoing1 = 1'd0; +reg liteethudpipcore_liteethmac_status1_first = 1'd1; +reg liteethudpipcore_liteethmac_status1_last = 1'd0; +wire liteethudpipcore_liteethmac_status1_ongoing0; +reg liteethudpipcore_liteethmac_status1_ongoing1 = 1'd0; +reg [1:0] liteethudpipcore_liteethmac_sel0 = 2'd0; +reg liteethudpipcore_liteethmac_first = 1'd1; +reg liteethudpipcore_liteethmac_last = 1'd0; +wire liteethudpipcore_liteethmac_ongoing0; +reg liteethudpipcore_liteethmac_ongoing1 = 1'd0; +reg [1:0] liteethudpipcore_liteethmac_sel1 = 2'd0; +reg [1:0] liteethudpipcore_liteethmac_sel_ongoing = 2'd0; +reg [1:0] liteethudpipcore_liteethmac_liteethmacpacketizer_state = 2'd0; +reg [1:0] liteethudpipcore_liteethmac_liteethmacpacketizer_next_state = 2'd0; +reg [3:0] ethcore_mac_packetizer_count_liteethmacpacketizer_next_value0 = 4'd0; +reg ethcore_mac_packetizer_count_liteethmacpacketizer_next_value_ce0 = 1'd0; +reg ethcore_mac_packetizer_fsm_from_idle_liteethmacpacketizer_next_value1 = 1'd0; +reg ethcore_mac_packetizer_fsm_from_idle_liteethmacpacketizer_next_value_ce1 = 1'd0; +reg [1:0] liteethudpipcore_liteethmac_liteethmacdepacketizer_state = 2'd0; +reg [1:0] liteethudpipcore_liteethmac_liteethmacdepacketizer_next_state = 2'd0; +reg [3:0] ethcore_mac_depacketizer_count_liteethmacdepacketizer_next_value0 = 4'd0; +reg ethcore_mac_depacketizer_count_liteethmacdepacketizer_next_value_ce0 = 1'd0; +reg ethcore_mac_depacketizer_fsm_from_idle_liteethmacdepacketizer_next_value1 = 1'd0; +reg ethcore_mac_depacketizer_fsm_from_idle_liteethmacdepacketizer_next_value_ce1 = 1'd0; +reg [1:0] liteethudpipcore_liteetharptx_liteetharppacketizer_state = 2'd0; +reg [1:0] liteethudpipcore_liteetharptx_liteetharppacketizer_next_state = 2'd0; +reg [4:0] ethcore_arp_tx_packetizer_count_liteetharp_liteetharppacketizer_next_value0 = 5'd0; +reg ethcore_arp_tx_packetizer_count_liteetharp_liteetharppacketizer_next_value_ce0 = 1'd0; +reg ethcore_arp_tx_packetizer_fsm_from_idle_liteetharp_liteetharppacketizer_next_value1 = 1'd0; +reg ethcore_arp_tx_packetizer_fsm_from_idle_liteetharp_liteetharppacketizer_next_value_ce1 = 1'd0; +reg liteethudpipcore_liteetharptx_fsm_state = 1'd0; +reg liteethudpipcore_liteetharptx_fsm_next_state = 1'd0; +reg [5:0] ethcore_arp_tx_counter_liteetharp_fsm_next_value = 6'd0; +reg ethcore_arp_tx_counter_liteetharp_fsm_next_value_ce = 1'd0; +reg [1:0] liteethudpipcore_liteetharprx_liteetharpdepacketizer_state = 2'd0; +reg [1:0] liteethudpipcore_liteetharprx_liteetharpdepacketizer_next_state = 2'd0; +reg [4:0] ethcore_arp_rx_depacketizer_count_liteetharp_next_value0 = 5'd0; +reg ethcore_arp_rx_depacketizer_count_liteetharp_next_value_ce0 = 1'd0; +reg ethcore_arp_rx_depacketizer_fsm_from_idle_liteetharp_next_value1 = 1'd0; +reg ethcore_arp_rx_depacketizer_fsm_from_idle_liteetharp_next_value_ce1 = 1'd0; +reg [1:0] liteethudpipcore_liteetharprx_fsm_state = 2'd0; +reg [1:0] liteethudpipcore_liteetharprx_fsm_next_state = 2'd0; +reg [2:0] liteethudpipcore_state = 3'd0; +reg [2:0] liteethudpipcore_next_state = 3'd0; +reg [1:0] liteethudpipcore_liteethip_liteethiptx_liteethipv4packetizer_state = 2'd0; +reg [1:0] liteethudpipcore_liteethip_liteethiptx_liteethipv4packetizer_next_state = 2'd0; +reg [4:0] ethcore_ip_tx_packetizer_count_liteethip_liteethipv4packetizer_next_value0 = 5'd0; +reg ethcore_ip_tx_packetizer_count_liteethip_liteethipv4packetizer_next_value_ce0 = 1'd0; +reg ethcore_ip_tx_packetizer_fsm_from_idle_liteethip_liteethipv4packetizer_next_value1 = 1'd0; +reg ethcore_ip_tx_packetizer_fsm_from_idle_liteethip_liteethipv4packetizer_next_value_ce1 = 1'd0; +reg [2:0] liteethudpipcore_liteethip_liteethiptx_fsm_state = 3'd0; +reg [2:0] liteethudpipcore_liteethip_liteethiptx_fsm_next_state = 3'd0; +reg [47:0] ethcore_ip_tx_target_mac_liteethip_fsm_next_value = 48'd0; +reg ethcore_ip_tx_target_mac_liteethip_fsm_next_value_ce = 1'd0; +reg [1:0] liteethudpipcore_liteethip_liteethiprx_liteethipv4depacketizer_state = 2'd0; +reg [1:0] liteethudpipcore_liteethip_liteethiprx_liteethipv4depacketizer_next_state = 2'd0; +reg [4:0] ethcore_ip_rx_depacketizer_count_liteethip_next_value0 = 5'd0; +reg ethcore_ip_rx_depacketizer_count_liteethip_next_value_ce0 = 1'd0; +reg ethcore_ip_rx_depacketizer_fsm_from_idle_liteethip_next_value1 = 1'd0; +reg ethcore_ip_rx_depacketizer_fsm_from_idle_liteethip_next_value_ce1 = 1'd0; +reg [1:0] liteethudpipcore_liteethip_liteethiprx_fsm_state = 2'd0; +reg [1:0] liteethudpipcore_liteethip_liteethiprx_fsm_next_state = 2'd0; +reg [1:0] liteethudpipcore_liteethip_request = 2'd0; +reg liteethudpipcore_liteethip_grant = 1'd0; +reg liteethudpipcore_liteethip_status0_first = 1'd1; +reg liteethudpipcore_liteethip_status0_last = 1'd0; +wire liteethudpipcore_liteethip_status0_ongoing0; +reg liteethudpipcore_liteethip_status0_ongoing1 = 1'd0; +reg liteethudpipcore_liteethip_status1_first = 1'd1; +reg liteethudpipcore_liteethip_status1_last = 1'd0; +wire liteethudpipcore_liteethip_status1_ongoing0; +reg liteethudpipcore_liteethip_status1_ongoing1 = 1'd0; +reg [1:0] liteethudpipcore_liteethip_sel0 = 2'd0; +reg liteethudpipcore_liteethip_first = 1'd1; +reg liteethudpipcore_liteethip_last = 1'd0; +wire liteethudpipcore_liteethip_ongoing0; +reg liteethudpipcore_liteethip_ongoing1 = 1'd0; +reg [1:0] liteethudpipcore_liteethip_sel1 = 2'd0; +reg [1:0] liteethudpipcore_liteethip_sel_ongoing = 2'd0; +reg [1:0] liteethudpipcore_liteethicmptx_liteethicmppacketizer_state = 2'd0; +reg [1:0] liteethudpipcore_liteethicmptx_liteethicmppacketizer_next_state = 2'd0; +reg [2:0] ethcore_icmp_tx_packetizer_count_liteethicmptx_next_value0 = 3'd0; +reg ethcore_icmp_tx_packetizer_count_liteethicmptx_next_value_ce0 = 1'd0; +reg ethcore_icmp_tx_packetizer_fsm_from_idle_liteethicmptx_next_value1 = 1'd0; +reg ethcore_icmp_tx_packetizer_fsm_from_idle_liteethicmptx_next_value_ce1 = 1'd0; +reg liteethudpipcore_liteethicmptx_fsm_state = 1'd0; +reg liteethudpipcore_liteethicmptx_fsm_next_state = 1'd0; +reg [1:0] liteethudpipcore_liteethicmprx_liteethicmpdepacketizer_state = 2'd0; +reg [1:0] liteethudpipcore_liteethicmprx_liteethicmpdepacketizer_next_state = 2'd0; +reg [2:0] ethcore_icmp_rx_depacketizer_count_liteethicmprx_next_value0 = 3'd0; +reg ethcore_icmp_rx_depacketizer_count_liteethicmprx_next_value_ce0 = 1'd0; +reg ethcore_icmp_rx_depacketizer_fsm_from_idle_liteethicmprx_next_value1 = 1'd0; +reg ethcore_icmp_rx_depacketizer_fsm_from_idle_liteethicmprx_next_value_ce1 = 1'd0; +reg [1:0] liteethudpipcore_liteethicmprx_fsm_state = 2'd0; +reg [1:0] liteethudpipcore_liteethicmprx_fsm_next_state = 2'd0; +reg [1:0] liteethudpipcore_liteethudp_liteethudptx_liteethudppacketizer_state = 2'd0; +reg [1:0] liteethudpipcore_liteethudp_liteethudptx_liteethudppacketizer_next_state = 2'd0; +reg [2:0] ethcore_tx_packetizer_count_liteethudptx_next_value0 = 3'd0; +reg ethcore_tx_packetizer_count_liteethudptx_next_value_ce0 = 1'd0; +reg ethcore_tx_packetizer_fsm_from_idle_liteethudptx_next_value1 = 1'd0; +reg ethcore_tx_packetizer_fsm_from_idle_liteethudptx_next_value_ce1 = 1'd0; +reg liteethudpipcore_liteethudp_liteethudptx_fsm_state = 1'd0; +reg liteethudpipcore_liteethudp_liteethudptx_fsm_next_state = 1'd0; +reg [1:0] liteethudpipcore_liteethudp_liteethudprx_liteethudpdepacketizer_state = 2'd0; +reg [1:0] liteethudpipcore_liteethudp_liteethudprx_liteethudpdepacketizer_next_state = 2'd0; +reg [2:0] ethcore_rx_depacketizer_count_liteethudprx_next_value0 = 3'd0; +reg ethcore_rx_depacketizer_count_liteethudprx_next_value_ce0 = 1'd0; +reg ethcore_rx_depacketizer_fsm_from_idle_liteethudprx_next_value1 = 1'd0; +reg ethcore_rx_depacketizer_fsm_from_idle_liteethudprx_next_value_ce1 = 1'd0; +reg [1:0] liteethudpipcore_liteethudp_liteethudprx_fsm_state = 2'd0; +reg [1:0] liteethudpipcore_liteethudp_liteethudprx_fsm_next_state = 2'd0; +reg liteethudpipcore_liteethudp_sel = 1'd0; +reg [1:0] liteethetherbonepackettx_liteethetherbonepacketpacketizer_state = 2'd0; +reg [1:0] liteethetherbonepackettx_liteethetherbonepacketpacketizer_next_state = 2'd0; +reg etherbone_tx_packetizer_count_liteethetherbonepackettx_next_value0 = 1'd0; +reg etherbone_tx_packetizer_count_liteethetherbonepackettx_next_value_ce0 = 1'd0; +reg etherbone_tx_packetizer_fsm_from_idle_liteethetherbonepackettx_next_value1 = 1'd0; +reg etherbone_tx_packetizer_fsm_from_idle_liteethetherbonepackettx_next_value_ce1 = 1'd0; +reg liteethetherbonepackettx_fsm_state = 1'd0; +reg liteethetherbonepackettx_fsm_next_state = 1'd0; +reg [1:0] liteethetherbonepacketrx_liteethetherbonepacketdepacketizer_state = 2'd0; +reg [1:0] liteethetherbonepacketrx_liteethetherbonepacketdepacketizer_next_state = 2'd0; +reg etherbone_rx_depacketizer_count_liteethetherbonepacketrx_next_value0 = 1'd0; +reg etherbone_rx_depacketizer_count_liteethetherbonepacketrx_next_value_ce0 = 1'd0; +reg etherbone_rx_depacketizer_fsm_from_idle_liteethetherbonepacketrx_next_value1 = 1'd0; +reg etherbone_rx_depacketizer_fsm_from_idle_liteethetherbonepacketrx_next_value_ce1 = 1'd0; +reg [1:0] liteethetherbonepacketrx_fsm_state = 2'd0; +reg [1:0] liteethetherbonepacketrx_fsm_next_state = 2'd0; +reg liteethetherboneprobe_state = 1'd0; +reg liteethetherboneprobe_next_state = 1'd0; +reg [1:0] liteethetherbonerecorddepacketizer_state = 2'd0; +reg [1:0] liteethetherbonerecorddepacketizer_next_state = 2'd0; +reg etherbone_record_depacketizer_count_liteethetherbonerecorddepacketizer_next_value0 = 1'd0; +reg etherbone_record_depacketizer_count_liteethetherbonerecorddepacketizer_next_value_ce0 = 1'd0; +reg etherbone_record_depacketizer_fsm_from_idle_liteethetherbonerecorddepacketizer_next_value1 = 1'd0; +reg etherbone_record_depacketizer_fsm_from_idle_liteethetherbonerecorddepacketizer_next_value_ce1 = 1'd0; +reg [1:0] liteethetherbonerecordreceiver_state = 2'd0; +reg [1:0] liteethetherbonerecordreceiver_next_state = 2'd0; +reg [1:0] liteethetherbonerecordsender_state = 2'd0; +reg [1:0] liteethetherbonerecordsender_next_state = 2'd0; +reg [1:0] liteethetherbonerecordpacketizer_state = 2'd0; +reg [1:0] liteethetherbonerecordpacketizer_next_state = 2'd0; +reg etherbone_record_packetizer_count_liteethetherbonerecordpacketizer_next_value0 = 1'd0; +reg etherbone_record_packetizer_count_liteethetherbonerecordpacketizer_next_value_ce0 = 1'd0; +reg etherbone_record_packetizer_fsm_from_idle_liteethetherbonerecordpacketizer_next_value1 = 1'd0; +reg etherbone_record_packetizer_fsm_from_idle_liteethetherbonerecordpacketizer_next_value_ce1 = 1'd0; +reg [1:0] liteethetherbonewishbonemaster_state = 2'd0; +reg [1:0] liteethetherbonewishbonemaster_next_state = 2'd0; +reg [1:0] litepcietlpdepacketizer_state = 2'd0; +reg [1:0] litepcietlpdepacketizer_next_state = 2'd0; +reg depacketizer_header_extracter_first_litepcietlpdepacketizer_next_value0 = 1'd0; +reg depacketizer_header_extracter_first_litepcietlpdepacketizer_next_value_ce0 = 1'd0; +reg depacketizer_header_extracter_last_litepcietlpdepacketizer_next_value1 = 1'd0; +reg depacketizer_header_extracter_last_litepcietlpdepacketizer_next_value_ce1 = 1'd0; +reg depacketizer_header_extracter_count_litepcietlpdepacketizer_next_value2 = 1'd0; +reg depacketizer_header_extracter_count_litepcietlpdepacketizer_next_value_ce2 = 1'd0; +reg [31:0] litepcietlpdepacketizer_next_value0 = 32'd0; +reg litepcietlpdepacketizer_next_value_ce0 = 1'd0; +reg [31:0] litepcietlpdepacketizer_next_value1 = 32'd0; +reg litepcietlpdepacketizer_next_value_ce1 = 1'd0; +reg [31:0] litepcietlpdepacketizer_next_value2 = 32'd0; +reg litepcietlpdepacketizer_next_value_ce2 = 1'd0; +reg [31:0] litepcietlpdepacketizer_next_value3 = 32'd0; +reg litepcietlpdepacketizer_next_value_ce3 = 1'd0; +reg [1:0] litepcietlppacketizer_state = 2'd0; +reg [1:0] litepcietlppacketizer_next_state = 2'd0; +wire sel; +reg master_in_sink_valid = 1'd0; +reg master_in_sink_ready = 1'd0; +reg master_in_sink_first = 1'd0; +reg master_in_sink_last = 1'd0; +reg master_in_sink_payload_we = 1'd0; +reg [31:0] master_in_sink_payload_adr = 32'd0; +reg [9:0] master_in_sink_payload_len = 10'd0; +reg [15:0] master_in_sink_payload_req_id = 16'd0; +reg [7:0] master_in_sink_payload_tag = 8'd0; +reg [63:0] master_in_sink_payload_dat = 64'd0; +reg [7:0] master_in_sink_payload_channel = 8'd0; +reg [7:0] master_in_sink_payload_user_id = 8'd0; +reg master_in_source_valid = 1'd0; +reg master_in_source_ready = 1'd0; +reg master_in_source_first = 1'd0; +reg master_in_source_last = 1'd0; +reg [31:0] master_in_source_payload_adr = 32'd0; +reg [9:0] master_in_source_payload_len = 10'd0; +reg master_in_source_payload_end = 1'd0; +reg [15:0] master_in_source_payload_req_id = 16'd0; +reg [15:0] master_in_source_payload_cmp_id = 16'd0; +reg master_in_source_payload_err = 1'd0; +reg [7:0] master_in_source_payload_tag = 8'd0; +reg [63:0] master_in_source_payload_dat = 64'd0; +reg [7:0] master_in_source_payload_channel = 8'd0; +reg [7:0] master_in_source_payload_user_id = 8'd0; +reg master_out_sink_valid = 1'd0; +reg master_out_sink_ready = 1'd0; +wire master_out_sink_first; +wire master_out_sink_last; +wire master_out_sink_payload_we; +wire [31:0] master_out_sink_payload_adr; +wire [9:0] master_out_sink_payload_len; +wire [15:0] master_out_sink_payload_req_id; +reg [7:0] master_out_sink_payload_tag = 8'd0; +wire [63:0] master_out_sink_payload_dat; +wire [7:0] master_out_sink_payload_channel; +wire [7:0] master_out_sink_payload_user_id; +wire master_out_source_valid; +reg master_out_source_ready = 1'd0; +wire master_out_source_first; +wire master_out_source_last; +wire [31:0] master_out_source_payload_adr; +wire [9:0] master_out_source_payload_len; +wire master_out_source_payload_end; +wire [15:0] master_out_source_payload_req_id; +wire [15:0] master_out_source_payload_cmp_id; +wire master_out_source_payload_err; +wire [7:0] master_out_source_payload_tag; +wire [63:0] master_out_source_payload_dat; +wire [7:0] master_out_source_payload_channel; +wire [7:0] master_out_source_payload_user_id; +reg tags_queue_sink_valid = 1'd0; +wire tags_queue_sink_ready; +reg tags_queue_sink_first = 1'd0; +reg tags_queue_sink_last = 1'd0; +reg [1:0] tags_queue_sink_payload_tag = 2'd0; +wire tags_queue_source_valid; +reg tags_queue_source_ready = 1'd0; +wire tags_queue_source_first; +wire tags_queue_source_last; +wire [1:0] tags_queue_source_payload_tag; +wire tags_queue_re; +reg tags_queue_readable = 1'd0; +wire tags_queue_syncfifo_we; +wire tags_queue_syncfifo_writable; +wire tags_queue_syncfifo_re; +wire tags_queue_syncfifo_readable; +wire [3:0] tags_queue_syncfifo_din; +wire [3:0] tags_queue_syncfifo_dout; +reg [2:0] tags_queue_level0 = 3'd0; +reg tags_queue_replace = 1'd0; +reg [1:0] tags_queue_produce = 2'd0; +reg [1:0] tags_queue_consume = 2'd0; +reg [1:0] tags_queue_wrport_adr = 2'd0; +wire [3:0] tags_queue_wrport_dat_r; +wire tags_queue_wrport_we; +wire [3:0] tags_queue_wrport_dat_w; +wire tags_queue_do_read; +wire [1:0] tags_queue_rdport_adr; +wire [3:0] tags_queue_rdport_dat_r; +wire tags_queue_rdport_re; +wire [2:0] tags_queue_level1; +wire [1:0] tags_queue_fifo_in_payload_tag; +wire tags_queue_fifo_in_first; +wire tags_queue_fifo_in_last; +wire [1:0] tags_queue_fifo_out_payload_tag; +wire tags_queue_fifo_out_first; +wire tags_queue_fifo_out_last; +reg requests_queue_sink_valid = 1'd0; +wire requests_queue_sink_ready; +reg requests_queue_sink_first = 1'd0; +reg requests_queue_sink_last = 1'd0; +wire [1:0] requests_queue_sink_payload_tag; +wire [7:0] requests_queue_sink_payload_channel; +wire [7:0] requests_queue_sink_payload_user_id; +wire requests_queue_source_valid; +reg requests_queue_source_ready = 1'd0; +wire requests_queue_source_first; +wire requests_queue_source_last; +wire [1:0] requests_queue_source_payload_tag; +wire [7:0] requests_queue_source_payload_channel; +wire [7:0] requests_queue_source_payload_user_id; +wire requests_queue_re; +reg requests_queue_readable = 1'd0; +wire requests_queue_syncfifo_we; +wire requests_queue_syncfifo_writable; +wire requests_queue_syncfifo_re; +wire requests_queue_syncfifo_readable; +wire [19:0] requests_queue_syncfifo_din; +wire [19:0] requests_queue_syncfifo_dout; +reg [2:0] requests_queue_level0 = 3'd0; +reg requests_queue_replace = 1'd0; +reg [1:0] requests_queue_produce = 2'd0; +reg [1:0] requests_queue_consume = 2'd0; +reg [1:0] requests_queue_wrport_adr = 2'd0; +wire [19:0] requests_queue_wrport_dat_r; +wire requests_queue_wrport_we; +wire [19:0] requests_queue_wrport_dat_w; +wire requests_queue_do_read; +wire [1:0] requests_queue_rdport_adr; +wire [19:0] requests_queue_rdport_dat_r; +wire requests_queue_rdport_re; +wire [2:0] requests_queue_level1; +wire [1:0] requests_queue_fifo_in_payload_tag; +wire [7:0] requests_queue_fifo_in_payload_channel; +wire [7:0] requests_queue_fifo_in_payload_user_id; +wire requests_queue_fifo_in_first; +wire requests_queue_fifo_in_last; +wire [1:0] requests_queue_fifo_out_payload_tag; +wire [7:0] requests_queue_fifo_out_payload_channel; +wire [7:0] requests_queue_fifo_out_payload_user_id; +wire requests_queue_fifo_out_first; +wire requests_queue_fifo_out_last; +reg cmp_reorder_valid = 1'd0; +reg cmp_reorder_ready = 1'd0; +wire cmp_reorder_first; +wire cmp_reorder_last; +wire [31:0] cmp_reorder_payload_adr; +wire [9:0] cmp_reorder_payload_len; +wire cmp_reorder_payload_end; +wire [15:0] cmp_reorder_payload_req_id; +wire [15:0] cmp_reorder_payload_cmp_id; +wire cmp_reorder_payload_err; +wire [7:0] cmp_reorder_payload_tag; +wire [63:0] cmp_reorder_payload_dat; +wire [7:0] cmp_reorder_payload_channel; +wire [7:0] cmp_reorder_payload_user_id; +reg syncfifo0_sink_valid = 1'd0; +wire syncfifo0_sink_ready; +reg syncfifo0_sink_first = 1'd0; +reg syncfifo0_sink_last = 1'd0; +reg [31:0] syncfifo0_sink_payload_adr = 32'd0; +reg [9:0] syncfifo0_sink_payload_len = 10'd0; +reg syncfifo0_sink_payload_end = 1'd0; +reg [15:0] syncfifo0_sink_payload_req_id = 16'd0; +reg [15:0] syncfifo0_sink_payload_cmp_id = 16'd0; +reg syncfifo0_sink_payload_err = 1'd0; +reg [7:0] syncfifo0_sink_payload_tag = 8'd0; +reg [63:0] syncfifo0_sink_payload_dat = 64'd0; +reg [7:0] syncfifo0_sink_payload_channel = 8'd0; +reg [7:0] syncfifo0_sink_payload_user_id = 8'd0; +wire syncfifo0_source_valid; +reg syncfifo0_source_ready = 1'd0; +wire syncfifo0_source_first; +wire syncfifo0_source_last; +wire [31:0] syncfifo0_source_payload_adr; +wire [9:0] syncfifo0_source_payload_len; +wire syncfifo0_source_payload_end; +wire [15:0] syncfifo0_source_payload_req_id; +wire [15:0] syncfifo0_source_payload_cmp_id; +wire syncfifo0_source_payload_err; +wire [7:0] syncfifo0_source_payload_tag; +wire [63:0] syncfifo0_source_payload_dat; +wire [7:0] syncfifo0_source_payload_channel; +wire [7:0] syncfifo0_source_payload_user_id; +wire syncfifo0_re; +reg syncfifo0_readable = 1'd0; +wire syncfifo0_syncfifo0_we; +wire syncfifo0_syncfifo0_writable; +wire syncfifo0_syncfifo0_re; +wire syncfifo0_syncfifo0_readable; +wire [165:0] syncfifo0_syncfifo0_din; +wire [165:0] syncfifo0_syncfifo0_dout; +reg [8:0] syncfifo0_level0 = 9'd0; +reg syncfifo0_replace = 1'd0; +reg [7:0] syncfifo0_produce = 8'd0; +reg [7:0] syncfifo0_consume = 8'd0; +reg [7:0] syncfifo0_wrport_adr = 8'd0; +wire [165:0] syncfifo0_wrport_dat_r; +wire syncfifo0_wrport_we; +wire [165:0] syncfifo0_wrport_dat_w; +wire syncfifo0_do_read; +wire [7:0] syncfifo0_rdport_adr; +wire [165:0] syncfifo0_rdport_dat_r; +wire syncfifo0_rdport_re; +wire [8:0] syncfifo0_level1; +wire [31:0] syncfifo0_fifo_in_payload_adr; +wire [9:0] syncfifo0_fifo_in_payload_len; +wire syncfifo0_fifo_in_payload_end; +wire [15:0] syncfifo0_fifo_in_payload_req_id; +wire [15:0] syncfifo0_fifo_in_payload_cmp_id; +wire syncfifo0_fifo_in_payload_err; +wire [7:0] syncfifo0_fifo_in_payload_tag; +wire [63:0] syncfifo0_fifo_in_payload_dat; +wire [7:0] syncfifo0_fifo_in_payload_channel; +wire [7:0] syncfifo0_fifo_in_payload_user_id; +wire syncfifo0_fifo_in_first; +wire syncfifo0_fifo_in_last; +wire [31:0] syncfifo0_fifo_out_payload_adr; +wire [9:0] syncfifo0_fifo_out_payload_len; +wire syncfifo0_fifo_out_payload_end; +wire [15:0] syncfifo0_fifo_out_payload_req_id; +wire [15:0] syncfifo0_fifo_out_payload_cmp_id; +wire syncfifo0_fifo_out_payload_err; +wire [7:0] syncfifo0_fifo_out_payload_tag; +wire [63:0] syncfifo0_fifo_out_payload_dat; +wire [7:0] syncfifo0_fifo_out_payload_channel; +wire [7:0] syncfifo0_fifo_out_payload_user_id; +wire syncfifo0_fifo_out_first; +wire syncfifo0_fifo_out_last; +reg syncfifo1_sink_valid = 1'd0; +wire syncfifo1_sink_ready; +reg syncfifo1_sink_first = 1'd0; +reg syncfifo1_sink_last = 1'd0; +reg [31:0] syncfifo1_sink_payload_adr = 32'd0; +reg [9:0] syncfifo1_sink_payload_len = 10'd0; +reg syncfifo1_sink_payload_end = 1'd0; +reg [15:0] syncfifo1_sink_payload_req_id = 16'd0; +reg [15:0] syncfifo1_sink_payload_cmp_id = 16'd0; +reg syncfifo1_sink_payload_err = 1'd0; +reg [7:0] syncfifo1_sink_payload_tag = 8'd0; +reg [63:0] syncfifo1_sink_payload_dat = 64'd0; +reg [7:0] syncfifo1_sink_payload_channel = 8'd0; +reg [7:0] syncfifo1_sink_payload_user_id = 8'd0; +wire syncfifo1_source_valid; +reg syncfifo1_source_ready = 1'd0; +wire syncfifo1_source_first; +wire syncfifo1_source_last; +wire [31:0] syncfifo1_source_payload_adr; +wire [9:0] syncfifo1_source_payload_len; +wire syncfifo1_source_payload_end; +wire [15:0] syncfifo1_source_payload_req_id; +wire [15:0] syncfifo1_source_payload_cmp_id; +wire syncfifo1_source_payload_err; +wire [7:0] syncfifo1_source_payload_tag; +wire [63:0] syncfifo1_source_payload_dat; +wire [7:0] syncfifo1_source_payload_channel; +wire [7:0] syncfifo1_source_payload_user_id; +wire syncfifo1_re; +reg syncfifo1_readable = 1'd0; +wire syncfifo1_syncfifo1_we; +wire syncfifo1_syncfifo1_writable; +wire syncfifo1_syncfifo1_re; +wire syncfifo1_syncfifo1_readable; +wire [165:0] syncfifo1_syncfifo1_din; +wire [165:0] syncfifo1_syncfifo1_dout; +reg [8:0] syncfifo1_level0 = 9'd0; +reg syncfifo1_replace = 1'd0; +reg [7:0] syncfifo1_produce = 8'd0; +reg [7:0] syncfifo1_consume = 8'd0; +reg [7:0] syncfifo1_wrport_adr = 8'd0; +wire [165:0] syncfifo1_wrport_dat_r; +wire syncfifo1_wrport_we; +wire [165:0] syncfifo1_wrport_dat_w; +wire syncfifo1_do_read; +wire [7:0] syncfifo1_rdport_adr; +wire [165:0] syncfifo1_rdport_dat_r; +wire syncfifo1_rdport_re; +wire [8:0] syncfifo1_level1; +wire [31:0] syncfifo1_fifo_in_payload_adr; +wire [9:0] syncfifo1_fifo_in_payload_len; +wire syncfifo1_fifo_in_payload_end; +wire [15:0] syncfifo1_fifo_in_payload_req_id; +wire [15:0] syncfifo1_fifo_in_payload_cmp_id; +wire syncfifo1_fifo_in_payload_err; +wire [7:0] syncfifo1_fifo_in_payload_tag; +wire [63:0] syncfifo1_fifo_in_payload_dat; +wire [7:0] syncfifo1_fifo_in_payload_channel; +wire [7:0] syncfifo1_fifo_in_payload_user_id; +wire syncfifo1_fifo_in_first; +wire syncfifo1_fifo_in_last; +wire [31:0] syncfifo1_fifo_out_payload_adr; +wire [9:0] syncfifo1_fifo_out_payload_len; +wire syncfifo1_fifo_out_payload_end; +wire [15:0] syncfifo1_fifo_out_payload_req_id; +wire [15:0] syncfifo1_fifo_out_payload_cmp_id; +wire syncfifo1_fifo_out_payload_err; +wire [7:0] syncfifo1_fifo_out_payload_tag; +wire [63:0] syncfifo1_fifo_out_payload_dat; +wire [7:0] syncfifo1_fifo_out_payload_channel; +wire [7:0] syncfifo1_fifo_out_payload_user_id; +wire syncfifo1_fifo_out_first; +wire syncfifo1_fifo_out_last; +reg syncfifo2_sink_valid = 1'd0; +wire syncfifo2_sink_ready; +reg syncfifo2_sink_first = 1'd0; +reg syncfifo2_sink_last = 1'd0; +reg [31:0] syncfifo2_sink_payload_adr = 32'd0; +reg [9:0] syncfifo2_sink_payload_len = 10'd0; +reg syncfifo2_sink_payload_end = 1'd0; +reg [15:0] syncfifo2_sink_payload_req_id = 16'd0; +reg [15:0] syncfifo2_sink_payload_cmp_id = 16'd0; +reg syncfifo2_sink_payload_err = 1'd0; +reg [7:0] syncfifo2_sink_payload_tag = 8'd0; +reg [63:0] syncfifo2_sink_payload_dat = 64'd0; +reg [7:0] syncfifo2_sink_payload_channel = 8'd0; +reg [7:0] syncfifo2_sink_payload_user_id = 8'd0; +wire syncfifo2_source_valid; +reg syncfifo2_source_ready = 1'd0; +wire syncfifo2_source_first; +wire syncfifo2_source_last; +wire [31:0] syncfifo2_source_payload_adr; +wire [9:0] syncfifo2_source_payload_len; +wire syncfifo2_source_payload_end; +wire [15:0] syncfifo2_source_payload_req_id; +wire [15:0] syncfifo2_source_payload_cmp_id; +wire syncfifo2_source_payload_err; +wire [7:0] syncfifo2_source_payload_tag; +wire [63:0] syncfifo2_source_payload_dat; +wire [7:0] syncfifo2_source_payload_channel; +wire [7:0] syncfifo2_source_payload_user_id; +wire syncfifo2_re; +reg syncfifo2_readable = 1'd0; +wire syncfifo2_syncfifo2_we; +wire syncfifo2_syncfifo2_writable; +wire syncfifo2_syncfifo2_re; +wire syncfifo2_syncfifo2_readable; +wire [165:0] syncfifo2_syncfifo2_din; +wire [165:0] syncfifo2_syncfifo2_dout; +reg [8:0] syncfifo2_level0 = 9'd0; +reg syncfifo2_replace = 1'd0; +reg [7:0] syncfifo2_produce = 8'd0; +reg [7:0] syncfifo2_consume = 8'd0; +reg [7:0] syncfifo2_wrport_adr = 8'd0; +wire [165:0] syncfifo2_wrport_dat_r; +wire syncfifo2_wrport_we; +wire [165:0] syncfifo2_wrport_dat_w; +wire syncfifo2_do_read; +wire [7:0] syncfifo2_rdport_adr; +wire [165:0] syncfifo2_rdport_dat_r; +wire syncfifo2_rdport_re; +wire [8:0] syncfifo2_level1; +wire [31:0] syncfifo2_fifo_in_payload_adr; +wire [9:0] syncfifo2_fifo_in_payload_len; +wire syncfifo2_fifo_in_payload_end; +wire [15:0] syncfifo2_fifo_in_payload_req_id; +wire [15:0] syncfifo2_fifo_in_payload_cmp_id; +wire syncfifo2_fifo_in_payload_err; +wire [7:0] syncfifo2_fifo_in_payload_tag; +wire [63:0] syncfifo2_fifo_in_payload_dat; +wire [7:0] syncfifo2_fifo_in_payload_channel; +wire [7:0] syncfifo2_fifo_in_payload_user_id; +wire syncfifo2_fifo_in_first; +wire syncfifo2_fifo_in_last; +wire [31:0] syncfifo2_fifo_out_payload_adr; +wire [9:0] syncfifo2_fifo_out_payload_len; +wire syncfifo2_fifo_out_payload_end; +wire [15:0] syncfifo2_fifo_out_payload_req_id; +wire [15:0] syncfifo2_fifo_out_payload_cmp_id; +wire syncfifo2_fifo_out_payload_err; +wire [7:0] syncfifo2_fifo_out_payload_tag; +wire [63:0] syncfifo2_fifo_out_payload_dat; +wire [7:0] syncfifo2_fifo_out_payload_channel; +wire [7:0] syncfifo2_fifo_out_payload_user_id; +wire syncfifo2_fifo_out_first; +wire syncfifo2_fifo_out_last; +reg syncfifo3_sink_valid = 1'd0; +wire syncfifo3_sink_ready; +reg syncfifo3_sink_first = 1'd0; +reg syncfifo3_sink_last = 1'd0; +reg [31:0] syncfifo3_sink_payload_adr = 32'd0; +reg [9:0] syncfifo3_sink_payload_len = 10'd0; +reg syncfifo3_sink_payload_end = 1'd0; +reg [15:0] syncfifo3_sink_payload_req_id = 16'd0; +reg [15:0] syncfifo3_sink_payload_cmp_id = 16'd0; +reg syncfifo3_sink_payload_err = 1'd0; +reg [7:0] syncfifo3_sink_payload_tag = 8'd0; +reg [63:0] syncfifo3_sink_payload_dat = 64'd0; +reg [7:0] syncfifo3_sink_payload_channel = 8'd0; +reg [7:0] syncfifo3_sink_payload_user_id = 8'd0; +wire syncfifo3_source_valid; +reg syncfifo3_source_ready = 1'd0; +wire syncfifo3_source_first; +wire syncfifo3_source_last; +wire [31:0] syncfifo3_source_payload_adr; +wire [9:0] syncfifo3_source_payload_len; +wire syncfifo3_source_payload_end; +wire [15:0] syncfifo3_source_payload_req_id; +wire [15:0] syncfifo3_source_payload_cmp_id; +wire syncfifo3_source_payload_err; +wire [7:0] syncfifo3_source_payload_tag; +wire [63:0] syncfifo3_source_payload_dat; +wire [7:0] syncfifo3_source_payload_channel; +wire [7:0] syncfifo3_source_payload_user_id; +wire syncfifo3_re; +reg syncfifo3_readable = 1'd0; +wire syncfifo3_syncfifo3_we; +wire syncfifo3_syncfifo3_writable; +wire syncfifo3_syncfifo3_re; +wire syncfifo3_syncfifo3_readable; +wire [165:0] syncfifo3_syncfifo3_din; +wire [165:0] syncfifo3_syncfifo3_dout; +reg [8:0] syncfifo3_level0 = 9'd0; +reg syncfifo3_replace = 1'd0; +reg [7:0] syncfifo3_produce = 8'd0; +reg [7:0] syncfifo3_consume = 8'd0; +reg [7:0] syncfifo3_wrport_adr = 8'd0; +wire [165:0] syncfifo3_wrport_dat_r; +wire syncfifo3_wrport_we; +wire [165:0] syncfifo3_wrport_dat_w; +wire syncfifo3_do_read; +wire [7:0] syncfifo3_rdport_adr; +wire [165:0] syncfifo3_rdport_dat_r; +wire syncfifo3_rdport_re; +wire [8:0] syncfifo3_level1; +wire [31:0] syncfifo3_fifo_in_payload_adr; +wire [9:0] syncfifo3_fifo_in_payload_len; +wire syncfifo3_fifo_in_payload_end; +wire [15:0] syncfifo3_fifo_in_payload_req_id; +wire [15:0] syncfifo3_fifo_in_payload_cmp_id; +wire syncfifo3_fifo_in_payload_err; +wire [7:0] syncfifo3_fifo_in_payload_tag; +wire [63:0] syncfifo3_fifo_in_payload_dat; +wire [7:0] syncfifo3_fifo_in_payload_channel; +wire [7:0] syncfifo3_fifo_in_payload_user_id; +wire syncfifo3_fifo_in_first; +wire syncfifo3_fifo_in_last; +wire [31:0] syncfifo3_fifo_out_payload_adr; +wire [9:0] syncfifo3_fifo_out_payload_len; +wire syncfifo3_fifo_out_payload_end; +wire [15:0] syncfifo3_fifo_out_payload_req_id; +wire [15:0] syncfifo3_fifo_out_payload_cmp_id; +wire syncfifo3_fifo_out_payload_err; +wire [7:0] syncfifo3_fifo_out_payload_tag; +wire [63:0] syncfifo3_fifo_out_payload_dat; +wire [7:0] syncfifo3_fifo_out_payload_channel; +wire [7:0] syncfifo3_fifo_out_payload_user_id; +wire syncfifo3_fifo_out_first; +wire syncfifo3_fifo_out_last; +reg [1:0] fill_tag = 2'd0; +reg [1:0] arbiter0_request = 2'd0; +reg arbiter0_grant = 1'd0; +reg arbiter0_status0_first = 1'd1; +reg arbiter0_status0_last = 1'd0; +wire arbiter0_status0_ongoing0; +reg arbiter0_status0_ongoing1 = 1'd0; +reg arbiter0_status1_first = 1'd1; +reg arbiter0_status1_last = 1'd0; +wire arbiter0_status1_ongoing0; +reg arbiter0_status1_ongoing1 = 1'd0; +reg [1:0] dispatcher0_sel0 = 2'd0; +reg dispatcher0_first = 1'd1; +reg dispatcher0_last = 1'd0; +wire dispatcher0_ongoing0; +reg dispatcher0_ongoing1 = 1'd0; +reg [1:0] dispatcher0_sel1 = 2'd0; +reg [1:0] dispatcher0_sel_ongoing = 2'd0; +reg sink_valid = 1'd0; +reg sink_ready = 1'd0; +reg sink_first = 1'd0; +reg sink_last = 1'd0; +reg sink_payload_we = 1'd0; +reg [31:0] sink_payload_adr = 32'd0; +reg [9:0] sink_payload_len = 10'd0; +reg [15:0] sink_payload_req_id = 16'd0; +reg [7:0] sink_payload_tag = 8'd0; +reg [63:0] sink_payload_dat = 64'd0; +reg [7:0] sink_payload_channel = 8'd0; +reg [7:0] sink_payload_user_id = 8'd0; +reg source_valid = 1'd0; +reg source_ready = 1'd0; +reg source_first = 1'd0; +reg source_last = 1'd0; +reg [31:0] source_payload_adr = 32'd0; +reg [9:0] source_payload_len = 10'd0; +reg source_payload_end = 1'd0; +reg [15:0] source_payload_req_id = 16'd0; +reg [15:0] source_payload_cmp_id = 16'd0; +reg source_payload_err = 1'd0; +reg [7:0] source_payload_tag = 8'd0; +reg [63:0] source_payload_dat = 64'd0; +reg [7:0] source_payload_channel = 8'd0; +reg [7:0] source_payload_user_id = 8'd0; +reg [1:0] arbiter1_request = 2'd0; +reg arbiter1_grant = 1'd0; +reg arbiter1_status2_first = 1'd1; +reg arbiter1_status2_last = 1'd0; +wire arbiter1_status2_ongoing0; +reg arbiter1_status2_ongoing1 = 1'd0; +reg arbiter1_status3_first = 1'd1; +reg arbiter1_status3_last = 1'd0; +wire arbiter1_status3_ongoing0; +reg arbiter1_status3_ongoing1 = 1'd0; +reg [1:0] dispatcher1_sel0 = 2'd0; +reg dispatcher1_first = 1'd1; +reg dispatcher1_last = 1'd0; +wire dispatcher1_ongoing0; +reg dispatcher1_ongoing1 = 1'd0; +reg [1:0] dispatcher1_sel1 = 2'd0; +reg [1:0] dispatcher1_sel_ongoing = 2'd0; +reg [1:0] arbiter2_request = 2'd0; +reg arbiter2_grant = 1'd0; +reg arbiter2_status4_first = 1'd1; +reg arbiter2_status4_last = 1'd0; +wire arbiter2_status4_ongoing0; +reg arbiter2_status4_ongoing1 = 1'd0; +reg arbiter2_status5_first = 1'd1; +reg arbiter2_status5_last = 1'd0; +wire arbiter2_status5_ongoing0; +reg arbiter2_status5_ongoing1 = 1'd0; +reg [1:0] fsm0_state0 = 2'd0; +reg [1:0] fsm0_next_state0 = 2'd0; +reg [1:0] fsm1_state0 = 2'd0; +reg [1:0] fsm1_next_state0 = 2'd0; +reg [1:0] fill_tag_litepciecrossbar_next_value = 2'd0; +reg fill_tag_litepciecrossbar_next_value_ce = 1'd0; +reg [1:0] litepciewishbonebridge_state = 2'd0; +reg [1:0] litepciewishbonebridge_next_state = 2'd0; +reg [1:0] bufferizeendpoints0_state0 = 2'd0; +reg [1:0] bufferizeendpoints0_next_state0 = 2'd0; +reg [31:0] pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_bufferizeendpoints0_next_value0 = 32'd0; +reg pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_bufferizeendpoints0_next_value_ce0 = 1'd0; +reg [31:0] pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_user_id_litepciedma0_bufferizeendpoints0_next_value1 = 32'd0; +reg pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_user_id_litepciedma0_bufferizeendpoints0_next_value_ce1 = 1'd0; +reg fsm0_state1 = 1'd0; +reg fsm0_next_state1 = 1'd0; +reg [12:0] pcie_dma0_writer_counter_litepciedma0_fsm0_next_value = 13'd0; +reg pcie_dma0_writer_counter_litepciedma0_fsm0_next_value_ce = 1'd0; +reg [1:0] bufferizeendpoints0_state1 = 2'd0; +reg [1:0] bufferizeendpoints0_next_state1 = 2'd0; +reg [31:0] pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_next_value0 = 32'd0; +reg pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_next_value_ce0 = 1'd0; +reg [31:0] pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_user_id_litepciedma0_next_value1 = 32'd0; +reg pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_user_id_litepciedma0_next_value_ce1 = 1'd0; +reg fsm0_state2 = 1'd0; +reg fsm0_next_state2 = 1'd0; +reg [1:0] bufferizeendpoints1_state0 = 2'd0; +reg [1:0] bufferizeendpoints1_next_state0 = 2'd0; +reg [31:0] pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_bufferizeendpoints1_next_value0 = 32'd0; +reg pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_bufferizeendpoints1_next_value_ce0 = 1'd0; +reg [31:0] pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_user_id_litepciedma1_bufferizeendpoints1_next_value1 = 32'd0; +reg pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_user_id_litepciedma1_bufferizeendpoints1_next_value_ce1 = 1'd0; +reg fsm1_state1 = 1'd0; +reg fsm1_next_state1 = 1'd0; +reg [12:0] pcie_dma1_writer_counter_litepciedma1_fsm1_next_value = 13'd0; +reg pcie_dma1_writer_counter_litepciedma1_fsm1_next_value_ce = 1'd0; +reg [1:0] bufferizeendpoints1_state1 = 2'd0; +reg [1:0] bufferizeendpoints1_next_state1 = 2'd0; +reg [31:0] pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_next_value0 = 32'd0; +reg pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_next_value_ce0 = 1'd0; +reg [31:0] pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_user_id_litepciedma1_next_value1 = 32'd0; +reg pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_user_id_litepciedma1_next_value_ce1 = 1'd0; +reg fsm1_state2 = 1'd0; +reg fsm1_next_state2 = 1'd0; +reg [3:0] edid_state = 4'd0; +reg [3:0] edid_next_state = 4'd0; +reg [1:0] dma_state = 2'd0; +reg [1:0] dma_next_state = 2'd0; +reg videoout_state = 1'd0; +reg videoout_next_state = 1'd0; +reg [27:0] hdmi_out0_core_dmareader_offset_videoout_next_value = 28'd0; +reg hdmi_out0_core_dmareader_offset_videoout_next_value_ce = 1'd0; +reg [13:0] netv2_adr = 14'd0; +reg netv2_we = 1'd0; +reg [31:0] netv2_dat_w = 32'd0; +wire [31:0] netv2_dat_r; +wire [29:0] netv2_wishbone_adr; +wire [31:0] netv2_wishbone_dat_w; +reg [31:0] netv2_wishbone_dat_r = 32'd0; +wire [3:0] netv2_wishbone_sel; +wire netv2_wishbone_cyc; +wire netv2_wishbone_stb; +reg netv2_wishbone_ack = 1'd0; +wire netv2_wishbone_we; +wire [2:0] netv2_wishbone_cti; +wire [1:0] netv2_wishbone_bte; +reg netv2_wishbone_err = 1'd0; +wire [29:0] shared_adr; +wire [31:0] shared_dat_w; +reg [31:0] shared_dat_r = 32'd0; +wire [3:0] shared_sel; +wire shared_cyc; +wire shared_stb; +reg shared_ack = 1'd0; +wire shared_we; +wire [2:0] shared_cti; +wire [1:0] shared_bte; +wire shared_err; +wire [3:0] request; +reg [1:0] grant = 2'd0; +reg [3:0] slave_sel = 4'd0; +reg [3:0] slave_sel_r = 4'd0; +reg error = 1'd0; +wire wait_1; +wire done; +reg [19:0] count = 20'd1000000; +wire [13:0] interface0_bank_bus_adr; +wire interface0_bank_bus_we; +wire [31:0] interface0_bank_bus_dat_w; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +wire csrbank0_sel; +wire [13:0] interface1_bank_bus_adr; +wire interface1_bank_bus_we; +wire [31:0] interface1_bank_bus_dat_w; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +wire csrbank1_reset0_re; +wire csrbank1_reset0_r; +wire csrbank1_reset0_we; +wire csrbank1_reset0_w; +wire csrbank1_scratch0_re; +wire [31:0] csrbank1_scratch0_r; +wire csrbank1_scratch0_we; +wire [31:0] csrbank1_scratch0_w; +wire csrbank1_bus_errors_re; +wire [31:0] csrbank1_bus_errors_r; +wire csrbank1_bus_errors_we; +wire [31:0] csrbank1_bus_errors_w; +wire csrbank1_sel; +wire [13:0] interface2_bank_bus_adr; +wire interface2_bank_bus_we; +wire [31:0] interface2_bank_bus_dat_w; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +wire csrbank2_rst0_re; +wire csrbank2_rst0_r; +wire csrbank2_rst0_we; +wire csrbank2_rst0_w; +wire csrbank2_half_sys8x_taps0_re; +wire [4:0] csrbank2_half_sys8x_taps0_r; +wire csrbank2_half_sys8x_taps0_we; +wire [4:0] csrbank2_half_sys8x_taps0_w; +wire csrbank2_wlevel_en0_re; +wire csrbank2_wlevel_en0_r; +wire csrbank2_wlevel_en0_we; +wire csrbank2_wlevel_en0_w; +wire csrbank2_dly_sel0_re; +wire [3:0] csrbank2_dly_sel0_r; +wire csrbank2_dly_sel0_we; +wire [3:0] csrbank2_dly_sel0_w; +wire csrbank2_rdphase0_re; +wire [1:0] csrbank2_rdphase0_r; +wire csrbank2_rdphase0_we; +wire [1:0] csrbank2_rdphase0_w; +wire csrbank2_wrphase0_re; +wire [1:0] csrbank2_wrphase0_r; +wire csrbank2_wrphase0_we; +wire [1:0] csrbank2_wrphase0_w; +wire csrbank2_sel; +wire [13:0] interface3_bank_bus_adr; +wire interface3_bank_bus_we; +wire [31:0] interface3_bank_bus_dat_w; +reg [31:0] interface3_bank_bus_dat_r = 32'd0; +wire csrbank3_id1_re; +wire [24:0] csrbank3_id1_r; +wire csrbank3_id1_we; +wire [24:0] csrbank3_id1_w; +wire csrbank3_id0_re; +wire [31:0] csrbank3_id0_r; +wire csrbank3_id0_we; +wire [31:0] csrbank3_id0_w; +wire csrbank3_sel; +wire [13:0] interface4_bank_bus_adr; +wire interface4_bank_bus_we; +wire [31:0] interface4_bank_bus_dat_w; +reg [31:0] interface4_bank_bus_dat_r = 32'd0; +wire csrbank4_crg_reset0_re; +wire csrbank4_crg_reset0_r; +wire csrbank4_crg_reset0_we; +wire csrbank4_crg_reset0_w; +wire csrbank4_mdio_w0_re; +wire [2:0] csrbank4_mdio_w0_r; +wire csrbank4_mdio_w0_we; +wire [2:0] csrbank4_mdio_w0_w; +wire csrbank4_mdio_r_re; +wire csrbank4_mdio_r_r; +wire csrbank4_mdio_r_we; +wire csrbank4_mdio_r_w; +wire csrbank4_sel; +wire [13:0] interface5_bank_bus_adr; +wire interface5_bank_bus_we; +wire [31:0] interface5_bank_bus_dat_w; +reg [31:0] interface5_bank_bus_dat_r = 32'd0; +wire csrbank5_spi_control0_re; +wire [15:0] csrbank5_spi_control0_r; +wire csrbank5_spi_control0_we; +wire [15:0] csrbank5_spi_control0_w; +wire csrbank5_spi_status_re; +wire csrbank5_spi_status_r; +wire csrbank5_spi_status_we; +wire csrbank5_spi_status_w; +wire csrbank5_spi_mosi1_re; +wire [7:0] csrbank5_spi_mosi1_r; +wire csrbank5_spi_mosi1_we; +wire [7:0] csrbank5_spi_mosi1_w; +wire csrbank5_spi_mosi0_re; +wire [31:0] csrbank5_spi_mosi0_r; +wire csrbank5_spi_mosi0_we; +wire [31:0] csrbank5_spi_mosi0_w; +wire csrbank5_spi_miso1_re; +wire [7:0] csrbank5_spi_miso1_r; +wire csrbank5_spi_miso1_we; +wire [7:0] csrbank5_spi_miso1_w; +wire csrbank5_spi_miso0_re; +wire [31:0] csrbank5_spi_miso0_r; +wire csrbank5_spi_miso0_we; +wire [31:0] csrbank5_spi_miso0_w; +wire csrbank5_spi_cs0_re; +wire csrbank5_spi_cs0_r; +wire csrbank5_spi_cs0_we; +wire csrbank5_spi_cs0_w; +wire csrbank5_spi_loopback0_re; +wire csrbank5_spi_loopback0_r; +wire csrbank5_spi_loopback0_we; +wire csrbank5_spi_loopback0_w; +wire csrbank5_sel; +wire [13:0] interface0_sram_bus_adr; +wire interface0_sram_bus_we; +wire [31:0] interface0_sram_bus_dat_w; +reg [31:0] interface0_sram_bus_dat_r = 32'd0; +wire [7:0] sram0_adr; +wire [7:0] sram0_dat_r; +wire sram0_we; +wire [7:0] sram0_dat_w; +wire sram0_sel; +reg sram0_sel_r = 1'd0; +wire [13:0] interface6_bank_bus_adr; +wire interface6_bank_bus_we; +wire [31:0] interface6_bank_bus_dat_w; +reg [31:0] interface6_bank_bus_dat_r = 32'd0; +wire csrbank6_edid_hpd_notif_re; +wire csrbank6_edid_hpd_notif_r; +wire csrbank6_edid_hpd_notif_we; +wire csrbank6_edid_hpd_notif_w; +wire csrbank6_edid_hpd_en0_re; +wire csrbank6_edid_hpd_en0_r; +wire csrbank6_edid_hpd_en0_we; +wire csrbank6_edid_hpd_en0_w; +wire csrbank6_clocking_mmcm_reset0_re; +wire csrbank6_clocking_mmcm_reset0_r; +wire csrbank6_clocking_mmcm_reset0_we; +wire csrbank6_clocking_mmcm_reset0_w; +wire csrbank6_clocking_locked_re; +wire csrbank6_clocking_locked_r; +wire csrbank6_clocking_locked_we; +wire csrbank6_clocking_locked_w; +wire csrbank6_clocking_mmcm_drdy_re; +wire csrbank6_clocking_mmcm_drdy_r; +wire csrbank6_clocking_mmcm_drdy_we; +wire csrbank6_clocking_mmcm_drdy_w; +wire csrbank6_clocking_mmcm_adr0_re; +wire [6:0] csrbank6_clocking_mmcm_adr0_r; +wire csrbank6_clocking_mmcm_adr0_we; +wire [6:0] csrbank6_clocking_mmcm_adr0_w; +wire csrbank6_clocking_mmcm_dat_w0_re; +wire [15:0] csrbank6_clocking_mmcm_dat_w0_r; +wire csrbank6_clocking_mmcm_dat_w0_we; +wire [15:0] csrbank6_clocking_mmcm_dat_w0_w; +wire csrbank6_clocking_mmcm_dat_r_re; +wire [15:0] csrbank6_clocking_mmcm_dat_r_r; +wire csrbank6_clocking_mmcm_dat_r_we; +wire [15:0] csrbank6_clocking_mmcm_dat_r_w; +wire csrbank6_clocking_mmcm_dat_o_r_re; +wire [15:0] csrbank6_clocking_mmcm_dat_o_r_r; +wire csrbank6_clocking_mmcm_dat_o_r_we; +wire [15:0] csrbank6_clocking_mmcm_dat_o_r_w; +wire csrbank6_clocking_mmcm_drdy_o_re; +wire csrbank6_clocking_mmcm_drdy_o_r; +wire csrbank6_clocking_mmcm_drdy_o_we; +wire csrbank6_clocking_mmcm_drdy_o_w; +wire csrbank6_data0_cap_phase_re; +wire [1:0] csrbank6_data0_cap_phase_r; +wire csrbank6_data0_cap_phase_we; +wire [1:0] csrbank6_data0_cap_phase_w; +wire csrbank6_data0_cap_cntvalueout_m_re; +wire [4:0] csrbank6_data0_cap_cntvalueout_m_r; +wire csrbank6_data0_cap_cntvalueout_m_we; +wire [4:0] csrbank6_data0_cap_cntvalueout_m_w; +wire csrbank6_data0_cap_cntvalueout_s_re; +wire [4:0] csrbank6_data0_cap_cntvalueout_s_r; +wire csrbank6_data0_cap_cntvalueout_s_we; +wire [4:0] csrbank6_data0_cap_cntvalueout_s_w; +wire csrbank6_data0_charsync_char_synced_re; +wire csrbank6_data0_charsync_char_synced_r; +wire csrbank6_data0_charsync_char_synced_we; +wire csrbank6_data0_charsync_char_synced_w; +wire csrbank6_data0_charsync_ctl_pos_re; +wire [3:0] csrbank6_data0_charsync_ctl_pos_r; +wire csrbank6_data0_charsync_ctl_pos_we; +wire [3:0] csrbank6_data0_charsync_ctl_pos_w; +wire csrbank6_data0_wer_value_re; +wire [23:0] csrbank6_data0_wer_value_r; +wire csrbank6_data0_wer_value_we; +wire [23:0] csrbank6_data0_wer_value_w; +wire csrbank6_data1_cap_phase_re; +wire [1:0] csrbank6_data1_cap_phase_r; +wire csrbank6_data1_cap_phase_we; +wire [1:0] csrbank6_data1_cap_phase_w; +wire csrbank6_data1_cap_cntvalueout_m_re; +wire [4:0] csrbank6_data1_cap_cntvalueout_m_r; +wire csrbank6_data1_cap_cntvalueout_m_we; +wire [4:0] csrbank6_data1_cap_cntvalueout_m_w; +wire csrbank6_data1_cap_cntvalueout_s_re; +wire [4:0] csrbank6_data1_cap_cntvalueout_s_r; +wire csrbank6_data1_cap_cntvalueout_s_we; +wire [4:0] csrbank6_data1_cap_cntvalueout_s_w; +wire csrbank6_data1_charsync_char_synced_re; +wire csrbank6_data1_charsync_char_synced_r; +wire csrbank6_data1_charsync_char_synced_we; +wire csrbank6_data1_charsync_char_synced_w; +wire csrbank6_data1_charsync_ctl_pos_re; +wire [3:0] csrbank6_data1_charsync_ctl_pos_r; +wire csrbank6_data1_charsync_ctl_pos_we; +wire [3:0] csrbank6_data1_charsync_ctl_pos_w; +wire csrbank6_data1_wer_value_re; +wire [23:0] csrbank6_data1_wer_value_r; +wire csrbank6_data1_wer_value_we; +wire [23:0] csrbank6_data1_wer_value_w; +wire csrbank6_data2_cap_phase_re; +wire [1:0] csrbank6_data2_cap_phase_r; +wire csrbank6_data2_cap_phase_we; +wire [1:0] csrbank6_data2_cap_phase_w; +wire csrbank6_data2_cap_cntvalueout_m_re; +wire [4:0] csrbank6_data2_cap_cntvalueout_m_r; +wire csrbank6_data2_cap_cntvalueout_m_we; +wire [4:0] csrbank6_data2_cap_cntvalueout_m_w; +wire csrbank6_data2_cap_cntvalueout_s_re; +wire [4:0] csrbank6_data2_cap_cntvalueout_s_r; +wire csrbank6_data2_cap_cntvalueout_s_we; +wire [4:0] csrbank6_data2_cap_cntvalueout_s_w; +wire csrbank6_data2_charsync_char_synced_re; +wire csrbank6_data2_charsync_char_synced_r; +wire csrbank6_data2_charsync_char_synced_we; +wire csrbank6_data2_charsync_char_synced_w; +wire csrbank6_data2_charsync_ctl_pos_re; +wire [3:0] csrbank6_data2_charsync_ctl_pos_r; +wire csrbank6_data2_charsync_ctl_pos_we; +wire [3:0] csrbank6_data2_charsync_ctl_pos_w; +wire csrbank6_data2_wer_value_re; +wire [23:0] csrbank6_data2_wer_value_r; +wire csrbank6_data2_wer_value_we; +wire [23:0] csrbank6_data2_wer_value_w; +wire csrbank6_chansync_channels_synced_re; +wire csrbank6_chansync_channels_synced_r; +wire csrbank6_chansync_channels_synced_we; +wire csrbank6_chansync_channels_synced_w; +wire csrbank6_resdetection_hres_re; +wire [10:0] csrbank6_resdetection_hres_r; +wire csrbank6_resdetection_hres_we; +wire [10:0] csrbank6_resdetection_hres_w; +wire csrbank6_resdetection_vres_re; +wire [10:0] csrbank6_resdetection_vres_r; +wire csrbank6_resdetection_vres_we; +wire [10:0] csrbank6_resdetection_vres_w; +wire csrbank6_dma_frame_size0_re; +wire [28:0] csrbank6_dma_frame_size0_r; +wire csrbank6_dma_frame_size0_we; +wire [28:0] csrbank6_dma_frame_size0_w; +wire csrbank6_dma_slot0_status0_re; +wire [1:0] csrbank6_dma_slot0_status0_r; +wire csrbank6_dma_slot0_status0_we; +wire [1:0] csrbank6_dma_slot0_status0_w; +wire csrbank6_dma_slot0_address0_re; +wire [28:0] csrbank6_dma_slot0_address0_r; +wire csrbank6_dma_slot0_address0_we; +wire [28:0] csrbank6_dma_slot0_address0_w; +wire csrbank6_dma_slot1_status0_re; +wire [1:0] csrbank6_dma_slot1_status0_r; +wire csrbank6_dma_slot1_status0_we; +wire [1:0] csrbank6_dma_slot1_status0_w; +wire csrbank6_dma_slot1_address0_re; +wire [28:0] csrbank6_dma_slot1_address0_r; +wire csrbank6_dma_slot1_address0_we; +wire [28:0] csrbank6_dma_slot1_address0_w; +wire csrbank6_dma_ev_enable0_re; +wire [1:0] csrbank6_dma_ev_enable0_r; +wire csrbank6_dma_ev_enable0_we; +wire [1:0] csrbank6_dma_ev_enable0_w; +wire csrbank6_sel; +wire [13:0] interface7_bank_bus_adr; +wire interface7_bank_bus_we; +wire [31:0] interface7_bank_bus_dat_w; +reg [31:0] interface7_bank_bus_dat_r = 32'd0; +wire csrbank7_value_re; +wire [31:0] csrbank7_value_r; +wire csrbank7_value_we; +wire [31:0] csrbank7_value_w; +wire csrbank7_sel; +wire [13:0] interface8_bank_bus_adr; +wire interface8_bank_bus_we; +wire [31:0] interface8_bank_bus_dat_w; +reg [31:0] interface8_bank_bus_dat_r = 32'd0; +wire csrbank8_core_underflow_enable0_re; +wire csrbank8_core_underflow_enable0_r; +wire csrbank8_core_underflow_enable0_we; +wire csrbank8_core_underflow_enable0_w; +wire csrbank8_core_underflow_counter_re; +wire [31:0] csrbank8_core_underflow_counter_r; +wire csrbank8_core_underflow_counter_we; +wire [31:0] csrbank8_core_underflow_counter_w; +wire csrbank8_core_initiator_enable0_re; +wire csrbank8_core_initiator_enable0_r; +wire csrbank8_core_initiator_enable0_we; +wire csrbank8_core_initiator_enable0_w; +wire csrbank8_core_initiator_hres0_re; +wire [11:0] csrbank8_core_initiator_hres0_r; +wire csrbank8_core_initiator_hres0_we; +wire [11:0] csrbank8_core_initiator_hres0_w; +wire csrbank8_core_initiator_hsync_start0_re; +wire [11:0] csrbank8_core_initiator_hsync_start0_r; +wire csrbank8_core_initiator_hsync_start0_we; +wire [11:0] csrbank8_core_initiator_hsync_start0_w; +wire csrbank8_core_initiator_hsync_end0_re; +wire [11:0] csrbank8_core_initiator_hsync_end0_r; +wire csrbank8_core_initiator_hsync_end0_we; +wire [11:0] csrbank8_core_initiator_hsync_end0_w; +wire csrbank8_core_initiator_hscan0_re; +wire [11:0] csrbank8_core_initiator_hscan0_r; +wire csrbank8_core_initiator_hscan0_we; +wire [11:0] csrbank8_core_initiator_hscan0_w; +wire csrbank8_core_initiator_vres0_re; +wire [11:0] csrbank8_core_initiator_vres0_r; +wire csrbank8_core_initiator_vres0_we; +wire [11:0] csrbank8_core_initiator_vres0_w; +wire csrbank8_core_initiator_vsync_start0_re; +wire [11:0] csrbank8_core_initiator_vsync_start0_r; +wire csrbank8_core_initiator_vsync_start0_we; +wire [11:0] csrbank8_core_initiator_vsync_start0_w; +wire csrbank8_core_initiator_vsync_end0_re; +wire [11:0] csrbank8_core_initiator_vsync_end0_r; +wire csrbank8_core_initiator_vsync_end0_we; +wire [11:0] csrbank8_core_initiator_vsync_end0_w; +wire csrbank8_core_initiator_vscan0_re; +wire [11:0] csrbank8_core_initiator_vscan0_r; +wire csrbank8_core_initiator_vscan0_we; +wire [11:0] csrbank8_core_initiator_vscan0_w; +wire csrbank8_core_initiator_base0_re; +wire [31:0] csrbank8_core_initiator_base0_r; +wire csrbank8_core_initiator_base0_we; +wire [31:0] csrbank8_core_initiator_base0_w; +wire csrbank8_core_initiator_length0_re; +wire [31:0] csrbank8_core_initiator_length0_r; +wire csrbank8_core_initiator_length0_we; +wire [31:0] csrbank8_core_initiator_length0_w; +wire csrbank8_core_dma_delay_base0_re; +wire [31:0] csrbank8_core_dma_delay_base0_r; +wire csrbank8_core_dma_delay_base0_we; +wire [31:0] csrbank8_core_dma_delay_base0_w; +wire csrbank8_driver_clocking_mmcm_reset0_re; +wire csrbank8_driver_clocking_mmcm_reset0_r; +wire csrbank8_driver_clocking_mmcm_reset0_we; +wire csrbank8_driver_clocking_mmcm_reset0_w; +wire csrbank8_driver_clocking_mmcm_drdy_re; +wire csrbank8_driver_clocking_mmcm_drdy_r; +wire csrbank8_driver_clocking_mmcm_drdy_we; +wire csrbank8_driver_clocking_mmcm_drdy_w; +wire csrbank8_driver_clocking_mmcm_adr0_re; +wire [6:0] csrbank8_driver_clocking_mmcm_adr0_r; +wire csrbank8_driver_clocking_mmcm_adr0_we; +wire [6:0] csrbank8_driver_clocking_mmcm_adr0_w; +wire csrbank8_driver_clocking_mmcm_dat_w0_re; +wire [15:0] csrbank8_driver_clocking_mmcm_dat_w0_r; +wire csrbank8_driver_clocking_mmcm_dat_w0_we; +wire [15:0] csrbank8_driver_clocking_mmcm_dat_w0_w; +wire csrbank8_driver_clocking_mmcm_dat_r_re; +wire [15:0] csrbank8_driver_clocking_mmcm_dat_r_r; +wire csrbank8_driver_clocking_mmcm_dat_r_we; +wire [15:0] csrbank8_driver_clocking_mmcm_dat_r_w; +wire csrbank8_sel; +wire [13:0] interface9_bank_bus_adr; +wire interface9_bank_bus_we; +wire [31:0] interface9_bank_bus_dat_w; +reg [31:0] interface9_bank_bus_dat_r = 32'd0; +wire csrbank9_addr0_re; +wire [4:0] csrbank9_addr0_r; +wire csrbank9_addr0_we; +wire [4:0] csrbank9_addr0_w; +wire csrbank9_data0_re; +wire [31:0] csrbank9_data0_r; +wire csrbank9_data0_we; +wire [31:0] csrbank9_data0_w; +wire csrbank9_send0_re; +wire csrbank9_send0_r; +wire csrbank9_send0_we; +wire csrbank9_send0_w; +wire csrbank9_done_re; +wire csrbank9_done_r; +wire csrbank9_done_we; +wire csrbank9_done_w; +wire csrbank9_sel; +wire [13:0] interface1_sram_bus_adr; +wire interface1_sram_bus_we; +wire [31:0] interface1_sram_bus_dat_w; +reg [31:0] interface1_sram_bus_dat_r = 32'd0; +wire [5:0] sram1_adr; +wire [7:0] sram1_dat_r; +wire sram1_sel; +reg sram1_sel_r = 1'd0; +wire [13:0] interface10_bank_bus_adr; +wire interface10_bank_bus_we; +wire [31:0] interface10_bank_bus_dat_w; +reg [31:0] interface10_bank_bus_dat_r = 32'd0; +wire csrbank10_writer_enable0_re; +wire csrbank10_writer_enable0_r; +wire csrbank10_writer_enable0_we; +wire csrbank10_writer_enable0_w; +wire csrbank10_writer_table_value1_re; +wire [25:0] csrbank10_writer_table_value1_r; +wire csrbank10_writer_table_value1_we; +wire [25:0] csrbank10_writer_table_value1_w; +wire csrbank10_writer_table_value0_re; +wire [31:0] csrbank10_writer_table_value0_r; +wire csrbank10_writer_table_value0_we; +wire [31:0] csrbank10_writer_table_value0_w; +wire csrbank10_writer_table_we0_re; +wire csrbank10_writer_table_we0_r; +wire csrbank10_writer_table_we0_we; +wire csrbank10_writer_table_we0_w; +wire csrbank10_writer_table_loop_prog_n0_re; +wire csrbank10_writer_table_loop_prog_n0_r; +wire csrbank10_writer_table_loop_prog_n0_we; +wire csrbank10_writer_table_loop_prog_n0_w; +wire csrbank10_writer_table_loop_status_re; +wire [31:0] csrbank10_writer_table_loop_status_r; +wire csrbank10_writer_table_loop_status_we; +wire [31:0] csrbank10_writer_table_loop_status_w; +wire csrbank10_writer_table_level_re; +wire [8:0] csrbank10_writer_table_level_r; +wire csrbank10_writer_table_level_we; +wire [8:0] csrbank10_writer_table_level_w; +wire csrbank10_writer_table_flush0_re; +wire csrbank10_writer_table_flush0_r; +wire csrbank10_writer_table_flush0_we; +wire csrbank10_writer_table_flush0_w; +wire csrbank10_reader_enable0_re; +wire csrbank10_reader_enable0_r; +wire csrbank10_reader_enable0_we; +wire csrbank10_reader_enable0_w; +wire csrbank10_reader_table_value1_re; +wire [25:0] csrbank10_reader_table_value1_r; +wire csrbank10_reader_table_value1_we; +wire [25:0] csrbank10_reader_table_value1_w; +wire csrbank10_reader_table_value0_re; +wire [31:0] csrbank10_reader_table_value0_r; +wire csrbank10_reader_table_value0_we; +wire [31:0] csrbank10_reader_table_value0_w; +wire csrbank10_reader_table_we0_re; +wire csrbank10_reader_table_we0_r; +wire csrbank10_reader_table_we0_we; +wire csrbank10_reader_table_we0_w; +wire csrbank10_reader_table_loop_prog_n0_re; +wire csrbank10_reader_table_loop_prog_n0_r; +wire csrbank10_reader_table_loop_prog_n0_we; +wire csrbank10_reader_table_loop_prog_n0_w; +wire csrbank10_reader_table_loop_status_re; +wire [31:0] csrbank10_reader_table_loop_status_r; +wire csrbank10_reader_table_loop_status_we; +wire [31:0] csrbank10_reader_table_loop_status_w; +wire csrbank10_reader_table_level_re; +wire [8:0] csrbank10_reader_table_level_r; +wire csrbank10_reader_table_level_we; +wire [8:0] csrbank10_reader_table_level_w; +wire csrbank10_reader_table_flush0_re; +wire csrbank10_reader_table_flush0_r; +wire csrbank10_reader_table_flush0_we; +wire csrbank10_reader_table_flush0_w; +wire csrbank10_loopback_enable0_re; +wire csrbank10_loopback_enable0_r; +wire csrbank10_loopback_enable0_we; +wire csrbank10_loopback_enable0_w; +wire csrbank10_buffering_reader_fifo_depth0_re; +wire [10:0] csrbank10_buffering_reader_fifo_depth0_r; +wire csrbank10_buffering_reader_fifo_depth0_we; +wire [10:0] csrbank10_buffering_reader_fifo_depth0_w; +wire csrbank10_buffering_reader_fifo_level_re; +wire [10:0] csrbank10_buffering_reader_fifo_level_r; +wire csrbank10_buffering_reader_fifo_level_we; +wire [10:0] csrbank10_buffering_reader_fifo_level_w; +wire csrbank10_buffering_writer_fifo_depth0_re; +wire [10:0] csrbank10_buffering_writer_fifo_depth0_r; +wire csrbank10_buffering_writer_fifo_depth0_we; +wire [10:0] csrbank10_buffering_writer_fifo_depth0_w; +wire csrbank10_buffering_writer_fifo_level_re; +wire [10:0] csrbank10_buffering_writer_fifo_level_r; +wire csrbank10_buffering_writer_fifo_level_we; +wire [10:0] csrbank10_buffering_writer_fifo_level_w; +wire csrbank10_sel; +wire [13:0] interface11_bank_bus_adr; +wire interface11_bank_bus_we; +wire [31:0] interface11_bank_bus_dat_w; +reg [31:0] interface11_bank_bus_dat_r = 32'd0; +wire csrbank11_writer_enable0_re; +wire csrbank11_writer_enable0_r; +wire csrbank11_writer_enable0_we; +wire csrbank11_writer_enable0_w; +wire csrbank11_writer_table_value1_re; +wire [25:0] csrbank11_writer_table_value1_r; +wire csrbank11_writer_table_value1_we; +wire [25:0] csrbank11_writer_table_value1_w; +wire csrbank11_writer_table_value0_re; +wire [31:0] csrbank11_writer_table_value0_r; +wire csrbank11_writer_table_value0_we; +wire [31:0] csrbank11_writer_table_value0_w; +wire csrbank11_writer_table_we0_re; +wire csrbank11_writer_table_we0_r; +wire csrbank11_writer_table_we0_we; +wire csrbank11_writer_table_we0_w; +wire csrbank11_writer_table_loop_prog_n0_re; +wire csrbank11_writer_table_loop_prog_n0_r; +wire csrbank11_writer_table_loop_prog_n0_we; +wire csrbank11_writer_table_loop_prog_n0_w; +wire csrbank11_writer_table_loop_status_re; +wire [31:0] csrbank11_writer_table_loop_status_r; +wire csrbank11_writer_table_loop_status_we; +wire [31:0] csrbank11_writer_table_loop_status_w; +wire csrbank11_writer_table_level_re; +wire [8:0] csrbank11_writer_table_level_r; +wire csrbank11_writer_table_level_we; +wire [8:0] csrbank11_writer_table_level_w; +wire csrbank11_writer_table_flush0_re; +wire csrbank11_writer_table_flush0_r; +wire csrbank11_writer_table_flush0_we; +wire csrbank11_writer_table_flush0_w; +wire csrbank11_reader_enable0_re; +wire csrbank11_reader_enable0_r; +wire csrbank11_reader_enable0_we; +wire csrbank11_reader_enable0_w; +wire csrbank11_reader_table_value1_re; +wire [25:0] csrbank11_reader_table_value1_r; +wire csrbank11_reader_table_value1_we; +wire [25:0] csrbank11_reader_table_value1_w; +wire csrbank11_reader_table_value0_re; +wire [31:0] csrbank11_reader_table_value0_r; +wire csrbank11_reader_table_value0_we; +wire [31:0] csrbank11_reader_table_value0_w; +wire csrbank11_reader_table_we0_re; +wire csrbank11_reader_table_we0_r; +wire csrbank11_reader_table_we0_we; +wire csrbank11_reader_table_we0_w; +wire csrbank11_reader_table_loop_prog_n0_re; +wire csrbank11_reader_table_loop_prog_n0_r; +wire csrbank11_reader_table_loop_prog_n0_we; +wire csrbank11_reader_table_loop_prog_n0_w; +wire csrbank11_reader_table_loop_status_re; +wire [31:0] csrbank11_reader_table_loop_status_r; +wire csrbank11_reader_table_loop_status_we; +wire [31:0] csrbank11_reader_table_loop_status_w; +wire csrbank11_reader_table_level_re; +wire [8:0] csrbank11_reader_table_level_r; +wire csrbank11_reader_table_level_we; +wire [8:0] csrbank11_reader_table_level_w; +wire csrbank11_reader_table_flush0_re; +wire csrbank11_reader_table_flush0_r; +wire csrbank11_reader_table_flush0_we; +wire csrbank11_reader_table_flush0_w; +wire csrbank11_loopback_enable0_re; +wire csrbank11_loopback_enable0_r; +wire csrbank11_loopback_enable0_we; +wire csrbank11_loopback_enable0_w; +wire csrbank11_buffering_reader_fifo_depth0_re; +wire [10:0] csrbank11_buffering_reader_fifo_depth0_r; +wire csrbank11_buffering_reader_fifo_depth0_we; +wire [10:0] csrbank11_buffering_reader_fifo_depth0_w; +wire csrbank11_buffering_reader_fifo_level_re; +wire [10:0] csrbank11_buffering_reader_fifo_level_r; +wire csrbank11_buffering_reader_fifo_level_we; +wire [10:0] csrbank11_buffering_reader_fifo_level_w; +wire csrbank11_buffering_writer_fifo_depth0_re; +wire [10:0] csrbank11_buffering_writer_fifo_depth0_r; +wire csrbank11_buffering_writer_fifo_depth0_we; +wire [10:0] csrbank11_buffering_writer_fifo_depth0_w; +wire csrbank11_buffering_writer_fifo_level_re; +wire [10:0] csrbank11_buffering_writer_fifo_level_r; +wire csrbank11_buffering_writer_fifo_level_we; +wire [10:0] csrbank11_buffering_writer_fifo_level_w; +wire csrbank11_sel; +wire [13:0] interface12_bank_bus_adr; +wire interface12_bank_bus_we; +wire [31:0] interface12_bank_bus_dat_w; +reg [31:0] interface12_bank_bus_dat_r = 32'd0; +wire csrbank12_enable0_re; +wire [31:0] csrbank12_enable0_r; +wire csrbank12_enable0_we; +wire [31:0] csrbank12_enable0_w; +wire csrbank12_clear0_re; +wire [31:0] csrbank12_clear0_r; +wire csrbank12_clear0_we; +wire [31:0] csrbank12_clear0_w; +wire csrbank12_vector_re; +wire [31:0] csrbank12_vector_r; +wire csrbank12_vector_we; +wire [31:0] csrbank12_vector_w; +wire csrbank12_sel; +wire [13:0] interface13_bank_bus_adr; +wire interface13_bank_bus_we; +wire [31:0] interface13_bank_bus_dat_w; +reg [31:0] interface13_bank_bus_dat_r = 32'd0; +wire csrbank13_link_status_re; +wire [9:0] csrbank13_link_status_r; +wire csrbank13_link_status_we; +wire [9:0] csrbank13_link_status_w; +wire csrbank13_msi_enable_re; +wire csrbank13_msi_enable_r; +wire csrbank13_msi_enable_we; +wire csrbank13_msi_enable_w; +wire csrbank13_msix_enable_re; +wire csrbank13_msix_enable_r; +wire csrbank13_msix_enable_we; +wire csrbank13_msix_enable_w; +wire csrbank13_bus_master_enable_re; +wire csrbank13_bus_master_enable_r; +wire csrbank13_bus_master_enable_we; +wire csrbank13_bus_master_enable_w; +wire csrbank13_max_request_size_re; +wire [15:0] csrbank13_max_request_size_r; +wire csrbank13_max_request_size_we; +wire [15:0] csrbank13_max_request_size_w; +wire csrbank13_max_payload_size_re; +wire [15:0] csrbank13_max_payload_size_r; +wire csrbank13_max_payload_size_we; +wire [15:0] csrbank13_max_payload_size_w; +wire csrbank13_sel; +wire [13:0] interface14_bank_bus_adr; +wire interface14_bank_bus_we; +wire [31:0] interface14_bank_bus_dat_w; +reg [31:0] interface14_bank_bus_dat_r = 32'd0; +wire csrbank14_dfii_control0_re; +wire [3:0] csrbank14_dfii_control0_r; +wire csrbank14_dfii_control0_we; +wire [3:0] csrbank14_dfii_control0_w; +wire csrbank14_dfii_pi0_command0_re; +wire [5:0] csrbank14_dfii_pi0_command0_r; +wire csrbank14_dfii_pi0_command0_we; +wire [5:0] csrbank14_dfii_pi0_command0_w; +wire csrbank14_dfii_pi0_address0_re; +wire [13:0] csrbank14_dfii_pi0_address0_r; +wire csrbank14_dfii_pi0_address0_we; +wire [13:0] csrbank14_dfii_pi0_address0_w; +wire csrbank14_dfii_pi0_baddress0_re; +wire [2:0] csrbank14_dfii_pi0_baddress0_r; +wire csrbank14_dfii_pi0_baddress0_we; +wire [2:0] csrbank14_dfii_pi0_baddress0_w; +wire csrbank14_dfii_pi0_wrdata1_re; +wire [31:0] csrbank14_dfii_pi0_wrdata1_r; +wire csrbank14_dfii_pi0_wrdata1_we; +wire [31:0] csrbank14_dfii_pi0_wrdata1_w; +wire csrbank14_dfii_pi0_wrdata0_re; +wire [31:0] csrbank14_dfii_pi0_wrdata0_r; +wire csrbank14_dfii_pi0_wrdata0_we; +wire [31:0] csrbank14_dfii_pi0_wrdata0_w; +wire csrbank14_dfii_pi0_rddata1_re; +wire [31:0] csrbank14_dfii_pi0_rddata1_r; +wire csrbank14_dfii_pi0_rddata1_we; +wire [31:0] csrbank14_dfii_pi0_rddata1_w; +wire csrbank14_dfii_pi0_rddata0_re; +wire [31:0] csrbank14_dfii_pi0_rddata0_r; +wire csrbank14_dfii_pi0_rddata0_we; +wire [31:0] csrbank14_dfii_pi0_rddata0_w; +wire csrbank14_dfii_pi1_command0_re; +wire [5:0] csrbank14_dfii_pi1_command0_r; +wire csrbank14_dfii_pi1_command0_we; +wire [5:0] csrbank14_dfii_pi1_command0_w; +wire csrbank14_dfii_pi1_address0_re; +wire [13:0] csrbank14_dfii_pi1_address0_r; +wire csrbank14_dfii_pi1_address0_we; +wire [13:0] csrbank14_dfii_pi1_address0_w; +wire csrbank14_dfii_pi1_baddress0_re; +wire [2:0] csrbank14_dfii_pi1_baddress0_r; +wire csrbank14_dfii_pi1_baddress0_we; +wire [2:0] csrbank14_dfii_pi1_baddress0_w; +wire csrbank14_dfii_pi1_wrdata1_re; +wire [31:0] csrbank14_dfii_pi1_wrdata1_r; +wire csrbank14_dfii_pi1_wrdata1_we; +wire [31:0] csrbank14_dfii_pi1_wrdata1_w; +wire csrbank14_dfii_pi1_wrdata0_re; +wire [31:0] csrbank14_dfii_pi1_wrdata0_r; +wire csrbank14_dfii_pi1_wrdata0_we; +wire [31:0] csrbank14_dfii_pi1_wrdata0_w; +wire csrbank14_dfii_pi1_rddata1_re; +wire [31:0] csrbank14_dfii_pi1_rddata1_r; +wire csrbank14_dfii_pi1_rddata1_we; +wire [31:0] csrbank14_dfii_pi1_rddata1_w; +wire csrbank14_dfii_pi1_rddata0_re; +wire [31:0] csrbank14_dfii_pi1_rddata0_r; +wire csrbank14_dfii_pi1_rddata0_we; +wire [31:0] csrbank14_dfii_pi1_rddata0_w; +wire csrbank14_dfii_pi2_command0_re; +wire [5:0] csrbank14_dfii_pi2_command0_r; +wire csrbank14_dfii_pi2_command0_we; +wire [5:0] csrbank14_dfii_pi2_command0_w; +wire csrbank14_dfii_pi2_address0_re; +wire [13:0] csrbank14_dfii_pi2_address0_r; +wire csrbank14_dfii_pi2_address0_we; +wire [13:0] csrbank14_dfii_pi2_address0_w; +wire csrbank14_dfii_pi2_baddress0_re; +wire [2:0] csrbank14_dfii_pi2_baddress0_r; +wire csrbank14_dfii_pi2_baddress0_we; +wire [2:0] csrbank14_dfii_pi2_baddress0_w; +wire csrbank14_dfii_pi2_wrdata1_re; +wire [31:0] csrbank14_dfii_pi2_wrdata1_r; +wire csrbank14_dfii_pi2_wrdata1_we; +wire [31:0] csrbank14_dfii_pi2_wrdata1_w; +wire csrbank14_dfii_pi2_wrdata0_re; +wire [31:0] csrbank14_dfii_pi2_wrdata0_r; +wire csrbank14_dfii_pi2_wrdata0_we; +wire [31:0] csrbank14_dfii_pi2_wrdata0_w; +wire csrbank14_dfii_pi2_rddata1_re; +wire [31:0] csrbank14_dfii_pi2_rddata1_r; +wire csrbank14_dfii_pi2_rddata1_we; +wire [31:0] csrbank14_dfii_pi2_rddata1_w; +wire csrbank14_dfii_pi2_rddata0_re; +wire [31:0] csrbank14_dfii_pi2_rddata0_r; +wire csrbank14_dfii_pi2_rddata0_we; +wire [31:0] csrbank14_dfii_pi2_rddata0_w; +wire csrbank14_dfii_pi3_command0_re; +wire [5:0] csrbank14_dfii_pi3_command0_r; +wire csrbank14_dfii_pi3_command0_we; +wire [5:0] csrbank14_dfii_pi3_command0_w; +wire csrbank14_dfii_pi3_address0_re; +wire [13:0] csrbank14_dfii_pi3_address0_r; +wire csrbank14_dfii_pi3_address0_we; +wire [13:0] csrbank14_dfii_pi3_address0_w; +wire csrbank14_dfii_pi3_baddress0_re; +wire [2:0] csrbank14_dfii_pi3_baddress0_r; +wire csrbank14_dfii_pi3_baddress0_we; +wire [2:0] csrbank14_dfii_pi3_baddress0_w; +wire csrbank14_dfii_pi3_wrdata1_re; +wire [31:0] csrbank14_dfii_pi3_wrdata1_r; +wire csrbank14_dfii_pi3_wrdata1_we; +wire [31:0] csrbank14_dfii_pi3_wrdata1_w; +wire csrbank14_dfii_pi3_wrdata0_re; +wire [31:0] csrbank14_dfii_pi3_wrdata0_r; +wire csrbank14_dfii_pi3_wrdata0_we; +wire [31:0] csrbank14_dfii_pi3_wrdata0_w; +wire csrbank14_dfii_pi3_rddata1_re; +wire [31:0] csrbank14_dfii_pi3_rddata1_r; +wire csrbank14_dfii_pi3_rddata1_we; +wire [31:0] csrbank14_dfii_pi3_rddata1_w; +wire csrbank14_dfii_pi3_rddata0_re; +wire [31:0] csrbank14_dfii_pi3_rddata0_r; +wire csrbank14_dfii_pi3_rddata0_we; +wire [31:0] csrbank14_dfii_pi3_rddata0_w; +wire csrbank14_sel; +wire [13:0] interface15_bank_bus_adr; +wire interface15_bank_bus_we; +wire [31:0] interface15_bank_bus_dat_w; +reg [31:0] interface15_bank_bus_dat_r = 32'd0; +wire csrbank15_load0_re; +wire [31:0] csrbank15_load0_r; +wire csrbank15_load0_we; +wire [31:0] csrbank15_load0_w; +wire csrbank15_reload0_re; +wire [31:0] csrbank15_reload0_r; +wire csrbank15_reload0_we; +wire [31:0] csrbank15_reload0_w; +wire csrbank15_en0_re; +wire csrbank15_en0_r; +wire csrbank15_en0_we; +wire csrbank15_en0_w; +wire csrbank15_update_value0_re; +wire csrbank15_update_value0_r; +wire csrbank15_update_value0_we; +wire csrbank15_update_value0_w; +wire csrbank15_value_re; +wire [31:0] csrbank15_value_r; +wire csrbank15_value_we; +wire [31:0] csrbank15_value_w; +wire csrbank15_ev_enable0_re; +wire csrbank15_ev_enable0_r; +wire csrbank15_ev_enable0_we; +wire csrbank15_ev_enable0_w; +wire csrbank15_sel; +wire [13:0] interface16_bank_bus_adr; +wire interface16_bank_bus_we; +wire [31:0] interface16_bank_bus_dat_w; +reg [31:0] interface16_bank_bus_dat_r = 32'd0; +wire csrbank16_txfull_re; +wire csrbank16_txfull_r; +wire csrbank16_txfull_we; +wire csrbank16_txfull_w; +wire csrbank16_rxempty_re; +wire csrbank16_rxempty_r; +wire csrbank16_rxempty_we; +wire csrbank16_rxempty_w; +wire csrbank16_ev_enable0_re; +wire [1:0] csrbank16_ev_enable0_r; +wire csrbank16_ev_enable0_we; +wire [1:0] csrbank16_ev_enable0_w; +wire csrbank16_txempty_re; +wire csrbank16_txempty_r; +wire csrbank16_txempty_we; +wire csrbank16_txempty_w; +wire csrbank16_rxfull_re; +wire csrbank16_rxfull_r; +wire csrbank16_rxfull_we; +wire csrbank16_rxfull_w; +wire csrbank16_xover_txfull_re; +wire csrbank16_xover_txfull_r; +wire csrbank16_xover_txfull_we; +wire csrbank16_xover_txfull_w; +wire csrbank16_xover_rxempty_re; +wire csrbank16_xover_rxempty_r; +wire csrbank16_xover_rxempty_we; +wire csrbank16_xover_rxempty_w; +wire csrbank16_xover_ev_enable0_re; +wire [1:0] csrbank16_xover_ev_enable0_r; +wire csrbank16_xover_ev_enable0_we; +wire [1:0] csrbank16_xover_ev_enable0_w; +wire csrbank16_xover_txempty_re; +wire csrbank16_xover_txempty_r; +wire csrbank16_xover_txempty_we; +wire csrbank16_xover_txempty_w; +wire csrbank16_xover_rxfull_re; +wire csrbank16_xover_rxfull_r; +wire csrbank16_xover_rxfull_we; +wire csrbank16_xover_rxfull_w; +wire csrbank16_sel; +wire [13:0] interface17_bank_bus_adr; +wire interface17_bank_bus_we; +wire [31:0] interface17_bank_bus_dat_w; +reg [31:0] interface17_bank_bus_dat_r = 32'd0; +wire csrbank17_temperature_re; +wire [11:0] csrbank17_temperature_r; +wire csrbank17_temperature_we; +wire [11:0] csrbank17_temperature_w; +wire csrbank17_vccint_re; +wire [11:0] csrbank17_vccint_r; +wire csrbank17_vccint_we; +wire [11:0] csrbank17_vccint_w; +wire csrbank17_vccaux_re; +wire [11:0] csrbank17_vccaux_r; +wire csrbank17_vccaux_we; +wire [11:0] csrbank17_vccaux_w; +wire csrbank17_vccbram_re; +wire [11:0] csrbank17_vccbram_r; +wire csrbank17_vccbram_we; +wire [11:0] csrbank17_vccbram_w; +wire csrbank17_eoc_re; +wire csrbank17_eoc_r; +wire csrbank17_eoc_we; +wire csrbank17_eoc_w; +wire csrbank17_eos_re; +wire csrbank17_eos_r; +wire csrbank17_eos_we; +wire csrbank17_eos_w; +wire csrbank17_sel; +wire [13:0] csr_interconnect_adr; +wire csr_interconnect_we; +wire [31:0] csr_interconnect_dat_w; +wire [31:0] csr_interconnect_dat_r; +reg [1:0] state = 2'd0; +reg [1:0] next_state = 2'd0; +reg [31:0] netv2_dat_w_next_value0 = 32'd0; +reg netv2_dat_w_next_value_ce0 = 1'd0; +reg [13:0] netv2_adr_next_value1 = 14'd0; +reg netv2_adr_next_value_ce1 = 1'd0; +reg netv2_we_next_value2 = 1'd0; +reg netv2_we_next_value_ce2 = 1'd0; +wire [15:0] rhs_slice_proxy0; +wire [15:0] rhs_slice_proxy1; +wire [47:0] rhs_slice_proxy2; +wire [47:0] rhs_slice_proxy3; +wire [47:0] rhs_slice_proxy4; +wire [47:0] rhs_slice_proxy5; +wire [47:0] rhs_slice_proxy6; +wire [47:0] rhs_slice_proxy7; +wire [47:0] rhs_slice_proxy8; +wire [47:0] rhs_slice_proxy9; +wire [47:0] rhs_slice_proxy10; +wire [47:0] rhs_slice_proxy11; +wire [47:0] rhs_slice_proxy12; +wire [47:0] rhs_slice_proxy13; +wire [7:0] rhs_slice_proxy14; +wire [15:0] rhs_slice_proxy15; +wire [15:0] rhs_slice_proxy16; +wire [15:0] rhs_slice_proxy17; +wire [15:0] rhs_slice_proxy18; +wire [15:0] rhs_slice_proxy19; +wire [15:0] rhs_slice_proxy20; +wire [7:0] rhs_slice_proxy21; +wire [31:0] rhs_slice_proxy22; +wire [31:0] rhs_slice_proxy23; +wire [31:0] rhs_slice_proxy24; +wire [31:0] rhs_slice_proxy25; +wire [47:0] rhs_slice_proxy26; +wire [47:0] rhs_slice_proxy27; +wire [47:0] rhs_slice_proxy28; +wire [47:0] rhs_slice_proxy29; +wire [47:0] rhs_slice_proxy30; +wire [47:0] rhs_slice_proxy31; +wire [31:0] rhs_slice_proxy32; +wire [31:0] rhs_slice_proxy33; +wire [31:0] rhs_slice_proxy34; +wire [31:0] rhs_slice_proxy35; +wire [47:0] rhs_slice_proxy36; +wire [47:0] rhs_slice_proxy37; +wire [47:0] rhs_slice_proxy38; +wire [47:0] rhs_slice_proxy39; +wire [47:0] rhs_slice_proxy40; +wire [47:0] rhs_slice_proxy41; +wire [15:0] rhs_slice_proxy42; +wire [15:0] rhs_slice_proxy43; +wire [15:0] rhs_slice_proxy44; +wire [15:0] rhs_slice_proxy45; +wire [3:0] rhs_slice_proxy46; +wire [7:0] rhs_slice_proxy47; +wire [31:0] rhs_slice_proxy48; +wire [31:0] rhs_slice_proxy49; +wire [31:0] rhs_slice_proxy50; +wire [31:0] rhs_slice_proxy51; +wire [31:0] rhs_slice_proxy52; +wire [31:0] rhs_slice_proxy53; +wire [31:0] rhs_slice_proxy54; +wire [31:0] rhs_slice_proxy55; +wire [15:0] rhs_slice_proxy56; +wire [15:0] rhs_slice_proxy57; +wire [7:0] rhs_slice_proxy58; +wire [3:0] rhs_slice_proxy59; +wire [15:0] rhs_slice_proxy60; +wire [15:0] rhs_slice_proxy61; +wire [7:0] rhs_slice_proxy62; +wire [7:0] rhs_slice_proxy63; +wire [31:0] rhs_slice_proxy64; +wire [31:0] rhs_slice_proxy65; +wire [31:0] rhs_slice_proxy66; +wire [31:0] rhs_slice_proxy67; +wire [15:0] rhs_slice_proxy68; +wire [15:0] rhs_slice_proxy69; +wire [15:0] rhs_slice_proxy70; +wire [15:0] rhs_slice_proxy71; +wire [15:0] rhs_slice_proxy72; +wire [15:0] rhs_slice_proxy73; +wire [15:0] rhs_slice_proxy74; +wire [15:0] rhs_slice_proxy75; +wire [3:0] rhs_slice_proxy76; +wire [15:0] rhs_slice_proxy77; +wire [15:0] rhs_slice_proxy78; +wire rhs_slice_proxy79; +wire rhs_slice_proxy80; +wire [3:0] rhs_slice_proxy81; +wire rhs_slice_proxy82; +wire [3:0] rhs_slice_proxy83; +wire rhs_slice_proxy84; +wire [7:0] rhs_slice_proxy85; +wire rhs_slice_proxy86; +wire rhs_slice_proxy87; +wire [7:0] rhs_slice_proxy88; +wire rhs_slice_proxy89; +wire rhs_slice_proxy90; +wire [7:0] rhs_slice_proxy91; +wire rhs_slice_proxy92; +wire [31:0] rhs_slice_proxy93; +wire [31:0] rhs_slice_proxy94; +wire [31:0] rhs_slice_proxy95; +wire [31:0] rhs_slice_proxy96; +wire [31:0] rhs_slice_proxy97; +wire [31:0] rhs_slice_proxy98; +wire [31:0] rhs_slice_proxy99; +wire [31:0] rhs_slice_proxy100; +wire [3:0] rhs_slice_proxy101; +wire [3:0] rhs_slice_proxy102; +wire [3:0] rhs_slice_proxy103; +wire [3:0] rhs_slice_proxy104; +wire [3:0] rhs_slice_proxy105; +wire [3:0] rhs_slice_proxy106; +wire [3:0] rhs_slice_proxy107; +wire [3:0] rhs_slice_proxy108; +wire [31:0] cases_slice_proxy0; +wire [31:0] cases_slice_proxy1; +wire [31:0] cases_slice_proxy2; +wire [31:0] cases_slice_proxy3; +wire [3:0] cases_slice_proxy4; +wire [3:0] cases_slice_proxy5; +wire [3:0] cases_slice_proxy6; +wire [3:0] cases_slice_proxy7; +wire [31:0] cases_slice_proxy8; +wire [31:0] cases_slice_proxy9; +wire [31:0] cases_slice_proxy10; +wire [31:0] cases_slice_proxy11; +wire [31:0] cases_slice_proxy12; +wire [31:0] cases_slice_proxy13; +wire [31:0] cases_slice_proxy14; +wire [31:0] cases_slice_proxy15; +wire [7:0] slice_proxy0; +wire [7:0] slice_proxy1; +wire [7:0] slice_proxy2; +wire [7:0] slice_proxy3; +wire [7:0] slice_proxy4; +wire [7:0] slice_proxy5; +wire [7:0] slice_proxy6; +wire [7:0] slice_proxy7; +wire [7:0] slice_proxy8; +wire [7:0] slice_proxy9; +wire [7:0] slice_proxy10; +wire [7:0] slice_proxy11; +wire [7:0] slice_proxy12; +wire [7:0] slice_proxy13; +wire [7:0] slice_proxy14; +wire [7:0] slice_proxy15; +wire [7:0] slice_proxy16; +wire [7:0] slice_proxy17; +wire [7:0] slice_proxy18; +wire [7:0] slice_proxy19; +wire [7:0] slice_proxy20; +wire [7:0] slice_proxy21; +wire [7:0] slice_proxy22; +wire [7:0] slice_proxy23; +wire [7:0] slice_proxy24; +wire [7:0] slice_proxy25; +wire [7:0] slice_proxy26; +wire [7:0] slice_proxy27; +wire [7:0] slice_proxy28; +wire [7:0] slice_proxy29; +wire [7:0] slice_proxy30; +wire [7:0] slice_proxy31; +reg comb_rhs_array_muxed0 = 1'd0; +reg [13:0] comb_rhs_array_muxed1 = 14'd0; +reg [2:0] comb_rhs_array_muxed2 = 3'd0; +reg comb_rhs_array_muxed3 = 1'd0; +reg comb_rhs_array_muxed4 = 1'd0; +reg comb_rhs_array_muxed5 = 1'd0; +reg comb_t_array_muxed0 = 1'd0; +reg comb_t_array_muxed1 = 1'd0; +reg comb_t_array_muxed2 = 1'd0; +reg comb_rhs_array_muxed6 = 1'd0; +reg [13:0] comb_rhs_array_muxed7 = 14'd0; +reg [2:0] comb_rhs_array_muxed8 = 3'd0; +reg comb_rhs_array_muxed9 = 1'd0; +reg comb_rhs_array_muxed10 = 1'd0; +reg comb_rhs_array_muxed11 = 1'd0; +reg comb_t_array_muxed3 = 1'd0; +reg comb_t_array_muxed4 = 1'd0; +reg comb_t_array_muxed5 = 1'd0; +reg [20:0] comb_rhs_array_muxed12 = 21'd0; +reg comb_rhs_array_muxed13 = 1'd0; +reg comb_rhs_array_muxed14 = 1'd0; +reg [20:0] comb_rhs_array_muxed15 = 21'd0; +reg comb_rhs_array_muxed16 = 1'd0; +reg comb_rhs_array_muxed17 = 1'd0; +reg [20:0] comb_rhs_array_muxed18 = 21'd0; +reg comb_rhs_array_muxed19 = 1'd0; +reg comb_rhs_array_muxed20 = 1'd0; +reg [20:0] comb_rhs_array_muxed21 = 21'd0; +reg comb_rhs_array_muxed22 = 1'd0; +reg comb_rhs_array_muxed23 = 1'd0; +reg [20:0] comb_rhs_array_muxed24 = 21'd0; +reg comb_rhs_array_muxed25 = 1'd0; +reg comb_rhs_array_muxed26 = 1'd0; +reg [20:0] comb_rhs_array_muxed27 = 21'd0; +reg comb_rhs_array_muxed28 = 1'd0; +reg comb_rhs_array_muxed29 = 1'd0; +reg [20:0] comb_rhs_array_muxed30 = 21'd0; +reg comb_rhs_array_muxed31 = 1'd0; +reg comb_rhs_array_muxed32 = 1'd0; +reg [20:0] comb_rhs_array_muxed33 = 21'd0; +reg comb_rhs_array_muxed34 = 1'd0; +reg comb_rhs_array_muxed35 = 1'd0; +reg [23:0] comb_rhs_array_muxed36 = 24'd0; +reg comb_rhs_array_muxed37 = 1'd0; +reg [29:0] comb_rhs_array_muxed38 = 30'd0; +reg [31:0] comb_rhs_array_muxed39 = 32'd0; +reg [3:0] comb_rhs_array_muxed40 = 4'd0; +reg comb_rhs_array_muxed41 = 1'd0; +reg comb_rhs_array_muxed42 = 1'd0; +reg comb_rhs_array_muxed43 = 1'd0; +reg [2:0] comb_rhs_array_muxed44 = 3'd0; +reg [1:0] comb_rhs_array_muxed45 = 2'd0; +reg [9:0] sync_rhs_array_muxed0 = 10'd0; +reg [9:0] sync_rhs_array_muxed1 = 10'd0; +reg [9:0] sync_rhs_array_muxed2 = 10'd0; +reg sync_t_array_muxed = 1'd0; +reg [2:0] sync_array_muxed0 = 3'd0; +reg [13:0] sync_array_muxed1 = 14'd0; +reg sync_array_muxed2 = 1'd0; +reg sync_array_muxed3 = 1'd0; +reg sync_array_muxed4 = 1'd0; +reg sync_array_muxed5 = 1'd0; +reg sync_array_muxed6 = 1'd0; +reg [2:0] sync_array_muxed7 = 3'd0; +reg [13:0] sync_array_muxed8 = 14'd0; +reg sync_array_muxed9 = 1'd0; +reg sync_array_muxed10 = 1'd0; +reg sync_array_muxed11 = 1'd0; +reg sync_array_muxed12 = 1'd0; +reg sync_array_muxed13 = 1'd0; +reg [2:0] sync_array_muxed14 = 3'd0; +reg [13:0] sync_array_muxed15 = 14'd0; +reg sync_array_muxed16 = 1'd0; +reg sync_array_muxed17 = 1'd0; +reg sync_array_muxed18 = 1'd0; +reg sync_array_muxed19 = 1'd0; +reg sync_array_muxed20 = 1'd0; +reg [2:0] sync_array_muxed21 = 3'd0; +reg [13:0] sync_array_muxed22 = 14'd0; +reg sync_array_muxed23 = 1'd0; +reg sync_array_muxed24 = 1'd0; +reg sync_array_muxed25 = 1'd0; +reg sync_array_muxed26 = 1'd0; +reg sync_array_muxed27 = 1'd0; +wire xilinxasyncresetsynchronizerimpl0; +wire xilinxasyncresetsynchronizerimpl0_rst_meta; +wire xilinxasyncresetsynchronizerimpl1; +wire xilinxasyncresetsynchronizerimpl1_rst_meta; +wire xilinxasyncresetsynchronizerimpl1_expr; +wire xilinxasyncresetsynchronizerimpl2; +wire xilinxasyncresetsynchronizerimpl2_rst_meta; +wire xilinxasyncresetsynchronizerimpl2_expr; +wire xilinxasyncresetsynchronizerimpl3; +wire xilinxasyncresetsynchronizerimpl3_rst_meta; +wire xilinxasyncresetsynchronizerimpl4; +wire xilinxasyncresetsynchronizerimpl4_rst_meta; +wire xilinxasyncresetsynchronizerimpl5; +wire xilinxasyncresetsynchronizerimpl5_rst_meta; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs1 = 1'd0; +wire xilinxasyncresetsynchronizerimpl6_rst_meta; +wire xilinxasyncresetsynchronizerimpl7_rst_meta; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl1_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl1_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl2_regs0 = 2'd0; +(* async_reg = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl2_regs1 = 2'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl3_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl3_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl4_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl4_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl5_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl5_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [6:0] xilinxmultiregimpl6_regs0 = 7'd0; +(* async_reg = "true", dont_touch = "true" *) reg [6:0] xilinxmultiregimpl6_regs1 = 7'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [6:0] xilinxmultiregimpl7_regs0 = 7'd0; +(* async_reg = "true", dont_touch = "true" *) reg [6:0] xilinxmultiregimpl7_regs1 = 7'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [6:0] xilinxmultiregimpl8_regs0 = 7'd0; +(* async_reg = "true", dont_touch = "true" *) reg [6:0] xilinxmultiregimpl8_regs1 = 7'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [6:0] xilinxmultiregimpl9_regs0 = 7'd0; +(* async_reg = "true", dont_touch = "true" *) reg [6:0] xilinxmultiregimpl9_regs1 = 7'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl10_regs0 = 3'd0; +(* async_reg = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl10_regs1 = 3'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl11_regs0 = 3'd0; +(* async_reg = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl11_regs1 = 3'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl12_regs0 = 3'd0; +(* async_reg = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl12_regs1 = 3'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl13_regs0 = 3'd0; +(* async_reg = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl13_regs1 = 3'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl14_regs0 = 3'd0; +(* async_reg = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl14_regs1 = 3'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl15_regs0 = 3'd0; +(* async_reg = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl15_regs1 = 3'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl16_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl16_regs1 = 1'd0; +wire xilinxmultiregimpl16; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [15:0] xilinxmultiregimpl17_regs0 = 16'd0; +(* async_reg = "true", dont_touch = "true" *) reg [15:0] xilinxmultiregimpl17_regs1 = 16'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [15:0] xilinxmultiregimpl18_regs0 = 16'd0; +(* async_reg = "true", dont_touch = "true" *) reg [15:0] xilinxmultiregimpl18_regs1 = 16'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl19_regs0 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl19_regs1 = 6'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl20_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl20_regs1 = 1'd0; +wire xilinxmultiregimpl20; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl21_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl21_regs1 = 1'd0; +wire xilinxmultiregimpl21; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl22_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl22_regs1 = 1'd0; +wire xilinxasyncresetsynchronizerimpl8; +wire xilinxasyncresetsynchronizerimpl8_rst_meta; +wire xilinxasyncresetsynchronizerimpl9; +wire xilinxasyncresetsynchronizerimpl9_rst_meta; +wire xilinxasyncresetsynchronizerimpl10; +wire xilinxasyncresetsynchronizerimpl10_rst_meta; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl23_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl23_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl24_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl24_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [4:0] xilinxmultiregimpl25_regs0 = 5'd0; +(* async_reg = "true", dont_touch = "true" *) reg [4:0] xilinxmultiregimpl25_regs1 = 5'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl26_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl26_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl27_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl27_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [4:0] xilinxmultiregimpl28_regs0 = 5'd0; +(* async_reg = "true", dont_touch = "true" *) reg [4:0] xilinxmultiregimpl28_regs1 = 5'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl29_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl29_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl30_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl30_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl31_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl31_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl32_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl32_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl33_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl33_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl34_regs0 = 2'd0; +(* async_reg = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl34_regs1 = 2'd0; +wire xilinxmultiregimpl34; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl35_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl35_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl36_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl36_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl37_regs0 = 4'd0; +(* async_reg = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl37_regs1 = 4'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl38_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl38_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl39_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl39_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl40_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl40_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [4:0] xilinxmultiregimpl41_regs0 = 5'd0; +(* async_reg = "true", dont_touch = "true" *) reg [4:0] xilinxmultiregimpl41_regs1 = 5'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl42_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl42_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl43_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl43_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [4:0] xilinxmultiregimpl44_regs0 = 5'd0; +(* async_reg = "true", dont_touch = "true" *) reg [4:0] xilinxmultiregimpl44_regs1 = 5'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl45_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl45_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl46_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl46_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl47_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl47_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl48_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl48_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl49_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl49_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl50_regs0 = 2'd0; +(* async_reg = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl50_regs1 = 2'd0; +wire xilinxmultiregimpl50; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl51_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl51_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl52_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl52_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl53_regs0 = 4'd0; +(* async_reg = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl53_regs1 = 4'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl54_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl54_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl55_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl55_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl56_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl56_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [4:0] xilinxmultiregimpl57_regs0 = 5'd0; +(* async_reg = "true", dont_touch = "true" *) reg [4:0] xilinxmultiregimpl57_regs1 = 5'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl58_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl58_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl59_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl59_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [4:0] xilinxmultiregimpl60_regs0 = 5'd0; +(* async_reg = "true", dont_touch = "true" *) reg [4:0] xilinxmultiregimpl60_regs1 = 5'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl61_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl61_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl62_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl62_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl63_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl63_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl64_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl64_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl65_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl65_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl66_regs0 = 2'd0; +(* async_reg = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl66_regs1 = 2'd0; +wire xilinxmultiregimpl66; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl67_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl67_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl68_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl68_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl69_regs0 = 4'd0; +(* async_reg = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl69_regs1 = 4'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl70_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl70_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl71_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl71_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [10:0] xilinxmultiregimpl72_regs0 = 11'd0; +(* async_reg = "true", dont_touch = "true" *) reg [10:0] xilinxmultiregimpl72_regs1 = 11'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [10:0] xilinxmultiregimpl73_regs0 = 11'd0; +(* async_reg = "true", dont_touch = "true" *) reg [10:0] xilinxmultiregimpl73_regs1 = 11'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [9:0] xilinxmultiregimpl74_regs0 = 10'd0; +(* async_reg = "true", dont_touch = "true" *) reg [9:0] xilinxmultiregimpl74_regs1 = 10'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [9:0] xilinxmultiregimpl75_regs0 = 10'd0; +(* async_reg = "true", dont_touch = "true" *) reg [9:0] xilinxmultiregimpl75_regs1 = 10'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl76_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl76_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl77_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl77_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl78_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl78_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl79_regs0 = 3'd0; +(* async_reg = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl79_regs1 = 3'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl80_regs0 = 3'd0; +(* async_reg = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl80_regs1 = 3'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [4:0] xilinxmultiregimpl81_regs0 = 5'd0; +(* async_reg = "true", dont_touch = "true" *) reg [4:0] xilinxmultiregimpl81_regs1 = 5'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [4:0] xilinxmultiregimpl82_regs0 = 5'd0; +(* async_reg = "true", dont_touch = "true" *) reg [4:0] xilinxmultiregimpl82_regs1 = 5'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl83_regs0 = 3'd0; +(* async_reg = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl83_regs1 = 3'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl84_regs0 = 3'd0; +(* async_reg = "true", dont_touch = "true" *) reg [2:0] xilinxmultiregimpl84_regs1 = 3'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl85_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl85_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl86_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl86_regs1 = 1'd0; + +assign netv2_cpu_reset = netv2_soccontroller_reset; +assign s7pciephy_msi_valid = pcie_msi_source_valid; +assign pcie_msi_source_ready = s7pciephy_msi_ready; +assign s7pciephy_msi_first = pcie_msi_source_first; +assign s7pciephy_msi_last = pcie_msi_source_last; +assign s7pciephy_msi_payload_dat = pcie_msi_source_payload_dat; +always @(*) begin + pcie_msi_irqs <= 32'd0; + pcie_msi_irqs[0] <= pcie_dma0_reader_irq; + pcie_msi_irqs[1] <= pcie_dma0_writer_irq; + pcie_msi_irqs[2] <= pcie_dma1_reader_irq; + pcie_msi_irqs[3] <= pcie_dma1_writer_irq; +end +assign freqmeter = hdmi_in0_pix_clk; +assign netv2_soccontroller_bus_error = error; +always @(*) begin + netv2_cpu_interrupt <= 32'd0; + netv2_cpu_interrupt[1] <= netv2_irq; + netv2_cpu_interrupt[0] <= netv2_uartcrossover_irq; +end +assign netv2_soccontroller_reset = netv2_soccontroller_reset_re; +assign netv2_soccontroller_bus_errors_status = netv2_soccontroller_bus_errors; +assign netv2_netv2_adr = netv2_netv2_ram_bus_adr[12:0]; +assign netv2_netv2_ram_bus_dat_r = netv2_netv2_dat_r; +always @(*) begin + netv2_ram_we <= 4'd0; + netv2_ram_we[0] <= (((netv2_ram_bus_ram_bus_cyc & netv2_ram_bus_ram_bus_stb) & netv2_ram_bus_ram_bus_we) & netv2_ram_bus_ram_bus_sel[0]); + netv2_ram_we[1] <= (((netv2_ram_bus_ram_bus_cyc & netv2_ram_bus_ram_bus_stb) & netv2_ram_bus_ram_bus_we) & netv2_ram_bus_ram_bus_sel[1]); + netv2_ram_we[2] <= (((netv2_ram_bus_ram_bus_cyc & netv2_ram_bus_ram_bus_stb) & netv2_ram_bus_ram_bus_we) & netv2_ram_bus_ram_bus_sel[2]); + netv2_ram_we[3] <= (((netv2_ram_bus_ram_bus_cyc & netv2_ram_bus_ram_bus_stb) & netv2_ram_bus_ram_bus_we) & netv2_ram_bus_ram_bus_sel[3]); +end +assign netv2_ram_adr = netv2_ram_bus_ram_bus_adr[10:0]; +assign netv2_ram_bus_ram_bus_dat_r = netv2_ram_dat_r; +assign netv2_ram_dat_w = netv2_ram_bus_ram_bus_dat_w; +assign netv2_uartcrossover_tx_fifo_sink_valid = netv2_uartcrossover_rxtx_re; +assign netv2_uartcrossover_tx_fifo_sink_payload_data = netv2_uartcrossover_rxtx_r; +assign netv2_uartcrossover_txfull_status = (~netv2_uartcrossover_tx_fifo_sink_ready); +assign netv2_uartcrossover_txempty_status = (~netv2_uartcrossover_tx_fifo_source_valid); +assign netv2_uartcrossover_uartcrossover_source_valid = netv2_uartcrossover_tx_fifo_source_valid; +assign netv2_uartcrossover_tx_fifo_source_ready = netv2_uartcrossover_uartcrossover_source_ready; +assign netv2_uartcrossover_uartcrossover_source_first = netv2_uartcrossover_tx_fifo_source_first; +assign netv2_uartcrossover_uartcrossover_source_last = netv2_uartcrossover_tx_fifo_source_last; +assign netv2_uartcrossover_uartcrossover_source_payload_data = netv2_uartcrossover_tx_fifo_source_payload_data; +assign netv2_uartcrossover_tx_trigger = (~netv2_uartcrossover_tx_fifo_sink_ready); +assign netv2_uartcrossover_rx_fifo_sink_valid = netv2_uartcrossover_uartcrossover_sink_valid; +assign netv2_uartcrossover_uartcrossover_sink_ready = netv2_uartcrossover_rx_fifo_sink_ready; +assign netv2_uartcrossover_rx_fifo_sink_first = netv2_uartcrossover_uartcrossover_sink_first; +assign netv2_uartcrossover_rx_fifo_sink_last = netv2_uartcrossover_uartcrossover_sink_last; +assign netv2_uartcrossover_rx_fifo_sink_payload_data = netv2_uartcrossover_uartcrossover_sink_payload_data; +assign netv2_uartcrossover_rxempty_status = (~netv2_uartcrossover_rx_fifo_source_valid); +assign netv2_uartcrossover_rxfull_status = (~netv2_uartcrossover_rx_fifo_sink_ready); +assign netv2_uartcrossover_rxtx_w = netv2_uartcrossover_rx_fifo_source_payload_data; +assign netv2_uartcrossover_rx_fifo_source_ready = (netv2_uartcrossover_rx_clear | (1'd0 & netv2_uartcrossover_rxtx_we)); +assign netv2_uartcrossover_rx_trigger = (~netv2_uartcrossover_rx_fifo_source_valid); +assign netv2_xover_uart_sink_valid = netv2_uartcrossover_uartcrossover_source_valid; +assign netv2_uartcrossover_uartcrossover_source_ready = netv2_xover_uart_sink_ready; +assign netv2_xover_uart_sink_first = netv2_uartcrossover_uartcrossover_source_first; +assign netv2_xover_uart_sink_last = netv2_uartcrossover_uartcrossover_source_last; +assign netv2_xover_uart_sink_payload_data = netv2_uartcrossover_uartcrossover_source_payload_data; +assign netv2_uartcrossover_uartcrossover_sink_valid = netv2_xover_uart_source_valid; +assign netv2_xover_uart_source_ready = netv2_uartcrossover_uartcrossover_sink_ready; +assign netv2_uartcrossover_uartcrossover_sink_first = netv2_xover_uart_source_first; +assign netv2_uartcrossover_uartcrossover_sink_last = netv2_xover_uart_source_last; +assign netv2_uartcrossover_uartcrossover_sink_payload_data = netv2_xover_uart_source_payload_data; +always @(*) begin + netv2_uartcrossover_tx_clear <= 1'd0; + if ((netv2_uartcrossover_eventmanager_pending_re & netv2_uartcrossover_eventmanager_pending_r[0])) begin + netv2_uartcrossover_tx_clear <= 1'd1; + end +end +always @(*) begin + netv2_uartcrossover_eventmanager_status_w <= 2'd0; + netv2_uartcrossover_eventmanager_status_w[0] <= netv2_uartcrossover_tx_status; + netv2_uartcrossover_eventmanager_status_w[1] <= netv2_uartcrossover_rx_status; +end +always @(*) begin + netv2_uartcrossover_rx_clear <= 1'd0; + if ((netv2_uartcrossover_eventmanager_pending_re & netv2_uartcrossover_eventmanager_pending_r[1])) begin + netv2_uartcrossover_rx_clear <= 1'd1; + end +end +always @(*) begin + netv2_uartcrossover_eventmanager_pending_w <= 2'd0; + netv2_uartcrossover_eventmanager_pending_w[0] <= netv2_uartcrossover_tx_pending; + netv2_uartcrossover_eventmanager_pending_w[1] <= netv2_uartcrossover_rx_pending; +end +assign netv2_uartcrossover_irq = ((netv2_uartcrossover_eventmanager_pending_w[0] & netv2_uartcrossover_eventmanager_storage[0]) | (netv2_uartcrossover_eventmanager_pending_w[1] & netv2_uartcrossover_eventmanager_storage[1])); +assign netv2_uartcrossover_tx_status = netv2_uartcrossover_tx_trigger; +assign netv2_uartcrossover_rx_status = netv2_uartcrossover_rx_trigger; +assign netv2_uartcrossover_tx_fifo_syncfifo_din = {netv2_uartcrossover_tx_fifo_fifo_in_last, netv2_uartcrossover_tx_fifo_fifo_in_first, netv2_uartcrossover_tx_fifo_fifo_in_payload_data}; +assign {netv2_uartcrossover_tx_fifo_fifo_out_last, netv2_uartcrossover_tx_fifo_fifo_out_first, netv2_uartcrossover_tx_fifo_fifo_out_payload_data} = netv2_uartcrossover_tx_fifo_syncfifo_dout; +assign netv2_uartcrossover_tx_fifo_sink_ready = netv2_uartcrossover_tx_fifo_syncfifo_writable; +assign netv2_uartcrossover_tx_fifo_syncfifo_we = netv2_uartcrossover_tx_fifo_sink_valid; +assign netv2_uartcrossover_tx_fifo_fifo_in_first = netv2_uartcrossover_tx_fifo_sink_first; +assign netv2_uartcrossover_tx_fifo_fifo_in_last = netv2_uartcrossover_tx_fifo_sink_last; +assign netv2_uartcrossover_tx_fifo_fifo_in_payload_data = netv2_uartcrossover_tx_fifo_sink_payload_data; +assign netv2_uartcrossover_tx_fifo_source_valid = netv2_uartcrossover_tx_fifo_readable; +assign netv2_uartcrossover_tx_fifo_source_first = netv2_uartcrossover_tx_fifo_fifo_out_first; +assign netv2_uartcrossover_tx_fifo_source_last = netv2_uartcrossover_tx_fifo_fifo_out_last; +assign netv2_uartcrossover_tx_fifo_source_payload_data = netv2_uartcrossover_tx_fifo_fifo_out_payload_data; +assign netv2_uartcrossover_tx_fifo_re = netv2_uartcrossover_tx_fifo_source_ready; +assign netv2_uartcrossover_tx_fifo_syncfifo_re = (netv2_uartcrossover_tx_fifo_syncfifo_readable & ((~netv2_uartcrossover_tx_fifo_readable) | netv2_uartcrossover_tx_fifo_re)); +assign netv2_uartcrossover_tx_fifo_level1 = (netv2_uartcrossover_tx_fifo_level0 + netv2_uartcrossover_tx_fifo_readable); +always @(*) begin + netv2_uartcrossover_tx_fifo_wrport_adr <= 4'd0; + if (netv2_uartcrossover_tx_fifo_replace) begin + netv2_uartcrossover_tx_fifo_wrport_adr <= (netv2_uartcrossover_tx_fifo_produce - 1'd1); + end else begin + netv2_uartcrossover_tx_fifo_wrport_adr <= netv2_uartcrossover_tx_fifo_produce; + end +end +assign netv2_uartcrossover_tx_fifo_wrport_dat_w = netv2_uartcrossover_tx_fifo_syncfifo_din; +assign netv2_uartcrossover_tx_fifo_wrport_we = (netv2_uartcrossover_tx_fifo_syncfifo_we & (netv2_uartcrossover_tx_fifo_syncfifo_writable | netv2_uartcrossover_tx_fifo_replace)); +assign netv2_uartcrossover_tx_fifo_do_read = (netv2_uartcrossover_tx_fifo_syncfifo_readable & netv2_uartcrossover_tx_fifo_syncfifo_re); +assign netv2_uartcrossover_tx_fifo_rdport_adr = netv2_uartcrossover_tx_fifo_consume; +assign netv2_uartcrossover_tx_fifo_syncfifo_dout = netv2_uartcrossover_tx_fifo_rdport_dat_r; +assign netv2_uartcrossover_tx_fifo_rdport_re = netv2_uartcrossover_tx_fifo_do_read; +assign netv2_uartcrossover_tx_fifo_syncfifo_writable = (netv2_uartcrossover_tx_fifo_level0 != 5'd16); +assign netv2_uartcrossover_tx_fifo_syncfifo_readable = (netv2_uartcrossover_tx_fifo_level0 != 1'd0); +assign netv2_uartcrossover_rx_fifo_syncfifo_din = {netv2_uartcrossover_rx_fifo_fifo_in_last, netv2_uartcrossover_rx_fifo_fifo_in_first, netv2_uartcrossover_rx_fifo_fifo_in_payload_data}; +assign {netv2_uartcrossover_rx_fifo_fifo_out_last, netv2_uartcrossover_rx_fifo_fifo_out_first, netv2_uartcrossover_rx_fifo_fifo_out_payload_data} = netv2_uartcrossover_rx_fifo_syncfifo_dout; +assign netv2_uartcrossover_rx_fifo_sink_ready = netv2_uartcrossover_rx_fifo_syncfifo_writable; +assign netv2_uartcrossover_rx_fifo_syncfifo_we = netv2_uartcrossover_rx_fifo_sink_valid; +assign netv2_uartcrossover_rx_fifo_fifo_in_first = netv2_uartcrossover_rx_fifo_sink_first; +assign netv2_uartcrossover_rx_fifo_fifo_in_last = netv2_uartcrossover_rx_fifo_sink_last; +assign netv2_uartcrossover_rx_fifo_fifo_in_payload_data = netv2_uartcrossover_rx_fifo_sink_payload_data; +assign netv2_uartcrossover_rx_fifo_source_valid = netv2_uartcrossover_rx_fifo_readable; +assign netv2_uartcrossover_rx_fifo_source_first = netv2_uartcrossover_rx_fifo_fifo_out_first; +assign netv2_uartcrossover_rx_fifo_source_last = netv2_uartcrossover_rx_fifo_fifo_out_last; +assign netv2_uartcrossover_rx_fifo_source_payload_data = netv2_uartcrossover_rx_fifo_fifo_out_payload_data; +assign netv2_uartcrossover_rx_fifo_re = netv2_uartcrossover_rx_fifo_source_ready; +assign netv2_uartcrossover_rx_fifo_syncfifo_re = (netv2_uartcrossover_rx_fifo_syncfifo_readable & ((~netv2_uartcrossover_rx_fifo_readable) | netv2_uartcrossover_rx_fifo_re)); +assign netv2_uartcrossover_rx_fifo_level1 = (netv2_uartcrossover_rx_fifo_level0 + netv2_uartcrossover_rx_fifo_readable); +always @(*) begin + netv2_uartcrossover_rx_fifo_wrport_adr <= 4'd0; + if (netv2_uartcrossover_rx_fifo_replace) begin + netv2_uartcrossover_rx_fifo_wrport_adr <= (netv2_uartcrossover_rx_fifo_produce - 1'd1); + end else begin + netv2_uartcrossover_rx_fifo_wrport_adr <= netv2_uartcrossover_rx_fifo_produce; + end +end +assign netv2_uartcrossover_rx_fifo_wrport_dat_w = netv2_uartcrossover_rx_fifo_syncfifo_din; +assign netv2_uartcrossover_rx_fifo_wrport_we = (netv2_uartcrossover_rx_fifo_syncfifo_we & (netv2_uartcrossover_rx_fifo_syncfifo_writable | netv2_uartcrossover_rx_fifo_replace)); +assign netv2_uartcrossover_rx_fifo_do_read = (netv2_uartcrossover_rx_fifo_syncfifo_readable & netv2_uartcrossover_rx_fifo_syncfifo_re); +assign netv2_uartcrossover_rx_fifo_rdport_adr = netv2_uartcrossover_rx_fifo_consume; +assign netv2_uartcrossover_rx_fifo_syncfifo_dout = netv2_uartcrossover_rx_fifo_rdport_dat_r; +assign netv2_uartcrossover_rx_fifo_rdport_re = netv2_uartcrossover_rx_fifo_do_read; +assign netv2_uartcrossover_rx_fifo_syncfifo_writable = (netv2_uartcrossover_rx_fifo_level0 != 5'd16); +assign netv2_uartcrossover_rx_fifo_syncfifo_readable = (netv2_uartcrossover_rx_fifo_level0 != 1'd0); +assign netv2_xover_tx_fifo_sink_valid = netv2_xover_rxtx_re; +assign netv2_xover_tx_fifo_sink_payload_data = netv2_xover_rxtx_r; +assign netv2_xover_txfull_status = (~netv2_xover_tx_fifo_sink_ready); +assign netv2_xover_txempty_status = (~netv2_xover_tx_fifo_source_valid); +assign netv2_xover_uart_source_valid = netv2_xover_tx_fifo_source_valid; +assign netv2_xover_tx_fifo_source_ready = netv2_xover_uart_source_ready; +assign netv2_xover_uart_source_first = netv2_xover_tx_fifo_source_first; +assign netv2_xover_uart_source_last = netv2_xover_tx_fifo_source_last; +assign netv2_xover_uart_source_payload_data = netv2_xover_tx_fifo_source_payload_data; +assign netv2_xover_tx_trigger = (~netv2_xover_tx_fifo_sink_ready); +assign netv2_xover_rx_fifo_sink_valid = netv2_xover_uart_sink_valid; +assign netv2_xover_uart_sink_ready = netv2_xover_rx_fifo_sink_ready; +assign netv2_xover_rx_fifo_sink_first = netv2_xover_uart_sink_first; +assign netv2_xover_rx_fifo_sink_last = netv2_xover_uart_sink_last; +assign netv2_xover_rx_fifo_sink_payload_data = netv2_xover_uart_sink_payload_data; +assign netv2_xover_rxempty_status = (~netv2_xover_rx_fifo_source_valid); +assign netv2_xover_rxfull_status = (~netv2_xover_rx_fifo_sink_ready); +assign netv2_xover_rxtx_w = netv2_xover_rx_fifo_source_payload_data; +assign netv2_xover_rx_fifo_source_ready = (netv2_xover_rx_clear | (1'd1 & netv2_xover_rxtx_we)); +assign netv2_xover_rx_trigger = (~netv2_xover_rx_fifo_source_valid); +always @(*) begin + netv2_xover_tx_clear <= 1'd0; + if ((netv2_xover_eventmanager_pending_re & netv2_xover_eventmanager_pending_r[0])) begin + netv2_xover_tx_clear <= 1'd1; + end +end +always @(*) begin + netv2_xover_eventmanager_status_w <= 2'd0; + netv2_xover_eventmanager_status_w[0] <= netv2_xover_tx_status; + netv2_xover_eventmanager_status_w[1] <= netv2_xover_rx_status; +end +always @(*) begin + netv2_xover_rx_clear <= 1'd0; + if ((netv2_xover_eventmanager_pending_re & netv2_xover_eventmanager_pending_r[1])) begin + netv2_xover_rx_clear <= 1'd1; + end +end +always @(*) begin + netv2_xover_eventmanager_pending_w <= 2'd0; + netv2_xover_eventmanager_pending_w[0] <= netv2_xover_tx_pending; + netv2_xover_eventmanager_pending_w[1] <= netv2_xover_rx_pending; +end +assign netv2_xover_irq = ((netv2_xover_eventmanager_pending_w[0] & netv2_xover_eventmanager_storage[0]) | (netv2_xover_eventmanager_pending_w[1] & netv2_xover_eventmanager_storage[1])); +assign netv2_xover_tx_status = netv2_xover_tx_trigger; +assign netv2_xover_rx_status = netv2_xover_rx_trigger; +assign netv2_xover_tx_fifo_sink_ready = ((~netv2_xover_tx_fifo_source_valid) | netv2_xover_tx_fifo_source_ready); +assign netv2_xover_rx_fifo_sink_ready = ((~netv2_xover_rx_fifo_source_valid) | netv2_xover_rx_fifo_source_ready); +assign netv2_zero_trigger = (netv2_value != 1'd0); +assign netv2_eventmanager_status_w = netv2_zero_status; +always @(*) begin + netv2_zero_clear <= 1'd0; + if ((netv2_eventmanager_pending_re & netv2_eventmanager_pending_r)) begin + netv2_zero_clear <= 1'd1; + end +end +assign netv2_eventmanager_pending_w = netv2_zero_pending; +assign netv2_irq = (netv2_eventmanager_pending_w & netv2_eventmanager_storage); +assign netv2_zero_status = netv2_zero_trigger; +assign crg_clkin = clk50; +assign sys_clk = crg_clkout_buf0; +assign sys4x_clk = crg_clkout_buf1; +assign sys4x_dqs_clk = crg_clkout_buf2; +assign clk200_clk = crg_clkout_buf3; +assign clk100_clk = crg_clkout_buf4; +assign eth_clk = crg_clkout_buf5; +assign dna_clk = dna_count[0]; +always @(*) begin + xadc_den <= 1'd0; + xadc_dadr <= 7'd0; + if ((~xadc_drp_en)) begin + xadc_den <= xadc_eoc; + xadc_dadr <= xadc_channel; + end +end +assign icap_i = icap_send; +assign icap_addr = icap_addr_storage; +assign icap_data = icap_data_storage; +assign icap_send = icap_send_re; +assign icap_done_status = icap_done; +assign icap_o = (icap_toggle_o ^ icap_toggle_o_r); +assign flash_cs_n = flash_pads_cs_n; +assign flash_mosi = flash_pads_mosi; +assign flash_pads_miso = flash_miso; +assign flash_start0 = flash_start1; +assign flash_length0 = flash_length1; +assign flash_mosi1 = flash_mosi_storage; +assign flash_done1 = flash_done0; +assign flash_miso_status = flash_miso1; +assign flash_cs = flash_cs_storage; +assign flash_loopback = flash_loopback_storage; +assign flash_clk_rise = (flash_clk_divider1 == (flash_clk_divider0[15:1] - 1'd1)); +assign flash_clk_fall = (flash_clk_divider1 == (flash_clk_divider0 - 1'd1)); +always @(*) begin + flash_clk_enable <= 1'd0; + flash_cs_enable <= 1'd0; + flash_done0 <= 1'd0; + flash_mosi_latch <= 1'd0; + flash_irq <= 1'd0; + flash_miso_latch <= 1'd0; + s7spiflash_next_state <= 2'd0; + flash_count_s7spiflash_next_value <= 6'd0; + flash_count_s7spiflash_next_value_ce <= 1'd0; + s7spiflash_next_state <= s7spiflash_state; + case (s7spiflash_state) + 1'd1: begin + flash_count_s7spiflash_next_value <= 1'd0; + flash_count_s7spiflash_next_value_ce <= 1'd1; + if (flash_clk_fall) begin + flash_cs_enable <= 1'd1; + s7spiflash_next_state <= 2'd2; + end + end + 2'd2: begin + flash_clk_enable <= 1'd1; + flash_cs_enable <= 1'd1; + if (flash_clk_fall) begin + flash_count_s7spiflash_next_value <= (flash_count + 1'd1); + flash_count_s7spiflash_next_value_ce <= 1'd1; + if ((flash_count == (flash_length0 - 1'd1))) begin + s7spiflash_next_state <= 2'd3; + end + end + end + 2'd3: begin + flash_cs_enable <= 1'd1; + if (flash_clk_rise) begin + flash_miso_latch <= 1'd1; + flash_irq <= 1'd1; + s7spiflash_next_state <= 1'd0; + end + end + default: begin + flash_done0 <= 1'd1; + if (flash_start0) begin + flash_done0 <= 1'd0; + flash_mosi_latch <= 1'd1; + s7spiflash_next_state <= 1'd1; + end + end + endcase +end +assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble); +assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble); +always @(*) begin + a7ddrphy_dfi_p0_rddata <= 64'd0; + a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0]; + a7ddrphy_dfi_p0_rddata[32] <= a7ddrphy_bitslip04[1]; + a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0]; + a7ddrphy_dfi_p0_rddata[33] <= a7ddrphy_bitslip14[1]; + a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip24[0]; + a7ddrphy_dfi_p0_rddata[34] <= a7ddrphy_bitslip24[1]; + a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip34[0]; + a7ddrphy_dfi_p0_rddata[35] <= a7ddrphy_bitslip34[1]; + a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0]; + a7ddrphy_dfi_p0_rddata[36] <= a7ddrphy_bitslip42[1]; + a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0]; + a7ddrphy_dfi_p0_rddata[37] <= a7ddrphy_bitslip52[1]; + a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0]; + a7ddrphy_dfi_p0_rddata[38] <= a7ddrphy_bitslip62[1]; + a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0]; + a7ddrphy_dfi_p0_rddata[39] <= a7ddrphy_bitslip72[1]; + a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0]; + a7ddrphy_dfi_p0_rddata[40] <= a7ddrphy_bitslip82[1]; + a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0]; + a7ddrphy_dfi_p0_rddata[41] <= a7ddrphy_bitslip92[1]; + a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0]; + a7ddrphy_dfi_p0_rddata[42] <= a7ddrphy_bitslip102[1]; + a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0]; + a7ddrphy_dfi_p0_rddata[43] <= a7ddrphy_bitslip112[1]; + a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0]; + a7ddrphy_dfi_p0_rddata[44] <= a7ddrphy_bitslip122[1]; + a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0]; + a7ddrphy_dfi_p0_rddata[45] <= a7ddrphy_bitslip132[1]; + a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0]; + a7ddrphy_dfi_p0_rddata[46] <= a7ddrphy_bitslip142[1]; + a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0]; + a7ddrphy_dfi_p0_rddata[47] <= a7ddrphy_bitslip152[1]; + a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip162[0]; + a7ddrphy_dfi_p0_rddata[48] <= a7ddrphy_bitslip162[1]; + a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip172[0]; + a7ddrphy_dfi_p0_rddata[49] <= a7ddrphy_bitslip172[1]; + a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip182[0]; + a7ddrphy_dfi_p0_rddata[50] <= a7ddrphy_bitslip182[1]; + a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip192[0]; + a7ddrphy_dfi_p0_rddata[51] <= a7ddrphy_bitslip192[1]; + a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip202[0]; + a7ddrphy_dfi_p0_rddata[52] <= a7ddrphy_bitslip202[1]; + a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip212[0]; + a7ddrphy_dfi_p0_rddata[53] <= a7ddrphy_bitslip212[1]; + a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip222[0]; + a7ddrphy_dfi_p0_rddata[54] <= a7ddrphy_bitslip222[1]; + a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip232[0]; + a7ddrphy_dfi_p0_rddata[55] <= a7ddrphy_bitslip232[1]; + a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip242[0]; + a7ddrphy_dfi_p0_rddata[56] <= a7ddrphy_bitslip242[1]; + a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip252[0]; + a7ddrphy_dfi_p0_rddata[57] <= a7ddrphy_bitslip252[1]; + a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip262[0]; + a7ddrphy_dfi_p0_rddata[58] <= a7ddrphy_bitslip262[1]; + a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip272[0]; + a7ddrphy_dfi_p0_rddata[59] <= a7ddrphy_bitslip272[1]; + a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip282[0]; + a7ddrphy_dfi_p0_rddata[60] <= a7ddrphy_bitslip282[1]; + a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip292[0]; + a7ddrphy_dfi_p0_rddata[61] <= a7ddrphy_bitslip292[1]; + a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip302[0]; + a7ddrphy_dfi_p0_rddata[62] <= a7ddrphy_bitslip302[1]; + a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip312[0]; + a7ddrphy_dfi_p0_rddata[63] <= a7ddrphy_bitslip312[1]; +end +always @(*) begin + a7ddrphy_dfi_p1_rddata <= 64'd0; + a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2]; + a7ddrphy_dfi_p1_rddata[32] <= a7ddrphy_bitslip04[3]; + a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2]; + a7ddrphy_dfi_p1_rddata[33] <= a7ddrphy_bitslip14[3]; + a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip24[2]; + a7ddrphy_dfi_p1_rddata[34] <= a7ddrphy_bitslip24[3]; + a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip34[2]; + a7ddrphy_dfi_p1_rddata[35] <= a7ddrphy_bitslip34[3]; + a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2]; + a7ddrphy_dfi_p1_rddata[36] <= a7ddrphy_bitslip42[3]; + a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2]; + a7ddrphy_dfi_p1_rddata[37] <= a7ddrphy_bitslip52[3]; + a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2]; + a7ddrphy_dfi_p1_rddata[38] <= a7ddrphy_bitslip62[3]; + a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2]; + a7ddrphy_dfi_p1_rddata[39] <= a7ddrphy_bitslip72[3]; + a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2]; + a7ddrphy_dfi_p1_rddata[40] <= a7ddrphy_bitslip82[3]; + a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2]; + a7ddrphy_dfi_p1_rddata[41] <= a7ddrphy_bitslip92[3]; + a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2]; + a7ddrphy_dfi_p1_rddata[42] <= a7ddrphy_bitslip102[3]; + a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2]; + a7ddrphy_dfi_p1_rddata[43] <= a7ddrphy_bitslip112[3]; + a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2]; + a7ddrphy_dfi_p1_rddata[44] <= a7ddrphy_bitslip122[3]; + a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2]; + a7ddrphy_dfi_p1_rddata[45] <= a7ddrphy_bitslip132[3]; + a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2]; + a7ddrphy_dfi_p1_rddata[46] <= a7ddrphy_bitslip142[3]; + a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2]; + a7ddrphy_dfi_p1_rddata[47] <= a7ddrphy_bitslip152[3]; + a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip162[2]; + a7ddrphy_dfi_p1_rddata[48] <= a7ddrphy_bitslip162[3]; + a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip172[2]; + a7ddrphy_dfi_p1_rddata[49] <= a7ddrphy_bitslip172[3]; + a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip182[2]; + a7ddrphy_dfi_p1_rddata[50] <= a7ddrphy_bitslip182[3]; + a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip192[2]; + a7ddrphy_dfi_p1_rddata[51] <= a7ddrphy_bitslip192[3]; + a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip202[2]; + a7ddrphy_dfi_p1_rddata[52] <= a7ddrphy_bitslip202[3]; + a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip212[2]; + a7ddrphy_dfi_p1_rddata[53] <= a7ddrphy_bitslip212[3]; + a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip222[2]; + a7ddrphy_dfi_p1_rddata[54] <= a7ddrphy_bitslip222[3]; + a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip232[2]; + a7ddrphy_dfi_p1_rddata[55] <= a7ddrphy_bitslip232[3]; + a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip242[2]; + a7ddrphy_dfi_p1_rddata[56] <= a7ddrphy_bitslip242[3]; + a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip252[2]; + a7ddrphy_dfi_p1_rddata[57] <= a7ddrphy_bitslip252[3]; + a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip262[2]; + a7ddrphy_dfi_p1_rddata[58] <= a7ddrphy_bitslip262[3]; + a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip272[2]; + a7ddrphy_dfi_p1_rddata[59] <= a7ddrphy_bitslip272[3]; + a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip282[2]; + a7ddrphy_dfi_p1_rddata[60] <= a7ddrphy_bitslip282[3]; + a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip292[2]; + a7ddrphy_dfi_p1_rddata[61] <= a7ddrphy_bitslip292[3]; + a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip302[2]; + a7ddrphy_dfi_p1_rddata[62] <= a7ddrphy_bitslip302[3]; + a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip312[2]; + a7ddrphy_dfi_p1_rddata[63] <= a7ddrphy_bitslip312[3]; +end +always @(*) begin + a7ddrphy_dfi_p2_rddata <= 64'd0; + a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4]; + a7ddrphy_dfi_p2_rddata[32] <= a7ddrphy_bitslip04[5]; + a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4]; + a7ddrphy_dfi_p2_rddata[33] <= a7ddrphy_bitslip14[5]; + a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip24[4]; + a7ddrphy_dfi_p2_rddata[34] <= a7ddrphy_bitslip24[5]; + a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip34[4]; + a7ddrphy_dfi_p2_rddata[35] <= a7ddrphy_bitslip34[5]; + a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4]; + a7ddrphy_dfi_p2_rddata[36] <= a7ddrphy_bitslip42[5]; + a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4]; + a7ddrphy_dfi_p2_rddata[37] <= a7ddrphy_bitslip52[5]; + a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4]; + a7ddrphy_dfi_p2_rddata[38] <= a7ddrphy_bitslip62[5]; + a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4]; + a7ddrphy_dfi_p2_rddata[39] <= a7ddrphy_bitslip72[5]; + a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4]; + a7ddrphy_dfi_p2_rddata[40] <= a7ddrphy_bitslip82[5]; + a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4]; + a7ddrphy_dfi_p2_rddata[41] <= a7ddrphy_bitslip92[5]; + a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4]; + a7ddrphy_dfi_p2_rddata[42] <= a7ddrphy_bitslip102[5]; + a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4]; + a7ddrphy_dfi_p2_rddata[43] <= a7ddrphy_bitslip112[5]; + a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4]; + a7ddrphy_dfi_p2_rddata[44] <= a7ddrphy_bitslip122[5]; + a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4]; + a7ddrphy_dfi_p2_rddata[45] <= a7ddrphy_bitslip132[5]; + a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4]; + a7ddrphy_dfi_p2_rddata[46] <= a7ddrphy_bitslip142[5]; + a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4]; + a7ddrphy_dfi_p2_rddata[47] <= a7ddrphy_bitslip152[5]; + a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip162[4]; + a7ddrphy_dfi_p2_rddata[48] <= a7ddrphy_bitslip162[5]; + a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip172[4]; + a7ddrphy_dfi_p2_rddata[49] <= a7ddrphy_bitslip172[5]; + a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip182[4]; + a7ddrphy_dfi_p2_rddata[50] <= a7ddrphy_bitslip182[5]; + a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip192[4]; + a7ddrphy_dfi_p2_rddata[51] <= a7ddrphy_bitslip192[5]; + a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip202[4]; + a7ddrphy_dfi_p2_rddata[52] <= a7ddrphy_bitslip202[5]; + a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip212[4]; + a7ddrphy_dfi_p2_rddata[53] <= a7ddrphy_bitslip212[5]; + a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip222[4]; + a7ddrphy_dfi_p2_rddata[54] <= a7ddrphy_bitslip222[5]; + a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip232[4]; + a7ddrphy_dfi_p2_rddata[55] <= a7ddrphy_bitslip232[5]; + a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip242[4]; + a7ddrphy_dfi_p2_rddata[56] <= a7ddrphy_bitslip242[5]; + a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip252[4]; + a7ddrphy_dfi_p2_rddata[57] <= a7ddrphy_bitslip252[5]; + a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip262[4]; + a7ddrphy_dfi_p2_rddata[58] <= a7ddrphy_bitslip262[5]; + a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip272[4]; + a7ddrphy_dfi_p2_rddata[59] <= a7ddrphy_bitslip272[5]; + a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip282[4]; + a7ddrphy_dfi_p2_rddata[60] <= a7ddrphy_bitslip282[5]; + a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip292[4]; + a7ddrphy_dfi_p2_rddata[61] <= a7ddrphy_bitslip292[5]; + a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip302[4]; + a7ddrphy_dfi_p2_rddata[62] <= a7ddrphy_bitslip302[5]; + a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip312[4]; + a7ddrphy_dfi_p2_rddata[63] <= a7ddrphy_bitslip312[5]; +end +always @(*) begin + a7ddrphy_dfi_p3_rddata <= 64'd0; + a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6]; + a7ddrphy_dfi_p3_rddata[32] <= a7ddrphy_bitslip04[7]; + a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6]; + a7ddrphy_dfi_p3_rddata[33] <= a7ddrphy_bitslip14[7]; + a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip24[6]; + a7ddrphy_dfi_p3_rddata[34] <= a7ddrphy_bitslip24[7]; + a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip34[6]; + a7ddrphy_dfi_p3_rddata[35] <= a7ddrphy_bitslip34[7]; + a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6]; + a7ddrphy_dfi_p3_rddata[36] <= a7ddrphy_bitslip42[7]; + a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6]; + a7ddrphy_dfi_p3_rddata[37] <= a7ddrphy_bitslip52[7]; + a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6]; + a7ddrphy_dfi_p3_rddata[38] <= a7ddrphy_bitslip62[7]; + a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6]; + a7ddrphy_dfi_p3_rddata[39] <= a7ddrphy_bitslip72[7]; + a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6]; + a7ddrphy_dfi_p3_rddata[40] <= a7ddrphy_bitslip82[7]; + a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6]; + a7ddrphy_dfi_p3_rddata[41] <= a7ddrphy_bitslip92[7]; + a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6]; + a7ddrphy_dfi_p3_rddata[42] <= a7ddrphy_bitslip102[7]; + a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6]; + a7ddrphy_dfi_p3_rddata[43] <= a7ddrphy_bitslip112[7]; + a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6]; + a7ddrphy_dfi_p3_rddata[44] <= a7ddrphy_bitslip122[7]; + a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6]; + a7ddrphy_dfi_p3_rddata[45] <= a7ddrphy_bitslip132[7]; + a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6]; + a7ddrphy_dfi_p3_rddata[46] <= a7ddrphy_bitslip142[7]; + a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6]; + a7ddrphy_dfi_p3_rddata[47] <= a7ddrphy_bitslip152[7]; + a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip162[6]; + a7ddrphy_dfi_p3_rddata[48] <= a7ddrphy_bitslip162[7]; + a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip172[6]; + a7ddrphy_dfi_p3_rddata[49] <= a7ddrphy_bitslip172[7]; + a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip182[6]; + a7ddrphy_dfi_p3_rddata[50] <= a7ddrphy_bitslip182[7]; + a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip192[6]; + a7ddrphy_dfi_p3_rddata[51] <= a7ddrphy_bitslip192[7]; + a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip202[6]; + a7ddrphy_dfi_p3_rddata[52] <= a7ddrphy_bitslip202[7]; + a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip212[6]; + a7ddrphy_dfi_p3_rddata[53] <= a7ddrphy_bitslip212[7]; + a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip222[6]; + a7ddrphy_dfi_p3_rddata[54] <= a7ddrphy_bitslip222[7]; + a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip232[6]; + a7ddrphy_dfi_p3_rddata[55] <= a7ddrphy_bitslip232[7]; + a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip242[6]; + a7ddrphy_dfi_p3_rddata[56] <= a7ddrphy_bitslip242[7]; + a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip252[6]; + a7ddrphy_dfi_p3_rddata[57] <= a7ddrphy_bitslip252[7]; + a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip262[6]; + a7ddrphy_dfi_p3_rddata[58] <= a7ddrphy_bitslip262[7]; + a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip272[6]; + a7ddrphy_dfi_p3_rddata[59] <= a7ddrphy_bitslip272[7]; + a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip282[6]; + a7ddrphy_dfi_p3_rddata[60] <= a7ddrphy_bitslip282[7]; + a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip292[6]; + a7ddrphy_dfi_p3_rddata[61] <= a7ddrphy_bitslip292[7]; + a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip302[6]; + a7ddrphy_dfi_p3_rddata[62] <= a7ddrphy_bitslip302[7]; + a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip312[6]; + a7ddrphy_dfi_p3_rddata[63] <= a7ddrphy_bitslip312[7]; +end +assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); +assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); +assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); +assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); +assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1; +always @(*) begin + a7ddrphy_dqs_oe <= 1'd0; + if (a7ddrphy_wlevel_en_storage) begin + a7ddrphy_dqs_oe <= 1'd1; + end else begin + a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; + end +end +assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1)); +assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1)); +always @(*) begin + a7ddrphy_dqspattern_o0 <= 8'd0; + a7ddrphy_dqspattern_o0 <= 7'd85; + if (a7ddrphy_dqspattern0) begin + a7ddrphy_dqspattern_o0 <= 5'd21; + end + if (a7ddrphy_dqspattern1) begin + a7ddrphy_dqspattern_o0 <= 7'd84; + end + if (a7ddrphy_wlevel_en_storage) begin + a7ddrphy_dqspattern_o0 <= 1'd0; + if (a7ddrphy_wlevel_strobe_re) begin + a7ddrphy_dqspattern_o0 <= 1'd1; + end + end +end +always @(*) begin + a7ddrphy_bitslip00 <= 8'd0; + case (a7ddrphy_bitslip0_value0) + 1'd0: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip10 <= 8'd0; + case (a7ddrphy_bitslip1_value0) + 1'd0: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip20 <= 8'd0; + case (a7ddrphy_bitslip2_value0) + 1'd0: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip30 <= 8'd0; + case (a7ddrphy_bitslip3_value0) + 1'd0: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip01 <= 8'd0; + case (a7ddrphy_bitslip0_value1) + 1'd0: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip11 <= 8'd0; + case (a7ddrphy_bitslip1_value1) + 1'd0: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip21 <= 8'd0; + case (a7ddrphy_bitslip2_value1) + 1'd0: begin + a7ddrphy_bitslip21 <= a7ddrphy_bitslip2_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip21 <= a7ddrphy_bitslip2_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip21 <= a7ddrphy_bitslip2_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip21 <= a7ddrphy_bitslip2_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip21 <= a7ddrphy_bitslip2_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip21 <= a7ddrphy_bitslip2_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip21 <= a7ddrphy_bitslip2_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip21 <= a7ddrphy_bitslip2_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip31 <= 8'd0; + case (a7ddrphy_bitslip3_value1) + 1'd0: begin + a7ddrphy_bitslip31 <= a7ddrphy_bitslip3_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip31 <= a7ddrphy_bitslip3_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip31 <= a7ddrphy_bitslip3_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip31 <= a7ddrphy_bitslip3_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip31 <= a7ddrphy_bitslip3_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip31 <= a7ddrphy_bitslip3_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip31 <= a7ddrphy_bitslip3_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip31 <= a7ddrphy_bitslip3_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip02 <= 8'd0; + case (a7ddrphy_bitslip0_value2) + 1'd0: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip04 <= 8'd0; + case (a7ddrphy_bitslip0_value3) + 1'd0: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip12 <= 8'd0; + case (a7ddrphy_bitslip1_value2) + 1'd0: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip14 <= 8'd0; + case (a7ddrphy_bitslip1_value3) + 1'd0: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip22 <= 8'd0; + case (a7ddrphy_bitslip2_value2) + 1'd0: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r2[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r2[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r2[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r2[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r2[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r2[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r2[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r2[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip24 <= 8'd0; + case (a7ddrphy_bitslip2_value3) + 1'd0: begin + a7ddrphy_bitslip24 <= a7ddrphy_bitslip2_r3[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip24 <= a7ddrphy_bitslip2_r3[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip24 <= a7ddrphy_bitslip2_r3[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip24 <= a7ddrphy_bitslip2_r3[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip24 <= a7ddrphy_bitslip2_r3[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip24 <= a7ddrphy_bitslip2_r3[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip24 <= a7ddrphy_bitslip2_r3[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip24 <= a7ddrphy_bitslip2_r3[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip32 <= 8'd0; + case (a7ddrphy_bitslip3_value2) + 1'd0: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r2[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r2[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r2[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r2[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r2[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r2[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r2[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r2[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip34 <= 8'd0; + case (a7ddrphy_bitslip3_value3) + 1'd0: begin + a7ddrphy_bitslip34 <= a7ddrphy_bitslip3_r3[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip34 <= a7ddrphy_bitslip3_r3[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip34 <= a7ddrphy_bitslip3_r3[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip34 <= a7ddrphy_bitslip3_r3[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip34 <= a7ddrphy_bitslip3_r3[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip34 <= a7ddrphy_bitslip3_r3[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip34 <= a7ddrphy_bitslip3_r3[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip34 <= a7ddrphy_bitslip3_r3[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip40 <= 8'd0; + case (a7ddrphy_bitslip4_value0) + 1'd0: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip42 <= 8'd0; + case (a7ddrphy_bitslip4_value1) + 1'd0: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip50 <= 8'd0; + case (a7ddrphy_bitslip5_value0) + 1'd0: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip52 <= 8'd0; + case (a7ddrphy_bitslip5_value1) + 1'd0: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip60 <= 8'd0; + case (a7ddrphy_bitslip6_value0) + 1'd0: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip62 <= 8'd0; + case (a7ddrphy_bitslip6_value1) + 1'd0: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip70 <= 8'd0; + case (a7ddrphy_bitslip7_value0) + 1'd0: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip72 <= 8'd0; + case (a7ddrphy_bitslip7_value1) + 1'd0: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip80 <= 8'd0; + case (a7ddrphy_bitslip8_value0) + 1'd0: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip82 <= 8'd0; + case (a7ddrphy_bitslip8_value1) + 1'd0: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip90 <= 8'd0; + case (a7ddrphy_bitslip9_value0) + 1'd0: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip92 <= 8'd0; + case (a7ddrphy_bitslip9_value1) + 1'd0: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip100 <= 8'd0; + case (a7ddrphy_bitslip10_value0) + 1'd0: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip102 <= 8'd0; + case (a7ddrphy_bitslip10_value1) + 1'd0: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip110 <= 8'd0; + case (a7ddrphy_bitslip11_value0) + 1'd0: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip112 <= 8'd0; + case (a7ddrphy_bitslip11_value1) + 1'd0: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip120 <= 8'd0; + case (a7ddrphy_bitslip12_value0) + 1'd0: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip122 <= 8'd0; + case (a7ddrphy_bitslip12_value1) + 1'd0: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip130 <= 8'd0; + case (a7ddrphy_bitslip13_value0) + 1'd0: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip132 <= 8'd0; + case (a7ddrphy_bitslip13_value1) + 1'd0: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip140 <= 8'd0; + case (a7ddrphy_bitslip14_value0) + 1'd0: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip142 <= 8'd0; + case (a7ddrphy_bitslip14_value1) + 1'd0: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip150 <= 8'd0; + case (a7ddrphy_bitslip15_value0) + 1'd0: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip152 <= 8'd0; + case (a7ddrphy_bitslip15_value1) + 1'd0: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip160 <= 8'd0; + case (a7ddrphy_bitslip16_value0) + 1'd0: begin + a7ddrphy_bitslip160 <= a7ddrphy_bitslip16_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip160 <= a7ddrphy_bitslip16_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip160 <= a7ddrphy_bitslip16_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip160 <= a7ddrphy_bitslip16_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip160 <= a7ddrphy_bitslip16_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip160 <= a7ddrphy_bitslip16_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip160 <= a7ddrphy_bitslip16_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip160 <= a7ddrphy_bitslip16_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip162 <= 8'd0; + case (a7ddrphy_bitslip16_value1) + 1'd0: begin + a7ddrphy_bitslip162 <= a7ddrphy_bitslip16_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip162 <= a7ddrphy_bitslip16_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip162 <= a7ddrphy_bitslip16_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip162 <= a7ddrphy_bitslip16_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip162 <= a7ddrphy_bitslip16_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip162 <= a7ddrphy_bitslip16_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip162 <= a7ddrphy_bitslip16_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip162 <= a7ddrphy_bitslip16_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip170 <= 8'd0; + case (a7ddrphy_bitslip17_value0) + 1'd0: begin + a7ddrphy_bitslip170 <= a7ddrphy_bitslip17_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip170 <= a7ddrphy_bitslip17_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip170 <= a7ddrphy_bitslip17_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip170 <= a7ddrphy_bitslip17_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip170 <= a7ddrphy_bitslip17_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip170 <= a7ddrphy_bitslip17_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip170 <= a7ddrphy_bitslip17_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip170 <= a7ddrphy_bitslip17_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip172 <= 8'd0; + case (a7ddrphy_bitslip17_value1) + 1'd0: begin + a7ddrphy_bitslip172 <= a7ddrphy_bitslip17_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip172 <= a7ddrphy_bitslip17_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip172 <= a7ddrphy_bitslip17_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip172 <= a7ddrphy_bitslip17_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip172 <= a7ddrphy_bitslip17_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip172 <= a7ddrphy_bitslip17_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip172 <= a7ddrphy_bitslip17_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip172 <= a7ddrphy_bitslip17_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip180 <= 8'd0; + case (a7ddrphy_bitslip18_value0) + 1'd0: begin + a7ddrphy_bitslip180 <= a7ddrphy_bitslip18_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip180 <= a7ddrphy_bitslip18_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip180 <= a7ddrphy_bitslip18_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip180 <= a7ddrphy_bitslip18_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip180 <= a7ddrphy_bitslip18_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip180 <= a7ddrphy_bitslip18_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip180 <= a7ddrphy_bitslip18_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip180 <= a7ddrphy_bitslip18_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip182 <= 8'd0; + case (a7ddrphy_bitslip18_value1) + 1'd0: begin + a7ddrphy_bitslip182 <= a7ddrphy_bitslip18_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip182 <= a7ddrphy_bitslip18_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip182 <= a7ddrphy_bitslip18_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip182 <= a7ddrphy_bitslip18_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip182 <= a7ddrphy_bitslip18_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip182 <= a7ddrphy_bitslip18_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip182 <= a7ddrphy_bitslip18_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip182 <= a7ddrphy_bitslip18_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip190 <= 8'd0; + case (a7ddrphy_bitslip19_value0) + 1'd0: begin + a7ddrphy_bitslip190 <= a7ddrphy_bitslip19_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip190 <= a7ddrphy_bitslip19_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip190 <= a7ddrphy_bitslip19_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip190 <= a7ddrphy_bitslip19_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip190 <= a7ddrphy_bitslip19_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip190 <= a7ddrphy_bitslip19_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip190 <= a7ddrphy_bitslip19_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip190 <= a7ddrphy_bitslip19_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip192 <= 8'd0; + case (a7ddrphy_bitslip19_value1) + 1'd0: begin + a7ddrphy_bitslip192 <= a7ddrphy_bitslip19_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip192 <= a7ddrphy_bitslip19_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip192 <= a7ddrphy_bitslip19_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip192 <= a7ddrphy_bitslip19_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip192 <= a7ddrphy_bitslip19_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip192 <= a7ddrphy_bitslip19_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip192 <= a7ddrphy_bitslip19_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip192 <= a7ddrphy_bitslip19_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip200 <= 8'd0; + case (a7ddrphy_bitslip20_value0) + 1'd0: begin + a7ddrphy_bitslip200 <= a7ddrphy_bitslip20_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip200 <= a7ddrphy_bitslip20_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip200 <= a7ddrphy_bitslip20_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip200 <= a7ddrphy_bitslip20_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip200 <= a7ddrphy_bitslip20_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip200 <= a7ddrphy_bitslip20_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip200 <= a7ddrphy_bitslip20_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip200 <= a7ddrphy_bitslip20_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip202 <= 8'd0; + case (a7ddrphy_bitslip20_value1) + 1'd0: begin + a7ddrphy_bitslip202 <= a7ddrphy_bitslip20_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip202 <= a7ddrphy_bitslip20_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip202 <= a7ddrphy_bitslip20_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip202 <= a7ddrphy_bitslip20_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip202 <= a7ddrphy_bitslip20_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip202 <= a7ddrphy_bitslip20_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip202 <= a7ddrphy_bitslip20_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip202 <= a7ddrphy_bitslip20_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip210 <= 8'd0; + case (a7ddrphy_bitslip21_value0) + 1'd0: begin + a7ddrphy_bitslip210 <= a7ddrphy_bitslip21_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip210 <= a7ddrphy_bitslip21_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip210 <= a7ddrphy_bitslip21_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip210 <= a7ddrphy_bitslip21_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip210 <= a7ddrphy_bitslip21_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip210 <= a7ddrphy_bitslip21_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip210 <= a7ddrphy_bitslip21_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip210 <= a7ddrphy_bitslip21_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip212 <= 8'd0; + case (a7ddrphy_bitslip21_value1) + 1'd0: begin + a7ddrphy_bitslip212 <= a7ddrphy_bitslip21_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip212 <= a7ddrphy_bitslip21_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip212 <= a7ddrphy_bitslip21_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip212 <= a7ddrphy_bitslip21_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip212 <= a7ddrphy_bitslip21_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip212 <= a7ddrphy_bitslip21_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip212 <= a7ddrphy_bitslip21_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip212 <= a7ddrphy_bitslip21_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip220 <= 8'd0; + case (a7ddrphy_bitslip22_value0) + 1'd0: begin + a7ddrphy_bitslip220 <= a7ddrphy_bitslip22_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip220 <= a7ddrphy_bitslip22_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip220 <= a7ddrphy_bitslip22_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip220 <= a7ddrphy_bitslip22_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip220 <= a7ddrphy_bitslip22_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip220 <= a7ddrphy_bitslip22_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip220 <= a7ddrphy_bitslip22_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip220 <= a7ddrphy_bitslip22_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip222 <= 8'd0; + case (a7ddrphy_bitslip22_value1) + 1'd0: begin + a7ddrphy_bitslip222 <= a7ddrphy_bitslip22_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip222 <= a7ddrphy_bitslip22_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip222 <= a7ddrphy_bitslip22_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip222 <= a7ddrphy_bitslip22_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip222 <= a7ddrphy_bitslip22_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip222 <= a7ddrphy_bitslip22_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip222 <= a7ddrphy_bitslip22_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip222 <= a7ddrphy_bitslip22_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip230 <= 8'd0; + case (a7ddrphy_bitslip23_value0) + 1'd0: begin + a7ddrphy_bitslip230 <= a7ddrphy_bitslip23_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip230 <= a7ddrphy_bitslip23_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip230 <= a7ddrphy_bitslip23_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip230 <= a7ddrphy_bitslip23_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip230 <= a7ddrphy_bitslip23_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip230 <= a7ddrphy_bitslip23_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip230 <= a7ddrphy_bitslip23_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip230 <= a7ddrphy_bitslip23_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip232 <= 8'd0; + case (a7ddrphy_bitslip23_value1) + 1'd0: begin + a7ddrphy_bitslip232 <= a7ddrphy_bitslip23_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip232 <= a7ddrphy_bitslip23_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip232 <= a7ddrphy_bitslip23_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip232 <= a7ddrphy_bitslip23_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip232 <= a7ddrphy_bitslip23_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip232 <= a7ddrphy_bitslip23_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip232 <= a7ddrphy_bitslip23_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip232 <= a7ddrphy_bitslip23_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip240 <= 8'd0; + case (a7ddrphy_bitslip24_value0) + 1'd0: begin + a7ddrphy_bitslip240 <= a7ddrphy_bitslip24_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip240 <= a7ddrphy_bitslip24_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip240 <= a7ddrphy_bitslip24_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip240 <= a7ddrphy_bitslip24_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip240 <= a7ddrphy_bitslip24_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip240 <= a7ddrphy_bitslip24_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip240 <= a7ddrphy_bitslip24_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip240 <= a7ddrphy_bitslip24_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip242 <= 8'd0; + case (a7ddrphy_bitslip24_value1) + 1'd0: begin + a7ddrphy_bitslip242 <= a7ddrphy_bitslip24_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip242 <= a7ddrphy_bitslip24_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip242 <= a7ddrphy_bitslip24_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip242 <= a7ddrphy_bitslip24_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip242 <= a7ddrphy_bitslip24_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip242 <= a7ddrphy_bitslip24_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip242 <= a7ddrphy_bitslip24_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip242 <= a7ddrphy_bitslip24_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip250 <= 8'd0; + case (a7ddrphy_bitslip25_value0) + 1'd0: begin + a7ddrphy_bitslip250 <= a7ddrphy_bitslip25_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip250 <= a7ddrphy_bitslip25_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip250 <= a7ddrphy_bitslip25_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip250 <= a7ddrphy_bitslip25_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip250 <= a7ddrphy_bitslip25_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip250 <= a7ddrphy_bitslip25_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip250 <= a7ddrphy_bitslip25_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip250 <= a7ddrphy_bitslip25_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip252 <= 8'd0; + case (a7ddrphy_bitslip25_value1) + 1'd0: begin + a7ddrphy_bitslip252 <= a7ddrphy_bitslip25_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip252 <= a7ddrphy_bitslip25_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip252 <= a7ddrphy_bitslip25_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip252 <= a7ddrphy_bitslip25_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip252 <= a7ddrphy_bitslip25_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip252 <= a7ddrphy_bitslip25_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip252 <= a7ddrphy_bitslip25_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip252 <= a7ddrphy_bitslip25_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip260 <= 8'd0; + case (a7ddrphy_bitslip26_value0) + 1'd0: begin + a7ddrphy_bitslip260 <= a7ddrphy_bitslip26_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip260 <= a7ddrphy_bitslip26_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip260 <= a7ddrphy_bitslip26_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip260 <= a7ddrphy_bitslip26_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip260 <= a7ddrphy_bitslip26_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip260 <= a7ddrphy_bitslip26_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip260 <= a7ddrphy_bitslip26_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip260 <= a7ddrphy_bitslip26_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip262 <= 8'd0; + case (a7ddrphy_bitslip26_value1) + 1'd0: begin + a7ddrphy_bitslip262 <= a7ddrphy_bitslip26_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip262 <= a7ddrphy_bitslip26_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip262 <= a7ddrphy_bitslip26_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip262 <= a7ddrphy_bitslip26_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip262 <= a7ddrphy_bitslip26_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip262 <= a7ddrphy_bitslip26_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip262 <= a7ddrphy_bitslip26_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip262 <= a7ddrphy_bitslip26_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip270 <= 8'd0; + case (a7ddrphy_bitslip27_value0) + 1'd0: begin + a7ddrphy_bitslip270 <= a7ddrphy_bitslip27_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip270 <= a7ddrphy_bitslip27_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip270 <= a7ddrphy_bitslip27_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip270 <= a7ddrphy_bitslip27_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip270 <= a7ddrphy_bitslip27_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip270 <= a7ddrphy_bitslip27_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip270 <= a7ddrphy_bitslip27_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip270 <= a7ddrphy_bitslip27_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip272 <= 8'd0; + case (a7ddrphy_bitslip27_value1) + 1'd0: begin + a7ddrphy_bitslip272 <= a7ddrphy_bitslip27_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip272 <= a7ddrphy_bitslip27_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip272 <= a7ddrphy_bitslip27_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip272 <= a7ddrphy_bitslip27_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip272 <= a7ddrphy_bitslip27_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip272 <= a7ddrphy_bitslip27_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip272 <= a7ddrphy_bitslip27_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip272 <= a7ddrphy_bitslip27_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip280 <= 8'd0; + case (a7ddrphy_bitslip28_value0) + 1'd0: begin + a7ddrphy_bitslip280 <= a7ddrphy_bitslip28_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip280 <= a7ddrphy_bitslip28_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip280 <= a7ddrphy_bitslip28_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip280 <= a7ddrphy_bitslip28_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip280 <= a7ddrphy_bitslip28_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip280 <= a7ddrphy_bitslip28_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip280 <= a7ddrphy_bitslip28_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip280 <= a7ddrphy_bitslip28_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip282 <= 8'd0; + case (a7ddrphy_bitslip28_value1) + 1'd0: begin + a7ddrphy_bitslip282 <= a7ddrphy_bitslip28_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip282 <= a7ddrphy_bitslip28_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip282 <= a7ddrphy_bitslip28_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip282 <= a7ddrphy_bitslip28_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip282 <= a7ddrphy_bitslip28_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip282 <= a7ddrphy_bitslip28_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip282 <= a7ddrphy_bitslip28_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip282 <= a7ddrphy_bitslip28_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip290 <= 8'd0; + case (a7ddrphy_bitslip29_value0) + 1'd0: begin + a7ddrphy_bitslip290 <= a7ddrphy_bitslip29_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip290 <= a7ddrphy_bitslip29_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip290 <= a7ddrphy_bitslip29_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip290 <= a7ddrphy_bitslip29_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip290 <= a7ddrphy_bitslip29_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip290 <= a7ddrphy_bitslip29_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip290 <= a7ddrphy_bitslip29_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip290 <= a7ddrphy_bitslip29_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip292 <= 8'd0; + case (a7ddrphy_bitslip29_value1) + 1'd0: begin + a7ddrphy_bitslip292 <= a7ddrphy_bitslip29_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip292 <= a7ddrphy_bitslip29_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip292 <= a7ddrphy_bitslip29_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip292 <= a7ddrphy_bitslip29_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip292 <= a7ddrphy_bitslip29_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip292 <= a7ddrphy_bitslip29_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip292 <= a7ddrphy_bitslip29_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip292 <= a7ddrphy_bitslip29_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip300 <= 8'd0; + case (a7ddrphy_bitslip30_value0) + 1'd0: begin + a7ddrphy_bitslip300 <= a7ddrphy_bitslip30_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip300 <= a7ddrphy_bitslip30_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip300 <= a7ddrphy_bitslip30_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip300 <= a7ddrphy_bitslip30_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip300 <= a7ddrphy_bitslip30_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip300 <= a7ddrphy_bitslip30_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip300 <= a7ddrphy_bitslip30_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip300 <= a7ddrphy_bitslip30_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip302 <= 8'd0; + case (a7ddrphy_bitslip30_value1) + 1'd0: begin + a7ddrphy_bitslip302 <= a7ddrphy_bitslip30_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip302 <= a7ddrphy_bitslip30_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip302 <= a7ddrphy_bitslip30_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip302 <= a7ddrphy_bitslip30_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip302 <= a7ddrphy_bitslip30_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip302 <= a7ddrphy_bitslip30_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip302 <= a7ddrphy_bitslip30_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip302 <= a7ddrphy_bitslip30_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip310 <= 8'd0; + case (a7ddrphy_bitslip31_value0) + 1'd0: begin + a7ddrphy_bitslip310 <= a7ddrphy_bitslip31_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip310 <= a7ddrphy_bitslip31_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip310 <= a7ddrphy_bitslip31_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip310 <= a7ddrphy_bitslip31_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip310 <= a7ddrphy_bitslip31_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip310 <= a7ddrphy_bitslip31_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip310 <= a7ddrphy_bitslip31_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip310 <= a7ddrphy_bitslip31_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip312 <= 8'd0; + case (a7ddrphy_bitslip31_value1) + 1'd0: begin + a7ddrphy_bitslip312 <= a7ddrphy_bitslip31_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip312 <= a7ddrphy_bitslip31_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip312 <= a7ddrphy_bitslip31_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip312 <= a7ddrphy_bitslip31_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip312 <= a7ddrphy_bitslip31_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip312 <= a7ddrphy_bitslip31_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip312 <= a7ddrphy_bitslip31_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip312 <= a7ddrphy_bitslip31_r1[15:8]; + end + endcase +end +assign a7ddrphy_dfi_p0_address = netv2_sdram_master_p0_address; +assign a7ddrphy_dfi_p0_bank = netv2_sdram_master_p0_bank; +assign a7ddrphy_dfi_p0_cas_n = netv2_sdram_master_p0_cas_n; +assign a7ddrphy_dfi_p0_cs_n = netv2_sdram_master_p0_cs_n; +assign a7ddrphy_dfi_p0_ras_n = netv2_sdram_master_p0_ras_n; +assign a7ddrphy_dfi_p0_we_n = netv2_sdram_master_p0_we_n; +assign a7ddrphy_dfi_p0_cke = netv2_sdram_master_p0_cke; +assign a7ddrphy_dfi_p0_odt = netv2_sdram_master_p0_odt; +assign a7ddrphy_dfi_p0_reset_n = netv2_sdram_master_p0_reset_n; +assign a7ddrphy_dfi_p0_act_n = netv2_sdram_master_p0_act_n; +assign a7ddrphy_dfi_p0_wrdata = netv2_sdram_master_p0_wrdata; +assign a7ddrphy_dfi_p0_wrdata_en = netv2_sdram_master_p0_wrdata_en; +assign a7ddrphy_dfi_p0_wrdata_mask = netv2_sdram_master_p0_wrdata_mask; +assign a7ddrphy_dfi_p0_rddata_en = netv2_sdram_master_p0_rddata_en; +assign netv2_sdram_master_p0_rddata = a7ddrphy_dfi_p0_rddata; +assign netv2_sdram_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid; +assign a7ddrphy_dfi_p1_address = netv2_sdram_master_p1_address; +assign a7ddrphy_dfi_p1_bank = netv2_sdram_master_p1_bank; +assign a7ddrphy_dfi_p1_cas_n = netv2_sdram_master_p1_cas_n; +assign a7ddrphy_dfi_p1_cs_n = netv2_sdram_master_p1_cs_n; +assign a7ddrphy_dfi_p1_ras_n = netv2_sdram_master_p1_ras_n; +assign a7ddrphy_dfi_p1_we_n = netv2_sdram_master_p1_we_n; +assign a7ddrphy_dfi_p1_cke = netv2_sdram_master_p1_cke; +assign a7ddrphy_dfi_p1_odt = netv2_sdram_master_p1_odt; +assign a7ddrphy_dfi_p1_reset_n = netv2_sdram_master_p1_reset_n; +assign a7ddrphy_dfi_p1_act_n = netv2_sdram_master_p1_act_n; +assign a7ddrphy_dfi_p1_wrdata = netv2_sdram_master_p1_wrdata; +assign a7ddrphy_dfi_p1_wrdata_en = netv2_sdram_master_p1_wrdata_en; +assign a7ddrphy_dfi_p1_wrdata_mask = netv2_sdram_master_p1_wrdata_mask; +assign a7ddrphy_dfi_p1_rddata_en = netv2_sdram_master_p1_rddata_en; +assign netv2_sdram_master_p1_rddata = a7ddrphy_dfi_p1_rddata; +assign netv2_sdram_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid; +assign a7ddrphy_dfi_p2_address = netv2_sdram_master_p2_address; +assign a7ddrphy_dfi_p2_bank = netv2_sdram_master_p2_bank; +assign a7ddrphy_dfi_p2_cas_n = netv2_sdram_master_p2_cas_n; +assign a7ddrphy_dfi_p2_cs_n = netv2_sdram_master_p2_cs_n; +assign a7ddrphy_dfi_p2_ras_n = netv2_sdram_master_p2_ras_n; +assign a7ddrphy_dfi_p2_we_n = netv2_sdram_master_p2_we_n; +assign a7ddrphy_dfi_p2_cke = netv2_sdram_master_p2_cke; +assign a7ddrphy_dfi_p2_odt = netv2_sdram_master_p2_odt; +assign a7ddrphy_dfi_p2_reset_n = netv2_sdram_master_p2_reset_n; +assign a7ddrphy_dfi_p2_act_n = netv2_sdram_master_p2_act_n; +assign a7ddrphy_dfi_p2_wrdata = netv2_sdram_master_p2_wrdata; +assign a7ddrphy_dfi_p2_wrdata_en = netv2_sdram_master_p2_wrdata_en; +assign a7ddrphy_dfi_p2_wrdata_mask = netv2_sdram_master_p2_wrdata_mask; +assign a7ddrphy_dfi_p2_rddata_en = netv2_sdram_master_p2_rddata_en; +assign netv2_sdram_master_p2_rddata = a7ddrphy_dfi_p2_rddata; +assign netv2_sdram_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid; +assign a7ddrphy_dfi_p3_address = netv2_sdram_master_p3_address; +assign a7ddrphy_dfi_p3_bank = netv2_sdram_master_p3_bank; +assign a7ddrphy_dfi_p3_cas_n = netv2_sdram_master_p3_cas_n; +assign a7ddrphy_dfi_p3_cs_n = netv2_sdram_master_p3_cs_n; +assign a7ddrphy_dfi_p3_ras_n = netv2_sdram_master_p3_ras_n; +assign a7ddrphy_dfi_p3_we_n = netv2_sdram_master_p3_we_n; +assign a7ddrphy_dfi_p3_cke = netv2_sdram_master_p3_cke; +assign a7ddrphy_dfi_p3_odt = netv2_sdram_master_p3_odt; +assign a7ddrphy_dfi_p3_reset_n = netv2_sdram_master_p3_reset_n; +assign a7ddrphy_dfi_p3_act_n = netv2_sdram_master_p3_act_n; +assign a7ddrphy_dfi_p3_wrdata = netv2_sdram_master_p3_wrdata; +assign a7ddrphy_dfi_p3_wrdata_en = netv2_sdram_master_p3_wrdata_en; +assign a7ddrphy_dfi_p3_wrdata_mask = netv2_sdram_master_p3_wrdata_mask; +assign a7ddrphy_dfi_p3_rddata_en = netv2_sdram_master_p3_rddata_en; +assign netv2_sdram_master_p3_rddata = a7ddrphy_dfi_p3_rddata; +assign netv2_sdram_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid; +assign netv2_sdram_slave_p0_address = netv2_sdram_dfi_p0_address; +assign netv2_sdram_slave_p0_bank = netv2_sdram_dfi_p0_bank; +assign netv2_sdram_slave_p0_cas_n = netv2_sdram_dfi_p0_cas_n; +assign netv2_sdram_slave_p0_cs_n = netv2_sdram_dfi_p0_cs_n; +assign netv2_sdram_slave_p0_ras_n = netv2_sdram_dfi_p0_ras_n; +assign netv2_sdram_slave_p0_we_n = netv2_sdram_dfi_p0_we_n; +assign netv2_sdram_slave_p0_cke = netv2_sdram_dfi_p0_cke; +assign netv2_sdram_slave_p0_odt = netv2_sdram_dfi_p0_odt; +assign netv2_sdram_slave_p0_reset_n = netv2_sdram_dfi_p0_reset_n; +assign netv2_sdram_slave_p0_act_n = netv2_sdram_dfi_p0_act_n; +assign netv2_sdram_slave_p0_wrdata = netv2_sdram_dfi_p0_wrdata; +assign netv2_sdram_slave_p0_wrdata_en = netv2_sdram_dfi_p0_wrdata_en; +assign netv2_sdram_slave_p0_wrdata_mask = netv2_sdram_dfi_p0_wrdata_mask; +assign netv2_sdram_slave_p0_rddata_en = netv2_sdram_dfi_p0_rddata_en; +assign netv2_sdram_dfi_p0_rddata = netv2_sdram_slave_p0_rddata; +assign netv2_sdram_dfi_p0_rddata_valid = netv2_sdram_slave_p0_rddata_valid; +assign netv2_sdram_slave_p1_address = netv2_sdram_dfi_p1_address; +assign netv2_sdram_slave_p1_bank = netv2_sdram_dfi_p1_bank; +assign netv2_sdram_slave_p1_cas_n = netv2_sdram_dfi_p1_cas_n; +assign netv2_sdram_slave_p1_cs_n = netv2_sdram_dfi_p1_cs_n; +assign netv2_sdram_slave_p1_ras_n = netv2_sdram_dfi_p1_ras_n; +assign netv2_sdram_slave_p1_we_n = netv2_sdram_dfi_p1_we_n; +assign netv2_sdram_slave_p1_cke = netv2_sdram_dfi_p1_cke; +assign netv2_sdram_slave_p1_odt = netv2_sdram_dfi_p1_odt; +assign netv2_sdram_slave_p1_reset_n = netv2_sdram_dfi_p1_reset_n; +assign netv2_sdram_slave_p1_act_n = netv2_sdram_dfi_p1_act_n; +assign netv2_sdram_slave_p1_wrdata = netv2_sdram_dfi_p1_wrdata; +assign netv2_sdram_slave_p1_wrdata_en = netv2_sdram_dfi_p1_wrdata_en; +assign netv2_sdram_slave_p1_wrdata_mask = netv2_sdram_dfi_p1_wrdata_mask; +assign netv2_sdram_slave_p1_rddata_en = netv2_sdram_dfi_p1_rddata_en; +assign netv2_sdram_dfi_p1_rddata = netv2_sdram_slave_p1_rddata; +assign netv2_sdram_dfi_p1_rddata_valid = netv2_sdram_slave_p1_rddata_valid; +assign netv2_sdram_slave_p2_address = netv2_sdram_dfi_p2_address; +assign netv2_sdram_slave_p2_bank = netv2_sdram_dfi_p2_bank; +assign netv2_sdram_slave_p2_cas_n = netv2_sdram_dfi_p2_cas_n; +assign netv2_sdram_slave_p2_cs_n = netv2_sdram_dfi_p2_cs_n; +assign netv2_sdram_slave_p2_ras_n = netv2_sdram_dfi_p2_ras_n; +assign netv2_sdram_slave_p2_we_n = netv2_sdram_dfi_p2_we_n; +assign netv2_sdram_slave_p2_cke = netv2_sdram_dfi_p2_cke; +assign netv2_sdram_slave_p2_odt = netv2_sdram_dfi_p2_odt; +assign netv2_sdram_slave_p2_reset_n = netv2_sdram_dfi_p2_reset_n; +assign netv2_sdram_slave_p2_act_n = netv2_sdram_dfi_p2_act_n; +assign netv2_sdram_slave_p2_wrdata = netv2_sdram_dfi_p2_wrdata; +assign netv2_sdram_slave_p2_wrdata_en = netv2_sdram_dfi_p2_wrdata_en; +assign netv2_sdram_slave_p2_wrdata_mask = netv2_sdram_dfi_p2_wrdata_mask; +assign netv2_sdram_slave_p2_rddata_en = netv2_sdram_dfi_p2_rddata_en; +assign netv2_sdram_dfi_p2_rddata = netv2_sdram_slave_p2_rddata; +assign netv2_sdram_dfi_p2_rddata_valid = netv2_sdram_slave_p2_rddata_valid; +assign netv2_sdram_slave_p3_address = netv2_sdram_dfi_p3_address; +assign netv2_sdram_slave_p3_bank = netv2_sdram_dfi_p3_bank; +assign netv2_sdram_slave_p3_cas_n = netv2_sdram_dfi_p3_cas_n; +assign netv2_sdram_slave_p3_cs_n = netv2_sdram_dfi_p3_cs_n; +assign netv2_sdram_slave_p3_ras_n = netv2_sdram_dfi_p3_ras_n; +assign netv2_sdram_slave_p3_we_n = netv2_sdram_dfi_p3_we_n; +assign netv2_sdram_slave_p3_cke = netv2_sdram_dfi_p3_cke; +assign netv2_sdram_slave_p3_odt = netv2_sdram_dfi_p3_odt; +assign netv2_sdram_slave_p3_reset_n = netv2_sdram_dfi_p3_reset_n; +assign netv2_sdram_slave_p3_act_n = netv2_sdram_dfi_p3_act_n; +assign netv2_sdram_slave_p3_wrdata = netv2_sdram_dfi_p3_wrdata; +assign netv2_sdram_slave_p3_wrdata_en = netv2_sdram_dfi_p3_wrdata_en; +assign netv2_sdram_slave_p3_wrdata_mask = netv2_sdram_dfi_p3_wrdata_mask; +assign netv2_sdram_slave_p3_rddata_en = netv2_sdram_dfi_p3_rddata_en; +assign netv2_sdram_dfi_p3_rddata = netv2_sdram_slave_p3_rddata; +assign netv2_sdram_dfi_p3_rddata_valid = netv2_sdram_slave_p3_rddata_valid; +always @(*) begin + netv2_sdram_master_p2_cs_n <= 1'd1; + netv2_sdram_master_p2_ras_n <= 1'd1; + netv2_sdram_master_p2_we_n <= 1'd1; + netv2_sdram_master_p2_cke <= 1'd0; + netv2_sdram_master_p2_odt <= 1'd0; + netv2_sdram_master_p2_reset_n <= 1'd0; + netv2_sdram_master_p2_act_n <= 1'd1; + netv2_sdram_master_p2_wrdata <= 64'd0; + netv2_sdram_inti_p3_rddata <= 64'd0; + netv2_sdram_master_p2_wrdata_en <= 1'd0; + netv2_sdram_inti_p3_rddata_valid <= 1'd0; + netv2_sdram_master_p2_wrdata_mask <= 8'd0; + netv2_sdram_master_p2_rddata_en <= 1'd0; + netv2_sdram_master_p3_address <= 14'd0; + netv2_sdram_master_p3_bank <= 3'd0; + netv2_sdram_master_p3_cas_n <= 1'd1; + netv2_sdram_master_p3_cs_n <= 1'd1; + netv2_sdram_master_p3_ras_n <= 1'd1; + netv2_sdram_master_p3_we_n <= 1'd1; + netv2_sdram_master_p3_cke <= 1'd0; + netv2_sdram_master_p3_odt <= 1'd0; + netv2_sdram_master_p3_reset_n <= 1'd0; + netv2_sdram_master_p3_act_n <= 1'd1; + netv2_sdram_master_p3_wrdata <= 64'd0; + netv2_sdram_master_p3_wrdata_en <= 1'd0; + netv2_sdram_master_p3_wrdata_mask <= 8'd0; + netv2_sdram_master_p3_rddata_en <= 1'd0; + netv2_sdram_slave_p0_rddata <= 64'd0; + netv2_sdram_slave_p0_rddata_valid <= 1'd0; + netv2_sdram_slave_p1_rddata <= 64'd0; + netv2_sdram_slave_p1_rddata_valid <= 1'd0; + netv2_sdram_slave_p2_rddata <= 64'd0; + netv2_sdram_slave_p2_rddata_valid <= 1'd0; + netv2_sdram_slave_p3_rddata <= 64'd0; + netv2_sdram_slave_p3_rddata_valid <= 1'd0; + netv2_sdram_inti_p0_rddata <= 64'd0; + netv2_sdram_inti_p0_rddata_valid <= 1'd0; + netv2_sdram_master_p0_address <= 14'd0; + netv2_sdram_master_p0_bank <= 3'd0; + netv2_sdram_master_p0_cas_n <= 1'd1; + netv2_sdram_master_p0_cs_n <= 1'd1; + netv2_sdram_master_p0_ras_n <= 1'd1; + netv2_sdram_master_p0_we_n <= 1'd1; + netv2_sdram_master_p0_cke <= 1'd0; + netv2_sdram_master_p0_odt <= 1'd0; + netv2_sdram_master_p0_reset_n <= 1'd0; + netv2_sdram_master_p0_act_n <= 1'd1; + netv2_sdram_master_p0_wrdata <= 64'd0; + netv2_sdram_inti_p1_rddata <= 64'd0; + netv2_sdram_master_p0_wrdata_en <= 1'd0; + netv2_sdram_inti_p1_rddata_valid <= 1'd0; + netv2_sdram_master_p0_wrdata_mask <= 8'd0; + netv2_sdram_master_p0_rddata_en <= 1'd0; + netv2_sdram_master_p1_address <= 14'd0; + netv2_sdram_master_p1_bank <= 3'd0; + netv2_sdram_master_p1_cas_n <= 1'd1; + netv2_sdram_master_p1_cs_n <= 1'd1; + netv2_sdram_master_p1_ras_n <= 1'd1; + netv2_sdram_master_p1_we_n <= 1'd1; + netv2_sdram_master_p1_cke <= 1'd0; + netv2_sdram_master_p1_odt <= 1'd0; + netv2_sdram_master_p1_reset_n <= 1'd0; + netv2_sdram_master_p1_act_n <= 1'd1; + netv2_sdram_master_p1_wrdata <= 64'd0; + netv2_sdram_inti_p2_rddata <= 64'd0; + netv2_sdram_master_p1_wrdata_en <= 1'd0; + netv2_sdram_inti_p2_rddata_valid <= 1'd0; + netv2_sdram_master_p1_wrdata_mask <= 8'd0; + netv2_sdram_master_p1_rddata_en <= 1'd0; + netv2_sdram_master_p2_address <= 14'd0; + netv2_sdram_master_p2_bank <= 3'd0; + netv2_sdram_master_p2_cas_n <= 1'd1; + if (netv2_sdram_sel) begin + netv2_sdram_master_p0_address <= netv2_sdram_slave_p0_address; + netv2_sdram_master_p0_bank <= netv2_sdram_slave_p0_bank; + netv2_sdram_master_p0_cas_n <= netv2_sdram_slave_p0_cas_n; + netv2_sdram_master_p0_cs_n <= netv2_sdram_slave_p0_cs_n; + netv2_sdram_master_p0_ras_n <= netv2_sdram_slave_p0_ras_n; + netv2_sdram_master_p0_we_n <= netv2_sdram_slave_p0_we_n; + netv2_sdram_master_p0_cke <= netv2_sdram_slave_p0_cke; + netv2_sdram_master_p0_odt <= netv2_sdram_slave_p0_odt; + netv2_sdram_master_p0_reset_n <= netv2_sdram_slave_p0_reset_n; + netv2_sdram_master_p0_act_n <= netv2_sdram_slave_p0_act_n; + netv2_sdram_master_p0_wrdata <= netv2_sdram_slave_p0_wrdata; + netv2_sdram_master_p0_wrdata_en <= netv2_sdram_slave_p0_wrdata_en; + netv2_sdram_master_p0_wrdata_mask <= netv2_sdram_slave_p0_wrdata_mask; + netv2_sdram_master_p0_rddata_en <= netv2_sdram_slave_p0_rddata_en; + netv2_sdram_slave_p0_rddata <= netv2_sdram_master_p0_rddata; + netv2_sdram_slave_p0_rddata_valid <= netv2_sdram_master_p0_rddata_valid; + netv2_sdram_master_p1_address <= netv2_sdram_slave_p1_address; + netv2_sdram_master_p1_bank <= netv2_sdram_slave_p1_bank; + netv2_sdram_master_p1_cas_n <= netv2_sdram_slave_p1_cas_n; + netv2_sdram_master_p1_cs_n <= netv2_sdram_slave_p1_cs_n; + netv2_sdram_master_p1_ras_n <= netv2_sdram_slave_p1_ras_n; + netv2_sdram_master_p1_we_n <= netv2_sdram_slave_p1_we_n; + netv2_sdram_master_p1_cke <= netv2_sdram_slave_p1_cke; + netv2_sdram_master_p1_odt <= netv2_sdram_slave_p1_odt; + netv2_sdram_master_p1_reset_n <= netv2_sdram_slave_p1_reset_n; + netv2_sdram_master_p1_act_n <= netv2_sdram_slave_p1_act_n; + netv2_sdram_master_p1_wrdata <= netv2_sdram_slave_p1_wrdata; + netv2_sdram_master_p1_wrdata_en <= netv2_sdram_slave_p1_wrdata_en; + netv2_sdram_master_p1_wrdata_mask <= netv2_sdram_slave_p1_wrdata_mask; + netv2_sdram_master_p1_rddata_en <= netv2_sdram_slave_p1_rddata_en; + netv2_sdram_slave_p1_rddata <= netv2_sdram_master_p1_rddata; + netv2_sdram_slave_p1_rddata_valid <= netv2_sdram_master_p1_rddata_valid; + netv2_sdram_master_p2_address <= netv2_sdram_slave_p2_address; + netv2_sdram_master_p2_bank <= netv2_sdram_slave_p2_bank; + netv2_sdram_master_p2_cas_n <= netv2_sdram_slave_p2_cas_n; + netv2_sdram_master_p2_cs_n <= netv2_sdram_slave_p2_cs_n; + netv2_sdram_master_p2_ras_n <= netv2_sdram_slave_p2_ras_n; + netv2_sdram_master_p2_we_n <= netv2_sdram_slave_p2_we_n; + netv2_sdram_master_p2_cke <= netv2_sdram_slave_p2_cke; + netv2_sdram_master_p2_odt <= netv2_sdram_slave_p2_odt; + netv2_sdram_master_p2_reset_n <= netv2_sdram_slave_p2_reset_n; + netv2_sdram_master_p2_act_n <= netv2_sdram_slave_p2_act_n; + netv2_sdram_master_p2_wrdata <= netv2_sdram_slave_p2_wrdata; + netv2_sdram_master_p2_wrdata_en <= netv2_sdram_slave_p2_wrdata_en; + netv2_sdram_master_p2_wrdata_mask <= netv2_sdram_slave_p2_wrdata_mask; + netv2_sdram_master_p2_rddata_en <= netv2_sdram_slave_p2_rddata_en; + netv2_sdram_slave_p2_rddata <= netv2_sdram_master_p2_rddata; + netv2_sdram_slave_p2_rddata_valid <= netv2_sdram_master_p2_rddata_valid; + netv2_sdram_master_p3_address <= netv2_sdram_slave_p3_address; + netv2_sdram_master_p3_bank <= netv2_sdram_slave_p3_bank; + netv2_sdram_master_p3_cas_n <= netv2_sdram_slave_p3_cas_n; + netv2_sdram_master_p3_cs_n <= netv2_sdram_slave_p3_cs_n; + netv2_sdram_master_p3_ras_n <= netv2_sdram_slave_p3_ras_n; + netv2_sdram_master_p3_we_n <= netv2_sdram_slave_p3_we_n; + netv2_sdram_master_p3_cke <= netv2_sdram_slave_p3_cke; + netv2_sdram_master_p3_odt <= netv2_sdram_slave_p3_odt; + netv2_sdram_master_p3_reset_n <= netv2_sdram_slave_p3_reset_n; + netv2_sdram_master_p3_act_n <= netv2_sdram_slave_p3_act_n; + netv2_sdram_master_p3_wrdata <= netv2_sdram_slave_p3_wrdata; + netv2_sdram_master_p3_wrdata_en <= netv2_sdram_slave_p3_wrdata_en; + netv2_sdram_master_p3_wrdata_mask <= netv2_sdram_slave_p3_wrdata_mask; + netv2_sdram_master_p3_rddata_en <= netv2_sdram_slave_p3_rddata_en; + netv2_sdram_slave_p3_rddata <= netv2_sdram_master_p3_rddata; + netv2_sdram_slave_p3_rddata_valid <= netv2_sdram_master_p3_rddata_valid; + end else begin + netv2_sdram_master_p0_address <= netv2_sdram_inti_p0_address; + netv2_sdram_master_p0_bank <= netv2_sdram_inti_p0_bank; + netv2_sdram_master_p0_cas_n <= netv2_sdram_inti_p0_cas_n; + netv2_sdram_master_p0_cs_n <= netv2_sdram_inti_p0_cs_n; + netv2_sdram_master_p0_ras_n <= netv2_sdram_inti_p0_ras_n; + netv2_sdram_master_p0_we_n <= netv2_sdram_inti_p0_we_n; + netv2_sdram_master_p0_cke <= netv2_sdram_inti_p0_cke; + netv2_sdram_master_p0_odt <= netv2_sdram_inti_p0_odt; + netv2_sdram_master_p0_reset_n <= netv2_sdram_inti_p0_reset_n; + netv2_sdram_master_p0_act_n <= netv2_sdram_inti_p0_act_n; + netv2_sdram_master_p0_wrdata <= netv2_sdram_inti_p0_wrdata; + netv2_sdram_master_p0_wrdata_en <= netv2_sdram_inti_p0_wrdata_en; + netv2_sdram_master_p0_wrdata_mask <= netv2_sdram_inti_p0_wrdata_mask; + netv2_sdram_master_p0_rddata_en <= netv2_sdram_inti_p0_rddata_en; + netv2_sdram_inti_p0_rddata <= netv2_sdram_master_p0_rddata; + netv2_sdram_inti_p0_rddata_valid <= netv2_sdram_master_p0_rddata_valid; + netv2_sdram_master_p1_address <= netv2_sdram_inti_p1_address; + netv2_sdram_master_p1_bank <= netv2_sdram_inti_p1_bank; + netv2_sdram_master_p1_cas_n <= netv2_sdram_inti_p1_cas_n; + netv2_sdram_master_p1_cs_n <= netv2_sdram_inti_p1_cs_n; + netv2_sdram_master_p1_ras_n <= netv2_sdram_inti_p1_ras_n; + netv2_sdram_master_p1_we_n <= netv2_sdram_inti_p1_we_n; + netv2_sdram_master_p1_cke <= netv2_sdram_inti_p1_cke; + netv2_sdram_master_p1_odt <= netv2_sdram_inti_p1_odt; + netv2_sdram_master_p1_reset_n <= netv2_sdram_inti_p1_reset_n; + netv2_sdram_master_p1_act_n <= netv2_sdram_inti_p1_act_n; + netv2_sdram_master_p1_wrdata <= netv2_sdram_inti_p1_wrdata; + netv2_sdram_master_p1_wrdata_en <= netv2_sdram_inti_p1_wrdata_en; + netv2_sdram_master_p1_wrdata_mask <= netv2_sdram_inti_p1_wrdata_mask; + netv2_sdram_master_p1_rddata_en <= netv2_sdram_inti_p1_rddata_en; + netv2_sdram_inti_p1_rddata <= netv2_sdram_master_p1_rddata; + netv2_sdram_inti_p1_rddata_valid <= netv2_sdram_master_p1_rddata_valid; + netv2_sdram_master_p2_address <= netv2_sdram_inti_p2_address; + netv2_sdram_master_p2_bank <= netv2_sdram_inti_p2_bank; + netv2_sdram_master_p2_cas_n <= netv2_sdram_inti_p2_cas_n; + netv2_sdram_master_p2_cs_n <= netv2_sdram_inti_p2_cs_n; + netv2_sdram_master_p2_ras_n <= netv2_sdram_inti_p2_ras_n; + netv2_sdram_master_p2_we_n <= netv2_sdram_inti_p2_we_n; + netv2_sdram_master_p2_cke <= netv2_sdram_inti_p2_cke; + netv2_sdram_master_p2_odt <= netv2_sdram_inti_p2_odt; + netv2_sdram_master_p2_reset_n <= netv2_sdram_inti_p2_reset_n; + netv2_sdram_master_p2_act_n <= netv2_sdram_inti_p2_act_n; + netv2_sdram_master_p2_wrdata <= netv2_sdram_inti_p2_wrdata; + netv2_sdram_master_p2_wrdata_en <= netv2_sdram_inti_p2_wrdata_en; + netv2_sdram_master_p2_wrdata_mask <= netv2_sdram_inti_p2_wrdata_mask; + netv2_sdram_master_p2_rddata_en <= netv2_sdram_inti_p2_rddata_en; + netv2_sdram_inti_p2_rddata <= netv2_sdram_master_p2_rddata; + netv2_sdram_inti_p2_rddata_valid <= netv2_sdram_master_p2_rddata_valid; + netv2_sdram_master_p3_address <= netv2_sdram_inti_p3_address; + netv2_sdram_master_p3_bank <= netv2_sdram_inti_p3_bank; + netv2_sdram_master_p3_cas_n <= netv2_sdram_inti_p3_cas_n; + netv2_sdram_master_p3_cs_n <= netv2_sdram_inti_p3_cs_n; + netv2_sdram_master_p3_ras_n <= netv2_sdram_inti_p3_ras_n; + netv2_sdram_master_p3_we_n <= netv2_sdram_inti_p3_we_n; + netv2_sdram_master_p3_cke <= netv2_sdram_inti_p3_cke; + netv2_sdram_master_p3_odt <= netv2_sdram_inti_p3_odt; + netv2_sdram_master_p3_reset_n <= netv2_sdram_inti_p3_reset_n; + netv2_sdram_master_p3_act_n <= netv2_sdram_inti_p3_act_n; + netv2_sdram_master_p3_wrdata <= netv2_sdram_inti_p3_wrdata; + netv2_sdram_master_p3_wrdata_en <= netv2_sdram_inti_p3_wrdata_en; + netv2_sdram_master_p3_wrdata_mask <= netv2_sdram_inti_p3_wrdata_mask; + netv2_sdram_master_p3_rddata_en <= netv2_sdram_inti_p3_rddata_en; + netv2_sdram_inti_p3_rddata <= netv2_sdram_master_p3_rddata; + netv2_sdram_inti_p3_rddata_valid <= netv2_sdram_master_p3_rddata_valid; + end +end +assign netv2_sdram_inti_p0_cke = netv2_sdram_cke; +assign netv2_sdram_inti_p1_cke = netv2_sdram_cke; +assign netv2_sdram_inti_p2_cke = netv2_sdram_cke; +assign netv2_sdram_inti_p3_cke = netv2_sdram_cke; +assign netv2_sdram_inti_p0_odt = netv2_sdram_odt; +assign netv2_sdram_inti_p1_odt = netv2_sdram_odt; +assign netv2_sdram_inti_p2_odt = netv2_sdram_odt; +assign netv2_sdram_inti_p3_odt = netv2_sdram_odt; +assign netv2_sdram_inti_p0_reset_n = netv2_sdram_reset_n; +assign netv2_sdram_inti_p1_reset_n = netv2_sdram_reset_n; +assign netv2_sdram_inti_p2_reset_n = netv2_sdram_reset_n; +assign netv2_sdram_inti_p3_reset_n = netv2_sdram_reset_n; +always @(*) begin + netv2_sdram_inti_p0_cs_n <= 1'd1; + netv2_sdram_inti_p0_ras_n <= 1'd1; + netv2_sdram_inti_p0_we_n <= 1'd1; + netv2_sdram_inti_p0_cas_n <= 1'd1; + if (netv2_sdram_phaseinjector0_command_issue_re) begin + netv2_sdram_inti_p0_cs_n <= {1{(~netv2_sdram_phaseinjector0_command_storage[0])}}; + netv2_sdram_inti_p0_we_n <= (~netv2_sdram_phaseinjector0_command_storage[1]); + netv2_sdram_inti_p0_cas_n <= (~netv2_sdram_phaseinjector0_command_storage[2]); + netv2_sdram_inti_p0_ras_n <= (~netv2_sdram_phaseinjector0_command_storage[3]); + end else begin + netv2_sdram_inti_p0_cs_n <= {1{1'd1}}; + netv2_sdram_inti_p0_we_n <= 1'd1; + netv2_sdram_inti_p0_cas_n <= 1'd1; + netv2_sdram_inti_p0_ras_n <= 1'd1; + end +end +assign netv2_sdram_inti_p0_address = netv2_sdram_phaseinjector0_address_storage; +assign netv2_sdram_inti_p0_bank = netv2_sdram_phaseinjector0_baddress_storage; +assign netv2_sdram_inti_p0_wrdata_en = (netv2_sdram_phaseinjector0_command_issue_re & netv2_sdram_phaseinjector0_command_storage[4]); +assign netv2_sdram_inti_p0_rddata_en = (netv2_sdram_phaseinjector0_command_issue_re & netv2_sdram_phaseinjector0_command_storage[5]); +assign netv2_sdram_inti_p0_wrdata = netv2_sdram_phaseinjector0_wrdata_storage; +assign netv2_sdram_inti_p0_wrdata_mask = 1'd0; +always @(*) begin + netv2_sdram_inti_p1_cs_n <= 1'd1; + netv2_sdram_inti_p1_ras_n <= 1'd1; + netv2_sdram_inti_p1_we_n <= 1'd1; + netv2_sdram_inti_p1_cas_n <= 1'd1; + if (netv2_sdram_phaseinjector1_command_issue_re) begin + netv2_sdram_inti_p1_cs_n <= {1{(~netv2_sdram_phaseinjector1_command_storage[0])}}; + netv2_sdram_inti_p1_we_n <= (~netv2_sdram_phaseinjector1_command_storage[1]); + netv2_sdram_inti_p1_cas_n <= (~netv2_sdram_phaseinjector1_command_storage[2]); + netv2_sdram_inti_p1_ras_n <= (~netv2_sdram_phaseinjector1_command_storage[3]); + end else begin + netv2_sdram_inti_p1_cs_n <= {1{1'd1}}; + netv2_sdram_inti_p1_we_n <= 1'd1; + netv2_sdram_inti_p1_cas_n <= 1'd1; + netv2_sdram_inti_p1_ras_n <= 1'd1; + end +end +assign netv2_sdram_inti_p1_address = netv2_sdram_phaseinjector1_address_storage; +assign netv2_sdram_inti_p1_bank = netv2_sdram_phaseinjector1_baddress_storage; +assign netv2_sdram_inti_p1_wrdata_en = (netv2_sdram_phaseinjector1_command_issue_re & netv2_sdram_phaseinjector1_command_storage[4]); +assign netv2_sdram_inti_p1_rddata_en = (netv2_sdram_phaseinjector1_command_issue_re & netv2_sdram_phaseinjector1_command_storage[5]); +assign netv2_sdram_inti_p1_wrdata = netv2_sdram_phaseinjector1_wrdata_storage; +assign netv2_sdram_inti_p1_wrdata_mask = 1'd0; +always @(*) begin + netv2_sdram_inti_p2_cs_n <= 1'd1; + netv2_sdram_inti_p2_ras_n <= 1'd1; + netv2_sdram_inti_p2_we_n <= 1'd1; + netv2_sdram_inti_p2_cas_n <= 1'd1; + if (netv2_sdram_phaseinjector2_command_issue_re) begin + netv2_sdram_inti_p2_cs_n <= {1{(~netv2_sdram_phaseinjector2_command_storage[0])}}; + netv2_sdram_inti_p2_we_n <= (~netv2_sdram_phaseinjector2_command_storage[1]); + netv2_sdram_inti_p2_cas_n <= (~netv2_sdram_phaseinjector2_command_storage[2]); + netv2_sdram_inti_p2_ras_n <= (~netv2_sdram_phaseinjector2_command_storage[3]); + end else begin + netv2_sdram_inti_p2_cs_n <= {1{1'd1}}; + netv2_sdram_inti_p2_we_n <= 1'd1; + netv2_sdram_inti_p2_cas_n <= 1'd1; + netv2_sdram_inti_p2_ras_n <= 1'd1; + end +end +assign netv2_sdram_inti_p2_address = netv2_sdram_phaseinjector2_address_storage; +assign netv2_sdram_inti_p2_bank = netv2_sdram_phaseinjector2_baddress_storage; +assign netv2_sdram_inti_p2_wrdata_en = (netv2_sdram_phaseinjector2_command_issue_re & netv2_sdram_phaseinjector2_command_storage[4]); +assign netv2_sdram_inti_p2_rddata_en = (netv2_sdram_phaseinjector2_command_issue_re & netv2_sdram_phaseinjector2_command_storage[5]); +assign netv2_sdram_inti_p2_wrdata = netv2_sdram_phaseinjector2_wrdata_storage; +assign netv2_sdram_inti_p2_wrdata_mask = 1'd0; +always @(*) begin + netv2_sdram_inti_p3_cs_n <= 1'd1; + netv2_sdram_inti_p3_ras_n <= 1'd1; + netv2_sdram_inti_p3_we_n <= 1'd1; + netv2_sdram_inti_p3_cas_n <= 1'd1; + if (netv2_sdram_phaseinjector3_command_issue_re) begin + netv2_sdram_inti_p3_cs_n <= {1{(~netv2_sdram_phaseinjector3_command_storage[0])}}; + netv2_sdram_inti_p3_we_n <= (~netv2_sdram_phaseinjector3_command_storage[1]); + netv2_sdram_inti_p3_cas_n <= (~netv2_sdram_phaseinjector3_command_storage[2]); + netv2_sdram_inti_p3_ras_n <= (~netv2_sdram_phaseinjector3_command_storage[3]); + end else begin + netv2_sdram_inti_p3_cs_n <= {1{1'd1}}; + netv2_sdram_inti_p3_we_n <= 1'd1; + netv2_sdram_inti_p3_cas_n <= 1'd1; + netv2_sdram_inti_p3_ras_n <= 1'd1; + end +end +assign netv2_sdram_inti_p3_address = netv2_sdram_phaseinjector3_address_storage; +assign netv2_sdram_inti_p3_bank = netv2_sdram_phaseinjector3_baddress_storage; +assign netv2_sdram_inti_p3_wrdata_en = (netv2_sdram_phaseinjector3_command_issue_re & netv2_sdram_phaseinjector3_command_storage[4]); +assign netv2_sdram_inti_p3_rddata_en = (netv2_sdram_phaseinjector3_command_issue_re & netv2_sdram_phaseinjector3_command_storage[5]); +assign netv2_sdram_inti_p3_wrdata = netv2_sdram_phaseinjector3_wrdata_storage; +assign netv2_sdram_inti_p3_wrdata_mask = 1'd0; +assign netv2_sdram_bankmachine0_req_valid = netv2_sdram_interface_bank0_valid; +assign netv2_sdram_interface_bank0_ready = netv2_sdram_bankmachine0_req_ready; +assign netv2_sdram_bankmachine0_req_we = netv2_sdram_interface_bank0_we; +assign netv2_sdram_bankmachine0_req_addr = netv2_sdram_interface_bank0_addr; +assign netv2_sdram_interface_bank0_lock = netv2_sdram_bankmachine0_req_lock; +assign netv2_sdram_interface_bank0_wdata_ready = netv2_sdram_bankmachine0_req_wdata_ready; +assign netv2_sdram_interface_bank0_rdata_valid = netv2_sdram_bankmachine0_req_rdata_valid; +assign netv2_sdram_bankmachine1_req_valid = netv2_sdram_interface_bank1_valid; +assign netv2_sdram_interface_bank1_ready = netv2_sdram_bankmachine1_req_ready; +assign netv2_sdram_bankmachine1_req_we = netv2_sdram_interface_bank1_we; +assign netv2_sdram_bankmachine1_req_addr = netv2_sdram_interface_bank1_addr; +assign netv2_sdram_interface_bank1_lock = netv2_sdram_bankmachine1_req_lock; +assign netv2_sdram_interface_bank1_wdata_ready = netv2_sdram_bankmachine1_req_wdata_ready; +assign netv2_sdram_interface_bank1_rdata_valid = netv2_sdram_bankmachine1_req_rdata_valid; +assign netv2_sdram_bankmachine2_req_valid = netv2_sdram_interface_bank2_valid; +assign netv2_sdram_interface_bank2_ready = netv2_sdram_bankmachine2_req_ready; +assign netv2_sdram_bankmachine2_req_we = netv2_sdram_interface_bank2_we; +assign netv2_sdram_bankmachine2_req_addr = netv2_sdram_interface_bank2_addr; +assign netv2_sdram_interface_bank2_lock = netv2_sdram_bankmachine2_req_lock; +assign netv2_sdram_interface_bank2_wdata_ready = netv2_sdram_bankmachine2_req_wdata_ready; +assign netv2_sdram_interface_bank2_rdata_valid = netv2_sdram_bankmachine2_req_rdata_valid; +assign netv2_sdram_bankmachine3_req_valid = netv2_sdram_interface_bank3_valid; +assign netv2_sdram_interface_bank3_ready = netv2_sdram_bankmachine3_req_ready; +assign netv2_sdram_bankmachine3_req_we = netv2_sdram_interface_bank3_we; +assign netv2_sdram_bankmachine3_req_addr = netv2_sdram_interface_bank3_addr; +assign netv2_sdram_interface_bank3_lock = netv2_sdram_bankmachine3_req_lock; +assign netv2_sdram_interface_bank3_wdata_ready = netv2_sdram_bankmachine3_req_wdata_ready; +assign netv2_sdram_interface_bank3_rdata_valid = netv2_sdram_bankmachine3_req_rdata_valid; +assign netv2_sdram_bankmachine4_req_valid = netv2_sdram_interface_bank4_valid; +assign netv2_sdram_interface_bank4_ready = netv2_sdram_bankmachine4_req_ready; +assign netv2_sdram_bankmachine4_req_we = netv2_sdram_interface_bank4_we; +assign netv2_sdram_bankmachine4_req_addr = netv2_sdram_interface_bank4_addr; +assign netv2_sdram_interface_bank4_lock = netv2_sdram_bankmachine4_req_lock; +assign netv2_sdram_interface_bank4_wdata_ready = netv2_sdram_bankmachine4_req_wdata_ready; +assign netv2_sdram_interface_bank4_rdata_valid = netv2_sdram_bankmachine4_req_rdata_valid; +assign netv2_sdram_bankmachine5_req_valid = netv2_sdram_interface_bank5_valid; +assign netv2_sdram_interface_bank5_ready = netv2_sdram_bankmachine5_req_ready; +assign netv2_sdram_bankmachine5_req_we = netv2_sdram_interface_bank5_we; +assign netv2_sdram_bankmachine5_req_addr = netv2_sdram_interface_bank5_addr; +assign netv2_sdram_interface_bank5_lock = netv2_sdram_bankmachine5_req_lock; +assign netv2_sdram_interface_bank5_wdata_ready = netv2_sdram_bankmachine5_req_wdata_ready; +assign netv2_sdram_interface_bank5_rdata_valid = netv2_sdram_bankmachine5_req_rdata_valid; +assign netv2_sdram_bankmachine6_req_valid = netv2_sdram_interface_bank6_valid; +assign netv2_sdram_interface_bank6_ready = netv2_sdram_bankmachine6_req_ready; +assign netv2_sdram_bankmachine6_req_we = netv2_sdram_interface_bank6_we; +assign netv2_sdram_bankmachine6_req_addr = netv2_sdram_interface_bank6_addr; +assign netv2_sdram_interface_bank6_lock = netv2_sdram_bankmachine6_req_lock; +assign netv2_sdram_interface_bank6_wdata_ready = netv2_sdram_bankmachine6_req_wdata_ready; +assign netv2_sdram_interface_bank6_rdata_valid = netv2_sdram_bankmachine6_req_rdata_valid; +assign netv2_sdram_bankmachine7_req_valid = netv2_sdram_interface_bank7_valid; +assign netv2_sdram_interface_bank7_ready = netv2_sdram_bankmachine7_req_ready; +assign netv2_sdram_bankmachine7_req_we = netv2_sdram_interface_bank7_we; +assign netv2_sdram_bankmachine7_req_addr = netv2_sdram_interface_bank7_addr; +assign netv2_sdram_interface_bank7_lock = netv2_sdram_bankmachine7_req_lock; +assign netv2_sdram_interface_bank7_wdata_ready = netv2_sdram_bankmachine7_req_wdata_ready; +assign netv2_sdram_interface_bank7_rdata_valid = netv2_sdram_bankmachine7_req_rdata_valid; +assign netv2_sdram_timer_wait = (~netv2_sdram_timer_done0); +assign netv2_sdram_postponer_req_i = netv2_sdram_timer_done0; +assign netv2_sdram_wants_refresh = netv2_sdram_postponer_req_o; +assign netv2_sdram_wants_zqcs = netv2_sdram_zqcs_timer_done0; +assign netv2_sdram_zqcs_timer_wait = (~netv2_sdram_zqcs_executer_done); +assign netv2_sdram_timer_done1 = (netv2_sdram_timer_count1 == 1'd0); +assign netv2_sdram_timer_done0 = netv2_sdram_timer_done1; +assign netv2_sdram_timer_count0 = netv2_sdram_timer_count1; +assign netv2_sdram_sequencer_start1 = (netv2_sdram_sequencer_start0 | (netv2_sdram_sequencer_count != 1'd0)); +assign netv2_sdram_sequencer_done0 = (netv2_sdram_sequencer_done1 & (netv2_sdram_sequencer_count == 1'd0)); +assign netv2_sdram_zqcs_timer_done1 = (netv2_sdram_zqcs_timer_count1 == 1'd0); +assign netv2_sdram_zqcs_timer_done0 = netv2_sdram_zqcs_timer_done1; +assign netv2_sdram_zqcs_timer_count0 = netv2_sdram_zqcs_timer_count1; +always @(*) begin + litedramcore_refresher_next_state <= 2'd0; + netv2_sdram_zqcs_executer_start <= 1'd0; + netv2_sdram_cmd_last <= 1'd0; + netv2_sdram_sequencer_start0 <= 1'd0; + netv2_sdram_cmd_valid <= 1'd0; + litedramcore_refresher_next_state <= litedramcore_refresher_state; + case (litedramcore_refresher_state) + 1'd1: begin + netv2_sdram_cmd_valid <= 1'd1; + if (netv2_sdram_cmd_ready) begin + netv2_sdram_sequencer_start0 <= 1'd1; + litedramcore_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + netv2_sdram_cmd_valid <= 1'd1; + if (netv2_sdram_sequencer_done0) begin + if (netv2_sdram_wants_zqcs) begin + netv2_sdram_zqcs_executer_start <= 1'd1; + litedramcore_refresher_next_state <= 2'd3; + end else begin + netv2_sdram_cmd_valid <= 1'd0; + netv2_sdram_cmd_last <= 1'd1; + litedramcore_refresher_next_state <= 1'd0; + end + end + end + 2'd3: begin + netv2_sdram_cmd_valid <= 1'd1; + if (netv2_sdram_zqcs_executer_done) begin + netv2_sdram_cmd_valid <= 1'd0; + netv2_sdram_cmd_last <= 1'd1; + litedramcore_refresher_next_state <= 1'd0; + end + end + default: begin + if (1'd1) begin + if (netv2_sdram_wants_refresh) begin + litedramcore_refresher_next_state <= 1'd1; + end + end + end + endcase +end +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = netv2_sdram_bankmachine0_req_valid; +assign netv2_sdram_bankmachine0_req_ready = netv2_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = netv2_sdram_bankmachine0_req_we; +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = netv2_sdram_bankmachine0_req_addr; +assign netv2_sdram_bankmachine0_cmd_buffer_sink_valid = netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_valid; +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_ready = netv2_sdram_bankmachine0_cmd_buffer_sink_ready; +assign netv2_sdram_bankmachine0_cmd_buffer_sink_first = netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_first; +assign netv2_sdram_bankmachine0_cmd_buffer_sink_last = netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_last; +assign netv2_sdram_bankmachine0_cmd_buffer_sink_payload_we = netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; +assign netv2_sdram_bankmachine0_cmd_buffer_sink_payload_addr = netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +assign netv2_sdram_bankmachine0_cmd_buffer_source_ready = (netv2_sdram_bankmachine0_req_wdata_ready | netv2_sdram_bankmachine0_req_rdata_valid); +assign netv2_sdram_bankmachine0_req_lock = (netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_valid | netv2_sdram_bankmachine0_cmd_buffer_source_valid); +assign netv2_sdram_bankmachine0_row_hit = (netv2_sdram_bankmachine0_row == netv2_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]); +assign netv2_sdram_bankmachine0_cmd_payload_ba = 1'd0; +always @(*) begin + netv2_sdram_bankmachine0_cmd_payload_a <= 14'd0; + if (netv2_sdram_bankmachine0_row_col_n_addr_sel) begin + netv2_sdram_bankmachine0_cmd_payload_a <= netv2_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]; + end else begin + netv2_sdram_bankmachine0_cmd_payload_a <= ((netv2_sdram_bankmachine0_auto_precharge <<< 4'd10) | {netv2_sdram_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign netv2_sdram_bankmachine0_twtpcon_valid = ((netv2_sdram_bankmachine0_cmd_valid & netv2_sdram_bankmachine0_cmd_ready) & netv2_sdram_bankmachine0_cmd_payload_is_write); +assign netv2_sdram_bankmachine0_trccon_valid = ((netv2_sdram_bankmachine0_cmd_valid & netv2_sdram_bankmachine0_cmd_ready) & netv2_sdram_bankmachine0_row_open); +assign netv2_sdram_bankmachine0_trascon_valid = ((netv2_sdram_bankmachine0_cmd_valid & netv2_sdram_bankmachine0_cmd_ready) & netv2_sdram_bankmachine0_row_open); +always @(*) begin + netv2_sdram_bankmachine0_auto_precharge <= 1'd0; + if ((netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_valid & netv2_sdram_bankmachine0_cmd_buffer_source_valid)) begin + if ((netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != netv2_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin + netv2_sdram_bankmachine0_auto_precharge <= (netv2_sdram_bankmachine0_row_close == 1'd0); + end + end +end +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = netv2_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = netv2_sdram_bankmachine0_cmd_buffer_lookahead_sink_first; +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = netv2_sdram_bankmachine0_cmd_buffer_lookahead_sink_last; +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = netv2_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = netv2_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_valid = netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_first = netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_last = netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = netv2_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = netv2_sdram_bankmachine0_cmd_buffer_lookahead_source_ready; +always @(*) begin + netv2_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (netv2_sdram_bankmachine0_cmd_buffer_lookahead_replace) begin + netv2_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (netv2_sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); + end else begin + netv2_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= netv2_sdram_bankmachine0_cmd_buffer_lookahead_produce; + end +end +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | netv2_sdram_bankmachine0_cmd_buffer_lookahead_replace)); +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_do_read = (netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = netv2_sdram_bankmachine0_cmd_buffer_lookahead_consume; +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = netv2_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (netv2_sdram_bankmachine0_cmd_buffer_lookahead_level != 4'd8); +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (netv2_sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0); +assign netv2_sdram_bankmachine0_cmd_buffer_sink_ready = ((~netv2_sdram_bankmachine0_cmd_buffer_source_valid) | netv2_sdram_bankmachine0_cmd_buffer_source_ready); +always @(*) begin + litedramcore_bankmachine0_next_state <= 4'd0; + netv2_sdram_bankmachine0_cmd_payload_cas <= 1'd0; + netv2_sdram_bankmachine0_cmd_payload_ras <= 1'd0; + netv2_sdram_bankmachine0_cmd_payload_we <= 1'd0; + netv2_sdram_bankmachine0_row_col_n_addr_sel <= 1'd0; + netv2_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0; + netv2_sdram_bankmachine0_cmd_payload_is_read <= 1'd0; + netv2_sdram_bankmachine0_cmd_payload_is_write <= 1'd0; + netv2_sdram_bankmachine0_req_wdata_ready <= 1'd0; + netv2_sdram_bankmachine0_req_rdata_valid <= 1'd0; + netv2_sdram_bankmachine0_refresh_gnt <= 1'd0; + netv2_sdram_bankmachine0_cmd_valid <= 1'd0; + netv2_sdram_bankmachine0_row_open <= 1'd0; + netv2_sdram_bankmachine0_row_close <= 1'd0; + litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((netv2_sdram_bankmachine0_twtpcon_ready & netv2_sdram_bankmachine0_trascon_ready)) begin + netv2_sdram_bankmachine0_cmd_valid <= 1'd1; + if (netv2_sdram_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end + netv2_sdram_bankmachine0_cmd_payload_ras <= 1'd1; + netv2_sdram_bankmachine0_cmd_payload_we <= 1'd1; + netv2_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + netv2_sdram_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + if ((netv2_sdram_bankmachine0_twtpcon_ready & netv2_sdram_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end + netv2_sdram_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + if (netv2_sdram_bankmachine0_trccon_ready) begin + netv2_sdram_bankmachine0_row_col_n_addr_sel <= 1'd1; + netv2_sdram_bankmachine0_row_open <= 1'd1; + netv2_sdram_bankmachine0_cmd_valid <= 1'd1; + netv2_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if (netv2_sdram_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd7; + end + netv2_sdram_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (netv2_sdram_bankmachine0_twtpcon_ready) begin + netv2_sdram_bankmachine0_refresh_gnt <= 1'd1; + end + netv2_sdram_bankmachine0_row_close <= 1'd1; + netv2_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if ((~netv2_sdram_bankmachine0_refresh_req)) begin + litedramcore_bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine0_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine0_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine0_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine0_next_state <= 1'd0; + end + default: begin + if (netv2_sdram_bankmachine0_refresh_req) begin + litedramcore_bankmachine0_next_state <= 3'd4; + end else begin + if (netv2_sdram_bankmachine0_cmd_buffer_source_valid) begin + if (netv2_sdram_bankmachine0_row_opened) begin + if (netv2_sdram_bankmachine0_row_hit) begin + netv2_sdram_bankmachine0_cmd_valid <= 1'd1; + if (netv2_sdram_bankmachine0_cmd_buffer_source_payload_we) begin + netv2_sdram_bankmachine0_req_wdata_ready <= netv2_sdram_bankmachine0_cmd_ready; + netv2_sdram_bankmachine0_cmd_payload_is_write <= 1'd1; + netv2_sdram_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + netv2_sdram_bankmachine0_req_rdata_valid <= netv2_sdram_bankmachine0_cmd_ready; + netv2_sdram_bankmachine0_cmd_payload_is_read <= 1'd1; + end + netv2_sdram_bankmachine0_cmd_payload_cas <= 1'd1; + if ((netv2_sdram_bankmachine0_cmd_ready & netv2_sdram_bankmachine0_auto_precharge)) begin + litedramcore_bankmachine0_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine0_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +end +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = netv2_sdram_bankmachine1_req_valid; +assign netv2_sdram_bankmachine1_req_ready = netv2_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = netv2_sdram_bankmachine1_req_we; +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = netv2_sdram_bankmachine1_req_addr; +assign netv2_sdram_bankmachine1_cmd_buffer_sink_valid = netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_valid; +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_ready = netv2_sdram_bankmachine1_cmd_buffer_sink_ready; +assign netv2_sdram_bankmachine1_cmd_buffer_sink_first = netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_first; +assign netv2_sdram_bankmachine1_cmd_buffer_sink_last = netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_last; +assign netv2_sdram_bankmachine1_cmd_buffer_sink_payload_we = netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; +assign netv2_sdram_bankmachine1_cmd_buffer_sink_payload_addr = netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +assign netv2_sdram_bankmachine1_cmd_buffer_source_ready = (netv2_sdram_bankmachine1_req_wdata_ready | netv2_sdram_bankmachine1_req_rdata_valid); +assign netv2_sdram_bankmachine1_req_lock = (netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_valid | netv2_sdram_bankmachine1_cmd_buffer_source_valid); +assign netv2_sdram_bankmachine1_row_hit = (netv2_sdram_bankmachine1_row == netv2_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]); +assign netv2_sdram_bankmachine1_cmd_payload_ba = 1'd1; +always @(*) begin + netv2_sdram_bankmachine1_cmd_payload_a <= 14'd0; + if (netv2_sdram_bankmachine1_row_col_n_addr_sel) begin + netv2_sdram_bankmachine1_cmd_payload_a <= netv2_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]; + end else begin + netv2_sdram_bankmachine1_cmd_payload_a <= ((netv2_sdram_bankmachine1_auto_precharge <<< 4'd10) | {netv2_sdram_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign netv2_sdram_bankmachine1_twtpcon_valid = ((netv2_sdram_bankmachine1_cmd_valid & netv2_sdram_bankmachine1_cmd_ready) & netv2_sdram_bankmachine1_cmd_payload_is_write); +assign netv2_sdram_bankmachine1_trccon_valid = ((netv2_sdram_bankmachine1_cmd_valid & netv2_sdram_bankmachine1_cmd_ready) & netv2_sdram_bankmachine1_row_open); +assign netv2_sdram_bankmachine1_trascon_valid = ((netv2_sdram_bankmachine1_cmd_valid & netv2_sdram_bankmachine1_cmd_ready) & netv2_sdram_bankmachine1_row_open); +always @(*) begin + netv2_sdram_bankmachine1_auto_precharge <= 1'd0; + if ((netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_valid & netv2_sdram_bankmachine1_cmd_buffer_source_valid)) begin + if ((netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != netv2_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin + netv2_sdram_bankmachine1_auto_precharge <= (netv2_sdram_bankmachine1_row_close == 1'd0); + end + end +end +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = netv2_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = netv2_sdram_bankmachine1_cmd_buffer_lookahead_sink_first; +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = netv2_sdram_bankmachine1_cmd_buffer_lookahead_sink_last; +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = netv2_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = netv2_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_valid = netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_first = netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_last = netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = netv2_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = netv2_sdram_bankmachine1_cmd_buffer_lookahead_source_ready; +always @(*) begin + netv2_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (netv2_sdram_bankmachine1_cmd_buffer_lookahead_replace) begin + netv2_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (netv2_sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); + end else begin + netv2_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= netv2_sdram_bankmachine1_cmd_buffer_lookahead_produce; + end +end +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | netv2_sdram_bankmachine1_cmd_buffer_lookahead_replace)); +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_do_read = (netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = netv2_sdram_bankmachine1_cmd_buffer_lookahead_consume; +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = netv2_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (netv2_sdram_bankmachine1_cmd_buffer_lookahead_level != 4'd8); +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (netv2_sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0); +assign netv2_sdram_bankmachine1_cmd_buffer_sink_ready = ((~netv2_sdram_bankmachine1_cmd_buffer_source_valid) | netv2_sdram_bankmachine1_cmd_buffer_source_ready); +always @(*) begin + litedramcore_bankmachine1_next_state <= 4'd0; + netv2_sdram_bankmachine1_cmd_payload_cas <= 1'd0; + netv2_sdram_bankmachine1_cmd_payload_ras <= 1'd0; + netv2_sdram_bankmachine1_cmd_payload_we <= 1'd0; + netv2_sdram_bankmachine1_row_col_n_addr_sel <= 1'd0; + netv2_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0; + netv2_sdram_bankmachine1_cmd_payload_is_read <= 1'd0; + netv2_sdram_bankmachine1_cmd_payload_is_write <= 1'd0; + netv2_sdram_bankmachine1_req_wdata_ready <= 1'd0; + netv2_sdram_bankmachine1_req_rdata_valid <= 1'd0; + netv2_sdram_bankmachine1_refresh_gnt <= 1'd0; + netv2_sdram_bankmachine1_cmd_valid <= 1'd0; + netv2_sdram_bankmachine1_row_open <= 1'd0; + netv2_sdram_bankmachine1_row_close <= 1'd0; + litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((netv2_sdram_bankmachine1_twtpcon_ready & netv2_sdram_bankmachine1_trascon_ready)) begin + netv2_sdram_bankmachine1_cmd_valid <= 1'd1; + if (netv2_sdram_bankmachine1_cmd_ready) begin + litedramcore_bankmachine1_next_state <= 3'd5; + end + netv2_sdram_bankmachine1_cmd_payload_ras <= 1'd1; + netv2_sdram_bankmachine1_cmd_payload_we <= 1'd1; + netv2_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + netv2_sdram_bankmachine1_row_close <= 1'd1; + end + 2'd2: begin + if ((netv2_sdram_bankmachine1_twtpcon_ready & netv2_sdram_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_next_state <= 3'd5; + end + netv2_sdram_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + if (netv2_sdram_bankmachine1_trccon_ready) begin + netv2_sdram_bankmachine1_row_col_n_addr_sel <= 1'd1; + netv2_sdram_bankmachine1_row_open <= 1'd1; + netv2_sdram_bankmachine1_cmd_valid <= 1'd1; + netv2_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if (netv2_sdram_bankmachine1_cmd_ready) begin + litedramcore_bankmachine1_next_state <= 3'd7; + end + netv2_sdram_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (netv2_sdram_bankmachine1_twtpcon_ready) begin + netv2_sdram_bankmachine1_refresh_gnt <= 1'd1; + end + netv2_sdram_bankmachine1_row_close <= 1'd1; + netv2_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if ((~netv2_sdram_bankmachine1_refresh_req)) begin + litedramcore_bankmachine1_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine1_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine1_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine1_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine1_next_state <= 1'd0; + end + default: begin + if (netv2_sdram_bankmachine1_refresh_req) begin + litedramcore_bankmachine1_next_state <= 3'd4; + end else begin + if (netv2_sdram_bankmachine1_cmd_buffer_source_valid) begin + if (netv2_sdram_bankmachine1_row_opened) begin + if (netv2_sdram_bankmachine1_row_hit) begin + netv2_sdram_bankmachine1_cmd_valid <= 1'd1; + if (netv2_sdram_bankmachine1_cmd_buffer_source_payload_we) begin + netv2_sdram_bankmachine1_req_wdata_ready <= netv2_sdram_bankmachine1_cmd_ready; + netv2_sdram_bankmachine1_cmd_payload_is_write <= 1'd1; + netv2_sdram_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + netv2_sdram_bankmachine1_req_rdata_valid <= netv2_sdram_bankmachine1_cmd_ready; + netv2_sdram_bankmachine1_cmd_payload_is_read <= 1'd1; + end + netv2_sdram_bankmachine1_cmd_payload_cas <= 1'd1; + if ((netv2_sdram_bankmachine1_cmd_ready & netv2_sdram_bankmachine1_auto_precharge)) begin + litedramcore_bankmachine1_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine1_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine1_next_state <= 2'd3; + end + end + end + end + endcase +end +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = netv2_sdram_bankmachine2_req_valid; +assign netv2_sdram_bankmachine2_req_ready = netv2_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = netv2_sdram_bankmachine2_req_we; +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = netv2_sdram_bankmachine2_req_addr; +assign netv2_sdram_bankmachine2_cmd_buffer_sink_valid = netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_valid; +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_ready = netv2_sdram_bankmachine2_cmd_buffer_sink_ready; +assign netv2_sdram_bankmachine2_cmd_buffer_sink_first = netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_first; +assign netv2_sdram_bankmachine2_cmd_buffer_sink_last = netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_last; +assign netv2_sdram_bankmachine2_cmd_buffer_sink_payload_we = netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; +assign netv2_sdram_bankmachine2_cmd_buffer_sink_payload_addr = netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +assign netv2_sdram_bankmachine2_cmd_buffer_source_ready = (netv2_sdram_bankmachine2_req_wdata_ready | netv2_sdram_bankmachine2_req_rdata_valid); +assign netv2_sdram_bankmachine2_req_lock = (netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_valid | netv2_sdram_bankmachine2_cmd_buffer_source_valid); +assign netv2_sdram_bankmachine2_row_hit = (netv2_sdram_bankmachine2_row == netv2_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]); +assign netv2_sdram_bankmachine2_cmd_payload_ba = 2'd2; +always @(*) begin + netv2_sdram_bankmachine2_cmd_payload_a <= 14'd0; + if (netv2_sdram_bankmachine2_row_col_n_addr_sel) begin + netv2_sdram_bankmachine2_cmd_payload_a <= netv2_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]; + end else begin + netv2_sdram_bankmachine2_cmd_payload_a <= ((netv2_sdram_bankmachine2_auto_precharge <<< 4'd10) | {netv2_sdram_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign netv2_sdram_bankmachine2_twtpcon_valid = ((netv2_sdram_bankmachine2_cmd_valid & netv2_sdram_bankmachine2_cmd_ready) & netv2_sdram_bankmachine2_cmd_payload_is_write); +assign netv2_sdram_bankmachine2_trccon_valid = ((netv2_sdram_bankmachine2_cmd_valid & netv2_sdram_bankmachine2_cmd_ready) & netv2_sdram_bankmachine2_row_open); +assign netv2_sdram_bankmachine2_trascon_valid = ((netv2_sdram_bankmachine2_cmd_valid & netv2_sdram_bankmachine2_cmd_ready) & netv2_sdram_bankmachine2_row_open); +always @(*) begin + netv2_sdram_bankmachine2_auto_precharge <= 1'd0; + if ((netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_valid & netv2_sdram_bankmachine2_cmd_buffer_source_valid)) begin + if ((netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != netv2_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin + netv2_sdram_bankmachine2_auto_precharge <= (netv2_sdram_bankmachine2_row_close == 1'd0); + end + end +end +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = netv2_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = netv2_sdram_bankmachine2_cmd_buffer_lookahead_sink_first; +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = netv2_sdram_bankmachine2_cmd_buffer_lookahead_sink_last; +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = netv2_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = netv2_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_valid = netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_first = netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_last = netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = netv2_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = netv2_sdram_bankmachine2_cmd_buffer_lookahead_source_ready; +always @(*) begin + netv2_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (netv2_sdram_bankmachine2_cmd_buffer_lookahead_replace) begin + netv2_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (netv2_sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); + end else begin + netv2_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= netv2_sdram_bankmachine2_cmd_buffer_lookahead_produce; + end +end +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | netv2_sdram_bankmachine2_cmd_buffer_lookahead_replace)); +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_do_read = (netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = netv2_sdram_bankmachine2_cmd_buffer_lookahead_consume; +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = netv2_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (netv2_sdram_bankmachine2_cmd_buffer_lookahead_level != 4'd8); +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (netv2_sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0); +assign netv2_sdram_bankmachine2_cmd_buffer_sink_ready = ((~netv2_sdram_bankmachine2_cmd_buffer_source_valid) | netv2_sdram_bankmachine2_cmd_buffer_source_ready); +always @(*) begin + litedramcore_bankmachine2_next_state <= 4'd0; + netv2_sdram_bankmachine2_cmd_payload_cas <= 1'd0; + netv2_sdram_bankmachine2_cmd_payload_ras <= 1'd0; + netv2_sdram_bankmachine2_cmd_payload_we <= 1'd0; + netv2_sdram_bankmachine2_row_col_n_addr_sel <= 1'd0; + netv2_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0; + netv2_sdram_bankmachine2_cmd_payload_is_read <= 1'd0; + netv2_sdram_bankmachine2_cmd_payload_is_write <= 1'd0; + netv2_sdram_bankmachine2_req_wdata_ready <= 1'd0; + netv2_sdram_bankmachine2_req_rdata_valid <= 1'd0; + netv2_sdram_bankmachine2_refresh_gnt <= 1'd0; + netv2_sdram_bankmachine2_cmd_valid <= 1'd0; + netv2_sdram_bankmachine2_row_open <= 1'd0; + netv2_sdram_bankmachine2_row_close <= 1'd0; + litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((netv2_sdram_bankmachine2_twtpcon_ready & netv2_sdram_bankmachine2_trascon_ready)) begin + netv2_sdram_bankmachine2_cmd_valid <= 1'd1; + if (netv2_sdram_bankmachine2_cmd_ready) begin + litedramcore_bankmachine2_next_state <= 3'd5; + end + netv2_sdram_bankmachine2_cmd_payload_ras <= 1'd1; + netv2_sdram_bankmachine2_cmd_payload_we <= 1'd1; + netv2_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + netv2_sdram_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + if ((netv2_sdram_bankmachine2_twtpcon_ready & netv2_sdram_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_next_state <= 3'd5; + end + netv2_sdram_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + if (netv2_sdram_bankmachine2_trccon_ready) begin + netv2_sdram_bankmachine2_row_col_n_addr_sel <= 1'd1; + netv2_sdram_bankmachine2_row_open <= 1'd1; + netv2_sdram_bankmachine2_cmd_valid <= 1'd1; + netv2_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if (netv2_sdram_bankmachine2_cmd_ready) begin + litedramcore_bankmachine2_next_state <= 3'd7; + end + netv2_sdram_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (netv2_sdram_bankmachine2_twtpcon_ready) begin + netv2_sdram_bankmachine2_refresh_gnt <= 1'd1; + end + netv2_sdram_bankmachine2_row_close <= 1'd1; + netv2_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if ((~netv2_sdram_bankmachine2_refresh_req)) begin + litedramcore_bankmachine2_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine2_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine2_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine2_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine2_next_state <= 1'd0; + end + default: begin + if (netv2_sdram_bankmachine2_refresh_req) begin + litedramcore_bankmachine2_next_state <= 3'd4; + end else begin + if (netv2_sdram_bankmachine2_cmd_buffer_source_valid) begin + if (netv2_sdram_bankmachine2_row_opened) begin + if (netv2_sdram_bankmachine2_row_hit) begin + netv2_sdram_bankmachine2_cmd_valid <= 1'd1; + if (netv2_sdram_bankmachine2_cmd_buffer_source_payload_we) begin + netv2_sdram_bankmachine2_req_wdata_ready <= netv2_sdram_bankmachine2_cmd_ready; + netv2_sdram_bankmachine2_cmd_payload_is_write <= 1'd1; + netv2_sdram_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + netv2_sdram_bankmachine2_req_rdata_valid <= netv2_sdram_bankmachine2_cmd_ready; + netv2_sdram_bankmachine2_cmd_payload_is_read <= 1'd1; + end + netv2_sdram_bankmachine2_cmd_payload_cas <= 1'd1; + if ((netv2_sdram_bankmachine2_cmd_ready & netv2_sdram_bankmachine2_auto_precharge)) begin + litedramcore_bankmachine2_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine2_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine2_next_state <= 2'd3; + end + end + end + end + endcase +end +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = netv2_sdram_bankmachine3_req_valid; +assign netv2_sdram_bankmachine3_req_ready = netv2_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = netv2_sdram_bankmachine3_req_we; +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = netv2_sdram_bankmachine3_req_addr; +assign netv2_sdram_bankmachine3_cmd_buffer_sink_valid = netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_valid; +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_ready = netv2_sdram_bankmachine3_cmd_buffer_sink_ready; +assign netv2_sdram_bankmachine3_cmd_buffer_sink_first = netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_first; +assign netv2_sdram_bankmachine3_cmd_buffer_sink_last = netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_last; +assign netv2_sdram_bankmachine3_cmd_buffer_sink_payload_we = netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; +assign netv2_sdram_bankmachine3_cmd_buffer_sink_payload_addr = netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +assign netv2_sdram_bankmachine3_cmd_buffer_source_ready = (netv2_sdram_bankmachine3_req_wdata_ready | netv2_sdram_bankmachine3_req_rdata_valid); +assign netv2_sdram_bankmachine3_req_lock = (netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_valid | netv2_sdram_bankmachine3_cmd_buffer_source_valid); +assign netv2_sdram_bankmachine3_row_hit = (netv2_sdram_bankmachine3_row == netv2_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]); +assign netv2_sdram_bankmachine3_cmd_payload_ba = 2'd3; +always @(*) begin + netv2_sdram_bankmachine3_cmd_payload_a <= 14'd0; + if (netv2_sdram_bankmachine3_row_col_n_addr_sel) begin + netv2_sdram_bankmachine3_cmd_payload_a <= netv2_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]; + end else begin + netv2_sdram_bankmachine3_cmd_payload_a <= ((netv2_sdram_bankmachine3_auto_precharge <<< 4'd10) | {netv2_sdram_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign netv2_sdram_bankmachine3_twtpcon_valid = ((netv2_sdram_bankmachine3_cmd_valid & netv2_sdram_bankmachine3_cmd_ready) & netv2_sdram_bankmachine3_cmd_payload_is_write); +assign netv2_sdram_bankmachine3_trccon_valid = ((netv2_sdram_bankmachine3_cmd_valid & netv2_sdram_bankmachine3_cmd_ready) & netv2_sdram_bankmachine3_row_open); +assign netv2_sdram_bankmachine3_trascon_valid = ((netv2_sdram_bankmachine3_cmd_valid & netv2_sdram_bankmachine3_cmd_ready) & netv2_sdram_bankmachine3_row_open); +always @(*) begin + netv2_sdram_bankmachine3_auto_precharge <= 1'd0; + if ((netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_valid & netv2_sdram_bankmachine3_cmd_buffer_source_valid)) begin + if ((netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != netv2_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin + netv2_sdram_bankmachine3_auto_precharge <= (netv2_sdram_bankmachine3_row_close == 1'd0); + end + end +end +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = netv2_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = netv2_sdram_bankmachine3_cmd_buffer_lookahead_sink_first; +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = netv2_sdram_bankmachine3_cmd_buffer_lookahead_sink_last; +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = netv2_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = netv2_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_valid = netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_first = netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_last = netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = netv2_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = netv2_sdram_bankmachine3_cmd_buffer_lookahead_source_ready; +always @(*) begin + netv2_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (netv2_sdram_bankmachine3_cmd_buffer_lookahead_replace) begin + netv2_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (netv2_sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); + end else begin + netv2_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= netv2_sdram_bankmachine3_cmd_buffer_lookahead_produce; + end +end +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | netv2_sdram_bankmachine3_cmd_buffer_lookahead_replace)); +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_do_read = (netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = netv2_sdram_bankmachine3_cmd_buffer_lookahead_consume; +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = netv2_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (netv2_sdram_bankmachine3_cmd_buffer_lookahead_level != 4'd8); +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (netv2_sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0); +assign netv2_sdram_bankmachine3_cmd_buffer_sink_ready = ((~netv2_sdram_bankmachine3_cmd_buffer_source_valid) | netv2_sdram_bankmachine3_cmd_buffer_source_ready); +always @(*) begin + litedramcore_bankmachine3_next_state <= 4'd0; + netv2_sdram_bankmachine3_cmd_payload_cas <= 1'd0; + netv2_sdram_bankmachine3_cmd_payload_ras <= 1'd0; + netv2_sdram_bankmachine3_cmd_payload_we <= 1'd0; + netv2_sdram_bankmachine3_row_col_n_addr_sel <= 1'd0; + netv2_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0; + netv2_sdram_bankmachine3_cmd_payload_is_read <= 1'd0; + netv2_sdram_bankmachine3_cmd_payload_is_write <= 1'd0; + netv2_sdram_bankmachine3_req_wdata_ready <= 1'd0; + netv2_sdram_bankmachine3_req_rdata_valid <= 1'd0; + netv2_sdram_bankmachine3_refresh_gnt <= 1'd0; + netv2_sdram_bankmachine3_cmd_valid <= 1'd0; + netv2_sdram_bankmachine3_row_open <= 1'd0; + netv2_sdram_bankmachine3_row_close <= 1'd0; + litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((netv2_sdram_bankmachine3_twtpcon_ready & netv2_sdram_bankmachine3_trascon_ready)) begin + netv2_sdram_bankmachine3_cmd_valid <= 1'd1; + if (netv2_sdram_bankmachine3_cmd_ready) begin + litedramcore_bankmachine3_next_state <= 3'd5; + end + netv2_sdram_bankmachine3_cmd_payload_ras <= 1'd1; + netv2_sdram_bankmachine3_cmd_payload_we <= 1'd1; + netv2_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + netv2_sdram_bankmachine3_row_close <= 1'd1; + end + 2'd2: begin + if ((netv2_sdram_bankmachine3_twtpcon_ready & netv2_sdram_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_next_state <= 3'd5; + end + netv2_sdram_bankmachine3_row_close <= 1'd1; + end + 2'd3: begin + if (netv2_sdram_bankmachine3_trccon_ready) begin + netv2_sdram_bankmachine3_row_col_n_addr_sel <= 1'd1; + netv2_sdram_bankmachine3_row_open <= 1'd1; + netv2_sdram_bankmachine3_cmd_valid <= 1'd1; + netv2_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if (netv2_sdram_bankmachine3_cmd_ready) begin + litedramcore_bankmachine3_next_state <= 3'd7; + end + netv2_sdram_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (netv2_sdram_bankmachine3_twtpcon_ready) begin + netv2_sdram_bankmachine3_refresh_gnt <= 1'd1; + end + netv2_sdram_bankmachine3_row_close <= 1'd1; + netv2_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if ((~netv2_sdram_bankmachine3_refresh_req)) begin + litedramcore_bankmachine3_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine3_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine3_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine3_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine3_next_state <= 1'd0; + end + default: begin + if (netv2_sdram_bankmachine3_refresh_req) begin + litedramcore_bankmachine3_next_state <= 3'd4; + end else begin + if (netv2_sdram_bankmachine3_cmd_buffer_source_valid) begin + if (netv2_sdram_bankmachine3_row_opened) begin + if (netv2_sdram_bankmachine3_row_hit) begin + netv2_sdram_bankmachine3_cmd_valid <= 1'd1; + if (netv2_sdram_bankmachine3_cmd_buffer_source_payload_we) begin + netv2_sdram_bankmachine3_req_wdata_ready <= netv2_sdram_bankmachine3_cmd_ready; + netv2_sdram_bankmachine3_cmd_payload_is_write <= 1'd1; + netv2_sdram_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + netv2_sdram_bankmachine3_req_rdata_valid <= netv2_sdram_bankmachine3_cmd_ready; + netv2_sdram_bankmachine3_cmd_payload_is_read <= 1'd1; + end + netv2_sdram_bankmachine3_cmd_payload_cas <= 1'd1; + if ((netv2_sdram_bankmachine3_cmd_ready & netv2_sdram_bankmachine3_auto_precharge)) begin + litedramcore_bankmachine3_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine3_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine3_next_state <= 2'd3; + end + end + end + end + endcase +end +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid = netv2_sdram_bankmachine4_req_valid; +assign netv2_sdram_bankmachine4_req_ready = netv2_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready; +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we = netv2_sdram_bankmachine4_req_we; +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = netv2_sdram_bankmachine4_req_addr; +assign netv2_sdram_bankmachine4_cmd_buffer_sink_valid = netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_valid; +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_ready = netv2_sdram_bankmachine4_cmd_buffer_sink_ready; +assign netv2_sdram_bankmachine4_cmd_buffer_sink_first = netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_first; +assign netv2_sdram_bankmachine4_cmd_buffer_sink_last = netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_last; +assign netv2_sdram_bankmachine4_cmd_buffer_sink_payload_we = netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we; +assign netv2_sdram_bankmachine4_cmd_buffer_sink_payload_addr = netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +assign netv2_sdram_bankmachine4_cmd_buffer_source_ready = (netv2_sdram_bankmachine4_req_wdata_ready | netv2_sdram_bankmachine4_req_rdata_valid); +assign netv2_sdram_bankmachine4_req_lock = (netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_valid | netv2_sdram_bankmachine4_cmd_buffer_source_valid); +assign netv2_sdram_bankmachine4_row_hit = (netv2_sdram_bankmachine4_row == netv2_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]); +assign netv2_sdram_bankmachine4_cmd_payload_ba = 3'd4; +always @(*) begin + netv2_sdram_bankmachine4_cmd_payload_a <= 14'd0; + if (netv2_sdram_bankmachine4_row_col_n_addr_sel) begin + netv2_sdram_bankmachine4_cmd_payload_a <= netv2_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]; + end else begin + netv2_sdram_bankmachine4_cmd_payload_a <= ((netv2_sdram_bankmachine4_auto_precharge <<< 4'd10) | {netv2_sdram_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign netv2_sdram_bankmachine4_twtpcon_valid = ((netv2_sdram_bankmachine4_cmd_valid & netv2_sdram_bankmachine4_cmd_ready) & netv2_sdram_bankmachine4_cmd_payload_is_write); +assign netv2_sdram_bankmachine4_trccon_valid = ((netv2_sdram_bankmachine4_cmd_valid & netv2_sdram_bankmachine4_cmd_ready) & netv2_sdram_bankmachine4_row_open); +assign netv2_sdram_bankmachine4_trascon_valid = ((netv2_sdram_bankmachine4_cmd_valid & netv2_sdram_bankmachine4_cmd_ready) & netv2_sdram_bankmachine4_row_open); +always @(*) begin + netv2_sdram_bankmachine4_auto_precharge <= 1'd0; + if ((netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_valid & netv2_sdram_bankmachine4_cmd_buffer_source_valid)) begin + if ((netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != netv2_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin + netv2_sdram_bankmachine4_auto_precharge <= (netv2_sdram_bankmachine4_row_close == 1'd0); + end + end +end +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last, netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first, netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready = netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = netv2_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid; +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first = netv2_sdram_bankmachine4_cmd_buffer_lookahead_sink_first; +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last = netv2_sdram_bankmachine4_cmd_buffer_lookahead_sink_last; +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = netv2_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = netv2_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_valid = netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_first = netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_last = netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we = netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr = netv2_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = netv2_sdram_bankmachine4_cmd_buffer_lookahead_source_ready; +always @(*) begin + netv2_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (netv2_sdram_bankmachine4_cmd_buffer_lookahead_replace) begin + netv2_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (netv2_sdram_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); + end else begin + netv2_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= netv2_sdram_bankmachine4_cmd_buffer_lookahead_produce; + end +end +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we = (netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | netv2_sdram_bankmachine4_cmd_buffer_lookahead_replace)); +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_do_read = (netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr = netv2_sdram_bankmachine4_cmd_buffer_lookahead_consume; +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = netv2_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (netv2_sdram_bankmachine4_cmd_buffer_lookahead_level != 4'd8); +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (netv2_sdram_bankmachine4_cmd_buffer_lookahead_level != 1'd0); +assign netv2_sdram_bankmachine4_cmd_buffer_sink_ready = ((~netv2_sdram_bankmachine4_cmd_buffer_source_valid) | netv2_sdram_bankmachine4_cmd_buffer_source_ready); +always @(*) begin + litedramcore_bankmachine4_next_state <= 4'd0; + netv2_sdram_bankmachine4_cmd_payload_cas <= 1'd0; + netv2_sdram_bankmachine4_cmd_payload_ras <= 1'd0; + netv2_sdram_bankmachine4_cmd_payload_we <= 1'd0; + netv2_sdram_bankmachine4_row_col_n_addr_sel <= 1'd0; + netv2_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd0; + netv2_sdram_bankmachine4_cmd_payload_is_read <= 1'd0; + netv2_sdram_bankmachine4_cmd_payload_is_write <= 1'd0; + netv2_sdram_bankmachine4_req_wdata_ready <= 1'd0; + netv2_sdram_bankmachine4_req_rdata_valid <= 1'd0; + netv2_sdram_bankmachine4_refresh_gnt <= 1'd0; + netv2_sdram_bankmachine4_cmd_valid <= 1'd0; + netv2_sdram_bankmachine4_row_open <= 1'd0; + netv2_sdram_bankmachine4_row_close <= 1'd0; + litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((netv2_sdram_bankmachine4_twtpcon_ready & netv2_sdram_bankmachine4_trascon_ready)) begin + netv2_sdram_bankmachine4_cmd_valid <= 1'd1; + if (netv2_sdram_bankmachine4_cmd_ready) begin + litedramcore_bankmachine4_next_state <= 3'd5; + end + netv2_sdram_bankmachine4_cmd_payload_ras <= 1'd1; + netv2_sdram_bankmachine4_cmd_payload_we <= 1'd1; + netv2_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + netv2_sdram_bankmachine4_row_close <= 1'd1; + end + 2'd2: begin + if ((netv2_sdram_bankmachine4_twtpcon_ready & netv2_sdram_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_next_state <= 3'd5; + end + netv2_sdram_bankmachine4_row_close <= 1'd1; + end + 2'd3: begin + if (netv2_sdram_bankmachine4_trccon_ready) begin + netv2_sdram_bankmachine4_row_col_n_addr_sel <= 1'd1; + netv2_sdram_bankmachine4_row_open <= 1'd1; + netv2_sdram_bankmachine4_cmd_valid <= 1'd1; + netv2_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if (netv2_sdram_bankmachine4_cmd_ready) begin + litedramcore_bankmachine4_next_state <= 3'd7; + end + netv2_sdram_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (netv2_sdram_bankmachine4_twtpcon_ready) begin + netv2_sdram_bankmachine4_refresh_gnt <= 1'd1; + end + netv2_sdram_bankmachine4_row_close <= 1'd1; + netv2_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if ((~netv2_sdram_bankmachine4_refresh_req)) begin + litedramcore_bankmachine4_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine4_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine4_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine4_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine4_next_state <= 1'd0; + end + default: begin + if (netv2_sdram_bankmachine4_refresh_req) begin + litedramcore_bankmachine4_next_state <= 3'd4; + end else begin + if (netv2_sdram_bankmachine4_cmd_buffer_source_valid) begin + if (netv2_sdram_bankmachine4_row_opened) begin + if (netv2_sdram_bankmachine4_row_hit) begin + netv2_sdram_bankmachine4_cmd_valid <= 1'd1; + if (netv2_sdram_bankmachine4_cmd_buffer_source_payload_we) begin + netv2_sdram_bankmachine4_req_wdata_ready <= netv2_sdram_bankmachine4_cmd_ready; + netv2_sdram_bankmachine4_cmd_payload_is_write <= 1'd1; + netv2_sdram_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + netv2_sdram_bankmachine4_req_rdata_valid <= netv2_sdram_bankmachine4_cmd_ready; + netv2_sdram_bankmachine4_cmd_payload_is_read <= 1'd1; + end + netv2_sdram_bankmachine4_cmd_payload_cas <= 1'd1; + if ((netv2_sdram_bankmachine4_cmd_ready & netv2_sdram_bankmachine4_auto_precharge)) begin + litedramcore_bankmachine4_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine4_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine4_next_state <= 2'd3; + end + end + end + end + endcase +end +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid = netv2_sdram_bankmachine5_req_valid; +assign netv2_sdram_bankmachine5_req_ready = netv2_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready; +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we = netv2_sdram_bankmachine5_req_we; +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = netv2_sdram_bankmachine5_req_addr; +assign netv2_sdram_bankmachine5_cmd_buffer_sink_valid = netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_valid; +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_ready = netv2_sdram_bankmachine5_cmd_buffer_sink_ready; +assign netv2_sdram_bankmachine5_cmd_buffer_sink_first = netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_first; +assign netv2_sdram_bankmachine5_cmd_buffer_sink_last = netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_last; +assign netv2_sdram_bankmachine5_cmd_buffer_sink_payload_we = netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we; +assign netv2_sdram_bankmachine5_cmd_buffer_sink_payload_addr = netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +assign netv2_sdram_bankmachine5_cmd_buffer_source_ready = (netv2_sdram_bankmachine5_req_wdata_ready | netv2_sdram_bankmachine5_req_rdata_valid); +assign netv2_sdram_bankmachine5_req_lock = (netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_valid | netv2_sdram_bankmachine5_cmd_buffer_source_valid); +assign netv2_sdram_bankmachine5_row_hit = (netv2_sdram_bankmachine5_row == netv2_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]); +assign netv2_sdram_bankmachine5_cmd_payload_ba = 3'd5; +always @(*) begin + netv2_sdram_bankmachine5_cmd_payload_a <= 14'd0; + if (netv2_sdram_bankmachine5_row_col_n_addr_sel) begin + netv2_sdram_bankmachine5_cmd_payload_a <= netv2_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]; + end else begin + netv2_sdram_bankmachine5_cmd_payload_a <= ((netv2_sdram_bankmachine5_auto_precharge <<< 4'd10) | {netv2_sdram_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign netv2_sdram_bankmachine5_twtpcon_valid = ((netv2_sdram_bankmachine5_cmd_valid & netv2_sdram_bankmachine5_cmd_ready) & netv2_sdram_bankmachine5_cmd_payload_is_write); +assign netv2_sdram_bankmachine5_trccon_valid = ((netv2_sdram_bankmachine5_cmd_valid & netv2_sdram_bankmachine5_cmd_ready) & netv2_sdram_bankmachine5_row_open); +assign netv2_sdram_bankmachine5_trascon_valid = ((netv2_sdram_bankmachine5_cmd_valid & netv2_sdram_bankmachine5_cmd_ready) & netv2_sdram_bankmachine5_row_open); +always @(*) begin + netv2_sdram_bankmachine5_auto_precharge <= 1'd0; + if ((netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_valid & netv2_sdram_bankmachine5_cmd_buffer_source_valid)) begin + if ((netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != netv2_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin + netv2_sdram_bankmachine5_auto_precharge <= (netv2_sdram_bankmachine5_row_close == 1'd0); + end + end +end +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last, netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first, netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready = netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = netv2_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid; +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first = netv2_sdram_bankmachine5_cmd_buffer_lookahead_sink_first; +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last = netv2_sdram_bankmachine5_cmd_buffer_lookahead_sink_last; +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = netv2_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = netv2_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_valid = netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_first = netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_last = netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we = netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr = netv2_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = netv2_sdram_bankmachine5_cmd_buffer_lookahead_source_ready; +always @(*) begin + netv2_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (netv2_sdram_bankmachine5_cmd_buffer_lookahead_replace) begin + netv2_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (netv2_sdram_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); + end else begin + netv2_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= netv2_sdram_bankmachine5_cmd_buffer_lookahead_produce; + end +end +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we = (netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | netv2_sdram_bankmachine5_cmd_buffer_lookahead_replace)); +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_do_read = (netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr = netv2_sdram_bankmachine5_cmd_buffer_lookahead_consume; +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = netv2_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (netv2_sdram_bankmachine5_cmd_buffer_lookahead_level != 4'd8); +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (netv2_sdram_bankmachine5_cmd_buffer_lookahead_level != 1'd0); +assign netv2_sdram_bankmachine5_cmd_buffer_sink_ready = ((~netv2_sdram_bankmachine5_cmd_buffer_source_valid) | netv2_sdram_bankmachine5_cmd_buffer_source_ready); +always @(*) begin + litedramcore_bankmachine5_next_state <= 4'd0; + netv2_sdram_bankmachine5_cmd_payload_cas <= 1'd0; + netv2_sdram_bankmachine5_cmd_payload_ras <= 1'd0; + netv2_sdram_bankmachine5_cmd_payload_we <= 1'd0; + netv2_sdram_bankmachine5_row_col_n_addr_sel <= 1'd0; + netv2_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd0; + netv2_sdram_bankmachine5_cmd_payload_is_read <= 1'd0; + netv2_sdram_bankmachine5_cmd_payload_is_write <= 1'd0; + netv2_sdram_bankmachine5_req_wdata_ready <= 1'd0; + netv2_sdram_bankmachine5_req_rdata_valid <= 1'd0; + netv2_sdram_bankmachine5_refresh_gnt <= 1'd0; + netv2_sdram_bankmachine5_cmd_valid <= 1'd0; + netv2_sdram_bankmachine5_row_open <= 1'd0; + netv2_sdram_bankmachine5_row_close <= 1'd0; + litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((netv2_sdram_bankmachine5_twtpcon_ready & netv2_sdram_bankmachine5_trascon_ready)) begin + netv2_sdram_bankmachine5_cmd_valid <= 1'd1; + if (netv2_sdram_bankmachine5_cmd_ready) begin + litedramcore_bankmachine5_next_state <= 3'd5; + end + netv2_sdram_bankmachine5_cmd_payload_ras <= 1'd1; + netv2_sdram_bankmachine5_cmd_payload_we <= 1'd1; + netv2_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + netv2_sdram_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + if ((netv2_sdram_bankmachine5_twtpcon_ready & netv2_sdram_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_next_state <= 3'd5; + end + netv2_sdram_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + if (netv2_sdram_bankmachine5_trccon_ready) begin + netv2_sdram_bankmachine5_row_col_n_addr_sel <= 1'd1; + netv2_sdram_bankmachine5_row_open <= 1'd1; + netv2_sdram_bankmachine5_cmd_valid <= 1'd1; + netv2_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; + if (netv2_sdram_bankmachine5_cmd_ready) begin + litedramcore_bankmachine5_next_state <= 3'd7; + end + netv2_sdram_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (netv2_sdram_bankmachine5_twtpcon_ready) begin + netv2_sdram_bankmachine5_refresh_gnt <= 1'd1; + end + netv2_sdram_bankmachine5_row_close <= 1'd1; + netv2_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; + if ((~netv2_sdram_bankmachine5_refresh_req)) begin + litedramcore_bankmachine5_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine5_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine5_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine5_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine5_next_state <= 1'd0; + end + default: begin + if (netv2_sdram_bankmachine5_refresh_req) begin + litedramcore_bankmachine5_next_state <= 3'd4; + end else begin + if (netv2_sdram_bankmachine5_cmd_buffer_source_valid) begin + if (netv2_sdram_bankmachine5_row_opened) begin + if (netv2_sdram_bankmachine5_row_hit) begin + netv2_sdram_bankmachine5_cmd_valid <= 1'd1; + if (netv2_sdram_bankmachine5_cmd_buffer_source_payload_we) begin + netv2_sdram_bankmachine5_req_wdata_ready <= netv2_sdram_bankmachine5_cmd_ready; + netv2_sdram_bankmachine5_cmd_payload_is_write <= 1'd1; + netv2_sdram_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + netv2_sdram_bankmachine5_req_rdata_valid <= netv2_sdram_bankmachine5_cmd_ready; + netv2_sdram_bankmachine5_cmd_payload_is_read <= 1'd1; + end + netv2_sdram_bankmachine5_cmd_payload_cas <= 1'd1; + if ((netv2_sdram_bankmachine5_cmd_ready & netv2_sdram_bankmachine5_auto_precharge)) begin + litedramcore_bankmachine5_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine5_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine5_next_state <= 2'd3; + end + end + end + end + endcase +end +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid = netv2_sdram_bankmachine6_req_valid; +assign netv2_sdram_bankmachine6_req_ready = netv2_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready; +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we = netv2_sdram_bankmachine6_req_we; +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = netv2_sdram_bankmachine6_req_addr; +assign netv2_sdram_bankmachine6_cmd_buffer_sink_valid = netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_valid; +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_ready = netv2_sdram_bankmachine6_cmd_buffer_sink_ready; +assign netv2_sdram_bankmachine6_cmd_buffer_sink_first = netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_first; +assign netv2_sdram_bankmachine6_cmd_buffer_sink_last = netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_last; +assign netv2_sdram_bankmachine6_cmd_buffer_sink_payload_we = netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we; +assign netv2_sdram_bankmachine6_cmd_buffer_sink_payload_addr = netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +assign netv2_sdram_bankmachine6_cmd_buffer_source_ready = (netv2_sdram_bankmachine6_req_wdata_ready | netv2_sdram_bankmachine6_req_rdata_valid); +assign netv2_sdram_bankmachine6_req_lock = (netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_valid | netv2_sdram_bankmachine6_cmd_buffer_source_valid); +assign netv2_sdram_bankmachine6_row_hit = (netv2_sdram_bankmachine6_row == netv2_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]); +assign netv2_sdram_bankmachine6_cmd_payload_ba = 3'd6; +always @(*) begin + netv2_sdram_bankmachine6_cmd_payload_a <= 14'd0; + if (netv2_sdram_bankmachine6_row_col_n_addr_sel) begin + netv2_sdram_bankmachine6_cmd_payload_a <= netv2_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]; + end else begin + netv2_sdram_bankmachine6_cmd_payload_a <= ((netv2_sdram_bankmachine6_auto_precharge <<< 4'd10) | {netv2_sdram_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign netv2_sdram_bankmachine6_twtpcon_valid = ((netv2_sdram_bankmachine6_cmd_valid & netv2_sdram_bankmachine6_cmd_ready) & netv2_sdram_bankmachine6_cmd_payload_is_write); +assign netv2_sdram_bankmachine6_trccon_valid = ((netv2_sdram_bankmachine6_cmd_valid & netv2_sdram_bankmachine6_cmd_ready) & netv2_sdram_bankmachine6_row_open); +assign netv2_sdram_bankmachine6_trascon_valid = ((netv2_sdram_bankmachine6_cmd_valid & netv2_sdram_bankmachine6_cmd_ready) & netv2_sdram_bankmachine6_row_open); +always @(*) begin + netv2_sdram_bankmachine6_auto_precharge <= 1'd0; + if ((netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_valid & netv2_sdram_bankmachine6_cmd_buffer_source_valid)) begin + if ((netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != netv2_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin + netv2_sdram_bankmachine6_auto_precharge <= (netv2_sdram_bankmachine6_row_close == 1'd0); + end + end +end +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last, netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first, netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready = netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = netv2_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid; +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first = netv2_sdram_bankmachine6_cmd_buffer_lookahead_sink_first; +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last = netv2_sdram_bankmachine6_cmd_buffer_lookahead_sink_last; +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = netv2_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = netv2_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_valid = netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_first = netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_last = netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we = netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr = netv2_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = netv2_sdram_bankmachine6_cmd_buffer_lookahead_source_ready; +always @(*) begin + netv2_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (netv2_sdram_bankmachine6_cmd_buffer_lookahead_replace) begin + netv2_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (netv2_sdram_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); + end else begin + netv2_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= netv2_sdram_bankmachine6_cmd_buffer_lookahead_produce; + end +end +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we = (netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | netv2_sdram_bankmachine6_cmd_buffer_lookahead_replace)); +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_do_read = (netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr = netv2_sdram_bankmachine6_cmd_buffer_lookahead_consume; +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = netv2_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (netv2_sdram_bankmachine6_cmd_buffer_lookahead_level != 4'd8); +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (netv2_sdram_bankmachine6_cmd_buffer_lookahead_level != 1'd0); +assign netv2_sdram_bankmachine6_cmd_buffer_sink_ready = ((~netv2_sdram_bankmachine6_cmd_buffer_source_valid) | netv2_sdram_bankmachine6_cmd_buffer_source_ready); +always @(*) begin + litedramcore_bankmachine6_next_state <= 4'd0; + netv2_sdram_bankmachine6_cmd_payload_cas <= 1'd0; + netv2_sdram_bankmachine6_cmd_payload_ras <= 1'd0; + netv2_sdram_bankmachine6_cmd_payload_we <= 1'd0; + netv2_sdram_bankmachine6_row_col_n_addr_sel <= 1'd0; + netv2_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd0; + netv2_sdram_bankmachine6_cmd_payload_is_read <= 1'd0; + netv2_sdram_bankmachine6_cmd_payload_is_write <= 1'd0; + netv2_sdram_bankmachine6_req_wdata_ready <= 1'd0; + netv2_sdram_bankmachine6_req_rdata_valid <= 1'd0; + netv2_sdram_bankmachine6_refresh_gnt <= 1'd0; + netv2_sdram_bankmachine6_cmd_valid <= 1'd0; + netv2_sdram_bankmachine6_row_open <= 1'd0; + netv2_sdram_bankmachine6_row_close <= 1'd0; + litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((netv2_sdram_bankmachine6_twtpcon_ready & netv2_sdram_bankmachine6_trascon_ready)) begin + netv2_sdram_bankmachine6_cmd_valid <= 1'd1; + if (netv2_sdram_bankmachine6_cmd_ready) begin + litedramcore_bankmachine6_next_state <= 3'd5; + end + netv2_sdram_bankmachine6_cmd_payload_ras <= 1'd1; + netv2_sdram_bankmachine6_cmd_payload_we <= 1'd1; + netv2_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + netv2_sdram_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + if ((netv2_sdram_bankmachine6_twtpcon_ready & netv2_sdram_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_next_state <= 3'd5; + end + netv2_sdram_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + if (netv2_sdram_bankmachine6_trccon_ready) begin + netv2_sdram_bankmachine6_row_col_n_addr_sel <= 1'd1; + netv2_sdram_bankmachine6_row_open <= 1'd1; + netv2_sdram_bankmachine6_cmd_valid <= 1'd1; + netv2_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if (netv2_sdram_bankmachine6_cmd_ready) begin + litedramcore_bankmachine6_next_state <= 3'd7; + end + netv2_sdram_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (netv2_sdram_bankmachine6_twtpcon_ready) begin + netv2_sdram_bankmachine6_refresh_gnt <= 1'd1; + end + netv2_sdram_bankmachine6_row_close <= 1'd1; + netv2_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if ((~netv2_sdram_bankmachine6_refresh_req)) begin + litedramcore_bankmachine6_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine6_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine6_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine6_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine6_next_state <= 1'd0; + end + default: begin + if (netv2_sdram_bankmachine6_refresh_req) begin + litedramcore_bankmachine6_next_state <= 3'd4; + end else begin + if (netv2_sdram_bankmachine6_cmd_buffer_source_valid) begin + if (netv2_sdram_bankmachine6_row_opened) begin + if (netv2_sdram_bankmachine6_row_hit) begin + netv2_sdram_bankmachine6_cmd_valid <= 1'd1; + if (netv2_sdram_bankmachine6_cmd_buffer_source_payload_we) begin + netv2_sdram_bankmachine6_req_wdata_ready <= netv2_sdram_bankmachine6_cmd_ready; + netv2_sdram_bankmachine6_cmd_payload_is_write <= 1'd1; + netv2_sdram_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + netv2_sdram_bankmachine6_req_rdata_valid <= netv2_sdram_bankmachine6_cmd_ready; + netv2_sdram_bankmachine6_cmd_payload_is_read <= 1'd1; + end + netv2_sdram_bankmachine6_cmd_payload_cas <= 1'd1; + if ((netv2_sdram_bankmachine6_cmd_ready & netv2_sdram_bankmachine6_auto_precharge)) begin + litedramcore_bankmachine6_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine6_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine6_next_state <= 2'd3; + end + end + end + end + endcase +end +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid = netv2_sdram_bankmachine7_req_valid; +assign netv2_sdram_bankmachine7_req_ready = netv2_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready; +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we = netv2_sdram_bankmachine7_req_we; +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = netv2_sdram_bankmachine7_req_addr; +assign netv2_sdram_bankmachine7_cmd_buffer_sink_valid = netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_valid; +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_ready = netv2_sdram_bankmachine7_cmd_buffer_sink_ready; +assign netv2_sdram_bankmachine7_cmd_buffer_sink_first = netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_first; +assign netv2_sdram_bankmachine7_cmd_buffer_sink_last = netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_last; +assign netv2_sdram_bankmachine7_cmd_buffer_sink_payload_we = netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we; +assign netv2_sdram_bankmachine7_cmd_buffer_sink_payload_addr = netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +assign netv2_sdram_bankmachine7_cmd_buffer_source_ready = (netv2_sdram_bankmachine7_req_wdata_ready | netv2_sdram_bankmachine7_req_rdata_valid); +assign netv2_sdram_bankmachine7_req_lock = (netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_valid | netv2_sdram_bankmachine7_cmd_buffer_source_valid); +assign netv2_sdram_bankmachine7_row_hit = (netv2_sdram_bankmachine7_row == netv2_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]); +assign netv2_sdram_bankmachine7_cmd_payload_ba = 3'd7; +always @(*) begin + netv2_sdram_bankmachine7_cmd_payload_a <= 14'd0; + if (netv2_sdram_bankmachine7_row_col_n_addr_sel) begin + netv2_sdram_bankmachine7_cmd_payload_a <= netv2_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]; + end else begin + netv2_sdram_bankmachine7_cmd_payload_a <= ((netv2_sdram_bankmachine7_auto_precharge <<< 4'd10) | {netv2_sdram_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign netv2_sdram_bankmachine7_twtpcon_valid = ((netv2_sdram_bankmachine7_cmd_valid & netv2_sdram_bankmachine7_cmd_ready) & netv2_sdram_bankmachine7_cmd_payload_is_write); +assign netv2_sdram_bankmachine7_trccon_valid = ((netv2_sdram_bankmachine7_cmd_valid & netv2_sdram_bankmachine7_cmd_ready) & netv2_sdram_bankmachine7_row_open); +assign netv2_sdram_bankmachine7_trascon_valid = ((netv2_sdram_bankmachine7_cmd_valid & netv2_sdram_bankmachine7_cmd_ready) & netv2_sdram_bankmachine7_row_open); +always @(*) begin + netv2_sdram_bankmachine7_auto_precharge <= 1'd0; + if ((netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_valid & netv2_sdram_bankmachine7_cmd_buffer_source_valid)) begin + if ((netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != netv2_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin + netv2_sdram_bankmachine7_auto_precharge <= (netv2_sdram_bankmachine7_row_close == 1'd0); + end + end +end +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last, netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first, netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready = netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = netv2_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid; +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first = netv2_sdram_bankmachine7_cmd_buffer_lookahead_sink_first; +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last = netv2_sdram_bankmachine7_cmd_buffer_lookahead_sink_last; +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = netv2_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = netv2_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_valid = netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_first = netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_last = netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we = netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr = netv2_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = netv2_sdram_bankmachine7_cmd_buffer_lookahead_source_ready; +always @(*) begin + netv2_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (netv2_sdram_bankmachine7_cmd_buffer_lookahead_replace) begin + netv2_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (netv2_sdram_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); + end else begin + netv2_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= netv2_sdram_bankmachine7_cmd_buffer_lookahead_produce; + end +end +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we = (netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | netv2_sdram_bankmachine7_cmd_buffer_lookahead_replace)); +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_do_read = (netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr = netv2_sdram_bankmachine7_cmd_buffer_lookahead_consume; +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = netv2_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (netv2_sdram_bankmachine7_cmd_buffer_lookahead_level != 4'd8); +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (netv2_sdram_bankmachine7_cmd_buffer_lookahead_level != 1'd0); +assign netv2_sdram_bankmachine7_cmd_buffer_sink_ready = ((~netv2_sdram_bankmachine7_cmd_buffer_source_valid) | netv2_sdram_bankmachine7_cmd_buffer_source_ready); +always @(*) begin + litedramcore_bankmachine7_next_state <= 4'd0; + netv2_sdram_bankmachine7_cmd_payload_cas <= 1'd0; + netv2_sdram_bankmachine7_cmd_payload_ras <= 1'd0; + netv2_sdram_bankmachine7_cmd_payload_we <= 1'd0; + netv2_sdram_bankmachine7_row_col_n_addr_sel <= 1'd0; + netv2_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd0; + netv2_sdram_bankmachine7_cmd_payload_is_read <= 1'd0; + netv2_sdram_bankmachine7_cmd_payload_is_write <= 1'd0; + netv2_sdram_bankmachine7_req_wdata_ready <= 1'd0; + netv2_sdram_bankmachine7_req_rdata_valid <= 1'd0; + netv2_sdram_bankmachine7_refresh_gnt <= 1'd0; + netv2_sdram_bankmachine7_cmd_valid <= 1'd0; + netv2_sdram_bankmachine7_row_open <= 1'd0; + netv2_sdram_bankmachine7_row_close <= 1'd0; + litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((netv2_sdram_bankmachine7_twtpcon_ready & netv2_sdram_bankmachine7_trascon_ready)) begin + netv2_sdram_bankmachine7_cmd_valid <= 1'd1; + if (netv2_sdram_bankmachine7_cmd_ready) begin + litedramcore_bankmachine7_next_state <= 3'd5; + end + netv2_sdram_bankmachine7_cmd_payload_ras <= 1'd1; + netv2_sdram_bankmachine7_cmd_payload_we <= 1'd1; + netv2_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + netv2_sdram_bankmachine7_row_close <= 1'd1; + end + 2'd2: begin + if ((netv2_sdram_bankmachine7_twtpcon_ready & netv2_sdram_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_next_state <= 3'd5; + end + netv2_sdram_bankmachine7_row_close <= 1'd1; + end + 2'd3: begin + if (netv2_sdram_bankmachine7_trccon_ready) begin + netv2_sdram_bankmachine7_row_col_n_addr_sel <= 1'd1; + netv2_sdram_bankmachine7_row_open <= 1'd1; + netv2_sdram_bankmachine7_cmd_valid <= 1'd1; + netv2_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if (netv2_sdram_bankmachine7_cmd_ready) begin + litedramcore_bankmachine7_next_state <= 3'd7; + end + netv2_sdram_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (netv2_sdram_bankmachine7_twtpcon_ready) begin + netv2_sdram_bankmachine7_refresh_gnt <= 1'd1; + end + netv2_sdram_bankmachine7_row_close <= 1'd1; + netv2_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if ((~netv2_sdram_bankmachine7_refresh_req)) begin + litedramcore_bankmachine7_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine7_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine7_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine7_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine7_next_state <= 1'd0; + end + default: begin + if (netv2_sdram_bankmachine7_refresh_req) begin + litedramcore_bankmachine7_next_state <= 3'd4; + end else begin + if (netv2_sdram_bankmachine7_cmd_buffer_source_valid) begin + if (netv2_sdram_bankmachine7_row_opened) begin + if (netv2_sdram_bankmachine7_row_hit) begin + netv2_sdram_bankmachine7_cmd_valid <= 1'd1; + if (netv2_sdram_bankmachine7_cmd_buffer_source_payload_we) begin + netv2_sdram_bankmachine7_req_wdata_ready <= netv2_sdram_bankmachine7_cmd_ready; + netv2_sdram_bankmachine7_cmd_payload_is_write <= 1'd1; + netv2_sdram_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + netv2_sdram_bankmachine7_req_rdata_valid <= netv2_sdram_bankmachine7_cmd_ready; + netv2_sdram_bankmachine7_cmd_payload_is_read <= 1'd1; + end + netv2_sdram_bankmachine7_cmd_payload_cas <= 1'd1; + if ((netv2_sdram_bankmachine7_cmd_ready & netv2_sdram_bankmachine7_auto_precharge)) begin + litedramcore_bankmachine7_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine7_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine7_next_state <= 2'd3; + end + end + end + end + endcase +end +assign netv2_sdram_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1); +assign netv2_sdram_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1); +assign netv2_sdram_trrdcon_valid = ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & ((netv2_sdram_choose_cmd_cmd_payload_ras & (~netv2_sdram_choose_cmd_cmd_payload_cas)) & (~netv2_sdram_choose_cmd_cmd_payload_we))); +assign netv2_sdram_tfawcon_valid = ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & ((netv2_sdram_choose_cmd_cmd_payload_ras & (~netv2_sdram_choose_cmd_cmd_payload_cas)) & (~netv2_sdram_choose_cmd_cmd_payload_we))); +assign netv2_sdram_ras_allowed = (netv2_sdram_trrdcon_ready & netv2_sdram_tfawcon_ready); +assign netv2_sdram_tccdcon_valid = ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & (netv2_sdram_choose_req_cmd_payload_is_write | netv2_sdram_choose_req_cmd_payload_is_read)); +assign netv2_sdram_cas_allowed = netv2_sdram_tccdcon_ready; +assign netv2_sdram_twtrcon_valid = ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_is_write); +assign netv2_sdram_read_available = ((((((((netv2_sdram_bankmachine0_cmd_valid & netv2_sdram_bankmachine0_cmd_payload_is_read) | (netv2_sdram_bankmachine1_cmd_valid & netv2_sdram_bankmachine1_cmd_payload_is_read)) | (netv2_sdram_bankmachine2_cmd_valid & netv2_sdram_bankmachine2_cmd_payload_is_read)) | (netv2_sdram_bankmachine3_cmd_valid & netv2_sdram_bankmachine3_cmd_payload_is_read)) | (netv2_sdram_bankmachine4_cmd_valid & netv2_sdram_bankmachine4_cmd_payload_is_read)) | (netv2_sdram_bankmachine5_cmd_valid & netv2_sdram_bankmachine5_cmd_payload_is_read)) | (netv2_sdram_bankmachine6_cmd_valid & netv2_sdram_bankmachine6_cmd_payload_is_read)) | (netv2_sdram_bankmachine7_cmd_valid & netv2_sdram_bankmachine7_cmd_payload_is_read)); +assign netv2_sdram_write_available = ((((((((netv2_sdram_bankmachine0_cmd_valid & netv2_sdram_bankmachine0_cmd_payload_is_write) | (netv2_sdram_bankmachine1_cmd_valid & netv2_sdram_bankmachine1_cmd_payload_is_write)) | (netv2_sdram_bankmachine2_cmd_valid & netv2_sdram_bankmachine2_cmd_payload_is_write)) | (netv2_sdram_bankmachine3_cmd_valid & netv2_sdram_bankmachine3_cmd_payload_is_write)) | (netv2_sdram_bankmachine4_cmd_valid & netv2_sdram_bankmachine4_cmd_payload_is_write)) | (netv2_sdram_bankmachine5_cmd_valid & netv2_sdram_bankmachine5_cmd_payload_is_write)) | (netv2_sdram_bankmachine6_cmd_valid & netv2_sdram_bankmachine6_cmd_payload_is_write)) | (netv2_sdram_bankmachine7_cmd_valid & netv2_sdram_bankmachine7_cmd_payload_is_write)); +assign netv2_sdram_max_time0 = (netv2_sdram_time0 == 1'd0); +assign netv2_sdram_max_time1 = (netv2_sdram_time1 == 1'd0); +assign netv2_sdram_bankmachine0_refresh_req = netv2_sdram_cmd_valid; +assign netv2_sdram_bankmachine1_refresh_req = netv2_sdram_cmd_valid; +assign netv2_sdram_bankmachine2_refresh_req = netv2_sdram_cmd_valid; +assign netv2_sdram_bankmachine3_refresh_req = netv2_sdram_cmd_valid; +assign netv2_sdram_bankmachine4_refresh_req = netv2_sdram_cmd_valid; +assign netv2_sdram_bankmachine5_refresh_req = netv2_sdram_cmd_valid; +assign netv2_sdram_bankmachine6_refresh_req = netv2_sdram_cmd_valid; +assign netv2_sdram_bankmachine7_refresh_req = netv2_sdram_cmd_valid; +assign netv2_sdram_go_to_refresh = (((((((netv2_sdram_bankmachine0_refresh_gnt & netv2_sdram_bankmachine1_refresh_gnt) & netv2_sdram_bankmachine2_refresh_gnt) & netv2_sdram_bankmachine3_refresh_gnt) & netv2_sdram_bankmachine4_refresh_gnt) & netv2_sdram_bankmachine5_refresh_gnt) & netv2_sdram_bankmachine6_refresh_gnt) & netv2_sdram_bankmachine7_refresh_gnt); +assign netv2_sdram_interface_rdata = {netv2_sdram_dfi_p3_rddata, netv2_sdram_dfi_p2_rddata, netv2_sdram_dfi_p1_rddata, netv2_sdram_dfi_p0_rddata}; +assign {netv2_sdram_dfi_p3_wrdata, netv2_sdram_dfi_p2_wrdata, netv2_sdram_dfi_p1_wrdata, netv2_sdram_dfi_p0_wrdata} = netv2_sdram_interface_wdata; +assign {netv2_sdram_dfi_p3_wrdata_mask, netv2_sdram_dfi_p2_wrdata_mask, netv2_sdram_dfi_p1_wrdata_mask, netv2_sdram_dfi_p0_wrdata_mask} = (~netv2_sdram_interface_wdata_we); +always @(*) begin + netv2_sdram_choose_cmd_valids <= 8'd0; + netv2_sdram_choose_cmd_valids[0] <= (netv2_sdram_bankmachine0_cmd_valid & (((netv2_sdram_bankmachine0_cmd_payload_is_cmd & netv2_sdram_choose_cmd_want_cmds) & ((~((netv2_sdram_bankmachine0_cmd_payload_ras & (~netv2_sdram_bankmachine0_cmd_payload_cas)) & (~netv2_sdram_bankmachine0_cmd_payload_we))) | netv2_sdram_choose_cmd_want_activates)) | ((netv2_sdram_bankmachine0_cmd_payload_is_read == netv2_sdram_choose_cmd_want_reads) & (netv2_sdram_bankmachine0_cmd_payload_is_write == netv2_sdram_choose_cmd_want_writes)))); + netv2_sdram_choose_cmd_valids[1] <= (netv2_sdram_bankmachine1_cmd_valid & (((netv2_sdram_bankmachine1_cmd_payload_is_cmd & netv2_sdram_choose_cmd_want_cmds) & ((~((netv2_sdram_bankmachine1_cmd_payload_ras & (~netv2_sdram_bankmachine1_cmd_payload_cas)) & (~netv2_sdram_bankmachine1_cmd_payload_we))) | netv2_sdram_choose_cmd_want_activates)) | ((netv2_sdram_bankmachine1_cmd_payload_is_read == netv2_sdram_choose_cmd_want_reads) & (netv2_sdram_bankmachine1_cmd_payload_is_write == netv2_sdram_choose_cmd_want_writes)))); + netv2_sdram_choose_cmd_valids[2] <= (netv2_sdram_bankmachine2_cmd_valid & (((netv2_sdram_bankmachine2_cmd_payload_is_cmd & netv2_sdram_choose_cmd_want_cmds) & ((~((netv2_sdram_bankmachine2_cmd_payload_ras & (~netv2_sdram_bankmachine2_cmd_payload_cas)) & (~netv2_sdram_bankmachine2_cmd_payload_we))) | netv2_sdram_choose_cmd_want_activates)) | ((netv2_sdram_bankmachine2_cmd_payload_is_read == netv2_sdram_choose_cmd_want_reads) & (netv2_sdram_bankmachine2_cmd_payload_is_write == netv2_sdram_choose_cmd_want_writes)))); + netv2_sdram_choose_cmd_valids[3] <= (netv2_sdram_bankmachine3_cmd_valid & (((netv2_sdram_bankmachine3_cmd_payload_is_cmd & netv2_sdram_choose_cmd_want_cmds) & ((~((netv2_sdram_bankmachine3_cmd_payload_ras & (~netv2_sdram_bankmachine3_cmd_payload_cas)) & (~netv2_sdram_bankmachine3_cmd_payload_we))) | netv2_sdram_choose_cmd_want_activates)) | ((netv2_sdram_bankmachine3_cmd_payload_is_read == netv2_sdram_choose_cmd_want_reads) & (netv2_sdram_bankmachine3_cmd_payload_is_write == netv2_sdram_choose_cmd_want_writes)))); + netv2_sdram_choose_cmd_valids[4] <= (netv2_sdram_bankmachine4_cmd_valid & (((netv2_sdram_bankmachine4_cmd_payload_is_cmd & netv2_sdram_choose_cmd_want_cmds) & ((~((netv2_sdram_bankmachine4_cmd_payload_ras & (~netv2_sdram_bankmachine4_cmd_payload_cas)) & (~netv2_sdram_bankmachine4_cmd_payload_we))) | netv2_sdram_choose_cmd_want_activates)) | ((netv2_sdram_bankmachine4_cmd_payload_is_read == netv2_sdram_choose_cmd_want_reads) & (netv2_sdram_bankmachine4_cmd_payload_is_write == netv2_sdram_choose_cmd_want_writes)))); + netv2_sdram_choose_cmd_valids[5] <= (netv2_sdram_bankmachine5_cmd_valid & (((netv2_sdram_bankmachine5_cmd_payload_is_cmd & netv2_sdram_choose_cmd_want_cmds) & ((~((netv2_sdram_bankmachine5_cmd_payload_ras & (~netv2_sdram_bankmachine5_cmd_payload_cas)) & (~netv2_sdram_bankmachine5_cmd_payload_we))) | netv2_sdram_choose_cmd_want_activates)) | ((netv2_sdram_bankmachine5_cmd_payload_is_read == netv2_sdram_choose_cmd_want_reads) & (netv2_sdram_bankmachine5_cmd_payload_is_write == netv2_sdram_choose_cmd_want_writes)))); + netv2_sdram_choose_cmd_valids[6] <= (netv2_sdram_bankmachine6_cmd_valid & (((netv2_sdram_bankmachine6_cmd_payload_is_cmd & netv2_sdram_choose_cmd_want_cmds) & ((~((netv2_sdram_bankmachine6_cmd_payload_ras & (~netv2_sdram_bankmachine6_cmd_payload_cas)) & (~netv2_sdram_bankmachine6_cmd_payload_we))) | netv2_sdram_choose_cmd_want_activates)) | ((netv2_sdram_bankmachine6_cmd_payload_is_read == netv2_sdram_choose_cmd_want_reads) & (netv2_sdram_bankmachine6_cmd_payload_is_write == netv2_sdram_choose_cmd_want_writes)))); + netv2_sdram_choose_cmd_valids[7] <= (netv2_sdram_bankmachine7_cmd_valid & (((netv2_sdram_bankmachine7_cmd_payload_is_cmd & netv2_sdram_choose_cmd_want_cmds) & ((~((netv2_sdram_bankmachine7_cmd_payload_ras & (~netv2_sdram_bankmachine7_cmd_payload_cas)) & (~netv2_sdram_bankmachine7_cmd_payload_we))) | netv2_sdram_choose_cmd_want_activates)) | ((netv2_sdram_bankmachine7_cmd_payload_is_read == netv2_sdram_choose_cmd_want_reads) & (netv2_sdram_bankmachine7_cmd_payload_is_write == netv2_sdram_choose_cmd_want_writes)))); +end +assign netv2_sdram_choose_cmd_request = netv2_sdram_choose_cmd_valids; +assign netv2_sdram_choose_cmd_cmd_valid = comb_rhs_array_muxed0; +assign netv2_sdram_choose_cmd_cmd_payload_a = comb_rhs_array_muxed1; +assign netv2_sdram_choose_cmd_cmd_payload_ba = comb_rhs_array_muxed2; +assign netv2_sdram_choose_cmd_cmd_payload_is_read = comb_rhs_array_muxed3; +assign netv2_sdram_choose_cmd_cmd_payload_is_write = comb_rhs_array_muxed4; +assign netv2_sdram_choose_cmd_cmd_payload_is_cmd = comb_rhs_array_muxed5; +always @(*) begin + netv2_sdram_choose_cmd_cmd_payload_cas <= 1'd0; + if (netv2_sdram_choose_cmd_cmd_valid) begin + netv2_sdram_choose_cmd_cmd_payload_cas <= comb_t_array_muxed0; + end +end +always @(*) begin + netv2_sdram_choose_cmd_cmd_payload_ras <= 1'd0; + if (netv2_sdram_choose_cmd_cmd_valid) begin + netv2_sdram_choose_cmd_cmd_payload_ras <= comb_t_array_muxed1; + end +end +always @(*) begin + netv2_sdram_choose_cmd_cmd_payload_we <= 1'd0; + if (netv2_sdram_choose_cmd_cmd_valid) begin + netv2_sdram_choose_cmd_cmd_payload_we <= comb_t_array_muxed2; + end +end +assign netv2_sdram_choose_cmd_ce = (netv2_sdram_choose_cmd_cmd_ready | (~netv2_sdram_choose_cmd_cmd_valid)); +always @(*) begin + netv2_sdram_choose_req_valids <= 8'd0; + netv2_sdram_choose_req_valids[0] <= (netv2_sdram_bankmachine0_cmd_valid & (((netv2_sdram_bankmachine0_cmd_payload_is_cmd & netv2_sdram_choose_req_want_cmds) & ((~((netv2_sdram_bankmachine0_cmd_payload_ras & (~netv2_sdram_bankmachine0_cmd_payload_cas)) & (~netv2_sdram_bankmachine0_cmd_payload_we))) | netv2_sdram_choose_req_want_activates)) | ((netv2_sdram_bankmachine0_cmd_payload_is_read == netv2_sdram_choose_req_want_reads) & (netv2_sdram_bankmachine0_cmd_payload_is_write == netv2_sdram_choose_req_want_writes)))); + netv2_sdram_choose_req_valids[1] <= (netv2_sdram_bankmachine1_cmd_valid & (((netv2_sdram_bankmachine1_cmd_payload_is_cmd & netv2_sdram_choose_req_want_cmds) & ((~((netv2_sdram_bankmachine1_cmd_payload_ras & (~netv2_sdram_bankmachine1_cmd_payload_cas)) & (~netv2_sdram_bankmachine1_cmd_payload_we))) | netv2_sdram_choose_req_want_activates)) | ((netv2_sdram_bankmachine1_cmd_payload_is_read == netv2_sdram_choose_req_want_reads) & (netv2_sdram_bankmachine1_cmd_payload_is_write == netv2_sdram_choose_req_want_writes)))); + netv2_sdram_choose_req_valids[2] <= (netv2_sdram_bankmachine2_cmd_valid & (((netv2_sdram_bankmachine2_cmd_payload_is_cmd & netv2_sdram_choose_req_want_cmds) & ((~((netv2_sdram_bankmachine2_cmd_payload_ras & (~netv2_sdram_bankmachine2_cmd_payload_cas)) & (~netv2_sdram_bankmachine2_cmd_payload_we))) | netv2_sdram_choose_req_want_activates)) | ((netv2_sdram_bankmachine2_cmd_payload_is_read == netv2_sdram_choose_req_want_reads) & (netv2_sdram_bankmachine2_cmd_payload_is_write == netv2_sdram_choose_req_want_writes)))); + netv2_sdram_choose_req_valids[3] <= (netv2_sdram_bankmachine3_cmd_valid & (((netv2_sdram_bankmachine3_cmd_payload_is_cmd & netv2_sdram_choose_req_want_cmds) & ((~((netv2_sdram_bankmachine3_cmd_payload_ras & (~netv2_sdram_bankmachine3_cmd_payload_cas)) & (~netv2_sdram_bankmachine3_cmd_payload_we))) | netv2_sdram_choose_req_want_activates)) | ((netv2_sdram_bankmachine3_cmd_payload_is_read == netv2_sdram_choose_req_want_reads) & (netv2_sdram_bankmachine3_cmd_payload_is_write == netv2_sdram_choose_req_want_writes)))); + netv2_sdram_choose_req_valids[4] <= (netv2_sdram_bankmachine4_cmd_valid & (((netv2_sdram_bankmachine4_cmd_payload_is_cmd & netv2_sdram_choose_req_want_cmds) & ((~((netv2_sdram_bankmachine4_cmd_payload_ras & (~netv2_sdram_bankmachine4_cmd_payload_cas)) & (~netv2_sdram_bankmachine4_cmd_payload_we))) | netv2_sdram_choose_req_want_activates)) | ((netv2_sdram_bankmachine4_cmd_payload_is_read == netv2_sdram_choose_req_want_reads) & (netv2_sdram_bankmachine4_cmd_payload_is_write == netv2_sdram_choose_req_want_writes)))); + netv2_sdram_choose_req_valids[5] <= (netv2_sdram_bankmachine5_cmd_valid & (((netv2_sdram_bankmachine5_cmd_payload_is_cmd & netv2_sdram_choose_req_want_cmds) & ((~((netv2_sdram_bankmachine5_cmd_payload_ras & (~netv2_sdram_bankmachine5_cmd_payload_cas)) & (~netv2_sdram_bankmachine5_cmd_payload_we))) | netv2_sdram_choose_req_want_activates)) | ((netv2_sdram_bankmachine5_cmd_payload_is_read == netv2_sdram_choose_req_want_reads) & (netv2_sdram_bankmachine5_cmd_payload_is_write == netv2_sdram_choose_req_want_writes)))); + netv2_sdram_choose_req_valids[6] <= (netv2_sdram_bankmachine6_cmd_valid & (((netv2_sdram_bankmachine6_cmd_payload_is_cmd & netv2_sdram_choose_req_want_cmds) & ((~((netv2_sdram_bankmachine6_cmd_payload_ras & (~netv2_sdram_bankmachine6_cmd_payload_cas)) & (~netv2_sdram_bankmachine6_cmd_payload_we))) | netv2_sdram_choose_req_want_activates)) | ((netv2_sdram_bankmachine6_cmd_payload_is_read == netv2_sdram_choose_req_want_reads) & (netv2_sdram_bankmachine6_cmd_payload_is_write == netv2_sdram_choose_req_want_writes)))); + netv2_sdram_choose_req_valids[7] <= (netv2_sdram_bankmachine7_cmd_valid & (((netv2_sdram_bankmachine7_cmd_payload_is_cmd & netv2_sdram_choose_req_want_cmds) & ((~((netv2_sdram_bankmachine7_cmd_payload_ras & (~netv2_sdram_bankmachine7_cmd_payload_cas)) & (~netv2_sdram_bankmachine7_cmd_payload_we))) | netv2_sdram_choose_req_want_activates)) | ((netv2_sdram_bankmachine7_cmd_payload_is_read == netv2_sdram_choose_req_want_reads) & (netv2_sdram_bankmachine7_cmd_payload_is_write == netv2_sdram_choose_req_want_writes)))); +end +assign netv2_sdram_choose_req_request = netv2_sdram_choose_req_valids; +assign netv2_sdram_choose_req_cmd_valid = comb_rhs_array_muxed6; +assign netv2_sdram_choose_req_cmd_payload_a = comb_rhs_array_muxed7; +assign netv2_sdram_choose_req_cmd_payload_ba = comb_rhs_array_muxed8; +assign netv2_sdram_choose_req_cmd_payload_is_read = comb_rhs_array_muxed9; +assign netv2_sdram_choose_req_cmd_payload_is_write = comb_rhs_array_muxed10; +assign netv2_sdram_choose_req_cmd_payload_is_cmd = comb_rhs_array_muxed11; +always @(*) begin + netv2_sdram_choose_req_cmd_payload_cas <= 1'd0; + if (netv2_sdram_choose_req_cmd_valid) begin + netv2_sdram_choose_req_cmd_payload_cas <= comb_t_array_muxed3; + end +end +always @(*) begin + netv2_sdram_choose_req_cmd_payload_ras <= 1'd0; + if (netv2_sdram_choose_req_cmd_valid) begin + netv2_sdram_choose_req_cmd_payload_ras <= comb_t_array_muxed4; + end +end +always @(*) begin + netv2_sdram_choose_req_cmd_payload_we <= 1'd0; + if (netv2_sdram_choose_req_cmd_valid) begin + netv2_sdram_choose_req_cmd_payload_we <= comb_t_array_muxed5; + end +end +always @(*) begin + netv2_sdram_bankmachine0_cmd_ready <= 1'd0; + if (((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & (netv2_sdram_choose_cmd_grant == 1'd0))) begin + netv2_sdram_bankmachine0_cmd_ready <= 1'd1; + end + if (((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & (netv2_sdram_choose_req_grant == 1'd0))) begin + netv2_sdram_bankmachine0_cmd_ready <= 1'd1; + end +end +always @(*) begin + netv2_sdram_bankmachine1_cmd_ready <= 1'd0; + if (((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & (netv2_sdram_choose_cmd_grant == 1'd1))) begin + netv2_sdram_bankmachine1_cmd_ready <= 1'd1; + end + if (((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & (netv2_sdram_choose_req_grant == 1'd1))) begin + netv2_sdram_bankmachine1_cmd_ready <= 1'd1; + end +end +always @(*) begin + netv2_sdram_bankmachine2_cmd_ready <= 1'd0; + if (((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & (netv2_sdram_choose_cmd_grant == 2'd2))) begin + netv2_sdram_bankmachine2_cmd_ready <= 1'd1; + end + if (((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & (netv2_sdram_choose_req_grant == 2'd2))) begin + netv2_sdram_bankmachine2_cmd_ready <= 1'd1; + end +end +always @(*) begin + netv2_sdram_bankmachine3_cmd_ready <= 1'd0; + if (((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & (netv2_sdram_choose_cmd_grant == 2'd3))) begin + netv2_sdram_bankmachine3_cmd_ready <= 1'd1; + end + if (((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & (netv2_sdram_choose_req_grant == 2'd3))) begin + netv2_sdram_bankmachine3_cmd_ready <= 1'd1; + end +end +always @(*) begin + netv2_sdram_bankmachine4_cmd_ready <= 1'd0; + if (((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & (netv2_sdram_choose_cmd_grant == 3'd4))) begin + netv2_sdram_bankmachine4_cmd_ready <= 1'd1; + end + if (((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & (netv2_sdram_choose_req_grant == 3'd4))) begin + netv2_sdram_bankmachine4_cmd_ready <= 1'd1; + end +end +always @(*) begin + netv2_sdram_bankmachine5_cmd_ready <= 1'd0; + if (((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & (netv2_sdram_choose_cmd_grant == 3'd5))) begin + netv2_sdram_bankmachine5_cmd_ready <= 1'd1; + end + if (((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & (netv2_sdram_choose_req_grant == 3'd5))) begin + netv2_sdram_bankmachine5_cmd_ready <= 1'd1; + end +end +always @(*) begin + netv2_sdram_bankmachine6_cmd_ready <= 1'd0; + if (((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & (netv2_sdram_choose_cmd_grant == 3'd6))) begin + netv2_sdram_bankmachine6_cmd_ready <= 1'd1; + end + if (((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & (netv2_sdram_choose_req_grant == 3'd6))) begin + netv2_sdram_bankmachine6_cmd_ready <= 1'd1; + end +end +always @(*) begin + netv2_sdram_bankmachine7_cmd_ready <= 1'd0; + if (((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & (netv2_sdram_choose_cmd_grant == 3'd7))) begin + netv2_sdram_bankmachine7_cmd_ready <= 1'd1; + end + if (((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & (netv2_sdram_choose_req_grant == 3'd7))) begin + netv2_sdram_bankmachine7_cmd_ready <= 1'd1; + end +end +assign netv2_sdram_choose_req_ce = (netv2_sdram_choose_req_cmd_ready | (~netv2_sdram_choose_req_cmd_valid)); +assign netv2_sdram_dfi_p0_reset_n = 1'd1; +assign netv2_sdram_dfi_p0_cke = {1{netv2_sdram_steerer0}}; +assign netv2_sdram_dfi_p0_odt = {1{netv2_sdram_steerer1}}; +assign netv2_sdram_dfi_p1_reset_n = 1'd1; +assign netv2_sdram_dfi_p1_cke = {1{netv2_sdram_steerer2}}; +assign netv2_sdram_dfi_p1_odt = {1{netv2_sdram_steerer3}}; +assign netv2_sdram_dfi_p2_reset_n = 1'd1; +assign netv2_sdram_dfi_p2_cke = {1{netv2_sdram_steerer4}}; +assign netv2_sdram_dfi_p2_odt = {1{netv2_sdram_steerer5}}; +assign netv2_sdram_dfi_p3_reset_n = 1'd1; +assign netv2_sdram_dfi_p3_cke = {1{netv2_sdram_steerer6}}; +assign netv2_sdram_dfi_p3_odt = {1{netv2_sdram_steerer7}}; +assign netv2_sdram_tfawcon_count = ((((netv2_sdram_tfawcon_window[0] + netv2_sdram_tfawcon_window[1]) + netv2_sdram_tfawcon_window[2]) + netv2_sdram_tfawcon_window[3]) + netv2_sdram_tfawcon_window[4]); +always @(*) begin + litedramcore_multiplexer_next_state <= 4'd0; + netv2_sdram_choose_req_cmd_ready <= 1'd0; + netv2_sdram_en1 <= 1'd0; + netv2_sdram_steerer_sel0 <= 2'd0; + netv2_sdram_cmd_ready <= 1'd0; + netv2_sdram_steerer_sel1 <= 2'd0; + netv2_sdram_steerer_sel2 <= 2'd0; + netv2_sdram_choose_cmd_want_activates <= 1'd0; + netv2_sdram_steerer_sel3 <= 2'd0; + netv2_sdram_en0 <= 1'd0; + netv2_sdram_choose_cmd_cmd_ready <= 1'd0; + netv2_sdram_choose_req_want_reads <= 1'd0; + netv2_sdram_choose_req_want_writes <= 1'd0; + litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; + case (litedramcore_multiplexer_state) + 1'd1: begin + netv2_sdram_en1 <= 1'd1; + netv2_sdram_choose_req_want_writes <= 1'd1; + if (1'd0) begin + netv2_sdram_choose_req_cmd_ready <= (netv2_sdram_cas_allowed & ((~((netv2_sdram_choose_req_cmd_payload_ras & (~netv2_sdram_choose_req_cmd_payload_cas)) & (~netv2_sdram_choose_req_cmd_payload_we))) | netv2_sdram_ras_allowed)); + end else begin + netv2_sdram_choose_cmd_want_activates <= netv2_sdram_ras_allowed; + netv2_sdram_choose_cmd_cmd_ready <= ((~((netv2_sdram_choose_cmd_cmd_payload_ras & (~netv2_sdram_choose_cmd_cmd_payload_cas)) & (~netv2_sdram_choose_cmd_cmd_payload_we))) | netv2_sdram_ras_allowed); + netv2_sdram_choose_req_cmd_ready <= netv2_sdram_cas_allowed; + end + netv2_sdram_steerer_sel0 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 1'd0)) begin + netv2_sdram_steerer_sel0 <= 2'd2; + end + if ((netv2_sdram_wrcmdphase == 1'd0)) begin + netv2_sdram_steerer_sel0 <= 1'd1; + end + netv2_sdram_steerer_sel1 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 1'd1)) begin + netv2_sdram_steerer_sel1 <= 2'd2; + end + if ((netv2_sdram_wrcmdphase == 1'd1)) begin + netv2_sdram_steerer_sel1 <= 1'd1; + end + netv2_sdram_steerer_sel2 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 2'd2)) begin + netv2_sdram_steerer_sel2 <= 2'd2; + end + if ((netv2_sdram_wrcmdphase == 2'd2)) begin + netv2_sdram_steerer_sel2 <= 1'd1; + end + netv2_sdram_steerer_sel3 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 2'd3)) begin + netv2_sdram_steerer_sel3 <= 2'd2; + end + if ((netv2_sdram_wrcmdphase == 2'd3)) begin + netv2_sdram_steerer_sel3 <= 1'd1; + end + if (netv2_sdram_read_available) begin + if (((~netv2_sdram_write_available) | netv2_sdram_max_time1)) begin + litedramcore_multiplexer_next_state <= 2'd3; + end + end + if (netv2_sdram_go_to_refresh) begin + litedramcore_multiplexer_next_state <= 2'd2; + end + end + 2'd2: begin + netv2_sdram_steerer_sel0 <= 2'd3; + netv2_sdram_cmd_ready <= 1'd1; + if (netv2_sdram_cmd_last) begin + litedramcore_multiplexer_next_state <= 1'd0; + end + end + 2'd3: begin + if (netv2_sdram_twtrcon_ready) begin + litedramcore_multiplexer_next_state <= 1'd0; + end + end + 3'd4: begin + litedramcore_multiplexer_next_state <= 3'd5; + end + 3'd5: begin + litedramcore_multiplexer_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_multiplexer_next_state <= 3'd7; + end + 3'd7: begin + litedramcore_multiplexer_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_multiplexer_next_state <= 4'd9; + end + 4'd9: begin + litedramcore_multiplexer_next_state <= 4'd10; + end + 4'd10: begin + litedramcore_multiplexer_next_state <= 1'd1; + end + default: begin + netv2_sdram_en0 <= 1'd1; + netv2_sdram_choose_req_want_reads <= 1'd1; + if (1'd0) begin + netv2_sdram_choose_req_cmd_ready <= (netv2_sdram_cas_allowed & ((~((netv2_sdram_choose_req_cmd_payload_ras & (~netv2_sdram_choose_req_cmd_payload_cas)) & (~netv2_sdram_choose_req_cmd_payload_we))) | netv2_sdram_ras_allowed)); + end else begin + netv2_sdram_choose_cmd_want_activates <= netv2_sdram_ras_allowed; + netv2_sdram_choose_cmd_cmd_ready <= ((~((netv2_sdram_choose_cmd_cmd_payload_ras & (~netv2_sdram_choose_cmd_cmd_payload_cas)) & (~netv2_sdram_choose_cmd_cmd_payload_we))) | netv2_sdram_ras_allowed); + netv2_sdram_choose_req_cmd_ready <= netv2_sdram_cas_allowed; + end + netv2_sdram_steerer_sel0 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 1'd0)) begin + netv2_sdram_steerer_sel0 <= 2'd2; + end + if ((netv2_sdram_rdcmdphase == 1'd0)) begin + netv2_sdram_steerer_sel0 <= 1'd1; + end + netv2_sdram_steerer_sel1 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 1'd1)) begin + netv2_sdram_steerer_sel1 <= 2'd2; + end + if ((netv2_sdram_rdcmdphase == 1'd1)) begin + netv2_sdram_steerer_sel1 <= 1'd1; + end + netv2_sdram_steerer_sel2 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 2'd2)) begin + netv2_sdram_steerer_sel2 <= 2'd2; + end + if ((netv2_sdram_rdcmdphase == 2'd2)) begin + netv2_sdram_steerer_sel2 <= 1'd1; + end + netv2_sdram_steerer_sel3 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 2'd3)) begin + netv2_sdram_steerer_sel3 <= 2'd2; + end + if ((netv2_sdram_rdcmdphase == 2'd3)) begin + netv2_sdram_steerer_sel3 <= 1'd1; + end + if (netv2_sdram_write_available) begin + if (((~netv2_sdram_read_available) | netv2_sdram_max_time0)) begin + litedramcore_multiplexer_next_state <= 3'd4; + end + end + if (netv2_sdram_go_to_refresh) begin + litedramcore_multiplexer_next_state <= 2'd2; + end + end + endcase +end +assign litedramcore_roundrobin0_request = {(((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 1'd0) & (~(((((((litedramcore_locked2 | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2))))) & litedramcrossbar_litedramnativeport1_cmd_valid0), (((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 1'd0) & (~(((((((litedramcore_locked1 | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & litedramcrossbar_litedramnativeport0_cmd_valid0), (((netv2_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & netv2_port_cmd_valid)}; +assign litedramcore_roundrobin0_ce = ((~netv2_sdram_interface_bank0_valid) & (~netv2_sdram_interface_bank0_lock)); +assign netv2_sdram_interface_bank0_addr = comb_rhs_array_muxed12; +assign netv2_sdram_interface_bank0_we = comb_rhs_array_muxed13; +assign netv2_sdram_interface_bank0_valid = comb_rhs_array_muxed14; +assign litedramcore_roundrobin1_request = {(((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 1'd1) & (~(((((((litedramcore_locked5 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2))))) & litedramcrossbar_litedramnativeport1_cmd_valid0), (((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 1'd1) & (~(((((((litedramcore_locked4 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & litedramcrossbar_litedramnativeport0_cmd_valid0), (((netv2_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked3 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & netv2_port_cmd_valid)}; +assign litedramcore_roundrobin1_ce = ((~netv2_sdram_interface_bank1_valid) & (~netv2_sdram_interface_bank1_lock)); +assign netv2_sdram_interface_bank1_addr = comb_rhs_array_muxed15; +assign netv2_sdram_interface_bank1_we = comb_rhs_array_muxed16; +assign netv2_sdram_interface_bank1_valid = comb_rhs_array_muxed17; +assign litedramcore_roundrobin2_request = {(((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 2'd2) & (~(((((((litedramcore_locked8 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2))))) & litedramcrossbar_litedramnativeport1_cmd_valid0), (((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 2'd2) & (~(((((((litedramcore_locked7 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & litedramcrossbar_litedramnativeport0_cmd_valid0), (((netv2_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked6 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & netv2_port_cmd_valid)}; +assign litedramcore_roundrobin2_ce = ((~netv2_sdram_interface_bank2_valid) & (~netv2_sdram_interface_bank2_lock)); +assign netv2_sdram_interface_bank2_addr = comb_rhs_array_muxed18; +assign netv2_sdram_interface_bank2_we = comb_rhs_array_muxed19; +assign netv2_sdram_interface_bank2_valid = comb_rhs_array_muxed20; +assign litedramcore_roundrobin3_request = {(((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 2'd3) & (~(((((((litedramcore_locked11 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2))))) & litedramcrossbar_litedramnativeport1_cmd_valid0), (((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 2'd3) & (~(((((((litedramcore_locked10 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & litedramcrossbar_litedramnativeport0_cmd_valid0), (((netv2_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked9 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & netv2_port_cmd_valid)}; +assign litedramcore_roundrobin3_ce = ((~netv2_sdram_interface_bank3_valid) & (~netv2_sdram_interface_bank3_lock)); +assign netv2_sdram_interface_bank3_addr = comb_rhs_array_muxed21; +assign netv2_sdram_interface_bank3_we = comb_rhs_array_muxed22; +assign netv2_sdram_interface_bank3_valid = comb_rhs_array_muxed23; +assign litedramcore_roundrobin4_request = {(((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 3'd4) & (~(((((((litedramcore_locked14 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2))))) & litedramcrossbar_litedramnativeport1_cmd_valid0), (((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 3'd4) & (~(((((((litedramcore_locked13 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & litedramcrossbar_litedramnativeport0_cmd_valid0), (((netv2_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked12 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & netv2_port_cmd_valid)}; +assign litedramcore_roundrobin4_ce = ((~netv2_sdram_interface_bank4_valid) & (~netv2_sdram_interface_bank4_lock)); +assign netv2_sdram_interface_bank4_addr = comb_rhs_array_muxed24; +assign netv2_sdram_interface_bank4_we = comb_rhs_array_muxed25; +assign netv2_sdram_interface_bank4_valid = comb_rhs_array_muxed26; +assign litedramcore_roundrobin5_request = {(((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 3'd5) & (~(((((((litedramcore_locked17 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2))))) & litedramcrossbar_litedramnativeport1_cmd_valid0), (((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 3'd5) & (~(((((((litedramcore_locked16 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & litedramcrossbar_litedramnativeport0_cmd_valid0), (((netv2_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked15 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & netv2_port_cmd_valid)}; +assign litedramcore_roundrobin5_ce = ((~netv2_sdram_interface_bank5_valid) & (~netv2_sdram_interface_bank5_lock)); +assign netv2_sdram_interface_bank5_addr = comb_rhs_array_muxed27; +assign netv2_sdram_interface_bank5_we = comb_rhs_array_muxed28; +assign netv2_sdram_interface_bank5_valid = comb_rhs_array_muxed29; +assign litedramcore_roundrobin6_request = {(((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 3'd6) & (~(((((((litedramcore_locked20 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2))))) & litedramcrossbar_litedramnativeport1_cmd_valid0), (((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 3'd6) & (~(((((((litedramcore_locked19 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & litedramcrossbar_litedramnativeport0_cmd_valid0), (((netv2_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked18 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & netv2_port_cmd_valid)}; +assign litedramcore_roundrobin6_ce = ((~netv2_sdram_interface_bank6_valid) & (~netv2_sdram_interface_bank6_lock)); +assign netv2_sdram_interface_bank6_addr = comb_rhs_array_muxed30; +assign netv2_sdram_interface_bank6_we = comb_rhs_array_muxed31; +assign netv2_sdram_interface_bank6_valid = comb_rhs_array_muxed32; +assign litedramcore_roundrobin7_request = {(((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 3'd7) & (~(((((((litedramcore_locked23 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))))) & litedramcrossbar_litedramnativeport1_cmd_valid0), (((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 3'd7) & (~(((((((litedramcore_locked22 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))))) & litedramcrossbar_litedramnativeport0_cmd_valid0), (((netv2_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked21 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & netv2_port_cmd_valid)}; +assign litedramcore_roundrobin7_ce = ((~netv2_sdram_interface_bank7_valid) & (~netv2_sdram_interface_bank7_lock)); +assign netv2_sdram_interface_bank7_addr = comb_rhs_array_muxed33; +assign netv2_sdram_interface_bank7_we = comb_rhs_array_muxed34; +assign netv2_sdram_interface_bank7_valid = comb_rhs_array_muxed35; +assign netv2_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((netv2_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & netv2_sdram_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((netv2_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked3 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & netv2_sdram_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((netv2_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked6 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & netv2_sdram_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((netv2_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked9 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & netv2_sdram_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((netv2_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked12 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & netv2_sdram_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((netv2_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked15 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & netv2_sdram_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((netv2_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked18 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & netv2_sdram_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((netv2_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked21 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & netv2_sdram_interface_bank7_ready)); +assign litedramcrossbar_litedramnativeport0_cmd_ready0 = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd1) & ((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 1'd0) & (~(((((((litedramcore_locked1 | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1)))))) & netv2_sdram_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd1) & ((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 1'd1) & (~(((((((litedramcore_locked4 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1)))))) & netv2_sdram_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd1) & ((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 2'd2) & (~(((((((litedramcore_locked7 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1)))))) & netv2_sdram_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd1) & ((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 2'd3) & (~(((((((litedramcore_locked10 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1)))))) & netv2_sdram_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd1) & ((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 3'd4) & (~(((((((litedramcore_locked13 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1)))))) & netv2_sdram_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd1) & ((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 3'd5) & (~(((((((litedramcore_locked16 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1)))))) & netv2_sdram_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd1) & ((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 3'd6) & (~(((((((litedramcore_locked19 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1)))))) & netv2_sdram_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd1) & ((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 3'd7) & (~(((((((litedramcore_locked22 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1)))))) & netv2_sdram_interface_bank7_ready)); +assign litedramcrossbar_litedramnativeport1_cmd_ready0 = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 2'd2) & ((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 1'd0) & (~(((((((litedramcore_locked2 | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2)))))) & netv2_sdram_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 2'd2) & ((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 1'd1) & (~(((((((litedramcore_locked5 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2)))))) & netv2_sdram_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 2'd2) & ((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 2'd2) & (~(((((((litedramcore_locked8 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2)))))) & netv2_sdram_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 2'd2) & ((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 2'd3) & (~(((((((litedramcore_locked11 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2)))))) & netv2_sdram_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 2'd2) & ((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 3'd4) & (~(((((((litedramcore_locked14 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2)))))) & netv2_sdram_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 2'd2) & ((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 3'd5) & (~(((((((litedramcore_locked17 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2)))))) & netv2_sdram_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 2'd2) & ((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 3'd6) & (~(((((((litedramcore_locked20 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2)))))) & netv2_sdram_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 2'd2) & ((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 3'd7) & (~(((((((litedramcore_locked23 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2)))))) & netv2_sdram_interface_bank7_ready)); +assign netv2_port_wdata_ready = litedramcore_new_master_wdata_ready1; +assign litedramcrossbar_litedramnativeport0_wdata_ready = litedramcore_new_master_wdata_ready3; +assign litedramcrossbar_litedramnativeport1_wdata_ready = litedramcore_new_master_wdata_ready5; +assign netv2_port_rdata_valid = litedramcore_new_master_rdata_valid8; +assign litedramcrossbar_litedramnativeport0_rdata_valid0 = litedramcore_new_master_rdata_valid17; +assign litedramcrossbar_litedramnativeport1_rdata_valid0 = litedramcore_new_master_rdata_valid26; +always @(*) begin + netv2_sdram_interface_wdata <= 256'd0; + netv2_sdram_interface_wdata_we <= 32'd0; + case ({litedramcore_new_master_wdata_ready5, litedramcore_new_master_wdata_ready3, litedramcore_new_master_wdata_ready1}) + 1'd1: begin + netv2_sdram_interface_wdata <= netv2_port_wdata_payload_data; + netv2_sdram_interface_wdata_we <= netv2_port_wdata_payload_we; + end + 2'd2: begin + netv2_sdram_interface_wdata <= litedramcrossbar_litedramnativeport0_wdata_payload_data; + netv2_sdram_interface_wdata_we <= litedramcrossbar_litedramnativeport0_wdata_payload_we; + end + 3'd4: begin + netv2_sdram_interface_wdata <= litedramcrossbar_litedramnativeport1_wdata_payload_data; + netv2_sdram_interface_wdata_we <= litedramcrossbar_litedramnativeport1_wdata_payload_we; + end + default: begin + netv2_sdram_interface_wdata <= 1'd0; + netv2_sdram_interface_wdata_we <= 1'd0; + end + endcase +end +assign netv2_port_rdata_payload_data = netv2_sdram_interface_rdata; +assign litedramcrossbar_litedramnativeport0_rdata_payload_data0 = netv2_sdram_interface_rdata; +assign litedramcrossbar_litedramnativeport1_rdata_payload_data0 = netv2_sdram_interface_rdata; +assign litedramcrossbar_cmd_cdc_cdc_sink_valid = litedramcrossbar_cmd_cdc_sink_sink_valid; +assign litedramcrossbar_cmd_cdc_sink_sink_ready = litedramcrossbar_cmd_cdc_cdc_sink_ready; +assign litedramcrossbar_cmd_cdc_cdc_sink_first = litedramcrossbar_cmd_cdc_sink_sink_first; +assign litedramcrossbar_cmd_cdc_cdc_sink_last = litedramcrossbar_cmd_cdc_sink_sink_last; +assign litedramcrossbar_cmd_cdc_cdc_sink_payload_we = litedramcrossbar_cmd_cdc_sink_sink_payload_we; +assign litedramcrossbar_cmd_cdc_cdc_sink_payload_addr = litedramcrossbar_cmd_cdc_sink_sink_payload_addr; +assign litedramcrossbar_cmd_cdc_source_source_valid = litedramcrossbar_cmd_cdc_cdc_source_valid; +assign litedramcrossbar_cmd_cdc_cdc_source_ready = litedramcrossbar_cmd_cdc_source_source_ready; +assign litedramcrossbar_cmd_cdc_source_source_first = litedramcrossbar_cmd_cdc_cdc_source_first; +assign litedramcrossbar_cmd_cdc_source_source_last = litedramcrossbar_cmd_cdc_cdc_source_last; +assign litedramcrossbar_cmd_cdc_source_source_payload_we = litedramcrossbar_cmd_cdc_cdc_source_payload_we; +assign litedramcrossbar_cmd_cdc_source_source_payload_addr = litedramcrossbar_cmd_cdc_cdc_source_payload_addr; +assign litedramcrossbar_cmd_cdc_cdc_asyncfifo_din = {litedramcrossbar_cmd_cdc_cdc_fifo_in_last, litedramcrossbar_cmd_cdc_cdc_fifo_in_first, litedramcrossbar_cmd_cdc_cdc_fifo_in_payload_addr, litedramcrossbar_cmd_cdc_cdc_fifo_in_payload_we}; +assign {litedramcrossbar_cmd_cdc_cdc_fifo_out_last, litedramcrossbar_cmd_cdc_cdc_fifo_out_first, litedramcrossbar_cmd_cdc_cdc_fifo_out_payload_addr, litedramcrossbar_cmd_cdc_cdc_fifo_out_payload_we} = litedramcrossbar_cmd_cdc_cdc_asyncfifo_dout; +assign litedramcrossbar_cmd_cdc_cdc_sink_ready = litedramcrossbar_cmd_cdc_cdc_asyncfifo_writable; +assign litedramcrossbar_cmd_cdc_cdc_asyncfifo_we = litedramcrossbar_cmd_cdc_cdc_sink_valid; +assign litedramcrossbar_cmd_cdc_cdc_fifo_in_first = litedramcrossbar_cmd_cdc_cdc_sink_first; +assign litedramcrossbar_cmd_cdc_cdc_fifo_in_last = litedramcrossbar_cmd_cdc_cdc_sink_last; +assign litedramcrossbar_cmd_cdc_cdc_fifo_in_payload_we = litedramcrossbar_cmd_cdc_cdc_sink_payload_we; +assign litedramcrossbar_cmd_cdc_cdc_fifo_in_payload_addr = litedramcrossbar_cmd_cdc_cdc_sink_payload_addr; +assign litedramcrossbar_cmd_cdc_cdc_source_valid = litedramcrossbar_cmd_cdc_cdc_asyncfifo_readable; +assign litedramcrossbar_cmd_cdc_cdc_source_first = litedramcrossbar_cmd_cdc_cdc_fifo_out_first; +assign litedramcrossbar_cmd_cdc_cdc_source_last = litedramcrossbar_cmd_cdc_cdc_fifo_out_last; +assign litedramcrossbar_cmd_cdc_cdc_source_payload_we = litedramcrossbar_cmd_cdc_cdc_fifo_out_payload_we; +assign litedramcrossbar_cmd_cdc_cdc_source_payload_addr = litedramcrossbar_cmd_cdc_cdc_fifo_out_payload_addr; +assign litedramcrossbar_cmd_cdc_cdc_asyncfifo_re = litedramcrossbar_cmd_cdc_cdc_source_ready; +assign litedramcrossbar_cmd_cdc_cdc_graycounter0_ce = (litedramcrossbar_cmd_cdc_cdc_asyncfifo_writable & litedramcrossbar_cmd_cdc_cdc_asyncfifo_we); +assign litedramcrossbar_cmd_cdc_cdc_graycounter1_ce = (litedramcrossbar_cmd_cdc_cdc_asyncfifo_readable & litedramcrossbar_cmd_cdc_cdc_asyncfifo_re); +assign litedramcrossbar_cmd_cdc_cdc_asyncfifo_writable = (((litedramcrossbar_cmd_cdc_cdc_graycounter0_q[2] == litedramcrossbar_cmd_cdc_cdc_consume_wdomain[2]) | (litedramcrossbar_cmd_cdc_cdc_graycounter0_q[1] == litedramcrossbar_cmd_cdc_cdc_consume_wdomain[1])) | (litedramcrossbar_cmd_cdc_cdc_graycounter0_q[0] != litedramcrossbar_cmd_cdc_cdc_consume_wdomain[0])); +assign litedramcrossbar_cmd_cdc_cdc_asyncfifo_readable = (litedramcrossbar_cmd_cdc_cdc_graycounter1_q != litedramcrossbar_cmd_cdc_cdc_produce_rdomain); +assign litedramcrossbar_cmd_cdc_cdc_wrport_adr = litedramcrossbar_cmd_cdc_cdc_graycounter0_q_binary[1:0]; +assign litedramcrossbar_cmd_cdc_cdc_wrport_dat_w = litedramcrossbar_cmd_cdc_cdc_asyncfifo_din; +assign litedramcrossbar_cmd_cdc_cdc_wrport_we = litedramcrossbar_cmd_cdc_cdc_graycounter0_ce; +assign litedramcrossbar_cmd_cdc_cdc_rdport_adr = litedramcrossbar_cmd_cdc_cdc_graycounter1_q_next_binary[1:0]; +assign litedramcrossbar_cmd_cdc_cdc_asyncfifo_dout = litedramcrossbar_cmd_cdc_cdc_rdport_dat_r; +always @(*) begin + litedramcrossbar_cmd_cdc_cdc_graycounter0_q_next_binary <= 3'd0; + if (litedramcrossbar_cmd_cdc_cdc_graycounter0_ce) begin + litedramcrossbar_cmd_cdc_cdc_graycounter0_q_next_binary <= (litedramcrossbar_cmd_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + litedramcrossbar_cmd_cdc_cdc_graycounter0_q_next_binary <= litedramcrossbar_cmd_cdc_cdc_graycounter0_q_binary; + end +end +assign litedramcrossbar_cmd_cdc_cdc_graycounter0_q_next = (litedramcrossbar_cmd_cdc_cdc_graycounter0_q_next_binary ^ litedramcrossbar_cmd_cdc_cdc_graycounter0_q_next_binary[2:1]); +always @(*) begin + litedramcrossbar_cmd_cdc_cdc_graycounter1_q_next_binary <= 3'd0; + if (litedramcrossbar_cmd_cdc_cdc_graycounter1_ce) begin + litedramcrossbar_cmd_cdc_cdc_graycounter1_q_next_binary <= (litedramcrossbar_cmd_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + litedramcrossbar_cmd_cdc_cdc_graycounter1_q_next_binary <= litedramcrossbar_cmd_cdc_cdc_graycounter1_q_binary; + end +end +assign litedramcrossbar_cmd_cdc_cdc_graycounter1_q_next = (litedramcrossbar_cmd_cdc_cdc_graycounter1_q_next_binary ^ litedramcrossbar_cmd_cdc_cdc_graycounter1_q_next_binary[2:1]); +assign litedramcrossbar_cmd_cdc_sink_sink_valid = litedramcrossbar_litedramnativeport0_cmd_valid1; +assign litedramcrossbar_litedramnativeport0_cmd_ready1 = litedramcrossbar_cmd_cdc_sink_sink_ready; +assign litedramcrossbar_cmd_cdc_sink_sink_first = litedramcrossbar_litedramnativeport0_cmd_first; +assign litedramcrossbar_cmd_cdc_sink_sink_last = litedramcrossbar_litedramnativeport0_cmd_last; +assign litedramcrossbar_cmd_cdc_sink_sink_payload_we = litedramcrossbar_litedramnativeport0_cmd_payload_we1; +assign litedramcrossbar_cmd_cdc_sink_sink_payload_addr = litedramcrossbar_litedramnativeport0_cmd_payload_addr1; +assign litedramcrossbar_litedramnativeport1_cmd_valid0 = litedramcrossbar_cmd_cdc_source_source_valid; +assign litedramcrossbar_cmd_cdc_source_source_ready = litedramcrossbar_litedramnativeport1_cmd_ready0; +assign litedramcrossbar_litedramnativeport1_cmd_first = litedramcrossbar_cmd_cdc_source_source_first; +assign litedramcrossbar_litedramnativeport1_cmd_last0 = litedramcrossbar_cmd_cdc_source_source_last; +assign litedramcrossbar_litedramnativeport1_cmd_payload_we0 = litedramcrossbar_cmd_cdc_source_source_payload_we; +assign litedramcrossbar_litedramnativeport1_cmd_payload_addr0 = litedramcrossbar_cmd_cdc_source_source_payload_addr; +assign litedramcrossbar_rdata_cdc_cdc_sink_valid = litedramcrossbar_rdata_cdc_sink_sink_valid; +assign litedramcrossbar_rdata_cdc_sink_sink_ready = litedramcrossbar_rdata_cdc_cdc_sink_ready; +assign litedramcrossbar_rdata_cdc_cdc_sink_first = litedramcrossbar_rdata_cdc_sink_sink_first; +assign litedramcrossbar_rdata_cdc_cdc_sink_last = litedramcrossbar_rdata_cdc_sink_sink_last; +assign litedramcrossbar_rdata_cdc_cdc_sink_payload_data = litedramcrossbar_rdata_cdc_sink_sink_payload_data; +assign litedramcrossbar_rdata_cdc_source_source_valid = litedramcrossbar_rdata_cdc_cdc_source_valid; +assign litedramcrossbar_rdata_cdc_cdc_source_ready = litedramcrossbar_rdata_cdc_source_source_ready; +assign litedramcrossbar_rdata_cdc_source_source_first = litedramcrossbar_rdata_cdc_cdc_source_first; +assign litedramcrossbar_rdata_cdc_source_source_last = litedramcrossbar_rdata_cdc_cdc_source_last; +assign litedramcrossbar_rdata_cdc_source_source_payload_data = litedramcrossbar_rdata_cdc_cdc_source_payload_data; +assign litedramcrossbar_rdata_cdc_cdc_asyncfifo_din = {litedramcrossbar_rdata_cdc_cdc_fifo_in_last, litedramcrossbar_rdata_cdc_cdc_fifo_in_first, litedramcrossbar_rdata_cdc_cdc_fifo_in_payload_data}; +assign {litedramcrossbar_rdata_cdc_cdc_fifo_out_last, litedramcrossbar_rdata_cdc_cdc_fifo_out_first, litedramcrossbar_rdata_cdc_cdc_fifo_out_payload_data} = litedramcrossbar_rdata_cdc_cdc_asyncfifo_dout; +assign litedramcrossbar_rdata_cdc_cdc_sink_ready = litedramcrossbar_rdata_cdc_cdc_asyncfifo_writable; +assign litedramcrossbar_rdata_cdc_cdc_asyncfifo_we = litedramcrossbar_rdata_cdc_cdc_sink_valid; +assign litedramcrossbar_rdata_cdc_cdc_fifo_in_first = litedramcrossbar_rdata_cdc_cdc_sink_first; +assign litedramcrossbar_rdata_cdc_cdc_fifo_in_last = litedramcrossbar_rdata_cdc_cdc_sink_last; +assign litedramcrossbar_rdata_cdc_cdc_fifo_in_payload_data = litedramcrossbar_rdata_cdc_cdc_sink_payload_data; +assign litedramcrossbar_rdata_cdc_cdc_source_valid = litedramcrossbar_rdata_cdc_cdc_asyncfifo_readable; +assign litedramcrossbar_rdata_cdc_cdc_source_first = litedramcrossbar_rdata_cdc_cdc_fifo_out_first; +assign litedramcrossbar_rdata_cdc_cdc_source_last = litedramcrossbar_rdata_cdc_cdc_fifo_out_last; +assign litedramcrossbar_rdata_cdc_cdc_source_payload_data = litedramcrossbar_rdata_cdc_cdc_fifo_out_payload_data; +assign litedramcrossbar_rdata_cdc_cdc_asyncfifo_re = litedramcrossbar_rdata_cdc_cdc_source_ready; +assign litedramcrossbar_rdata_cdc_cdc_graycounter0_ce = (litedramcrossbar_rdata_cdc_cdc_asyncfifo_writable & litedramcrossbar_rdata_cdc_cdc_asyncfifo_we); +assign litedramcrossbar_rdata_cdc_cdc_graycounter1_ce = (litedramcrossbar_rdata_cdc_cdc_asyncfifo_readable & litedramcrossbar_rdata_cdc_cdc_asyncfifo_re); +assign litedramcrossbar_rdata_cdc_cdc_asyncfifo_writable = (((litedramcrossbar_rdata_cdc_cdc_graycounter0_q[4] == litedramcrossbar_rdata_cdc_cdc_consume_wdomain[4]) | (litedramcrossbar_rdata_cdc_cdc_graycounter0_q[3] == litedramcrossbar_rdata_cdc_cdc_consume_wdomain[3])) | (litedramcrossbar_rdata_cdc_cdc_graycounter0_q[2:0] != litedramcrossbar_rdata_cdc_cdc_consume_wdomain[2:0])); +assign litedramcrossbar_rdata_cdc_cdc_asyncfifo_readable = (litedramcrossbar_rdata_cdc_cdc_graycounter1_q != litedramcrossbar_rdata_cdc_cdc_produce_rdomain); +assign litedramcrossbar_rdata_cdc_cdc_wrport_adr = litedramcrossbar_rdata_cdc_cdc_graycounter0_q_binary[3:0]; +assign litedramcrossbar_rdata_cdc_cdc_wrport_dat_w = litedramcrossbar_rdata_cdc_cdc_asyncfifo_din; +assign litedramcrossbar_rdata_cdc_cdc_wrport_we = litedramcrossbar_rdata_cdc_cdc_graycounter0_ce; +assign litedramcrossbar_rdata_cdc_cdc_rdport_adr = litedramcrossbar_rdata_cdc_cdc_graycounter1_q_next_binary[3:0]; +assign litedramcrossbar_rdata_cdc_cdc_asyncfifo_dout = litedramcrossbar_rdata_cdc_cdc_rdport_dat_r; +always @(*) begin + litedramcrossbar_rdata_cdc_cdc_graycounter0_q_next_binary <= 5'd0; + if (litedramcrossbar_rdata_cdc_cdc_graycounter0_ce) begin + litedramcrossbar_rdata_cdc_cdc_graycounter0_q_next_binary <= (litedramcrossbar_rdata_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + litedramcrossbar_rdata_cdc_cdc_graycounter0_q_next_binary <= litedramcrossbar_rdata_cdc_cdc_graycounter0_q_binary; + end +end +assign litedramcrossbar_rdata_cdc_cdc_graycounter0_q_next = (litedramcrossbar_rdata_cdc_cdc_graycounter0_q_next_binary ^ litedramcrossbar_rdata_cdc_cdc_graycounter0_q_next_binary[4:1]); +always @(*) begin + litedramcrossbar_rdata_cdc_cdc_graycounter1_q_next_binary <= 5'd0; + if (litedramcrossbar_rdata_cdc_cdc_graycounter1_ce) begin + litedramcrossbar_rdata_cdc_cdc_graycounter1_q_next_binary <= (litedramcrossbar_rdata_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + litedramcrossbar_rdata_cdc_cdc_graycounter1_q_next_binary <= litedramcrossbar_rdata_cdc_cdc_graycounter1_q_binary; + end +end +assign litedramcrossbar_rdata_cdc_cdc_graycounter1_q_next = (litedramcrossbar_rdata_cdc_cdc_graycounter1_q_next_binary ^ litedramcrossbar_rdata_cdc_cdc_graycounter1_q_next_binary[4:1]); +assign litedramcrossbar_rdata_cdc_sink_sink_valid = litedramcrossbar_litedramnativeport1_rdata_valid0; +assign litedramcrossbar_litedramnativeport1_rdata_ready0 = litedramcrossbar_rdata_cdc_sink_sink_ready; +assign litedramcrossbar_rdata_cdc_sink_sink_first = litedramcrossbar_litedramnativeport1_rdata_first0; +assign litedramcrossbar_rdata_cdc_sink_sink_last = litedramcrossbar_litedramnativeport1_rdata_last0; +assign litedramcrossbar_rdata_cdc_sink_sink_payload_data = litedramcrossbar_litedramnativeport1_rdata_payload_data0; +assign litedramcrossbar_litedramnativeport0_rdata_valid1 = litedramcrossbar_rdata_cdc_source_source_valid; +assign litedramcrossbar_rdata_cdc_source_source_ready = litedramcrossbar_litedramnativeport0_rdata_ready; +assign litedramcrossbar_litedramnativeport0_rdata_first = litedramcrossbar_rdata_cdc_source_source_first; +assign litedramcrossbar_litedramnativeport0_rdata_last = litedramcrossbar_rdata_cdc_source_source_last; +assign litedramcrossbar_litedramnativeport0_rdata_payload_data1 = litedramcrossbar_rdata_cdc_source_source_payload_data; +assign litedramcrossbar_cmd_buffer_source_ready = (litedramcrossbar_wdata_finished | litedramcrossbar_rdata_finished); +assign litedramcrossbar_addr_changed = (litedramcrossbar_cmd_addr[27:4] != litedramcrossbar_litedramnativeport1_cmd_payload_addr1[27:4]); +assign litedramcrossbar_rw_collision = ((litedramcrossbar_cmd_we & (litedramcrossbar_litedramnativeport1_cmd_valid1 & (~litedramcrossbar_litedramnativeport1_cmd_payload_we1))) & (~litedramcrossbar_addr_changed)); +assign litedramcrossbar_next_cmd = ((((litedramcrossbar_addr_changed | (litedramcrossbar_cmd_we != litedramcrossbar_litedramnativeport1_cmd_payload_we1)) | (litedramcrossbar_sel == 16'd65535)) | litedramcrossbar_cmd_last) | litedramcrossbar_litedramnativeport1_flush); +assign litedramcrossbar_rdata_fifo_sink_valid = litedramcrossbar_litedramnativeport0_rdata_valid1; +assign litedramcrossbar_litedramnativeport0_rdata_ready = litedramcrossbar_rdata_fifo_sink_ready; +assign litedramcrossbar_rdata_fifo_sink_first = litedramcrossbar_litedramnativeport0_rdata_first; +assign litedramcrossbar_rdata_fifo_sink_last = litedramcrossbar_litedramnativeport0_rdata_last; +assign litedramcrossbar_rdata_fifo_sink_payload_data = litedramcrossbar_litedramnativeport0_rdata_payload_data1; +assign litedramcrossbar_rdata_converter_sink_valid = litedramcrossbar_rdata_fifo_source_valid; +assign litedramcrossbar_rdata_fifo_source_ready = litedramcrossbar_rdata_converter_sink_ready; +assign litedramcrossbar_rdata_converter_sink_first = litedramcrossbar_rdata_fifo_source_first; +assign litedramcrossbar_rdata_converter_sink_last = litedramcrossbar_rdata_fifo_source_last; +assign litedramcrossbar_rdata_converter_sink_payload_data = litedramcrossbar_rdata_fifo_source_payload_data; +assign litedramcrossbar_rdata_chunk_valid = ((litedramcrossbar_cmd_buffer_source_payload_sel & litedramcrossbar_rdata_chunk) != 1'd0); +always @(*) begin + litedramcrossbar_litedramnativeport1_rdata_payload_data1 <= 16'd0; + litedramcrossbar_litedramnativeport1_rdata_valid1 <= 1'd0; + litedramcrossbar_rdata_converter_source_ready <= 1'd0; + litedramcrossbar_rdata_finished <= 1'd0; + if ((litedramcrossbar_cmd_buffer_source_valid & (~litedramcrossbar_cmd_buffer_source_payload_we))) begin + if (litedramcrossbar_rdata_chunk_valid) begin + litedramcrossbar_litedramnativeport1_rdata_valid1 <= litedramcrossbar_rdata_converter_source_valid; + litedramcrossbar_litedramnativeport1_rdata_payload_data1 <= litedramcrossbar_rdata_converter_source_payload_data; + litedramcrossbar_rdata_converter_source_ready <= litedramcrossbar_litedramnativeport1_rdata_ready1; + end else begin + litedramcrossbar_rdata_converter_source_ready <= 1'd1; + end + litedramcrossbar_rdata_finished <= ((litedramcrossbar_rdata_converter_source_valid & litedramcrossbar_rdata_converter_source_ready) & litedramcrossbar_rdata_chunk[15]); + end +end +assign litedramcrossbar_cmd_buffer_source_valid = litedramcrossbar_cmd_buffer_sink_valid; +assign litedramcrossbar_cmd_buffer_sink_ready = litedramcrossbar_cmd_buffer_source_ready; +assign litedramcrossbar_cmd_buffer_source_first = litedramcrossbar_cmd_buffer_sink_first; +assign litedramcrossbar_cmd_buffer_source_last = litedramcrossbar_cmd_buffer_sink_last; +assign litedramcrossbar_cmd_buffer_source_payload_sel = litedramcrossbar_cmd_buffer_sink_payload_sel; +assign litedramcrossbar_cmd_buffer_source_payload_we = litedramcrossbar_cmd_buffer_sink_payload_we; +always @(*) begin + litedramcore_next_state <= 2'd0; + litedramcrossbar_cmd_buffer_sink_valid <= 1'd0; + litedramcrossbar_cmd_addr_litedramcore_next_value0 <= 28'd0; + litedramcrossbar_cmd_addr_litedramcore_next_value_ce0 <= 1'd0; + litedramcrossbar_cmd_buffer_sink_payload_sel <= 16'd0; + litedramcrossbar_cmd_we_litedramcore_next_value1 <= 1'd0; + litedramcrossbar_cmd_buffer_sink_payload_we <= 1'd0; + litedramcrossbar_cmd_we_litedramcore_next_value_ce1 <= 1'd0; + litedramcrossbar_cmd_last_litedramcore_next_value2 <= 1'd0; + litedramcrossbar_cmd_last_litedramcore_next_value_ce2 <= 1'd0; + litedramcrossbar_sel_litedramcore_next_value3 <= 16'd0; + litedramcrossbar_sel_litedramcore_next_value_ce3 <= 1'd0; + litedramcrossbar_litedramnativeport1_cmd_ready1 <= 1'd0; + litedramcrossbar_litedramnativeport0_cmd_valid1 <= 1'd0; + litedramcrossbar_litedramnativeport0_cmd_payload_we1 <= 1'd0; + litedramcrossbar_litedramnativeport0_cmd_payload_addr1 <= 24'd0; + litedramcore_next_state <= litedramcore_state; + case (litedramcore_state) + 1'd1: begin + litedramcrossbar_litedramnativeport0_cmd_valid1 <= 1'd1; + litedramcrossbar_litedramnativeport0_cmd_payload_we1 <= litedramcrossbar_cmd_we; + litedramcrossbar_litedramnativeport0_cmd_payload_addr1 <= litedramcrossbar_cmd_addr[27:4]; + if (litedramcrossbar_litedramnativeport0_cmd_ready1) begin + if (litedramcrossbar_cmd_we) begin + litedramcore_next_state <= 1'd0; + end else begin + litedramcore_next_state <= 2'd2; + end + end + end + 2'd2: begin + if (litedramcrossbar_next_cmd) begin + litedramcore_next_state <= 2'd3; + end else begin + litedramcrossbar_litedramnativeport1_cmd_ready1 <= litedramcrossbar_litedramnativeport1_cmd_valid1; + litedramcrossbar_cmd_last_litedramcore_next_value2 <= litedramcrossbar_litedramnativeport1_cmd_last1; + litedramcrossbar_cmd_last_litedramcore_next_value_ce2 <= 1'd1; + litedramcrossbar_sel_litedramcore_next_value3 <= (litedramcrossbar_sel | (1'd1 <<< litedramcrossbar_litedramnativeport1_cmd_payload_addr1[3:0])); + litedramcrossbar_sel_litedramcore_next_value_ce3 <= 1'd1; + end + end + 2'd3: begin + litedramcrossbar_cmd_buffer_sink_valid <= 1'd1; + litedramcrossbar_cmd_buffer_sink_payload_sel <= litedramcrossbar_sel; + litedramcrossbar_cmd_buffer_sink_payload_we <= litedramcrossbar_cmd_we; + if (litedramcrossbar_cmd_buffer_sink_ready) begin + if (litedramcrossbar_cmd_we) begin + litedramcore_next_state <= 1'd1; + end else begin + litedramcore_next_state <= 1'd0; + end + end + end + default: begin + litedramcrossbar_litedramnativeport1_cmd_ready1 <= (litedramcrossbar_litedramnativeport1_cmd_valid1 & (~litedramcrossbar_read_lock)); + if (litedramcrossbar_litedramnativeport1_cmd_ready1) begin + litedramcrossbar_cmd_addr_litedramcore_next_value0 <= litedramcrossbar_litedramnativeport1_cmd_payload_addr1; + litedramcrossbar_cmd_addr_litedramcore_next_value_ce0 <= 1'd1; + litedramcrossbar_cmd_we_litedramcore_next_value1 <= litedramcrossbar_litedramnativeport1_cmd_payload_we1; + litedramcrossbar_cmd_we_litedramcore_next_value_ce1 <= 1'd1; + litedramcrossbar_cmd_last_litedramcore_next_value2 <= litedramcrossbar_litedramnativeport1_cmd_last1; + litedramcrossbar_cmd_last_litedramcore_next_value_ce2 <= 1'd1; + litedramcrossbar_sel_litedramcore_next_value3 <= (1'd1 <<< litedramcrossbar_litedramnativeport1_cmd_payload_addr1[3:0]); + litedramcrossbar_sel_litedramcore_next_value_ce3 <= 1'd1; + if (litedramcrossbar_litedramnativeport1_cmd_payload_we1) begin + litedramcore_next_state <= 2'd2; + end else begin + litedramcore_next_state <= 1'd1; + end + end + end + endcase +end +assign litedramcrossbar_rdata_fifo_syncfifo_din = {litedramcrossbar_rdata_fifo_fifo_in_last, litedramcrossbar_rdata_fifo_fifo_in_first, litedramcrossbar_rdata_fifo_fifo_in_payload_data}; +assign {litedramcrossbar_rdata_fifo_fifo_out_last, litedramcrossbar_rdata_fifo_fifo_out_first, litedramcrossbar_rdata_fifo_fifo_out_payload_data} = litedramcrossbar_rdata_fifo_syncfifo_dout; +assign litedramcrossbar_rdata_fifo_sink_ready = litedramcrossbar_rdata_fifo_syncfifo_writable; +assign litedramcrossbar_rdata_fifo_syncfifo_we = litedramcrossbar_rdata_fifo_sink_valid; +assign litedramcrossbar_rdata_fifo_fifo_in_first = litedramcrossbar_rdata_fifo_sink_first; +assign litedramcrossbar_rdata_fifo_fifo_in_last = litedramcrossbar_rdata_fifo_sink_last; +assign litedramcrossbar_rdata_fifo_fifo_in_payload_data = litedramcrossbar_rdata_fifo_sink_payload_data; +assign litedramcrossbar_rdata_fifo_source_valid = litedramcrossbar_rdata_fifo_syncfifo_readable; +assign litedramcrossbar_rdata_fifo_source_first = litedramcrossbar_rdata_fifo_fifo_out_first; +assign litedramcrossbar_rdata_fifo_source_last = litedramcrossbar_rdata_fifo_fifo_out_last; +assign litedramcrossbar_rdata_fifo_source_payload_data = litedramcrossbar_rdata_fifo_fifo_out_payload_data; +assign litedramcrossbar_rdata_fifo_syncfifo_re = litedramcrossbar_rdata_fifo_source_ready; +always @(*) begin + litedramcrossbar_rdata_fifo_wrport_adr <= 4'd0; + if (litedramcrossbar_rdata_fifo_replace) begin + litedramcrossbar_rdata_fifo_wrport_adr <= (litedramcrossbar_rdata_fifo_produce - 1'd1); + end else begin + litedramcrossbar_rdata_fifo_wrport_adr <= litedramcrossbar_rdata_fifo_produce; + end +end +assign litedramcrossbar_rdata_fifo_wrport_dat_w = litedramcrossbar_rdata_fifo_syncfifo_din; +assign litedramcrossbar_rdata_fifo_wrport_we = (litedramcrossbar_rdata_fifo_syncfifo_we & (litedramcrossbar_rdata_fifo_syncfifo_writable | litedramcrossbar_rdata_fifo_replace)); +assign litedramcrossbar_rdata_fifo_do_read = (litedramcrossbar_rdata_fifo_syncfifo_readable & litedramcrossbar_rdata_fifo_syncfifo_re); +assign litedramcrossbar_rdata_fifo_rdport_adr = litedramcrossbar_rdata_fifo_consume; +assign litedramcrossbar_rdata_fifo_syncfifo_dout = litedramcrossbar_rdata_fifo_rdport_dat_r; +assign litedramcrossbar_rdata_fifo_syncfifo_writable = (litedramcrossbar_rdata_fifo_level != 4'd15); +assign litedramcrossbar_rdata_fifo_syncfifo_readable = (litedramcrossbar_rdata_fifo_level != 1'd0); +assign litedramcrossbar_rdata_converter_converter_sink_valid = litedramcrossbar_rdata_converter_sink_valid; +assign litedramcrossbar_rdata_converter_converter_sink_first = litedramcrossbar_rdata_converter_sink_first; +assign litedramcrossbar_rdata_converter_converter_sink_last = litedramcrossbar_rdata_converter_sink_last; +assign litedramcrossbar_rdata_converter_sink_ready = litedramcrossbar_rdata_converter_converter_sink_ready; +always @(*) begin + litedramcrossbar_rdata_converter_converter_sink_payload_data <= 256'd0; + litedramcrossbar_rdata_converter_converter_sink_payload_data[15:0] <= litedramcrossbar_rdata_converter_sink_payload_data[15:0]; + litedramcrossbar_rdata_converter_converter_sink_payload_data[31:16] <= litedramcrossbar_rdata_converter_sink_payload_data[31:16]; + litedramcrossbar_rdata_converter_converter_sink_payload_data[47:32] <= litedramcrossbar_rdata_converter_sink_payload_data[47:32]; + litedramcrossbar_rdata_converter_converter_sink_payload_data[63:48] <= litedramcrossbar_rdata_converter_sink_payload_data[63:48]; + litedramcrossbar_rdata_converter_converter_sink_payload_data[79:64] <= litedramcrossbar_rdata_converter_sink_payload_data[79:64]; + litedramcrossbar_rdata_converter_converter_sink_payload_data[95:80] <= litedramcrossbar_rdata_converter_sink_payload_data[95:80]; + litedramcrossbar_rdata_converter_converter_sink_payload_data[111:96] <= litedramcrossbar_rdata_converter_sink_payload_data[111:96]; + litedramcrossbar_rdata_converter_converter_sink_payload_data[127:112] <= litedramcrossbar_rdata_converter_sink_payload_data[127:112]; + litedramcrossbar_rdata_converter_converter_sink_payload_data[143:128] <= litedramcrossbar_rdata_converter_sink_payload_data[143:128]; + litedramcrossbar_rdata_converter_converter_sink_payload_data[159:144] <= litedramcrossbar_rdata_converter_sink_payload_data[159:144]; + litedramcrossbar_rdata_converter_converter_sink_payload_data[175:160] <= litedramcrossbar_rdata_converter_sink_payload_data[175:160]; + litedramcrossbar_rdata_converter_converter_sink_payload_data[191:176] <= litedramcrossbar_rdata_converter_sink_payload_data[191:176]; + litedramcrossbar_rdata_converter_converter_sink_payload_data[207:192] <= litedramcrossbar_rdata_converter_sink_payload_data[207:192]; + litedramcrossbar_rdata_converter_converter_sink_payload_data[223:208] <= litedramcrossbar_rdata_converter_sink_payload_data[223:208]; + litedramcrossbar_rdata_converter_converter_sink_payload_data[239:224] <= litedramcrossbar_rdata_converter_sink_payload_data[239:224]; + litedramcrossbar_rdata_converter_converter_sink_payload_data[255:240] <= litedramcrossbar_rdata_converter_sink_payload_data[255:240]; +end +assign litedramcrossbar_rdata_converter_source_valid = litedramcrossbar_rdata_converter_source_source_valid; +assign litedramcrossbar_rdata_converter_source_first = litedramcrossbar_rdata_converter_source_source_first; +assign litedramcrossbar_rdata_converter_source_last = litedramcrossbar_rdata_converter_source_source_last; +assign litedramcrossbar_rdata_converter_source_source_ready = litedramcrossbar_rdata_converter_source_ready; +assign {litedramcrossbar_rdata_converter_source_payload_data} = litedramcrossbar_rdata_converter_source_source_payload_data; +assign litedramcrossbar_rdata_converter_source_source_valid = litedramcrossbar_rdata_converter_converter_source_valid; +assign litedramcrossbar_rdata_converter_converter_source_ready = litedramcrossbar_rdata_converter_source_source_ready; +assign litedramcrossbar_rdata_converter_source_source_first = litedramcrossbar_rdata_converter_converter_source_first; +assign litedramcrossbar_rdata_converter_source_source_last = litedramcrossbar_rdata_converter_converter_source_last; +assign litedramcrossbar_rdata_converter_source_source_payload_data = litedramcrossbar_rdata_converter_converter_source_payload_data; +assign litedramcrossbar_rdata_converter_converter_first = (litedramcrossbar_rdata_converter_converter_mux == 1'd0); +assign litedramcrossbar_rdata_converter_converter_last = (litedramcrossbar_rdata_converter_converter_mux == 4'd15); +assign litedramcrossbar_rdata_converter_converter_source_valid = litedramcrossbar_rdata_converter_converter_sink_valid; +assign litedramcrossbar_rdata_converter_converter_source_first = (litedramcrossbar_rdata_converter_converter_sink_first & litedramcrossbar_rdata_converter_converter_first); +assign litedramcrossbar_rdata_converter_converter_source_last = (litedramcrossbar_rdata_converter_converter_sink_last & litedramcrossbar_rdata_converter_converter_last); +assign litedramcrossbar_rdata_converter_converter_sink_ready = (litedramcrossbar_rdata_converter_converter_last & litedramcrossbar_rdata_converter_converter_source_ready); +always @(*) begin + litedramcrossbar_rdata_converter_converter_source_payload_data <= 16'd0; + case (litedramcrossbar_rdata_converter_converter_mux) + 1'd0: begin + litedramcrossbar_rdata_converter_converter_source_payload_data <= litedramcrossbar_rdata_converter_converter_sink_payload_data[255:240]; + end + 1'd1: begin + litedramcrossbar_rdata_converter_converter_source_payload_data <= litedramcrossbar_rdata_converter_converter_sink_payload_data[239:224]; + end + 2'd2: begin + litedramcrossbar_rdata_converter_converter_source_payload_data <= litedramcrossbar_rdata_converter_converter_sink_payload_data[223:208]; + end + 2'd3: begin + litedramcrossbar_rdata_converter_converter_source_payload_data <= litedramcrossbar_rdata_converter_converter_sink_payload_data[207:192]; + end + 3'd4: begin + litedramcrossbar_rdata_converter_converter_source_payload_data <= litedramcrossbar_rdata_converter_converter_sink_payload_data[191:176]; + end + 3'd5: begin + litedramcrossbar_rdata_converter_converter_source_payload_data <= litedramcrossbar_rdata_converter_converter_sink_payload_data[175:160]; + end + 3'd6: begin + litedramcrossbar_rdata_converter_converter_source_payload_data <= litedramcrossbar_rdata_converter_converter_sink_payload_data[159:144]; + end + 3'd7: begin + litedramcrossbar_rdata_converter_converter_source_payload_data <= litedramcrossbar_rdata_converter_converter_sink_payload_data[143:128]; + end + 4'd8: begin + litedramcrossbar_rdata_converter_converter_source_payload_data <= litedramcrossbar_rdata_converter_converter_sink_payload_data[127:112]; + end + 4'd9: begin + litedramcrossbar_rdata_converter_converter_source_payload_data <= litedramcrossbar_rdata_converter_converter_sink_payload_data[111:96]; + end + 4'd10: begin + litedramcrossbar_rdata_converter_converter_source_payload_data <= litedramcrossbar_rdata_converter_converter_sink_payload_data[95:80]; + end + 4'd11: begin + litedramcrossbar_rdata_converter_converter_source_payload_data <= litedramcrossbar_rdata_converter_converter_sink_payload_data[79:64]; + end + 4'd12: begin + litedramcrossbar_rdata_converter_converter_source_payload_data <= litedramcrossbar_rdata_converter_converter_sink_payload_data[63:48]; + end + 4'd13: begin + litedramcrossbar_rdata_converter_converter_source_payload_data <= litedramcrossbar_rdata_converter_converter_sink_payload_data[47:32]; + end + 4'd14: begin + litedramcrossbar_rdata_converter_converter_source_payload_data <= litedramcrossbar_rdata_converter_converter_sink_payload_data[31:16]; + end + default: begin + litedramcrossbar_rdata_converter_converter_source_payload_data <= litedramcrossbar_rdata_converter_converter_sink_payload_data[15:0]; + end + endcase +end +assign litedramcrossbar_rdata_converter_converter_source_payload_valid_token_count = litedramcrossbar_rdata_converter_converter_last; +assign netv2_data_port_adr = netv2_wb_sdram_adr[4:3]; +always @(*) begin + netv2_data_port_dat_w <= 256'd0; + netv2_data_port_we <= 32'd0; + if (netv2_write_from_slave) begin + netv2_data_port_dat_w <= netv2_interface_dat_r; + netv2_data_port_we <= {32{1'd1}}; + end else begin + netv2_data_port_dat_w <= {8{netv2_wb_sdram_dat_w}}; + if ((((netv2_wb_sdram_cyc & netv2_wb_sdram_stb) & netv2_wb_sdram_we) & netv2_wb_sdram_ack)) begin + netv2_data_port_we <= {({4{(netv2_wb_sdram_adr[2:0] == 1'd0)}} & netv2_wb_sdram_sel), ({4{(netv2_wb_sdram_adr[2:0] == 1'd1)}} & netv2_wb_sdram_sel), ({4{(netv2_wb_sdram_adr[2:0] == 2'd2)}} & netv2_wb_sdram_sel), ({4{(netv2_wb_sdram_adr[2:0] == 2'd3)}} & netv2_wb_sdram_sel), ({4{(netv2_wb_sdram_adr[2:0] == 3'd4)}} & netv2_wb_sdram_sel), ({4{(netv2_wb_sdram_adr[2:0] == 3'd5)}} & netv2_wb_sdram_sel), ({4{(netv2_wb_sdram_adr[2:0] == 3'd6)}} & netv2_wb_sdram_sel), ({4{(netv2_wb_sdram_adr[2:0] == 3'd7)}} & netv2_wb_sdram_sel)}; + end + end +end +assign netv2_interface_dat_w = netv2_data_port_dat_r; +assign netv2_interface_sel = 32'd4294967295; +always @(*) begin + netv2_wb_sdram_dat_r <= 32'd0; + case (netv2_adr_offset_r) + 1'd0: begin + netv2_wb_sdram_dat_r <= netv2_data_port_dat_r[255:224]; + end + 1'd1: begin + netv2_wb_sdram_dat_r <= netv2_data_port_dat_r[223:192]; + end + 2'd2: begin + netv2_wb_sdram_dat_r <= netv2_data_port_dat_r[191:160]; + end + 2'd3: begin + netv2_wb_sdram_dat_r <= netv2_data_port_dat_r[159:128]; + end + 3'd4: begin + netv2_wb_sdram_dat_r <= netv2_data_port_dat_r[127:96]; + end + 3'd5: begin + netv2_wb_sdram_dat_r <= netv2_data_port_dat_r[95:64]; + end + 3'd6: begin + netv2_wb_sdram_dat_r <= netv2_data_port_dat_r[63:32]; + end + default: begin + netv2_wb_sdram_dat_r <= netv2_data_port_dat_r[31:0]; + end + endcase +end +assign {netv2_tag_do_dirty, netv2_tag_do_tag} = netv2_tag_port_dat_r; +assign netv2_tag_port_dat_w = {netv2_tag_di_dirty, netv2_tag_di_tag}; +assign netv2_tag_port_adr = netv2_wb_sdram_adr[4:3]; +assign netv2_tag_di_tag = netv2_wb_sdram_adr[29:5]; +assign netv2_interface_adr = {netv2_tag_do_tag, netv2_wb_sdram_adr[4:3]}; +always @(*) begin + netv2_interface_cyc <= 1'd0; + netv2_interface_stb <= 1'd0; + fullmemorywe_next_state <= 2'd0; + netv2_interface_we <= 1'd0; + netv2_tag_di_dirty <= 1'd0; + netv2_word_clr <= 1'd0; + netv2_wb_sdram_ack <= 1'd0; + netv2_word_inc <= 1'd0; + netv2_write_from_slave <= 1'd0; + netv2_tag_port_we <= 1'd0; + fullmemorywe_next_state <= fullmemorywe_state; + case (fullmemorywe_state) + 1'd1: begin + netv2_word_clr <= 1'd1; + if ((netv2_tag_do_tag == netv2_wb_sdram_adr[29:5])) begin + netv2_wb_sdram_ack <= 1'd1; + if (netv2_wb_sdram_we) begin + netv2_tag_di_dirty <= 1'd1; + netv2_tag_port_we <= 1'd1; + end + fullmemorywe_next_state <= 1'd0; + end else begin + if (netv2_tag_do_dirty) begin + fullmemorywe_next_state <= 2'd2; + end else begin + netv2_tag_port_we <= 1'd1; + netv2_word_clr <= 1'd1; + fullmemorywe_next_state <= 2'd3; + end + end + end + 2'd2: begin + netv2_interface_stb <= 1'd1; + netv2_interface_cyc <= 1'd1; + netv2_interface_we <= 1'd1; + if (netv2_interface_ack) begin + netv2_word_inc <= 1'd1; + if (1'd1) begin + netv2_tag_port_we <= 1'd1; + netv2_word_clr <= 1'd1; + fullmemorywe_next_state <= 2'd3; + end + end + end + 2'd3: begin + netv2_interface_stb <= 1'd1; + netv2_interface_cyc <= 1'd1; + netv2_interface_we <= 1'd0; + if (netv2_interface_ack) begin + netv2_write_from_slave <= 1'd1; + netv2_word_inc <= 1'd1; + if (1'd1) begin + fullmemorywe_next_state <= 1'd1; + end else begin + fullmemorywe_next_state <= 2'd3; + end + end + end + default: begin + if ((netv2_wb_sdram_cyc & netv2_wb_sdram_stb)) begin + fullmemorywe_next_state <= 1'd1; + end + end + endcase +end +assign netv2_port_cmd_payload_addr = (netv2_interface_adr - 26'd33554432); +assign netv2_port_cmd_payload_we = netv2_interface_we; +assign netv2_port_wdata_payload_data = netv2_interface_dat_w; +assign netv2_port_wdata_payload_we = netv2_interface_sel; +assign netv2_interface_dat_r = netv2_port_rdata_payload_data; +assign netv2_port_flush = (~netv2_interface_cyc); +assign netv2_port_cmd_last = (~netv2_interface_we); +assign netv2_port_cmd_valid = ((netv2_interface_cyc & netv2_interface_stb) & (~netv2_cmd_consumed)); +assign netv2_port_wdata_valid = (((netv2_port_cmd_valid | netv2_cmd_consumed) & netv2_port_cmd_payload_we) & (~netv2_wdata_consumed)); +assign netv2_port_rdata_ready = ((netv2_port_cmd_valid | netv2_cmd_consumed) & (~netv2_port_cmd_payload_we)); +assign netv2_interface_ack = (netv2_ack_cmd & ((netv2_interface_we & netv2_ack_wdata) | ((~netv2_interface_we) & netv2_ack_rdata))); +assign netv2_ack_cmd = ((netv2_port_cmd_valid & netv2_port_cmd_ready) | netv2_cmd_consumed); +assign netv2_ack_wdata = ((netv2_port_wdata_valid & netv2_port_wdata_ready) | netv2_wdata_consumed); +assign netv2_ack_rdata = (netv2_port_rdata_valid & netv2_port_rdata_ready); +assign eth_rx_clk = eth_clk; +assign eth_tx_clk = eth_clk; +assign ethphy_reset0 = (ethphy_reset_storage | ethphy_reset1); +assign eth_rst_n = (~ethphy_reset0); +assign ethphy_counter_done = (ethphy_counter == 9'd256); +assign ethphy_counter_ce = (~ethphy_counter_done); +assign ethphy_reset1 = (~ethphy_counter_done); +assign ethphy_liteethphyrmiitx_converter_sink_valid = ethphy_liteethphyrmiitx_sink_sink_valid; +assign ethphy_liteethphyrmiitx_converter_sink_payload_data = ethphy_liteethphyrmiitx_sink_sink_payload_data; +assign ethphy_liteethphyrmiitx_sink_sink_ready = ethphy_liteethphyrmiitx_converter_sink_ready; +assign ethphy_liteethphyrmiitx_converter_source_ready = 1'd1; +assign ethphy_liteethphyrmiitx_converter_converter_sink_valid = ethphy_liteethphyrmiitx_converter_sink_valid; +assign ethphy_liteethphyrmiitx_converter_converter_sink_first = ethphy_liteethphyrmiitx_converter_sink_first; +assign ethphy_liteethphyrmiitx_converter_converter_sink_last = ethphy_liteethphyrmiitx_converter_sink_last; +assign ethphy_liteethphyrmiitx_converter_sink_ready = ethphy_liteethphyrmiitx_converter_converter_sink_ready; +always @(*) begin + ethphy_liteethphyrmiitx_converter_converter_sink_payload_data <= 8'd0; + ethphy_liteethphyrmiitx_converter_converter_sink_payload_data[1:0] <= ethphy_liteethphyrmiitx_converter_sink_payload_data[1:0]; + ethphy_liteethphyrmiitx_converter_converter_sink_payload_data[3:2] <= ethphy_liteethphyrmiitx_converter_sink_payload_data[3:2]; + ethphy_liteethphyrmiitx_converter_converter_sink_payload_data[5:4] <= ethphy_liteethphyrmiitx_converter_sink_payload_data[5:4]; + ethphy_liteethphyrmiitx_converter_converter_sink_payload_data[7:6] <= ethphy_liteethphyrmiitx_converter_sink_payload_data[7:6]; +end +assign ethphy_liteethphyrmiitx_converter_source_valid = ethphy_liteethphyrmiitx_converter_source_source_valid; +assign ethphy_liteethphyrmiitx_converter_source_first = ethphy_liteethphyrmiitx_converter_source_source_first; +assign ethphy_liteethphyrmiitx_converter_source_last = ethphy_liteethphyrmiitx_converter_source_source_last; +assign ethphy_liteethphyrmiitx_converter_source_source_ready = ethphy_liteethphyrmiitx_converter_source_ready; +assign {ethphy_liteethphyrmiitx_converter_source_payload_data} = ethphy_liteethphyrmiitx_converter_source_source_payload_data; +assign ethphy_liteethphyrmiitx_converter_source_source_valid = ethphy_liteethphyrmiitx_converter_converter_source_valid; +assign ethphy_liteethphyrmiitx_converter_converter_source_ready = ethphy_liteethphyrmiitx_converter_source_source_ready; +assign ethphy_liteethphyrmiitx_converter_source_source_first = ethphy_liteethphyrmiitx_converter_converter_source_first; +assign ethphy_liteethphyrmiitx_converter_source_source_last = ethphy_liteethphyrmiitx_converter_converter_source_last; +assign ethphy_liteethphyrmiitx_converter_source_source_payload_data = ethphy_liteethphyrmiitx_converter_converter_source_payload_data; +assign ethphy_liteethphyrmiitx_converter_converter_first = (ethphy_liteethphyrmiitx_converter_converter_mux == 1'd0); +assign ethphy_liteethphyrmiitx_converter_converter_last = (ethphy_liteethphyrmiitx_converter_converter_mux == 2'd3); +assign ethphy_liteethphyrmiitx_converter_converter_source_valid = ethphy_liteethphyrmiitx_converter_converter_sink_valid; +assign ethphy_liteethphyrmiitx_converter_converter_source_first = (ethphy_liteethphyrmiitx_converter_converter_sink_first & ethphy_liteethphyrmiitx_converter_converter_first); +assign ethphy_liteethphyrmiitx_converter_converter_source_last = (ethphy_liteethphyrmiitx_converter_converter_sink_last & ethphy_liteethphyrmiitx_converter_converter_last); +assign ethphy_liteethphyrmiitx_converter_converter_sink_ready = (ethphy_liteethphyrmiitx_converter_converter_last & ethphy_liteethphyrmiitx_converter_converter_source_ready); +always @(*) begin + ethphy_liteethphyrmiitx_converter_converter_source_payload_data <= 2'd0; + case (ethphy_liteethphyrmiitx_converter_converter_mux) + 1'd0: begin + ethphy_liteethphyrmiitx_converter_converter_source_payload_data <= ethphy_liteethphyrmiitx_converter_converter_sink_payload_data[1:0]; + end + 1'd1: begin + ethphy_liteethphyrmiitx_converter_converter_source_payload_data <= ethphy_liteethphyrmiitx_converter_converter_sink_payload_data[3:2]; + end + 2'd2: begin + ethphy_liteethphyrmiitx_converter_converter_source_payload_data <= ethphy_liteethphyrmiitx_converter_converter_sink_payload_data[5:4]; + end + default: begin + ethphy_liteethphyrmiitx_converter_converter_source_payload_data <= ethphy_liteethphyrmiitx_converter_converter_sink_payload_data[7:6]; + end + endcase +end +assign ethphy_liteethphyrmiitx_converter_converter_source_payload_valid_token_count = ethphy_liteethphyrmiitx_converter_converter_last; +assign ethphy_liteethphyrmiirx_source_source_valid = ethphy_liteethphyrmiirx_converter_source_valid; +assign ethphy_liteethphyrmiirx_converter_source_ready = ethphy_liteethphyrmiirx_source_source_ready; +assign ethphy_liteethphyrmiirx_source_source_first = ethphy_liteethphyrmiirx_converter_source_first; +assign ethphy_liteethphyrmiirx_source_source_last = ethphy_liteethphyrmiirx_converter_source_last; +assign ethphy_liteethphyrmiirx_source_source_payload_data = ethphy_liteethphyrmiirx_converter_source_payload_data; +assign ethphy_liteethphyrmiirx_converter_converter_sink_valid = ethphy_liteethphyrmiirx_converter_sink_valid0; +assign ethphy_liteethphyrmiirx_converter_converter_sink_first = ethphy_liteethphyrmiirx_converter_sink_first; +assign ethphy_liteethphyrmiirx_converter_converter_sink_last = ethphy_liteethphyrmiirx_converter_sink_last; +assign ethphy_liteethphyrmiirx_converter_sink_ready = ethphy_liteethphyrmiirx_converter_converter_sink_ready; +assign ethphy_liteethphyrmiirx_converter_converter_sink_payload_data = {ethphy_liteethphyrmiirx_converter_sink_payload_data}; +assign ethphy_liteethphyrmiirx_converter_source_valid = ethphy_liteethphyrmiirx_converter_source_source_valid; +assign ethphy_liteethphyrmiirx_converter_source_first = ethphy_liteethphyrmiirx_converter_source_source_first; +assign ethphy_liteethphyrmiirx_converter_source_last = ethphy_liteethphyrmiirx_converter_source_source_last; +assign ethphy_liteethphyrmiirx_converter_source_source_ready = ethphy_liteethphyrmiirx_converter_source_ready; +always @(*) begin + ethphy_liteethphyrmiirx_converter_source_payload_data <= 8'd0; + ethphy_liteethphyrmiirx_converter_source_payload_data[1:0] <= ethphy_liteethphyrmiirx_converter_source_source_payload_data[1:0]; + ethphy_liteethphyrmiirx_converter_source_payload_data[3:2] <= ethphy_liteethphyrmiirx_converter_source_source_payload_data[3:2]; + ethphy_liteethphyrmiirx_converter_source_payload_data[5:4] <= ethphy_liteethphyrmiirx_converter_source_source_payload_data[5:4]; + ethphy_liteethphyrmiirx_converter_source_payload_data[7:6] <= ethphy_liteethphyrmiirx_converter_source_source_payload_data[7:6]; +end +assign ethphy_liteethphyrmiirx_converter_source_source_valid = ethphy_liteethphyrmiirx_converter_converter_source_valid; +assign ethphy_liteethphyrmiirx_converter_converter_source_ready = ethphy_liteethphyrmiirx_converter_source_source_ready; +assign ethphy_liteethphyrmiirx_converter_source_source_first = ethphy_liteethphyrmiirx_converter_converter_source_first; +assign ethphy_liteethphyrmiirx_converter_source_source_last = ethphy_liteethphyrmiirx_converter_converter_source_last; +assign ethphy_liteethphyrmiirx_converter_source_source_payload_data = ethphy_liteethphyrmiirx_converter_converter_source_payload_data; +assign ethphy_liteethphyrmiirx_converter_converter_sink_ready = ((~ethphy_liteethphyrmiirx_converter_converter_strobe_all) | ethphy_liteethphyrmiirx_converter_converter_source_ready); +assign ethphy_liteethphyrmiirx_converter_converter_source_valid = ethphy_liteethphyrmiirx_converter_converter_strobe_all; +assign ethphy_liteethphyrmiirx_converter_converter_load_part = (ethphy_liteethphyrmiirx_converter_converter_sink_valid & ethphy_liteethphyrmiirx_converter_converter_sink_ready); +always @(*) begin + ethphy_liteethphyrmiirx_converter_sink_valid1 <= 1'd0; + ethphy_liteethphyrmiirx_converter_sink_data <= 2'd0; + ethphy_liteethphyrmiirx_converter_sink_last <= 1'd0; + liteethphyrmii_next_state <= 1'd0; + ethphy_liteethphyrmiirx_converter_reset <= 1'd0; + liteethphyrmii_next_state <= liteethphyrmii_state; + case (liteethphyrmii_state) + 1'd1: begin + ethphy_liteethphyrmiirx_converter_sink_valid1 <= 1'd1; + ethphy_liteethphyrmiirx_converter_sink_data <= ethphy_liteethphyrmiirx_rx_data; + if ((~(ethphy_liteethphyrmiirx_crs_dv | ethphy_liteethphyrmiirx_crs_dv_d))) begin + ethphy_liteethphyrmiirx_converter_sink_last <= 1'd1; + liteethphyrmii_next_state <= 1'd0; + end + end + default: begin + if ((ethphy_liteethphyrmiirx_crs_dv & (ethphy_liteethphyrmiirx_rx_data != 1'd0))) begin + ethphy_liteethphyrmiirx_converter_sink_valid1 <= 1'd1; + ethphy_liteethphyrmiirx_converter_sink_data <= ethphy_liteethphyrmiirx_rx_data; + liteethphyrmii_next_state <= 1'd1; + end else begin + ethphy_liteethphyrmiirx_converter_reset <= 1'd1; + end + end + endcase +end +assign eth_mdc = ethphy__w_storage[0]; +assign ethphy_data_oe = ethphy__w_storage[1]; +assign ethphy_data_w = ethphy__w_storage[2]; +assign ethcore_mac_packetizer_sink_valid = ethcore_mac_crossbar_source_valid; +assign ethcore_mac_crossbar_source_ready = ethcore_mac_packetizer_sink_ready; +assign ethcore_mac_packetizer_sink_first = ethcore_mac_crossbar_source_first; +assign ethcore_mac_packetizer_sink_last = ethcore_mac_crossbar_source_last; +assign ethcore_mac_packetizer_sink_payload_ethernet_type = ethcore_mac_crossbar_source_payload_ethernet_type; +assign ethcore_mac_packetizer_sink_payload_sender_mac = ethcore_mac_crossbar_source_payload_sender_mac; +assign ethcore_mac_packetizer_sink_payload_target_mac = ethcore_mac_crossbar_source_payload_target_mac; +assign ethcore_mac_packetizer_sink_payload_data = ethcore_mac_crossbar_source_payload_data; +assign ethcore_mac_packetizer_sink_payload_last_be = ethcore_mac_crossbar_source_payload_last_be; +assign ethcore_mac_packetizer_sink_payload_error = ethcore_mac_crossbar_source_payload_error; +assign ethcore_mac_tx_cdc_sink_valid = ethcore_mac_packetizer_source_valid; +assign ethcore_mac_packetizer_source_ready = ethcore_mac_tx_cdc_sink_ready; +assign ethcore_mac_tx_cdc_sink_first = ethcore_mac_packetizer_source_first; +assign ethcore_mac_tx_cdc_sink_last = ethcore_mac_packetizer_source_last; +assign ethcore_mac_tx_cdc_sink_payload_data = ethcore_mac_packetizer_source_payload_data; +assign ethcore_mac_tx_cdc_sink_payload_last_be = ethcore_mac_packetizer_source_payload_last_be; +assign ethcore_mac_tx_cdc_sink_payload_error = ethcore_mac_packetizer_source_payload_error; +assign ethcore_mac_depacketizer_sink_valid = ethcore_mac_rx_cdc_source_valid; +assign ethcore_mac_rx_cdc_source_ready = ethcore_mac_depacketizer_sink_ready; +assign ethcore_mac_depacketizer_sink_first = ethcore_mac_rx_cdc_source_first; +assign ethcore_mac_depacketizer_sink_last = ethcore_mac_rx_cdc_source_last; +assign ethcore_mac_depacketizer_sink_payload_data = ethcore_mac_rx_cdc_source_payload_data; +assign ethcore_mac_depacketizer_sink_payload_last_be = ethcore_mac_rx_cdc_source_payload_last_be; +assign ethcore_mac_depacketizer_sink_payload_error = ethcore_mac_rx_cdc_source_payload_error; +assign ethcore_mac_crossbar_sink_valid = ethcore_mac_depacketizer_source_valid; +assign ethcore_mac_depacketizer_source_ready = ethcore_mac_crossbar_sink_ready; +assign ethcore_mac_crossbar_sink_first = ethcore_mac_depacketizer_source_first; +assign ethcore_mac_crossbar_sink_last = ethcore_mac_depacketizer_source_last; +assign ethcore_mac_crossbar_sink_payload_ethernet_type = ethcore_mac_depacketizer_source_payload_ethernet_type; +assign ethcore_mac_crossbar_sink_payload_sender_mac = ethcore_mac_depacketizer_source_payload_sender_mac; +assign ethcore_mac_crossbar_sink_payload_target_mac = ethcore_mac_depacketizer_source_payload_target_mac; +assign ethcore_mac_crossbar_sink_payload_data = ethcore_mac_depacketizer_source_payload_data; +assign ethcore_mac_crossbar_sink_payload_last_be = ethcore_mac_depacketizer_source_payload_last_be; +assign ethcore_mac_crossbar_sink_payload_error = ethcore_mac_depacketizer_source_payload_error; +assign ethcore_mac_ps_preamble_error_i = ethcore_mac_preamble_checker_error; +assign ethcore_mac_ps_crc_error_i = ethcore_mac_liteethmaccrc32checker_error; +always @(*) begin + ethcore_mac_tx_gap_inserter_source_valid <= 1'd0; + liteethudpipcore_liteethmac_liteethmacgap_next_state <= 1'd0; + ethcore_mac_tx_gap_inserter_source_first <= 1'd0; + ethcore_mac_tx_gap_inserter_counter_liteethmacgap_next_value <= 4'd0; + ethcore_mac_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd0; + ethcore_mac_tx_gap_inserter_source_last <= 1'd0; + ethcore_mac_tx_gap_inserter_source_payload_data <= 8'd0; + ethcore_mac_tx_gap_inserter_source_payload_last_be <= 1'd0; + ethcore_mac_tx_gap_inserter_source_payload_error <= 1'd0; + ethcore_mac_tx_gap_inserter_sink_ready <= 1'd0; + liteethudpipcore_liteethmac_liteethmacgap_next_state <= liteethudpipcore_liteethmac_liteethmacgap_state; + case (liteethudpipcore_liteethmac_liteethmacgap_state) + 1'd1: begin + ethcore_mac_tx_gap_inserter_counter_liteethmacgap_next_value <= (ethcore_mac_tx_gap_inserter_counter + 1'd1); + ethcore_mac_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1; + if ((ethcore_mac_tx_gap_inserter_counter == 4'd11)) begin + liteethudpipcore_liteethmac_liteethmacgap_next_state <= 1'd0; + end + end + default: begin + ethcore_mac_tx_gap_inserter_counter_liteethmacgap_next_value <= 1'd0; + ethcore_mac_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1; + ethcore_mac_tx_gap_inserter_source_valid <= ethcore_mac_tx_gap_inserter_sink_valid; + ethcore_mac_tx_gap_inserter_sink_ready <= ethcore_mac_tx_gap_inserter_source_ready; + ethcore_mac_tx_gap_inserter_source_first <= ethcore_mac_tx_gap_inserter_sink_first; + ethcore_mac_tx_gap_inserter_source_last <= ethcore_mac_tx_gap_inserter_sink_last; + ethcore_mac_tx_gap_inserter_source_payload_data <= ethcore_mac_tx_gap_inserter_sink_payload_data; + ethcore_mac_tx_gap_inserter_source_payload_last_be <= ethcore_mac_tx_gap_inserter_sink_payload_last_be; + ethcore_mac_tx_gap_inserter_source_payload_error <= ethcore_mac_tx_gap_inserter_sink_payload_error; + if (((ethcore_mac_tx_gap_inserter_sink_valid & ethcore_mac_tx_gap_inserter_sink_last) & ethcore_mac_tx_gap_inserter_sink_ready)) begin + liteethudpipcore_liteethmac_liteethmacgap_next_state <= 1'd1; + end + end + endcase +end +assign ethcore_mac_preamble_inserter_source_payload_last_be = ethcore_mac_preamble_inserter_sink_payload_last_be; +always @(*) begin + ethcore_mac_preamble_inserter_count_liteethmacpreambleinserter_next_value <= 3'd0; + ethcore_mac_preamble_inserter_source_valid <= 1'd0; + ethcore_mac_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd0; + ethcore_mac_preamble_inserter_source_first <= 1'd0; + ethcore_mac_preamble_inserter_source_last <= 1'd0; + ethcore_mac_preamble_inserter_source_payload_data <= 8'd0; + ethcore_mac_preamble_inserter_source_payload_error <= 1'd0; + ethcore_mac_preamble_inserter_sink_ready <= 1'd0; + liteethudpipcore_liteethmac_liteethmacpreambleinserter_next_state <= 2'd0; + ethcore_mac_preamble_inserter_source_payload_data <= ethcore_mac_preamble_inserter_sink_payload_data; + liteethudpipcore_liteethmac_liteethmacpreambleinserter_next_state <= liteethudpipcore_liteethmac_liteethmacpreambleinserter_state; + case (liteethudpipcore_liteethmac_liteethmacpreambleinserter_state) + 1'd1: begin + ethcore_mac_preamble_inserter_source_valid <= 1'd1; + case (ethcore_mac_preamble_inserter_count) + 1'd0: begin + ethcore_mac_preamble_inserter_source_payload_data <= ethcore_mac_preamble_inserter_preamble[7:0]; + end + 1'd1: begin + ethcore_mac_preamble_inserter_source_payload_data <= ethcore_mac_preamble_inserter_preamble[15:8]; + end + 2'd2: begin + ethcore_mac_preamble_inserter_source_payload_data <= ethcore_mac_preamble_inserter_preamble[23:16]; + end + 2'd3: begin + ethcore_mac_preamble_inserter_source_payload_data <= ethcore_mac_preamble_inserter_preamble[31:24]; + end + 3'd4: begin + ethcore_mac_preamble_inserter_source_payload_data <= ethcore_mac_preamble_inserter_preamble[39:32]; + end + 3'd5: begin + ethcore_mac_preamble_inserter_source_payload_data <= ethcore_mac_preamble_inserter_preamble[47:40]; + end + 3'd6: begin + ethcore_mac_preamble_inserter_source_payload_data <= ethcore_mac_preamble_inserter_preamble[55:48]; + end + default: begin + ethcore_mac_preamble_inserter_source_payload_data <= ethcore_mac_preamble_inserter_preamble[63:56]; + end + endcase + if (ethcore_mac_preamble_inserter_source_ready) begin + if ((ethcore_mac_preamble_inserter_count == 3'd7)) begin + liteethudpipcore_liteethmac_liteethmacpreambleinserter_next_state <= 2'd2; + end else begin + ethcore_mac_preamble_inserter_count_liteethmacpreambleinserter_next_value <= (ethcore_mac_preamble_inserter_count + 1'd1); + ethcore_mac_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1; + end + end + end + 2'd2: begin + ethcore_mac_preamble_inserter_source_valid <= ethcore_mac_preamble_inserter_sink_valid; + ethcore_mac_preamble_inserter_sink_ready <= ethcore_mac_preamble_inserter_source_ready; + ethcore_mac_preamble_inserter_source_first <= ethcore_mac_preamble_inserter_sink_first; + ethcore_mac_preamble_inserter_source_last <= ethcore_mac_preamble_inserter_sink_last; + ethcore_mac_preamble_inserter_source_payload_error <= ethcore_mac_preamble_inserter_sink_payload_error; + if (((ethcore_mac_preamble_inserter_sink_valid & ethcore_mac_preamble_inserter_sink_last) & ethcore_mac_preamble_inserter_source_ready)) begin + liteethudpipcore_liteethmac_liteethmacpreambleinserter_next_state <= 1'd0; + end + end + default: begin + ethcore_mac_preamble_inserter_sink_ready <= 1'd1; + ethcore_mac_preamble_inserter_count_liteethmacpreambleinserter_next_value <= 1'd0; + ethcore_mac_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1; + if (ethcore_mac_preamble_inserter_sink_valid) begin + ethcore_mac_preamble_inserter_sink_ready <= 1'd0; + liteethudpipcore_liteethmac_liteethmacpreambleinserter_next_state <= 1'd1; + end + end + endcase +end +assign ethcore_mac_preamble_checker_source_payload_data = ethcore_mac_preamble_checker_sink_payload_data; +assign ethcore_mac_preamble_checker_source_payload_last_be = ethcore_mac_preamble_checker_sink_payload_last_be; +always @(*) begin + ethcore_mac_preamble_checker_sink_ready <= 1'd0; + ethcore_mac_preamble_checker_source_payload_error <= 1'd0; + ethcore_mac_preamble_checker_source_first <= 1'd0; + ethcore_mac_preamble_checker_error <= 1'd0; + ethcore_mac_preamble_checker_source_valid <= 1'd0; + liteethudpipcore_liteethmac_liteethmacpreamblechecker_next_state <= 1'd0; + ethcore_mac_preamble_checker_source_last <= 1'd0; + liteethudpipcore_liteethmac_liteethmacpreamblechecker_next_state <= liteethudpipcore_liteethmac_liteethmacpreamblechecker_state; + case (liteethudpipcore_liteethmac_liteethmacpreamblechecker_state) + 1'd1: begin + ethcore_mac_preamble_checker_source_valid <= ethcore_mac_preamble_checker_sink_valid; + ethcore_mac_preamble_checker_sink_ready <= ethcore_mac_preamble_checker_source_ready; + ethcore_mac_preamble_checker_source_first <= ethcore_mac_preamble_checker_sink_first; + ethcore_mac_preamble_checker_source_last <= ethcore_mac_preamble_checker_sink_last; + ethcore_mac_preamble_checker_source_payload_error <= ethcore_mac_preamble_checker_sink_payload_error; + if (((ethcore_mac_preamble_checker_source_valid & ethcore_mac_preamble_checker_source_last) & ethcore_mac_preamble_checker_source_ready)) begin + liteethudpipcore_liteethmac_liteethmacpreamblechecker_next_state <= 1'd0; + end + end + default: begin + ethcore_mac_preamble_checker_sink_ready <= 1'd1; + if (((ethcore_mac_preamble_checker_sink_valid & (~ethcore_mac_preamble_checker_sink_last)) & (ethcore_mac_preamble_checker_sink_payload_data == 8'd213))) begin + liteethudpipcore_liteethmac_liteethmacpreamblechecker_next_state <= 1'd1; + end + if ((ethcore_mac_preamble_checker_sink_valid & ethcore_mac_preamble_checker_sink_last)) begin + ethcore_mac_preamble_checker_error <= 1'd1; + end + end + endcase +end +assign ethcore_mac_liteethmaccrc32inserter_cnt_done = (ethcore_mac_liteethmaccrc32inserter_cnt == 1'd0); +assign ethcore_mac_liteethmaccrc32inserter_sink_valid = ethcore_mac_crc32_inserter_source_valid; +assign ethcore_mac_crc32_inserter_source_ready = ethcore_mac_liteethmaccrc32inserter_sink_ready; +assign ethcore_mac_liteethmaccrc32inserter_sink_first = ethcore_mac_crc32_inserter_source_first; +assign ethcore_mac_liteethmaccrc32inserter_sink_last = ethcore_mac_crc32_inserter_source_last; +assign ethcore_mac_liteethmaccrc32inserter_sink_payload_data = ethcore_mac_crc32_inserter_source_payload_data; +assign ethcore_mac_liteethmaccrc32inserter_sink_payload_last_be = ethcore_mac_crc32_inserter_source_payload_last_be; +assign ethcore_mac_liteethmaccrc32inserter_sink_payload_error = ethcore_mac_crc32_inserter_source_payload_error; +assign ethcore_mac_liteethmaccrc32inserter_data1 = ethcore_mac_liteethmaccrc32inserter_data0; +assign ethcore_mac_liteethmaccrc32inserter_last = ethcore_mac_liteethmaccrc32inserter_reg; +assign ethcore_mac_liteethmaccrc32inserter_value = (~{ethcore_mac_liteethmaccrc32inserter_reg[0], ethcore_mac_liteethmaccrc32inserter_reg[1], ethcore_mac_liteethmaccrc32inserter_reg[2], ethcore_mac_liteethmaccrc32inserter_reg[3], ethcore_mac_liteethmaccrc32inserter_reg[4], ethcore_mac_liteethmaccrc32inserter_reg[5], ethcore_mac_liteethmaccrc32inserter_reg[6], ethcore_mac_liteethmaccrc32inserter_reg[7], ethcore_mac_liteethmaccrc32inserter_reg[8], ethcore_mac_liteethmaccrc32inserter_reg[9], ethcore_mac_liteethmaccrc32inserter_reg[10], ethcore_mac_liteethmaccrc32inserter_reg[11], ethcore_mac_liteethmaccrc32inserter_reg[12], ethcore_mac_liteethmaccrc32inserter_reg[13], ethcore_mac_liteethmaccrc32inserter_reg[14], ethcore_mac_liteethmaccrc32inserter_reg[15], ethcore_mac_liteethmaccrc32inserter_reg[16], ethcore_mac_liteethmaccrc32inserter_reg[17], ethcore_mac_liteethmaccrc32inserter_reg[18], ethcore_mac_liteethmaccrc32inserter_reg[19], ethcore_mac_liteethmaccrc32inserter_reg[20], ethcore_mac_liteethmaccrc32inserter_reg[21], ethcore_mac_liteethmaccrc32inserter_reg[22], ethcore_mac_liteethmaccrc32inserter_reg[23], ethcore_mac_liteethmaccrc32inserter_reg[24], ethcore_mac_liteethmaccrc32inserter_reg[25], ethcore_mac_liteethmaccrc32inserter_reg[26], ethcore_mac_liteethmaccrc32inserter_reg[27], ethcore_mac_liteethmaccrc32inserter_reg[28], ethcore_mac_liteethmaccrc32inserter_reg[29], ethcore_mac_liteethmaccrc32inserter_reg[30], ethcore_mac_liteethmaccrc32inserter_reg[31]}); +assign ethcore_mac_liteethmaccrc32inserter_error = (ethcore_mac_liteethmaccrc32inserter_next != 32'd3338984827); +always @(*) begin + ethcore_mac_liteethmaccrc32inserter_next <= 32'd0; + ethcore_mac_liteethmaccrc32inserter_next[0] <= (((ethcore_mac_liteethmaccrc32inserter_last[24] ^ ethcore_mac_liteethmaccrc32inserter_last[30]) ^ ethcore_mac_liteethmaccrc32inserter_data1[1]) ^ ethcore_mac_liteethmaccrc32inserter_data1[7]); + ethcore_mac_liteethmaccrc32inserter_next[1] <= (((((((ethcore_mac_liteethmaccrc32inserter_last[25] ^ ethcore_mac_liteethmaccrc32inserter_last[31]) ^ ethcore_mac_liteethmaccrc32inserter_data1[0]) ^ ethcore_mac_liteethmaccrc32inserter_data1[6]) ^ ethcore_mac_liteethmaccrc32inserter_last[24]) ^ ethcore_mac_liteethmaccrc32inserter_last[30]) ^ ethcore_mac_liteethmaccrc32inserter_data1[1]) ^ ethcore_mac_liteethmaccrc32inserter_data1[7]); + ethcore_mac_liteethmaccrc32inserter_next[2] <= (((((((((ethcore_mac_liteethmaccrc32inserter_last[26] ^ ethcore_mac_liteethmaccrc32inserter_data1[5]) ^ ethcore_mac_liteethmaccrc32inserter_last[25]) ^ ethcore_mac_liteethmaccrc32inserter_last[31]) ^ ethcore_mac_liteethmaccrc32inserter_data1[0]) ^ ethcore_mac_liteethmaccrc32inserter_data1[6]) ^ ethcore_mac_liteethmaccrc32inserter_last[24]) ^ ethcore_mac_liteethmaccrc32inserter_last[30]) ^ ethcore_mac_liteethmaccrc32inserter_data1[1]) ^ ethcore_mac_liteethmaccrc32inserter_data1[7]); + ethcore_mac_liteethmaccrc32inserter_next[3] <= (((((((ethcore_mac_liteethmaccrc32inserter_last[27] ^ ethcore_mac_liteethmaccrc32inserter_data1[4]) ^ ethcore_mac_liteethmaccrc32inserter_last[26]) ^ ethcore_mac_liteethmaccrc32inserter_data1[5]) ^ ethcore_mac_liteethmaccrc32inserter_last[25]) ^ ethcore_mac_liteethmaccrc32inserter_last[31]) ^ ethcore_mac_liteethmaccrc32inserter_data1[0]) ^ ethcore_mac_liteethmaccrc32inserter_data1[6]); + ethcore_mac_liteethmaccrc32inserter_next[4] <= (((((((((ethcore_mac_liteethmaccrc32inserter_last[28] ^ ethcore_mac_liteethmaccrc32inserter_data1[3]) ^ ethcore_mac_liteethmaccrc32inserter_last[27]) ^ ethcore_mac_liteethmaccrc32inserter_data1[4]) ^ ethcore_mac_liteethmaccrc32inserter_last[26]) ^ ethcore_mac_liteethmaccrc32inserter_data1[5]) ^ ethcore_mac_liteethmaccrc32inserter_last[24]) ^ ethcore_mac_liteethmaccrc32inserter_last[30]) ^ ethcore_mac_liteethmaccrc32inserter_data1[1]) ^ ethcore_mac_liteethmaccrc32inserter_data1[7]); + ethcore_mac_liteethmaccrc32inserter_next[5] <= (((((((((((((ethcore_mac_liteethmaccrc32inserter_last[29] ^ ethcore_mac_liteethmaccrc32inserter_data1[2]) ^ ethcore_mac_liteethmaccrc32inserter_last[28]) ^ ethcore_mac_liteethmaccrc32inserter_data1[3]) ^ ethcore_mac_liteethmaccrc32inserter_last[27]) ^ ethcore_mac_liteethmaccrc32inserter_data1[4]) ^ ethcore_mac_liteethmaccrc32inserter_last[25]) ^ ethcore_mac_liteethmaccrc32inserter_last[31]) ^ ethcore_mac_liteethmaccrc32inserter_data1[0]) ^ ethcore_mac_liteethmaccrc32inserter_data1[6]) ^ ethcore_mac_liteethmaccrc32inserter_last[24]) ^ ethcore_mac_liteethmaccrc32inserter_last[30]) ^ ethcore_mac_liteethmaccrc32inserter_data1[1]) ^ ethcore_mac_liteethmaccrc32inserter_data1[7]); + ethcore_mac_liteethmaccrc32inserter_next[6] <= (((((((((((ethcore_mac_liteethmaccrc32inserter_last[30] ^ ethcore_mac_liteethmaccrc32inserter_data1[1]) ^ ethcore_mac_liteethmaccrc32inserter_last[29]) ^ ethcore_mac_liteethmaccrc32inserter_data1[2]) ^ ethcore_mac_liteethmaccrc32inserter_last[28]) ^ ethcore_mac_liteethmaccrc32inserter_data1[3]) ^ ethcore_mac_liteethmaccrc32inserter_last[26]) ^ ethcore_mac_liteethmaccrc32inserter_data1[5]) ^ ethcore_mac_liteethmaccrc32inserter_last[25]) ^ ethcore_mac_liteethmaccrc32inserter_last[31]) ^ ethcore_mac_liteethmaccrc32inserter_data1[0]) ^ ethcore_mac_liteethmaccrc32inserter_data1[6]); + ethcore_mac_liteethmaccrc32inserter_next[7] <= (((((((((ethcore_mac_liteethmaccrc32inserter_last[31] ^ ethcore_mac_liteethmaccrc32inserter_data1[0]) ^ ethcore_mac_liteethmaccrc32inserter_last[29]) ^ ethcore_mac_liteethmaccrc32inserter_data1[2]) ^ ethcore_mac_liteethmaccrc32inserter_last[27]) ^ ethcore_mac_liteethmaccrc32inserter_data1[4]) ^ ethcore_mac_liteethmaccrc32inserter_last[26]) ^ ethcore_mac_liteethmaccrc32inserter_data1[5]) ^ ethcore_mac_liteethmaccrc32inserter_last[24]) ^ ethcore_mac_liteethmaccrc32inserter_data1[7]); + ethcore_mac_liteethmaccrc32inserter_next[8] <= ((((((((ethcore_mac_liteethmaccrc32inserter_last[0] ^ ethcore_mac_liteethmaccrc32inserter_last[28]) ^ ethcore_mac_liteethmaccrc32inserter_data1[3]) ^ ethcore_mac_liteethmaccrc32inserter_last[27]) ^ ethcore_mac_liteethmaccrc32inserter_data1[4]) ^ ethcore_mac_liteethmaccrc32inserter_last[25]) ^ ethcore_mac_liteethmaccrc32inserter_data1[6]) ^ ethcore_mac_liteethmaccrc32inserter_last[24]) ^ ethcore_mac_liteethmaccrc32inserter_data1[7]); + ethcore_mac_liteethmaccrc32inserter_next[9] <= ((((((((ethcore_mac_liteethmaccrc32inserter_last[1] ^ ethcore_mac_liteethmaccrc32inserter_last[29]) ^ ethcore_mac_liteethmaccrc32inserter_data1[2]) ^ ethcore_mac_liteethmaccrc32inserter_last[28]) ^ ethcore_mac_liteethmaccrc32inserter_data1[3]) ^ ethcore_mac_liteethmaccrc32inserter_last[26]) ^ ethcore_mac_liteethmaccrc32inserter_data1[5]) ^ ethcore_mac_liteethmaccrc32inserter_last[25]) ^ ethcore_mac_liteethmaccrc32inserter_data1[6]); + ethcore_mac_liteethmaccrc32inserter_next[10] <= ((((((((ethcore_mac_liteethmaccrc32inserter_last[2] ^ ethcore_mac_liteethmaccrc32inserter_last[29]) ^ ethcore_mac_liteethmaccrc32inserter_data1[2]) ^ ethcore_mac_liteethmaccrc32inserter_last[27]) ^ ethcore_mac_liteethmaccrc32inserter_data1[4]) ^ ethcore_mac_liteethmaccrc32inserter_last[26]) ^ ethcore_mac_liteethmaccrc32inserter_data1[5]) ^ ethcore_mac_liteethmaccrc32inserter_last[24]) ^ ethcore_mac_liteethmaccrc32inserter_data1[7]); + ethcore_mac_liteethmaccrc32inserter_next[11] <= ((((((((ethcore_mac_liteethmaccrc32inserter_last[3] ^ ethcore_mac_liteethmaccrc32inserter_last[28]) ^ ethcore_mac_liteethmaccrc32inserter_data1[3]) ^ ethcore_mac_liteethmaccrc32inserter_last[27]) ^ ethcore_mac_liteethmaccrc32inserter_data1[4]) ^ ethcore_mac_liteethmaccrc32inserter_last[25]) ^ ethcore_mac_liteethmaccrc32inserter_data1[6]) ^ ethcore_mac_liteethmaccrc32inserter_last[24]) ^ ethcore_mac_liteethmaccrc32inserter_data1[7]); + ethcore_mac_liteethmaccrc32inserter_next[12] <= ((((((((((((ethcore_mac_liteethmaccrc32inserter_last[4] ^ ethcore_mac_liteethmaccrc32inserter_last[29]) ^ ethcore_mac_liteethmaccrc32inserter_data1[2]) ^ ethcore_mac_liteethmaccrc32inserter_last[28]) ^ ethcore_mac_liteethmaccrc32inserter_data1[3]) ^ ethcore_mac_liteethmaccrc32inserter_last[26]) ^ ethcore_mac_liteethmaccrc32inserter_data1[5]) ^ ethcore_mac_liteethmaccrc32inserter_last[25]) ^ ethcore_mac_liteethmaccrc32inserter_data1[6]) ^ ethcore_mac_liteethmaccrc32inserter_last[24]) ^ ethcore_mac_liteethmaccrc32inserter_last[30]) ^ ethcore_mac_liteethmaccrc32inserter_data1[1]) ^ ethcore_mac_liteethmaccrc32inserter_data1[7]); + ethcore_mac_liteethmaccrc32inserter_next[13] <= ((((((((((((ethcore_mac_liteethmaccrc32inserter_last[5] ^ ethcore_mac_liteethmaccrc32inserter_last[30]) ^ ethcore_mac_liteethmaccrc32inserter_data1[1]) ^ ethcore_mac_liteethmaccrc32inserter_last[29]) ^ ethcore_mac_liteethmaccrc32inserter_data1[2]) ^ ethcore_mac_liteethmaccrc32inserter_last[27]) ^ ethcore_mac_liteethmaccrc32inserter_data1[4]) ^ ethcore_mac_liteethmaccrc32inserter_last[26]) ^ ethcore_mac_liteethmaccrc32inserter_data1[5]) ^ ethcore_mac_liteethmaccrc32inserter_last[25]) ^ ethcore_mac_liteethmaccrc32inserter_last[31]) ^ ethcore_mac_liteethmaccrc32inserter_data1[0]) ^ ethcore_mac_liteethmaccrc32inserter_data1[6]); + ethcore_mac_liteethmaccrc32inserter_next[14] <= ((((((((((ethcore_mac_liteethmaccrc32inserter_last[6] ^ ethcore_mac_liteethmaccrc32inserter_last[31]) ^ ethcore_mac_liteethmaccrc32inserter_data1[0]) ^ ethcore_mac_liteethmaccrc32inserter_last[30]) ^ ethcore_mac_liteethmaccrc32inserter_data1[1]) ^ ethcore_mac_liteethmaccrc32inserter_last[28]) ^ ethcore_mac_liteethmaccrc32inserter_data1[3]) ^ ethcore_mac_liteethmaccrc32inserter_last[27]) ^ ethcore_mac_liteethmaccrc32inserter_data1[4]) ^ ethcore_mac_liteethmaccrc32inserter_last[26]) ^ ethcore_mac_liteethmaccrc32inserter_data1[5]); + ethcore_mac_liteethmaccrc32inserter_next[15] <= ((((((((ethcore_mac_liteethmaccrc32inserter_last[7] ^ ethcore_mac_liteethmaccrc32inserter_last[31]) ^ ethcore_mac_liteethmaccrc32inserter_data1[0]) ^ ethcore_mac_liteethmaccrc32inserter_last[29]) ^ ethcore_mac_liteethmaccrc32inserter_data1[2]) ^ ethcore_mac_liteethmaccrc32inserter_last[28]) ^ ethcore_mac_liteethmaccrc32inserter_data1[3]) ^ ethcore_mac_liteethmaccrc32inserter_last[27]) ^ ethcore_mac_liteethmaccrc32inserter_data1[4]); + ethcore_mac_liteethmaccrc32inserter_next[16] <= ((((((ethcore_mac_liteethmaccrc32inserter_last[8] ^ ethcore_mac_liteethmaccrc32inserter_last[29]) ^ ethcore_mac_liteethmaccrc32inserter_data1[2]) ^ ethcore_mac_liteethmaccrc32inserter_last[28]) ^ ethcore_mac_liteethmaccrc32inserter_data1[3]) ^ ethcore_mac_liteethmaccrc32inserter_last[24]) ^ ethcore_mac_liteethmaccrc32inserter_data1[7]); + ethcore_mac_liteethmaccrc32inserter_next[17] <= ((((((ethcore_mac_liteethmaccrc32inserter_last[9] ^ ethcore_mac_liteethmaccrc32inserter_last[30]) ^ ethcore_mac_liteethmaccrc32inserter_data1[1]) ^ ethcore_mac_liteethmaccrc32inserter_last[29]) ^ ethcore_mac_liteethmaccrc32inserter_data1[2]) ^ ethcore_mac_liteethmaccrc32inserter_last[25]) ^ ethcore_mac_liteethmaccrc32inserter_data1[6]); + ethcore_mac_liteethmaccrc32inserter_next[18] <= ((((((ethcore_mac_liteethmaccrc32inserter_last[10] ^ ethcore_mac_liteethmaccrc32inserter_last[31]) ^ ethcore_mac_liteethmaccrc32inserter_data1[0]) ^ ethcore_mac_liteethmaccrc32inserter_last[30]) ^ ethcore_mac_liteethmaccrc32inserter_data1[1]) ^ ethcore_mac_liteethmaccrc32inserter_last[26]) ^ ethcore_mac_liteethmaccrc32inserter_data1[5]); + ethcore_mac_liteethmaccrc32inserter_next[19] <= ((((ethcore_mac_liteethmaccrc32inserter_last[11] ^ ethcore_mac_liteethmaccrc32inserter_last[31]) ^ ethcore_mac_liteethmaccrc32inserter_data1[0]) ^ ethcore_mac_liteethmaccrc32inserter_last[27]) ^ ethcore_mac_liteethmaccrc32inserter_data1[4]); + ethcore_mac_liteethmaccrc32inserter_next[20] <= ((ethcore_mac_liteethmaccrc32inserter_last[12] ^ ethcore_mac_liteethmaccrc32inserter_last[28]) ^ ethcore_mac_liteethmaccrc32inserter_data1[3]); + ethcore_mac_liteethmaccrc32inserter_next[21] <= ((ethcore_mac_liteethmaccrc32inserter_last[13] ^ ethcore_mac_liteethmaccrc32inserter_last[29]) ^ ethcore_mac_liteethmaccrc32inserter_data1[2]); + ethcore_mac_liteethmaccrc32inserter_next[22] <= ((ethcore_mac_liteethmaccrc32inserter_last[14] ^ ethcore_mac_liteethmaccrc32inserter_last[24]) ^ ethcore_mac_liteethmaccrc32inserter_data1[7]); + ethcore_mac_liteethmaccrc32inserter_next[23] <= ((((((ethcore_mac_liteethmaccrc32inserter_last[15] ^ ethcore_mac_liteethmaccrc32inserter_last[25]) ^ ethcore_mac_liteethmaccrc32inserter_data1[6]) ^ ethcore_mac_liteethmaccrc32inserter_last[24]) ^ ethcore_mac_liteethmaccrc32inserter_last[30]) ^ ethcore_mac_liteethmaccrc32inserter_data1[1]) ^ ethcore_mac_liteethmaccrc32inserter_data1[7]); + ethcore_mac_liteethmaccrc32inserter_next[24] <= ((((((ethcore_mac_liteethmaccrc32inserter_last[16] ^ ethcore_mac_liteethmaccrc32inserter_last[26]) ^ ethcore_mac_liteethmaccrc32inserter_data1[5]) ^ ethcore_mac_liteethmaccrc32inserter_last[25]) ^ ethcore_mac_liteethmaccrc32inserter_last[31]) ^ ethcore_mac_liteethmaccrc32inserter_data1[0]) ^ ethcore_mac_liteethmaccrc32inserter_data1[6]); + ethcore_mac_liteethmaccrc32inserter_next[25] <= ((((ethcore_mac_liteethmaccrc32inserter_last[17] ^ ethcore_mac_liteethmaccrc32inserter_last[27]) ^ ethcore_mac_liteethmaccrc32inserter_data1[4]) ^ ethcore_mac_liteethmaccrc32inserter_last[26]) ^ ethcore_mac_liteethmaccrc32inserter_data1[5]); + ethcore_mac_liteethmaccrc32inserter_next[26] <= ((((((((ethcore_mac_liteethmaccrc32inserter_last[18] ^ ethcore_mac_liteethmaccrc32inserter_last[28]) ^ ethcore_mac_liteethmaccrc32inserter_data1[3]) ^ ethcore_mac_liteethmaccrc32inserter_last[27]) ^ ethcore_mac_liteethmaccrc32inserter_data1[4]) ^ ethcore_mac_liteethmaccrc32inserter_last[24]) ^ ethcore_mac_liteethmaccrc32inserter_last[30]) ^ ethcore_mac_liteethmaccrc32inserter_data1[1]) ^ ethcore_mac_liteethmaccrc32inserter_data1[7]); + ethcore_mac_liteethmaccrc32inserter_next[27] <= ((((((((ethcore_mac_liteethmaccrc32inserter_last[19] ^ ethcore_mac_liteethmaccrc32inserter_last[29]) ^ ethcore_mac_liteethmaccrc32inserter_data1[2]) ^ ethcore_mac_liteethmaccrc32inserter_last[28]) ^ ethcore_mac_liteethmaccrc32inserter_data1[3]) ^ ethcore_mac_liteethmaccrc32inserter_last[25]) ^ ethcore_mac_liteethmaccrc32inserter_last[31]) ^ ethcore_mac_liteethmaccrc32inserter_data1[0]) ^ ethcore_mac_liteethmaccrc32inserter_data1[6]); + ethcore_mac_liteethmaccrc32inserter_next[28] <= ((((((ethcore_mac_liteethmaccrc32inserter_last[20] ^ ethcore_mac_liteethmaccrc32inserter_last[30]) ^ ethcore_mac_liteethmaccrc32inserter_data1[1]) ^ ethcore_mac_liteethmaccrc32inserter_last[29]) ^ ethcore_mac_liteethmaccrc32inserter_data1[2]) ^ ethcore_mac_liteethmaccrc32inserter_last[26]) ^ ethcore_mac_liteethmaccrc32inserter_data1[5]); + ethcore_mac_liteethmaccrc32inserter_next[29] <= ((((((ethcore_mac_liteethmaccrc32inserter_last[21] ^ ethcore_mac_liteethmaccrc32inserter_last[31]) ^ ethcore_mac_liteethmaccrc32inserter_data1[0]) ^ ethcore_mac_liteethmaccrc32inserter_last[30]) ^ ethcore_mac_liteethmaccrc32inserter_data1[1]) ^ ethcore_mac_liteethmaccrc32inserter_last[27]) ^ ethcore_mac_liteethmaccrc32inserter_data1[4]); + ethcore_mac_liteethmaccrc32inserter_next[30] <= ((((ethcore_mac_liteethmaccrc32inserter_last[22] ^ ethcore_mac_liteethmaccrc32inserter_last[31]) ^ ethcore_mac_liteethmaccrc32inserter_data1[0]) ^ ethcore_mac_liteethmaccrc32inserter_last[28]) ^ ethcore_mac_liteethmaccrc32inserter_data1[3]); + ethcore_mac_liteethmaccrc32inserter_next[31] <= ((ethcore_mac_liteethmaccrc32inserter_last[23] ^ ethcore_mac_liteethmaccrc32inserter_last[29]) ^ ethcore_mac_liteethmaccrc32inserter_data1[2]); +end +always @(*) begin + ethcore_mac_liteethmaccrc32inserter_source_valid <= 1'd0; + ethcore_mac_liteethmaccrc32inserter_source_first <= 1'd0; + ethcore_mac_liteethmaccrc32inserter_source_last <= 1'd0; + ethcore_mac_liteethmaccrc32inserter_source_payload_data <= 8'd0; + ethcore_mac_liteethmaccrc32inserter_source_payload_last_be <= 1'd0; + ethcore_mac_liteethmaccrc32inserter_source_payload_error <= 1'd0; + liteethudpipcore_liteethmac_liteethmaccrc32inserter_next_state <= 2'd0; + ethcore_mac_liteethmaccrc32inserter_data0 <= 8'd0; + ethcore_mac_liteethmaccrc32inserter_is_ongoing0 <= 1'd0; + ethcore_mac_liteethmaccrc32inserter_sink_ready <= 1'd0; + ethcore_mac_liteethmaccrc32inserter_is_ongoing1 <= 1'd0; + ethcore_mac_liteethmaccrc32inserter_ce <= 1'd0; + ethcore_mac_liteethmaccrc32inserter_reset <= 1'd0; + liteethudpipcore_liteethmac_liteethmaccrc32inserter_next_state <= liteethudpipcore_liteethmac_liteethmaccrc32inserter_state; + case (liteethudpipcore_liteethmac_liteethmaccrc32inserter_state) + 1'd1: begin + ethcore_mac_liteethmaccrc32inserter_ce <= (ethcore_mac_liteethmaccrc32inserter_sink_valid & ethcore_mac_liteethmaccrc32inserter_source_ready); + ethcore_mac_liteethmaccrc32inserter_data0 <= ethcore_mac_liteethmaccrc32inserter_sink_payload_data; + ethcore_mac_liteethmaccrc32inserter_source_valid <= ethcore_mac_liteethmaccrc32inserter_sink_valid; + ethcore_mac_liteethmaccrc32inserter_sink_ready <= ethcore_mac_liteethmaccrc32inserter_source_ready; + ethcore_mac_liteethmaccrc32inserter_source_first <= ethcore_mac_liteethmaccrc32inserter_sink_first; + ethcore_mac_liteethmaccrc32inserter_source_last <= ethcore_mac_liteethmaccrc32inserter_sink_last; + ethcore_mac_liteethmaccrc32inserter_source_payload_data <= ethcore_mac_liteethmaccrc32inserter_sink_payload_data; + ethcore_mac_liteethmaccrc32inserter_source_payload_last_be <= ethcore_mac_liteethmaccrc32inserter_sink_payload_last_be; + ethcore_mac_liteethmaccrc32inserter_source_payload_error <= ethcore_mac_liteethmaccrc32inserter_sink_payload_error; + ethcore_mac_liteethmaccrc32inserter_source_last <= 1'd0; + if (((ethcore_mac_liteethmaccrc32inserter_sink_valid & ethcore_mac_liteethmaccrc32inserter_sink_last) & ethcore_mac_liteethmaccrc32inserter_source_ready)) begin + liteethudpipcore_liteethmac_liteethmaccrc32inserter_next_state <= 2'd2; + end + end + 2'd2: begin + ethcore_mac_liteethmaccrc32inserter_source_valid <= 1'd1; + case (ethcore_mac_liteethmaccrc32inserter_cnt) + 1'd0: begin + ethcore_mac_liteethmaccrc32inserter_source_payload_data <= ethcore_mac_liteethmaccrc32inserter_value[31:24]; + end + 1'd1: begin + ethcore_mac_liteethmaccrc32inserter_source_payload_data <= ethcore_mac_liteethmaccrc32inserter_value[23:16]; + end + 2'd2: begin + ethcore_mac_liteethmaccrc32inserter_source_payload_data <= ethcore_mac_liteethmaccrc32inserter_value[15:8]; + end + default: begin + ethcore_mac_liteethmaccrc32inserter_source_payload_data <= ethcore_mac_liteethmaccrc32inserter_value[7:0]; + end + endcase + if (ethcore_mac_liteethmaccrc32inserter_cnt_done) begin + ethcore_mac_liteethmaccrc32inserter_source_last <= 1'd1; + if (ethcore_mac_liteethmaccrc32inserter_source_ready) begin + liteethudpipcore_liteethmac_liteethmaccrc32inserter_next_state <= 1'd0; + end + end + ethcore_mac_liteethmaccrc32inserter_is_ongoing1 <= 1'd1; + end + default: begin + ethcore_mac_liteethmaccrc32inserter_reset <= 1'd1; + ethcore_mac_liteethmaccrc32inserter_sink_ready <= 1'd1; + if (ethcore_mac_liteethmaccrc32inserter_sink_valid) begin + ethcore_mac_liteethmaccrc32inserter_sink_ready <= 1'd0; + liteethudpipcore_liteethmac_liteethmaccrc32inserter_next_state <= 1'd1; + end + ethcore_mac_liteethmaccrc32inserter_is_ongoing0 <= 1'd1; + end + endcase +end +assign ethcore_mac_crc32_inserter_sink_ready = ((~ethcore_mac_crc32_inserter_source_valid) | ethcore_mac_crc32_inserter_source_ready); +assign ethcore_mac_liteethmaccrc32checker_fifo_full = (ethcore_mac_liteethmaccrc32checker_syncfifo_level == 3'd4); +assign ethcore_mac_liteethmaccrc32checker_fifo_in = (ethcore_mac_liteethmaccrc32checker_sink_sink_valid & ((~ethcore_mac_liteethmaccrc32checker_fifo_full) | ethcore_mac_liteethmaccrc32checker_fifo_out)); +assign ethcore_mac_liteethmaccrc32checker_fifo_out = (ethcore_mac_liteethmaccrc32checker_source_source_valid & ethcore_mac_liteethmaccrc32checker_source_source_ready); +assign ethcore_mac_liteethmaccrc32checker_syncfifo_sink_first = ethcore_mac_liteethmaccrc32checker_sink_sink_first; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_sink_last = ethcore_mac_liteethmaccrc32checker_sink_sink_last; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_sink_payload_data = ethcore_mac_liteethmaccrc32checker_sink_sink_payload_data; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_sink_payload_last_be = ethcore_mac_liteethmaccrc32checker_sink_sink_payload_last_be; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_sink_payload_error = ethcore_mac_liteethmaccrc32checker_sink_sink_payload_error; +always @(*) begin + ethcore_mac_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; + ethcore_mac_liteethmaccrc32checker_syncfifo_sink_valid <= ethcore_mac_liteethmaccrc32checker_sink_sink_valid; + ethcore_mac_liteethmaccrc32checker_syncfifo_sink_valid <= ethcore_mac_liteethmaccrc32checker_fifo_in; +end +always @(*) begin + ethcore_mac_liteethmaccrc32checker_sink_sink_ready <= 1'd0; + ethcore_mac_liteethmaccrc32checker_sink_sink_ready <= ethcore_mac_liteethmaccrc32checker_syncfifo_sink_ready; + ethcore_mac_liteethmaccrc32checker_sink_sink_ready <= ethcore_mac_liteethmaccrc32checker_fifo_in; +end +assign ethcore_mac_liteethmaccrc32checker_source_source_valid = (ethcore_mac_liteethmaccrc32checker_sink_sink_valid & ethcore_mac_liteethmaccrc32checker_fifo_full); +assign ethcore_mac_liteethmaccrc32checker_source_source_last = ethcore_mac_liteethmaccrc32checker_sink_sink_last; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_source_ready = ethcore_mac_liteethmaccrc32checker_fifo_out; +assign ethcore_mac_liteethmaccrc32checker_source_source_payload_data = ethcore_mac_liteethmaccrc32checker_syncfifo_source_payload_data; +assign ethcore_mac_liteethmaccrc32checker_source_source_payload_last_be = ethcore_mac_liteethmaccrc32checker_syncfifo_source_payload_last_be; +always @(*) begin + ethcore_mac_liteethmaccrc32checker_source_source_payload_error <= 1'd0; + ethcore_mac_liteethmaccrc32checker_source_source_payload_error <= ethcore_mac_liteethmaccrc32checker_syncfifo_source_payload_error; + ethcore_mac_liteethmaccrc32checker_source_source_payload_error <= (ethcore_mac_liteethmaccrc32checker_sink_sink_payload_error | ethcore_mac_liteethmaccrc32checker_crc_error); +end +assign ethcore_mac_liteethmaccrc32checker_error = ((ethcore_mac_liteethmaccrc32checker_source_source_valid & ethcore_mac_liteethmaccrc32checker_source_source_last) & ethcore_mac_liteethmaccrc32checker_crc_error); +assign ethcore_mac_liteethmaccrc32checker_crc_data0 = ethcore_mac_liteethmaccrc32checker_sink_sink_payload_data; +assign ethcore_mac_liteethmaccrc32checker_sink_sink_valid = ethcore_mac_crc32_checker_source_valid; +assign ethcore_mac_crc32_checker_source_ready = ethcore_mac_liteethmaccrc32checker_sink_sink_ready; +assign ethcore_mac_liteethmaccrc32checker_sink_sink_first = ethcore_mac_crc32_checker_source_first; +assign ethcore_mac_liteethmaccrc32checker_sink_sink_last = ethcore_mac_crc32_checker_source_last; +assign ethcore_mac_liteethmaccrc32checker_sink_sink_payload_data = ethcore_mac_crc32_checker_source_payload_data; +assign ethcore_mac_liteethmaccrc32checker_sink_sink_payload_last_be = ethcore_mac_crc32_checker_source_payload_last_be; +assign ethcore_mac_liteethmaccrc32checker_sink_sink_payload_error = ethcore_mac_crc32_checker_source_payload_error; +assign ethcore_mac_liteethmaccrc32checker_crc_data1 = ethcore_mac_liteethmaccrc32checker_crc_data0; +assign ethcore_mac_liteethmaccrc32checker_crc_last = ethcore_mac_liteethmaccrc32checker_crc_reg; +assign ethcore_mac_liteethmaccrc32checker_crc_value = (~{ethcore_mac_liteethmaccrc32checker_crc_reg[0], ethcore_mac_liteethmaccrc32checker_crc_reg[1], ethcore_mac_liteethmaccrc32checker_crc_reg[2], ethcore_mac_liteethmaccrc32checker_crc_reg[3], ethcore_mac_liteethmaccrc32checker_crc_reg[4], ethcore_mac_liteethmaccrc32checker_crc_reg[5], ethcore_mac_liteethmaccrc32checker_crc_reg[6], ethcore_mac_liteethmaccrc32checker_crc_reg[7], ethcore_mac_liteethmaccrc32checker_crc_reg[8], ethcore_mac_liteethmaccrc32checker_crc_reg[9], ethcore_mac_liteethmaccrc32checker_crc_reg[10], ethcore_mac_liteethmaccrc32checker_crc_reg[11], ethcore_mac_liteethmaccrc32checker_crc_reg[12], ethcore_mac_liteethmaccrc32checker_crc_reg[13], ethcore_mac_liteethmaccrc32checker_crc_reg[14], ethcore_mac_liteethmaccrc32checker_crc_reg[15], ethcore_mac_liteethmaccrc32checker_crc_reg[16], ethcore_mac_liteethmaccrc32checker_crc_reg[17], ethcore_mac_liteethmaccrc32checker_crc_reg[18], ethcore_mac_liteethmaccrc32checker_crc_reg[19], ethcore_mac_liteethmaccrc32checker_crc_reg[20], ethcore_mac_liteethmaccrc32checker_crc_reg[21], ethcore_mac_liteethmaccrc32checker_crc_reg[22], ethcore_mac_liteethmaccrc32checker_crc_reg[23], ethcore_mac_liteethmaccrc32checker_crc_reg[24], ethcore_mac_liteethmaccrc32checker_crc_reg[25], ethcore_mac_liteethmaccrc32checker_crc_reg[26], ethcore_mac_liteethmaccrc32checker_crc_reg[27], ethcore_mac_liteethmaccrc32checker_crc_reg[28], ethcore_mac_liteethmaccrc32checker_crc_reg[29], ethcore_mac_liteethmaccrc32checker_crc_reg[30], ethcore_mac_liteethmaccrc32checker_crc_reg[31]}); +assign ethcore_mac_liteethmaccrc32checker_crc_error = (ethcore_mac_liteethmaccrc32checker_crc_next != 32'd3338984827); +always @(*) begin + ethcore_mac_liteethmaccrc32checker_crc_next <= 32'd0; + ethcore_mac_liteethmaccrc32checker_crc_next[0] <= (((ethcore_mac_liteethmaccrc32checker_crc_last[24] ^ ethcore_mac_liteethmaccrc32checker_crc_last[30]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[1]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[7]); + ethcore_mac_liteethmaccrc32checker_crc_next[1] <= (((((((ethcore_mac_liteethmaccrc32checker_crc_last[25] ^ ethcore_mac_liteethmaccrc32checker_crc_last[31]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[0]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[6]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[24]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[30]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[1]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[7]); + ethcore_mac_liteethmaccrc32checker_crc_next[2] <= (((((((((ethcore_mac_liteethmaccrc32checker_crc_last[26] ^ ethcore_mac_liteethmaccrc32checker_crc_data1[5]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[25]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[31]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[0]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[6]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[24]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[30]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[1]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[7]); + ethcore_mac_liteethmaccrc32checker_crc_next[3] <= (((((((ethcore_mac_liteethmaccrc32checker_crc_last[27] ^ ethcore_mac_liteethmaccrc32checker_crc_data1[4]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[26]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[5]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[25]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[31]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[0]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[6]); + ethcore_mac_liteethmaccrc32checker_crc_next[4] <= (((((((((ethcore_mac_liteethmaccrc32checker_crc_last[28] ^ ethcore_mac_liteethmaccrc32checker_crc_data1[3]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[27]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[4]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[26]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[5]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[24]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[30]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[1]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[7]); + ethcore_mac_liteethmaccrc32checker_crc_next[5] <= (((((((((((((ethcore_mac_liteethmaccrc32checker_crc_last[29] ^ ethcore_mac_liteethmaccrc32checker_crc_data1[2]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[28]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[3]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[27]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[4]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[25]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[31]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[0]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[6]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[24]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[30]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[1]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[7]); + ethcore_mac_liteethmaccrc32checker_crc_next[6] <= (((((((((((ethcore_mac_liteethmaccrc32checker_crc_last[30] ^ ethcore_mac_liteethmaccrc32checker_crc_data1[1]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[29]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[2]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[28]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[3]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[26]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[5]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[25]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[31]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[0]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[6]); + ethcore_mac_liteethmaccrc32checker_crc_next[7] <= (((((((((ethcore_mac_liteethmaccrc32checker_crc_last[31] ^ ethcore_mac_liteethmaccrc32checker_crc_data1[0]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[29]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[2]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[27]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[4]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[26]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[5]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[24]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[7]); + ethcore_mac_liteethmaccrc32checker_crc_next[8] <= ((((((((ethcore_mac_liteethmaccrc32checker_crc_last[0] ^ ethcore_mac_liteethmaccrc32checker_crc_last[28]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[3]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[27]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[4]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[25]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[6]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[24]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[7]); + ethcore_mac_liteethmaccrc32checker_crc_next[9] <= ((((((((ethcore_mac_liteethmaccrc32checker_crc_last[1] ^ ethcore_mac_liteethmaccrc32checker_crc_last[29]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[2]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[28]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[3]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[26]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[5]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[25]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[6]); + ethcore_mac_liteethmaccrc32checker_crc_next[10] <= ((((((((ethcore_mac_liteethmaccrc32checker_crc_last[2] ^ ethcore_mac_liteethmaccrc32checker_crc_last[29]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[2]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[27]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[4]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[26]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[5]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[24]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[7]); + ethcore_mac_liteethmaccrc32checker_crc_next[11] <= ((((((((ethcore_mac_liteethmaccrc32checker_crc_last[3] ^ ethcore_mac_liteethmaccrc32checker_crc_last[28]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[3]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[27]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[4]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[25]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[6]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[24]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[7]); + ethcore_mac_liteethmaccrc32checker_crc_next[12] <= ((((((((((((ethcore_mac_liteethmaccrc32checker_crc_last[4] ^ ethcore_mac_liteethmaccrc32checker_crc_last[29]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[2]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[28]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[3]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[26]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[5]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[25]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[6]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[24]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[30]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[1]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[7]); + ethcore_mac_liteethmaccrc32checker_crc_next[13] <= ((((((((((((ethcore_mac_liteethmaccrc32checker_crc_last[5] ^ ethcore_mac_liteethmaccrc32checker_crc_last[30]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[1]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[29]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[2]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[27]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[4]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[26]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[5]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[25]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[31]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[0]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[6]); + ethcore_mac_liteethmaccrc32checker_crc_next[14] <= ((((((((((ethcore_mac_liteethmaccrc32checker_crc_last[6] ^ ethcore_mac_liteethmaccrc32checker_crc_last[31]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[0]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[30]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[1]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[28]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[3]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[27]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[4]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[26]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[5]); + ethcore_mac_liteethmaccrc32checker_crc_next[15] <= ((((((((ethcore_mac_liteethmaccrc32checker_crc_last[7] ^ ethcore_mac_liteethmaccrc32checker_crc_last[31]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[0]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[29]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[2]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[28]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[3]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[27]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[4]); + ethcore_mac_liteethmaccrc32checker_crc_next[16] <= ((((((ethcore_mac_liteethmaccrc32checker_crc_last[8] ^ ethcore_mac_liteethmaccrc32checker_crc_last[29]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[2]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[28]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[3]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[24]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[7]); + ethcore_mac_liteethmaccrc32checker_crc_next[17] <= ((((((ethcore_mac_liteethmaccrc32checker_crc_last[9] ^ ethcore_mac_liteethmaccrc32checker_crc_last[30]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[1]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[29]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[2]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[25]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[6]); + ethcore_mac_liteethmaccrc32checker_crc_next[18] <= ((((((ethcore_mac_liteethmaccrc32checker_crc_last[10] ^ ethcore_mac_liteethmaccrc32checker_crc_last[31]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[0]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[30]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[1]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[26]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[5]); + ethcore_mac_liteethmaccrc32checker_crc_next[19] <= ((((ethcore_mac_liteethmaccrc32checker_crc_last[11] ^ ethcore_mac_liteethmaccrc32checker_crc_last[31]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[0]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[27]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[4]); + ethcore_mac_liteethmaccrc32checker_crc_next[20] <= ((ethcore_mac_liteethmaccrc32checker_crc_last[12] ^ ethcore_mac_liteethmaccrc32checker_crc_last[28]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[3]); + ethcore_mac_liteethmaccrc32checker_crc_next[21] <= ((ethcore_mac_liteethmaccrc32checker_crc_last[13] ^ ethcore_mac_liteethmaccrc32checker_crc_last[29]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[2]); + ethcore_mac_liteethmaccrc32checker_crc_next[22] <= ((ethcore_mac_liteethmaccrc32checker_crc_last[14] ^ ethcore_mac_liteethmaccrc32checker_crc_last[24]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[7]); + ethcore_mac_liteethmaccrc32checker_crc_next[23] <= ((((((ethcore_mac_liteethmaccrc32checker_crc_last[15] ^ ethcore_mac_liteethmaccrc32checker_crc_last[25]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[6]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[24]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[30]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[1]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[7]); + ethcore_mac_liteethmaccrc32checker_crc_next[24] <= ((((((ethcore_mac_liteethmaccrc32checker_crc_last[16] ^ ethcore_mac_liteethmaccrc32checker_crc_last[26]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[5]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[25]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[31]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[0]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[6]); + ethcore_mac_liteethmaccrc32checker_crc_next[25] <= ((((ethcore_mac_liteethmaccrc32checker_crc_last[17] ^ ethcore_mac_liteethmaccrc32checker_crc_last[27]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[4]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[26]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[5]); + ethcore_mac_liteethmaccrc32checker_crc_next[26] <= ((((((((ethcore_mac_liteethmaccrc32checker_crc_last[18] ^ ethcore_mac_liteethmaccrc32checker_crc_last[28]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[3]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[27]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[4]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[24]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[30]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[1]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[7]); + ethcore_mac_liteethmaccrc32checker_crc_next[27] <= ((((((((ethcore_mac_liteethmaccrc32checker_crc_last[19] ^ ethcore_mac_liteethmaccrc32checker_crc_last[29]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[2]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[28]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[3]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[25]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[31]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[0]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[6]); + ethcore_mac_liteethmaccrc32checker_crc_next[28] <= ((((((ethcore_mac_liteethmaccrc32checker_crc_last[20] ^ ethcore_mac_liteethmaccrc32checker_crc_last[30]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[1]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[29]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[2]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[26]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[5]); + ethcore_mac_liteethmaccrc32checker_crc_next[29] <= ((((((ethcore_mac_liteethmaccrc32checker_crc_last[21] ^ ethcore_mac_liteethmaccrc32checker_crc_last[31]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[0]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[30]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[1]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[27]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[4]); + ethcore_mac_liteethmaccrc32checker_crc_next[30] <= ((((ethcore_mac_liteethmaccrc32checker_crc_last[22] ^ ethcore_mac_liteethmaccrc32checker_crc_last[31]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[0]) ^ ethcore_mac_liteethmaccrc32checker_crc_last[28]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[3]); + ethcore_mac_liteethmaccrc32checker_crc_next[31] <= ((ethcore_mac_liteethmaccrc32checker_crc_last[23] ^ ethcore_mac_liteethmaccrc32checker_crc_last[29]) ^ ethcore_mac_liteethmaccrc32checker_crc_data1[2]); +end +assign ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_din = {ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_in_last, ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_in_first, ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; +assign {ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_out_last, ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_out_first, ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_dout; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_sink_ready = ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_writable; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_we = ethcore_mac_liteethmaccrc32checker_syncfifo_sink_valid; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_in_first = ethcore_mac_liteethmaccrc32checker_syncfifo_sink_first; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_in_last = ethcore_mac_liteethmaccrc32checker_syncfifo_sink_last; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_in_payload_data = ethcore_mac_liteethmaccrc32checker_syncfifo_sink_payload_data; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = ethcore_mac_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_in_payload_error = ethcore_mac_liteethmaccrc32checker_syncfifo_sink_payload_error; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_source_valid = ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_readable; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_source_first = ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_out_first; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_source_last = ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_out_last; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_source_payload_data = ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_source_payload_last_be = ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_source_payload_error = ethcore_mac_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_re = ethcore_mac_liteethmaccrc32checker_syncfifo_source_ready; +always @(*) begin + ethcore_mac_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; + if (ethcore_mac_liteethmaccrc32checker_syncfifo_replace) begin + ethcore_mac_liteethmaccrc32checker_syncfifo_wrport_adr <= (ethcore_mac_liteethmaccrc32checker_syncfifo_produce - 1'd1); + end else begin + ethcore_mac_liteethmaccrc32checker_syncfifo_wrport_adr <= ethcore_mac_liteethmaccrc32checker_syncfifo_produce; + end +end +assign ethcore_mac_liteethmaccrc32checker_syncfifo_wrport_dat_w = ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_din; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_wrport_we = (ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_we & (ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_writable | ethcore_mac_liteethmaccrc32checker_syncfifo_replace)); +assign ethcore_mac_liteethmaccrc32checker_syncfifo_do_read = (ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_readable & ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_re); +assign ethcore_mac_liteethmaccrc32checker_syncfifo_rdport_adr = ethcore_mac_liteethmaccrc32checker_syncfifo_consume; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_dout = ethcore_mac_liteethmaccrc32checker_syncfifo_rdport_dat_r; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_writable = (ethcore_mac_liteethmaccrc32checker_syncfifo_level != 3'd5); +assign ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_readable = (ethcore_mac_liteethmaccrc32checker_syncfifo_level != 1'd0); +always @(*) begin + ethcore_mac_liteethmaccrc32checker_fifo_reset <= 1'd0; + liteethudpipcore_liteethmac_liteethmaccrc32checker_next_state <= 2'd0; + ethcore_mac_liteethmaccrc32checker_crc_ce <= 1'd0; + ethcore_mac_liteethmaccrc32checker_crc_reset <= 1'd0; + liteethudpipcore_liteethmac_liteethmaccrc32checker_next_state <= liteethudpipcore_liteethmac_liteethmaccrc32checker_state; + case (liteethudpipcore_liteethmac_liteethmaccrc32checker_state) + 1'd1: begin + if ((ethcore_mac_liteethmaccrc32checker_sink_sink_valid & ethcore_mac_liteethmaccrc32checker_sink_sink_ready)) begin + ethcore_mac_liteethmaccrc32checker_crc_ce <= 1'd1; + liteethudpipcore_liteethmac_liteethmaccrc32checker_next_state <= 2'd2; + end + end + 2'd2: begin + if ((ethcore_mac_liteethmaccrc32checker_sink_sink_valid & ethcore_mac_liteethmaccrc32checker_sink_sink_ready)) begin + ethcore_mac_liteethmaccrc32checker_crc_ce <= 1'd1; + if (ethcore_mac_liteethmaccrc32checker_sink_sink_last) begin + liteethudpipcore_liteethmac_liteethmaccrc32checker_next_state <= 1'd0; + end + end + end + default: begin + ethcore_mac_liteethmaccrc32checker_crc_reset <= 1'd1; + ethcore_mac_liteethmaccrc32checker_fifo_reset <= 1'd1; + liteethudpipcore_liteethmac_liteethmaccrc32checker_next_state <= 1'd1; + end + endcase +end +assign ethcore_mac_crc32_checker_sink_ready = ((~ethcore_mac_crc32_checker_source_valid) | ethcore_mac_crc32_checker_source_ready); +assign ethcore_mac_ps_preamble_error_o = (ethcore_mac_ps_preamble_error_toggle_o ^ ethcore_mac_ps_preamble_error_toggle_o_r); +assign ethcore_mac_ps_crc_error_o = (ethcore_mac_ps_crc_error_toggle_o ^ ethcore_mac_ps_crc_error_toggle_o_r); +assign ethcore_mac_padding_inserter_counter_done = (ethcore_mac_padding_inserter_counter >= 6'd59); +always @(*) begin + ethcore_mac_padding_inserter_source_valid <= 1'd0; + ethcore_mac_padding_inserter_source_first <= 1'd0; + ethcore_mac_padding_inserter_source_last <= 1'd0; + ethcore_mac_padding_inserter_source_payload_data <= 8'd0; + ethcore_mac_padding_inserter_source_payload_last_be <= 1'd0; + ethcore_mac_padding_inserter_source_payload_error <= 1'd0; + liteethudpipcore_liteethmac_liteethmacpaddinginserter_next_state <= 1'd0; + ethcore_mac_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 16'd0; + ethcore_mac_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd0; + ethcore_mac_padding_inserter_sink_ready <= 1'd0; + liteethudpipcore_liteethmac_liteethmacpaddinginserter_next_state <= liteethudpipcore_liteethmac_liteethmacpaddinginserter_state; + case (liteethudpipcore_liteethmac_liteethmacpaddinginserter_state) + 1'd1: begin + ethcore_mac_padding_inserter_source_valid <= 1'd1; + ethcore_mac_padding_inserter_source_last <= ethcore_mac_padding_inserter_counter_done; + ethcore_mac_padding_inserter_source_payload_data <= 1'd0; + if ((ethcore_mac_padding_inserter_source_valid & ethcore_mac_padding_inserter_source_ready)) begin + ethcore_mac_padding_inserter_counter_liteethmacpaddinginserter_next_value <= (ethcore_mac_padding_inserter_counter + 1'd1); + ethcore_mac_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; + if (ethcore_mac_padding_inserter_counter_done) begin + ethcore_mac_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0; + ethcore_mac_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; + liteethudpipcore_liteethmac_liteethmacpaddinginserter_next_state <= 1'd0; + end + end + end + default: begin + ethcore_mac_padding_inserter_source_valid <= ethcore_mac_padding_inserter_sink_valid; + ethcore_mac_padding_inserter_sink_ready <= ethcore_mac_padding_inserter_source_ready; + ethcore_mac_padding_inserter_source_first <= ethcore_mac_padding_inserter_sink_first; + ethcore_mac_padding_inserter_source_last <= ethcore_mac_padding_inserter_sink_last; + ethcore_mac_padding_inserter_source_payload_data <= ethcore_mac_padding_inserter_sink_payload_data; + ethcore_mac_padding_inserter_source_payload_last_be <= ethcore_mac_padding_inserter_sink_payload_last_be; + ethcore_mac_padding_inserter_source_payload_error <= ethcore_mac_padding_inserter_sink_payload_error; + if ((ethcore_mac_padding_inserter_source_valid & ethcore_mac_padding_inserter_source_ready)) begin + ethcore_mac_padding_inserter_counter_liteethmacpaddinginserter_next_value <= (ethcore_mac_padding_inserter_counter + 1'd1); + ethcore_mac_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; + if (ethcore_mac_padding_inserter_sink_last) begin + if ((~ethcore_mac_padding_inserter_counter_done)) begin + ethcore_mac_padding_inserter_source_last <= 1'd0; + liteethudpipcore_liteethmac_liteethmacpaddinginserter_next_state <= 1'd1; + end else begin + ethcore_mac_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0; + ethcore_mac_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; + end + end + end + end + endcase +end +assign ethcore_mac_padding_checker_source_valid = ethcore_mac_padding_checker_sink_valid; +assign ethcore_mac_padding_checker_sink_ready = ethcore_mac_padding_checker_source_ready; +assign ethcore_mac_padding_checker_source_first = ethcore_mac_padding_checker_sink_first; +assign ethcore_mac_padding_checker_source_last = ethcore_mac_padding_checker_sink_last; +assign ethcore_mac_padding_checker_source_payload_data = ethcore_mac_padding_checker_sink_payload_data; +assign ethcore_mac_padding_checker_source_payload_last_be = ethcore_mac_padding_checker_sink_payload_last_be; +assign ethcore_mac_padding_checker_source_payload_error = ethcore_mac_padding_checker_sink_payload_error; +assign ethcore_mac_tx_cdc_asyncfifo_din = {ethcore_mac_tx_cdc_fifo_in_last, ethcore_mac_tx_cdc_fifo_in_first, ethcore_mac_tx_cdc_fifo_in_payload_error, ethcore_mac_tx_cdc_fifo_in_payload_last_be, ethcore_mac_tx_cdc_fifo_in_payload_data}; +assign {ethcore_mac_tx_cdc_fifo_out_last, ethcore_mac_tx_cdc_fifo_out_first, ethcore_mac_tx_cdc_fifo_out_payload_error, ethcore_mac_tx_cdc_fifo_out_payload_last_be, ethcore_mac_tx_cdc_fifo_out_payload_data} = ethcore_mac_tx_cdc_asyncfifo_dout; +assign ethcore_mac_tx_cdc_sink_ready = ethcore_mac_tx_cdc_asyncfifo_writable; +assign ethcore_mac_tx_cdc_asyncfifo_we = ethcore_mac_tx_cdc_sink_valid; +assign ethcore_mac_tx_cdc_fifo_in_first = ethcore_mac_tx_cdc_sink_first; +assign ethcore_mac_tx_cdc_fifo_in_last = ethcore_mac_tx_cdc_sink_last; +assign ethcore_mac_tx_cdc_fifo_in_payload_data = ethcore_mac_tx_cdc_sink_payload_data; +assign ethcore_mac_tx_cdc_fifo_in_payload_last_be = ethcore_mac_tx_cdc_sink_payload_last_be; +assign ethcore_mac_tx_cdc_fifo_in_payload_error = ethcore_mac_tx_cdc_sink_payload_error; +assign ethcore_mac_tx_cdc_source_valid = ethcore_mac_tx_cdc_asyncfifo_readable; +assign ethcore_mac_tx_cdc_source_first = ethcore_mac_tx_cdc_fifo_out_first; +assign ethcore_mac_tx_cdc_source_last = ethcore_mac_tx_cdc_fifo_out_last; +assign ethcore_mac_tx_cdc_source_payload_data = ethcore_mac_tx_cdc_fifo_out_payload_data; +assign ethcore_mac_tx_cdc_source_payload_last_be = ethcore_mac_tx_cdc_fifo_out_payload_last_be; +assign ethcore_mac_tx_cdc_source_payload_error = ethcore_mac_tx_cdc_fifo_out_payload_error; +assign ethcore_mac_tx_cdc_asyncfifo_re = ethcore_mac_tx_cdc_source_ready; +assign ethcore_mac_tx_cdc_graycounter0_ce = (ethcore_mac_tx_cdc_asyncfifo_writable & ethcore_mac_tx_cdc_asyncfifo_we); +assign ethcore_mac_tx_cdc_graycounter1_ce = (ethcore_mac_tx_cdc_asyncfifo_readable & ethcore_mac_tx_cdc_asyncfifo_re); +assign ethcore_mac_tx_cdc_asyncfifo_writable = (((ethcore_mac_tx_cdc_graycounter0_q[6] == ethcore_mac_tx_cdc_consume_wdomain[6]) | (ethcore_mac_tx_cdc_graycounter0_q[5] == ethcore_mac_tx_cdc_consume_wdomain[5])) | (ethcore_mac_tx_cdc_graycounter0_q[4:0] != ethcore_mac_tx_cdc_consume_wdomain[4:0])); +assign ethcore_mac_tx_cdc_asyncfifo_readable = (ethcore_mac_tx_cdc_graycounter1_q != ethcore_mac_tx_cdc_produce_rdomain); +assign ethcore_mac_tx_cdc_wrport_adr = ethcore_mac_tx_cdc_graycounter0_q_binary[5:0]; +assign ethcore_mac_tx_cdc_wrport_dat_w = ethcore_mac_tx_cdc_asyncfifo_din; +assign ethcore_mac_tx_cdc_wrport_we = ethcore_mac_tx_cdc_graycounter0_ce; +assign ethcore_mac_tx_cdc_rdport_adr = ethcore_mac_tx_cdc_graycounter1_q_next_binary[5:0]; +assign ethcore_mac_tx_cdc_asyncfifo_dout = ethcore_mac_tx_cdc_rdport_dat_r; +always @(*) begin + ethcore_mac_tx_cdc_graycounter0_q_next_binary <= 7'd0; + if (ethcore_mac_tx_cdc_graycounter0_ce) begin + ethcore_mac_tx_cdc_graycounter0_q_next_binary <= (ethcore_mac_tx_cdc_graycounter0_q_binary + 1'd1); + end else begin + ethcore_mac_tx_cdc_graycounter0_q_next_binary <= ethcore_mac_tx_cdc_graycounter0_q_binary; + end +end +assign ethcore_mac_tx_cdc_graycounter0_q_next = (ethcore_mac_tx_cdc_graycounter0_q_next_binary ^ ethcore_mac_tx_cdc_graycounter0_q_next_binary[6:1]); +always @(*) begin + ethcore_mac_tx_cdc_graycounter1_q_next_binary <= 7'd0; + if (ethcore_mac_tx_cdc_graycounter1_ce) begin + ethcore_mac_tx_cdc_graycounter1_q_next_binary <= (ethcore_mac_tx_cdc_graycounter1_q_binary + 1'd1); + end else begin + ethcore_mac_tx_cdc_graycounter1_q_next_binary <= ethcore_mac_tx_cdc_graycounter1_q_binary; + end +end +assign ethcore_mac_tx_cdc_graycounter1_q_next = (ethcore_mac_tx_cdc_graycounter1_q_next_binary ^ ethcore_mac_tx_cdc_graycounter1_q_next_binary[6:1]); +assign ethcore_mac_rx_cdc_asyncfifo_din = {ethcore_mac_rx_cdc_fifo_in_last, ethcore_mac_rx_cdc_fifo_in_first, ethcore_mac_rx_cdc_fifo_in_payload_error, ethcore_mac_rx_cdc_fifo_in_payload_last_be, ethcore_mac_rx_cdc_fifo_in_payload_data}; +assign {ethcore_mac_rx_cdc_fifo_out_last, ethcore_mac_rx_cdc_fifo_out_first, ethcore_mac_rx_cdc_fifo_out_payload_error, ethcore_mac_rx_cdc_fifo_out_payload_last_be, ethcore_mac_rx_cdc_fifo_out_payload_data} = ethcore_mac_rx_cdc_asyncfifo_dout; +assign ethcore_mac_rx_cdc_sink_ready = ethcore_mac_rx_cdc_asyncfifo_writable; +assign ethcore_mac_rx_cdc_asyncfifo_we = ethcore_mac_rx_cdc_sink_valid; +assign ethcore_mac_rx_cdc_fifo_in_first = ethcore_mac_rx_cdc_sink_first; +assign ethcore_mac_rx_cdc_fifo_in_last = ethcore_mac_rx_cdc_sink_last; +assign ethcore_mac_rx_cdc_fifo_in_payload_data = ethcore_mac_rx_cdc_sink_payload_data; +assign ethcore_mac_rx_cdc_fifo_in_payload_last_be = ethcore_mac_rx_cdc_sink_payload_last_be; +assign ethcore_mac_rx_cdc_fifo_in_payload_error = ethcore_mac_rx_cdc_sink_payload_error; +assign ethcore_mac_rx_cdc_source_valid = ethcore_mac_rx_cdc_asyncfifo_readable; +assign ethcore_mac_rx_cdc_source_first = ethcore_mac_rx_cdc_fifo_out_first; +assign ethcore_mac_rx_cdc_source_last = ethcore_mac_rx_cdc_fifo_out_last; +assign ethcore_mac_rx_cdc_source_payload_data = ethcore_mac_rx_cdc_fifo_out_payload_data; +assign ethcore_mac_rx_cdc_source_payload_last_be = ethcore_mac_rx_cdc_fifo_out_payload_last_be; +assign ethcore_mac_rx_cdc_source_payload_error = ethcore_mac_rx_cdc_fifo_out_payload_error; +assign ethcore_mac_rx_cdc_asyncfifo_re = ethcore_mac_rx_cdc_source_ready; +assign ethcore_mac_rx_cdc_graycounter0_ce = (ethcore_mac_rx_cdc_asyncfifo_writable & ethcore_mac_rx_cdc_asyncfifo_we); +assign ethcore_mac_rx_cdc_graycounter1_ce = (ethcore_mac_rx_cdc_asyncfifo_readable & ethcore_mac_rx_cdc_asyncfifo_re); +assign ethcore_mac_rx_cdc_asyncfifo_writable = (((ethcore_mac_rx_cdc_graycounter0_q[6] == ethcore_mac_rx_cdc_consume_wdomain[6]) | (ethcore_mac_rx_cdc_graycounter0_q[5] == ethcore_mac_rx_cdc_consume_wdomain[5])) | (ethcore_mac_rx_cdc_graycounter0_q[4:0] != ethcore_mac_rx_cdc_consume_wdomain[4:0])); +assign ethcore_mac_rx_cdc_asyncfifo_readable = (ethcore_mac_rx_cdc_graycounter1_q != ethcore_mac_rx_cdc_produce_rdomain); +assign ethcore_mac_rx_cdc_wrport_adr = ethcore_mac_rx_cdc_graycounter0_q_binary[5:0]; +assign ethcore_mac_rx_cdc_wrport_dat_w = ethcore_mac_rx_cdc_asyncfifo_din; +assign ethcore_mac_rx_cdc_wrport_we = ethcore_mac_rx_cdc_graycounter0_ce; +assign ethcore_mac_rx_cdc_rdport_adr = ethcore_mac_rx_cdc_graycounter1_q_next_binary[5:0]; +assign ethcore_mac_rx_cdc_asyncfifo_dout = ethcore_mac_rx_cdc_rdport_dat_r; +always @(*) begin + ethcore_mac_rx_cdc_graycounter0_q_next_binary <= 7'd0; + if (ethcore_mac_rx_cdc_graycounter0_ce) begin + ethcore_mac_rx_cdc_graycounter0_q_next_binary <= (ethcore_mac_rx_cdc_graycounter0_q_binary + 1'd1); + end else begin + ethcore_mac_rx_cdc_graycounter0_q_next_binary <= ethcore_mac_rx_cdc_graycounter0_q_binary; + end +end +assign ethcore_mac_rx_cdc_graycounter0_q_next = (ethcore_mac_rx_cdc_graycounter0_q_next_binary ^ ethcore_mac_rx_cdc_graycounter0_q_next_binary[6:1]); +always @(*) begin + ethcore_mac_rx_cdc_graycounter1_q_next_binary <= 7'd0; + if (ethcore_mac_rx_cdc_graycounter1_ce) begin + ethcore_mac_rx_cdc_graycounter1_q_next_binary <= (ethcore_mac_rx_cdc_graycounter1_q_binary + 1'd1); + end else begin + ethcore_mac_rx_cdc_graycounter1_q_next_binary <= ethcore_mac_rx_cdc_graycounter1_q_binary; + end +end +assign ethcore_mac_rx_cdc_graycounter1_q_next = (ethcore_mac_rx_cdc_graycounter1_q_next_binary ^ ethcore_mac_rx_cdc_graycounter1_q_next_binary[6:1]); +assign ethcore_mac_padding_inserter_sink_valid = ethcore_mac_tx_cdc_source_valid; +assign ethcore_mac_tx_cdc_source_ready = ethcore_mac_padding_inserter_sink_ready; +assign ethcore_mac_padding_inserter_sink_first = ethcore_mac_tx_cdc_source_first; +assign ethcore_mac_padding_inserter_sink_last = ethcore_mac_tx_cdc_source_last; +assign ethcore_mac_padding_inserter_sink_payload_data = ethcore_mac_tx_cdc_source_payload_data; +assign ethcore_mac_padding_inserter_sink_payload_last_be = ethcore_mac_tx_cdc_source_payload_last_be; +assign ethcore_mac_padding_inserter_sink_payload_error = ethcore_mac_tx_cdc_source_payload_error; +assign ethcore_mac_crc32_inserter_sink_valid = ethcore_mac_padding_inserter_source_valid; +assign ethcore_mac_padding_inserter_source_ready = ethcore_mac_crc32_inserter_sink_ready; +assign ethcore_mac_crc32_inserter_sink_first = ethcore_mac_padding_inserter_source_first; +assign ethcore_mac_crc32_inserter_sink_last = ethcore_mac_padding_inserter_source_last; +assign ethcore_mac_crc32_inserter_sink_payload_data = ethcore_mac_padding_inserter_source_payload_data; +assign ethcore_mac_crc32_inserter_sink_payload_last_be = ethcore_mac_padding_inserter_source_payload_last_be; +assign ethcore_mac_crc32_inserter_sink_payload_error = ethcore_mac_padding_inserter_source_payload_error; +assign ethcore_mac_preamble_inserter_sink_valid = ethcore_mac_liteethmaccrc32inserter_source_valid; +assign ethcore_mac_liteethmaccrc32inserter_source_ready = ethcore_mac_preamble_inserter_sink_ready; +assign ethcore_mac_preamble_inserter_sink_first = ethcore_mac_liteethmaccrc32inserter_source_first; +assign ethcore_mac_preamble_inserter_sink_last = ethcore_mac_liteethmaccrc32inserter_source_last; +assign ethcore_mac_preamble_inserter_sink_payload_data = ethcore_mac_liteethmaccrc32inserter_source_payload_data; +assign ethcore_mac_preamble_inserter_sink_payload_last_be = ethcore_mac_liteethmaccrc32inserter_source_payload_last_be; +assign ethcore_mac_preamble_inserter_sink_payload_error = ethcore_mac_liteethmaccrc32inserter_source_payload_error; +assign ethcore_mac_tx_gap_inserter_sink_valid = ethcore_mac_preamble_inserter_source_valid; +assign ethcore_mac_preamble_inserter_source_ready = ethcore_mac_tx_gap_inserter_sink_ready; +assign ethcore_mac_tx_gap_inserter_sink_first = ethcore_mac_preamble_inserter_source_first; +assign ethcore_mac_tx_gap_inserter_sink_last = ethcore_mac_preamble_inserter_source_last; +assign ethcore_mac_tx_gap_inserter_sink_payload_data = ethcore_mac_preamble_inserter_source_payload_data; +assign ethcore_mac_tx_gap_inserter_sink_payload_last_be = ethcore_mac_preamble_inserter_source_payload_last_be; +assign ethcore_mac_tx_gap_inserter_sink_payload_error = ethcore_mac_preamble_inserter_source_payload_error; +assign ethphy_liteethphyrmiitx_sink_sink_valid = ethcore_mac_tx_gap_inserter_source_valid; +assign ethcore_mac_tx_gap_inserter_source_ready = ethphy_liteethphyrmiitx_sink_sink_ready; +assign ethphy_liteethphyrmiitx_sink_sink_first = ethcore_mac_tx_gap_inserter_source_first; +assign ethphy_liteethphyrmiitx_sink_sink_last = ethcore_mac_tx_gap_inserter_source_last; +assign ethphy_liteethphyrmiitx_sink_sink_payload_data = ethcore_mac_tx_gap_inserter_source_payload_data; +assign ethphy_liteethphyrmiitx_sink_sink_payload_last_be = ethcore_mac_tx_gap_inserter_source_payload_last_be; +assign ethphy_liteethphyrmiitx_sink_sink_payload_error = ethcore_mac_tx_gap_inserter_source_payload_error; +assign ethcore_mac_preamble_checker_sink_valid = ethphy_liteethphyrmiirx_source_source_valid; +assign ethphy_liteethphyrmiirx_source_source_ready = ethcore_mac_preamble_checker_sink_ready; +assign ethcore_mac_preamble_checker_sink_first = ethphy_liteethphyrmiirx_source_source_first; +assign ethcore_mac_preamble_checker_sink_last = ethphy_liteethphyrmiirx_source_source_last; +assign ethcore_mac_preamble_checker_sink_payload_data = ethphy_liteethphyrmiirx_source_source_payload_data; +assign ethcore_mac_preamble_checker_sink_payload_last_be = ethphy_liteethphyrmiirx_source_source_payload_last_be; +assign ethcore_mac_preamble_checker_sink_payload_error = ethphy_liteethphyrmiirx_source_source_payload_error; +assign ethcore_mac_crc32_checker_sink_valid = ethcore_mac_preamble_checker_source_valid; +assign ethcore_mac_preamble_checker_source_ready = ethcore_mac_crc32_checker_sink_ready; +assign ethcore_mac_crc32_checker_sink_first = ethcore_mac_preamble_checker_source_first; +assign ethcore_mac_crc32_checker_sink_last = ethcore_mac_preamble_checker_source_last; +assign ethcore_mac_crc32_checker_sink_payload_data = ethcore_mac_preamble_checker_source_payload_data; +assign ethcore_mac_crc32_checker_sink_payload_last_be = ethcore_mac_preamble_checker_source_payload_last_be; +assign ethcore_mac_crc32_checker_sink_payload_error = ethcore_mac_preamble_checker_source_payload_error; +assign ethcore_mac_padding_checker_sink_valid = ethcore_mac_liteethmaccrc32checker_source_source_valid; +assign ethcore_mac_liteethmaccrc32checker_source_source_ready = ethcore_mac_padding_checker_sink_ready; +assign ethcore_mac_padding_checker_sink_first = ethcore_mac_liteethmaccrc32checker_source_source_first; +assign ethcore_mac_padding_checker_sink_last = ethcore_mac_liteethmaccrc32checker_source_source_last; +assign ethcore_mac_padding_checker_sink_payload_data = ethcore_mac_liteethmaccrc32checker_source_source_payload_data; +assign ethcore_mac_padding_checker_sink_payload_last_be = ethcore_mac_liteethmaccrc32checker_source_source_payload_last_be; +assign ethcore_mac_padding_checker_sink_payload_error = ethcore_mac_liteethmaccrc32checker_source_source_payload_error; +assign ethcore_mac_rx_cdc_sink_valid = ethcore_mac_padding_checker_source_valid; +assign ethcore_mac_padding_checker_source_ready = ethcore_mac_rx_cdc_sink_ready; +assign ethcore_mac_rx_cdc_sink_first = ethcore_mac_padding_checker_source_first; +assign ethcore_mac_rx_cdc_sink_last = ethcore_mac_padding_checker_source_last; +assign ethcore_mac_rx_cdc_sink_payload_data = ethcore_mac_padding_checker_source_payload_data; +assign ethcore_mac_rx_cdc_sink_payload_last_be = ethcore_mac_padding_checker_source_payload_last_be; +assign ethcore_mac_rx_cdc_sink_payload_error = ethcore_mac_padding_checker_source_payload_error; +always @(*) begin + liteethudpipcore_liteethmac_sel0 <= 2'd0; + case (ethcore_mac_crossbar_sink_payload_ethernet_type) + 12'd2048: begin + liteethudpipcore_liteethmac_sel0 <= 2'd2; + end + 12'd2054: begin + liteethudpipcore_liteethmac_sel0 <= 1'd1; + end + default: begin + liteethudpipcore_liteethmac_sel0 <= 1'd0; + end + endcase +end +always @(*) begin + liteethudpipcore_liteethmac_request <= 2'd0; + liteethudpipcore_liteethmac_request[0] <= liteethudpipcore_liteethmac_status0_ongoing0; + liteethudpipcore_liteethmac_request[1] <= liteethudpipcore_liteethmac_status1_ongoing0; +end +always @(*) begin + ethcore_mac_crossbar_source_valid <= 1'd0; + ethcore_mac_crossbar_source_first <= 1'd0; + ethcore_mac_crossbar_source_last <= 1'd0; + ethcore_mac_crossbar_source_payload_ethernet_type <= 16'd0; + ethcore_mac_crossbar_source_payload_sender_mac <= 48'd0; + ethcore_mac_crossbar_source_payload_target_mac <= 48'd0; + ethcore_ip_mac_port_sink_ready <= 1'd0; + ethcore_mac_crossbar_source_payload_data <= 8'd0; + ethcore_mac_crossbar_source_payload_last_be <= 1'd0; + ethcore_mac_crossbar_source_payload_error <= 1'd0; + ethcore_arp_mac_port_sink_ready <= 1'd0; + case (liteethudpipcore_liteethmac_grant) + 1'd0: begin + ethcore_mac_crossbar_source_valid <= ethcore_arp_mac_port_sink_valid; + ethcore_arp_mac_port_sink_ready <= ethcore_mac_crossbar_source_ready; + ethcore_mac_crossbar_source_first <= ethcore_arp_mac_port_sink_first; + ethcore_mac_crossbar_source_last <= ethcore_arp_mac_port_sink_last; + ethcore_mac_crossbar_source_payload_ethernet_type <= ethcore_arp_mac_port_sink_payload_ethernet_type; + ethcore_mac_crossbar_source_payload_sender_mac <= ethcore_arp_mac_port_sink_payload_sender_mac; + ethcore_mac_crossbar_source_payload_target_mac <= ethcore_arp_mac_port_sink_payload_target_mac; + ethcore_mac_crossbar_source_payload_data <= ethcore_arp_mac_port_sink_payload_data; + ethcore_mac_crossbar_source_payload_last_be <= ethcore_arp_mac_port_sink_payload_last_be; + ethcore_mac_crossbar_source_payload_error <= ethcore_arp_mac_port_sink_payload_error; + end + 1'd1: begin + ethcore_mac_crossbar_source_valid <= ethcore_ip_mac_port_sink_valid; + ethcore_ip_mac_port_sink_ready <= ethcore_mac_crossbar_source_ready; + ethcore_mac_crossbar_source_first <= ethcore_ip_mac_port_sink_first; + ethcore_mac_crossbar_source_last <= ethcore_ip_mac_port_sink_last; + ethcore_mac_crossbar_source_payload_ethernet_type <= ethcore_ip_mac_port_sink_payload_ethernet_type; + ethcore_mac_crossbar_source_payload_sender_mac <= ethcore_ip_mac_port_sink_payload_sender_mac; + ethcore_mac_crossbar_source_payload_target_mac <= ethcore_ip_mac_port_sink_payload_target_mac; + ethcore_mac_crossbar_source_payload_data <= ethcore_ip_mac_port_sink_payload_data; + ethcore_mac_crossbar_source_payload_last_be <= ethcore_ip_mac_port_sink_payload_last_be; + ethcore_mac_crossbar_source_payload_error <= ethcore_ip_mac_port_sink_payload_error; + end + endcase +end +always @(*) begin + liteethudpipcore_liteethmac_status0_last <= 1'd0; + if (ethcore_arp_mac_port_sink_valid) begin + liteethudpipcore_liteethmac_status0_last <= (ethcore_arp_mac_port_sink_last & ethcore_arp_mac_port_sink_ready); + end +end +assign liteethudpipcore_liteethmac_status0_ongoing0 = ((ethcore_arp_mac_port_sink_valid | liteethudpipcore_liteethmac_status0_ongoing1) & (~liteethudpipcore_liteethmac_status0_last)); +always @(*) begin + liteethudpipcore_liteethmac_status1_last <= 1'd0; + if (ethcore_ip_mac_port_sink_valid) begin + liteethudpipcore_liteethmac_status1_last <= (ethcore_ip_mac_port_sink_last & ethcore_ip_mac_port_sink_ready); + end +end +assign liteethudpipcore_liteethmac_status1_ongoing0 = ((ethcore_ip_mac_port_sink_valid | liteethudpipcore_liteethmac_status1_ongoing1) & (~liteethudpipcore_liteethmac_status1_last)); +always @(*) begin + liteethudpipcore_liteethmac_sel1 <= 2'd0; + if (liteethudpipcore_liteethmac_first) begin + liteethudpipcore_liteethmac_sel1 <= liteethudpipcore_liteethmac_sel0; + end else begin + liteethudpipcore_liteethmac_sel1 <= liteethudpipcore_liteethmac_sel_ongoing; + end +end +always @(*) begin + ethcore_arp_mac_port_source_valid <= 1'd0; + ethcore_arp_mac_port_source_first <= 1'd0; + ethcore_arp_mac_port_source_last <= 1'd0; + ethcore_arp_mac_port_source_payload_ethernet_type <= 16'd0; + ethcore_arp_mac_port_source_payload_sender_mac <= 48'd0; + ethcore_arp_mac_port_source_payload_target_mac <= 48'd0; + ethcore_arp_mac_port_source_payload_data <= 8'd0; + ethcore_ip_mac_port_source_valid <= 1'd0; + ethcore_arp_mac_port_source_payload_last_be <= 1'd0; + ethcore_arp_mac_port_source_payload_error <= 1'd0; + ethcore_ip_mac_port_source_first <= 1'd0; + ethcore_ip_mac_port_source_last <= 1'd0; + ethcore_ip_mac_port_source_payload_ethernet_type <= 16'd0; + ethcore_ip_mac_port_source_payload_sender_mac <= 48'd0; + ethcore_ip_mac_port_source_payload_target_mac <= 48'd0; + ethcore_ip_mac_port_source_payload_data <= 8'd0; + ethcore_ip_mac_port_source_payload_last_be <= 1'd0; + ethcore_ip_mac_port_source_payload_error <= 1'd0; + ethcore_mac_crossbar_sink_ready <= 1'd0; + case (liteethudpipcore_liteethmac_sel1) + 1'd1: begin + ethcore_arp_mac_port_source_valid <= ethcore_mac_crossbar_sink_valid; + ethcore_mac_crossbar_sink_ready <= ethcore_arp_mac_port_source_ready; + ethcore_arp_mac_port_source_first <= ethcore_mac_crossbar_sink_first; + ethcore_arp_mac_port_source_last <= ethcore_mac_crossbar_sink_last; + ethcore_arp_mac_port_source_payload_ethernet_type <= ethcore_mac_crossbar_sink_payload_ethernet_type; + ethcore_arp_mac_port_source_payload_sender_mac <= ethcore_mac_crossbar_sink_payload_sender_mac; + ethcore_arp_mac_port_source_payload_target_mac <= ethcore_mac_crossbar_sink_payload_target_mac; + ethcore_arp_mac_port_source_payload_data <= ethcore_mac_crossbar_sink_payload_data; + ethcore_arp_mac_port_source_payload_last_be <= ethcore_mac_crossbar_sink_payload_last_be; + ethcore_arp_mac_port_source_payload_error <= ethcore_mac_crossbar_sink_payload_error; + end + 2'd2: begin + ethcore_ip_mac_port_source_valid <= ethcore_mac_crossbar_sink_valid; + ethcore_mac_crossbar_sink_ready <= ethcore_ip_mac_port_source_ready; + ethcore_ip_mac_port_source_first <= ethcore_mac_crossbar_sink_first; + ethcore_ip_mac_port_source_last <= ethcore_mac_crossbar_sink_last; + ethcore_ip_mac_port_source_payload_ethernet_type <= ethcore_mac_crossbar_sink_payload_ethernet_type; + ethcore_ip_mac_port_source_payload_sender_mac <= ethcore_mac_crossbar_sink_payload_sender_mac; + ethcore_ip_mac_port_source_payload_target_mac <= ethcore_mac_crossbar_sink_payload_target_mac; + ethcore_ip_mac_port_source_payload_data <= ethcore_mac_crossbar_sink_payload_data; + ethcore_ip_mac_port_source_payload_last_be <= ethcore_mac_crossbar_sink_payload_last_be; + ethcore_ip_mac_port_source_payload_error <= ethcore_mac_crossbar_sink_payload_error; + end + default: begin + ethcore_mac_crossbar_sink_ready <= 1'd1; + end + endcase +end +always @(*) begin + liteethudpipcore_liteethmac_last <= 1'd0; + if (ethcore_mac_crossbar_sink_valid) begin + liteethudpipcore_liteethmac_last <= (ethcore_mac_crossbar_sink_last & ethcore_mac_crossbar_sink_ready); + end +end +assign liteethudpipcore_liteethmac_ongoing0 = ((ethcore_mac_crossbar_sink_valid | liteethudpipcore_liteethmac_ongoing1) & (~liteethudpipcore_liteethmac_last)); +always @(*) begin + ethcore_mac_packetizer_header <= 112'd0; + ethcore_mac_packetizer_header[111:96] <= {ethcore_mac_packetizer_sink_payload_ethernet_type[7:0], ethcore_mac_packetizer_sink_payload_ethernet_type[15:8]}; + ethcore_mac_packetizer_header[95:48] <= {ethcore_mac_packetizer_sink_payload_sender_mac[7:0], ethcore_mac_packetizer_sink_payload_sender_mac[15:8], ethcore_mac_packetizer_sink_payload_sender_mac[23:16], ethcore_mac_packetizer_sink_payload_sender_mac[31:24], ethcore_mac_packetizer_sink_payload_sender_mac[39:32], ethcore_mac_packetizer_sink_payload_sender_mac[47:40]}; + ethcore_mac_packetizer_header[47:0] <= {ethcore_mac_packetizer_sink_payload_target_mac[7:0], ethcore_mac_packetizer_sink_payload_target_mac[15:8], ethcore_mac_packetizer_sink_payload_target_mac[23:16], ethcore_mac_packetizer_sink_payload_target_mac[31:24], ethcore_mac_packetizer_sink_payload_target_mac[39:32], ethcore_mac_packetizer_sink_payload_target_mac[47:40]}; +end +assign ethcore_mac_packetizer_source_payload_error = ethcore_mac_packetizer_sink_payload_error; +assign ethcore_mac_packetizer_source_payload_last_be = {ethcore_mac_packetizer_sink_payload_last_be}; +always @(*) begin + liteethudpipcore_liteethmac_liteethmacpacketizer_next_state <= 2'd0; + ethcore_mac_packetizer_source_last <= 1'd0; + ethcore_mac_packetizer_count_liteethmacpacketizer_next_value0 <= 4'd0; + ethcore_mac_packetizer_count_liteethmacpacketizer_next_value_ce0 <= 1'd0; + ethcore_mac_packetizer_source_payload_data <= 8'd0; + ethcore_mac_packetizer_sink_ready <= 1'd0; + ethcore_mac_packetizer_fsm_from_idle_liteethmacpacketizer_next_value1 <= 1'd0; + ethcore_mac_packetizer_fsm_from_idle_liteethmacpacketizer_next_value_ce1 <= 1'd0; + ethcore_mac_packetizer_sr_load <= 1'd0; + ethcore_mac_packetizer_sr_shift <= 1'd0; + ethcore_mac_packetizer_source_valid <= 1'd0; + liteethudpipcore_liteethmac_liteethmacpacketizer_next_state <= liteethudpipcore_liteethmac_liteethmacpacketizer_state; + case (liteethudpipcore_liteethmac_liteethmacpacketizer_state) + 1'd1: begin + ethcore_mac_packetizer_source_valid <= 1'd1; + ethcore_mac_packetizer_source_last <= 1'd0; + ethcore_mac_packetizer_source_payload_data <= ethcore_mac_packetizer_sr[111:8]; + if ((ethcore_mac_packetizer_source_valid & ethcore_mac_packetizer_source_ready)) begin + ethcore_mac_packetizer_sr_shift <= 1'd1; + if ((ethcore_mac_packetizer_count == 4'd13)) begin + ethcore_mac_packetizer_sr_shift <= 1'd0; + if (1'd0) begin + liteethudpipcore_liteethmac_liteethmacpacketizer_next_state <= 2'd3; + ethcore_mac_packetizer_count_liteethmacpacketizer_next_value0 <= (ethcore_mac_packetizer_count + 1'd1); + ethcore_mac_packetizer_count_liteethmacpacketizer_next_value_ce0 <= 1'd1; + end else begin + liteethudpipcore_liteethmac_liteethmacpacketizer_next_state <= 2'd2; + end + end else begin + ethcore_mac_packetizer_count_liteethmacpacketizer_next_value0 <= (ethcore_mac_packetizer_count + 1'd1); + ethcore_mac_packetizer_count_liteethmacpacketizer_next_value_ce0 <= 1'd1; + end + end + end + 2'd2: begin + ethcore_mac_packetizer_source_valid <= ethcore_mac_packetizer_sink_valid; + ethcore_mac_packetizer_source_last <= ethcore_mac_packetizer_sink_last; + ethcore_mac_packetizer_source_payload_data <= ethcore_mac_packetizer_sink_payload_data; + if ((ethcore_mac_packetizer_source_valid & ethcore_mac_packetizer_source_ready)) begin + ethcore_mac_packetizer_sink_ready <= 1'd1; + if (ethcore_mac_packetizer_source_last) begin + liteethudpipcore_liteethmac_liteethmacpacketizer_next_state <= 1'd0; + end + end + end + 2'd3: begin + ethcore_mac_packetizer_source_valid <= (ethcore_mac_packetizer_sink_valid | ethcore_mac_packetizer_sink_d_last); + ethcore_mac_packetizer_source_last <= ethcore_mac_packetizer_sink_d_last; + if (ethcore_mac_packetizer_fsm_from_idle) begin + ethcore_mac_packetizer_source_payload_data[0] <= ethcore_mac_packetizer_sr[111:16]; + end else begin + ethcore_mac_packetizer_source_payload_data[0] <= ethcore_mac_packetizer_sink_d_payload_data[7]; + end + ethcore_mac_packetizer_source_payload_data[7:0] <= ethcore_mac_packetizer_sink_payload_data; + if ((ethcore_mac_packetizer_source_valid & ethcore_mac_packetizer_source_ready)) begin + ethcore_mac_packetizer_sink_ready <= (~ethcore_mac_packetizer_source_last); + ethcore_mac_packetizer_fsm_from_idle_liteethmacpacketizer_next_value1 <= 1'd0; + ethcore_mac_packetizer_fsm_from_idle_liteethmacpacketizer_next_value_ce1 <= 1'd1; + if (ethcore_mac_packetizer_source_last) begin + liteethudpipcore_liteethmac_liteethmacpacketizer_next_state <= 1'd0; + end + end + end + default: begin + ethcore_mac_packetizer_sink_ready <= 1'd1; + ethcore_mac_packetizer_count_liteethmacpacketizer_next_value0 <= 1'd1; + ethcore_mac_packetizer_count_liteethmacpacketizer_next_value_ce0 <= 1'd1; + if (ethcore_mac_packetizer_sink_valid) begin + ethcore_mac_packetizer_sink_ready <= 1'd0; + ethcore_mac_packetizer_source_valid <= 1'd1; + ethcore_mac_packetizer_source_last <= 1'd0; + ethcore_mac_packetizer_source_payload_data <= ethcore_mac_packetizer_header[7:0]; + if ((ethcore_mac_packetizer_source_valid & ethcore_mac_packetizer_source_ready)) begin + ethcore_mac_packetizer_sr_load <= 1'd1; + ethcore_mac_packetizer_fsm_from_idle_liteethmacpacketizer_next_value1 <= 1'd1; + ethcore_mac_packetizer_fsm_from_idle_liteethmacpacketizer_next_value_ce1 <= 1'd1; + if (1'd0) begin + if (1'd0) begin + liteethudpipcore_liteethmac_liteethmacpacketizer_next_state <= 2'd3; + end else begin + liteethudpipcore_liteethmac_liteethmacpacketizer_next_state <= 2'd2; + end + end else begin + liteethudpipcore_liteethmac_liteethmacpacketizer_next_state <= 1'd1; + end + end + end + end + endcase +end +assign ethcore_mac_depacketizer_header = ethcore_mac_depacketizer_sr; +assign ethcore_mac_depacketizer_source_payload_ethernet_type = {rhs_slice_proxy1[7:0], rhs_slice_proxy0[15:8]}; +assign ethcore_mac_depacketizer_source_payload_sender_mac = {rhs_slice_proxy7[7:0], rhs_slice_proxy6[15:8], rhs_slice_proxy5[23:16], rhs_slice_proxy4[31:24], rhs_slice_proxy3[39:32], rhs_slice_proxy2[47:40]}; +assign ethcore_mac_depacketizer_source_payload_target_mac = {rhs_slice_proxy13[7:0], rhs_slice_proxy12[15:8], rhs_slice_proxy11[23:16], rhs_slice_proxy10[31:24], rhs_slice_proxy9[39:32], rhs_slice_proxy8[47:40]}; +assign ethcore_mac_depacketizer_source_payload_error = ethcore_mac_depacketizer_sink_payload_error; +assign ethcore_mac_depacketizer_source_payload_last_be = {ethcore_mac_depacketizer_sink_payload_last_be}; +always @(*) begin + ethcore_mac_depacketizer_sink_ready <= 1'd0; + ethcore_mac_depacketizer_sr_shift <= 1'd0; + ethcore_mac_depacketizer_sr_shift_leftover <= 1'd0; + ethcore_mac_depacketizer_source_valid <= 1'd0; + liteethudpipcore_liteethmac_liteethmacdepacketizer_next_state <= 2'd0; + ethcore_mac_depacketizer_count_liteethmacdepacketizer_next_value0 <= 4'd0; + ethcore_mac_depacketizer_count_liteethmacdepacketizer_next_value_ce0 <= 1'd0; + ethcore_mac_depacketizer_source_last <= 1'd0; + ethcore_mac_depacketizer_fsm_from_idle_liteethmacdepacketizer_next_value1 <= 1'd0; + ethcore_mac_depacketizer_fsm_from_idle_liteethmacdepacketizer_next_value_ce1 <= 1'd0; + ethcore_mac_depacketizer_source_payload_data <= 8'd0; + liteethudpipcore_liteethmac_liteethmacdepacketizer_next_state <= liteethudpipcore_liteethmac_liteethmacdepacketizer_state; + case (liteethudpipcore_liteethmac_liteethmacdepacketizer_state) + 1'd1: begin + ethcore_mac_depacketizer_sink_ready <= 1'd1; + if (ethcore_mac_depacketizer_sink_valid) begin + ethcore_mac_depacketizer_count_liteethmacdepacketizer_next_value0 <= (ethcore_mac_depacketizer_count + 1'd1); + ethcore_mac_depacketizer_count_liteethmacdepacketizer_next_value_ce0 <= 1'd1; + ethcore_mac_depacketizer_sr_shift <= 1'd1; + if ((ethcore_mac_depacketizer_count == 4'd13)) begin + if (1'd0) begin + ethcore_mac_depacketizer_count_liteethmacdepacketizer_next_value0 <= (ethcore_mac_depacketizer_count + 1'd1); + ethcore_mac_depacketizer_count_liteethmacdepacketizer_next_value_ce0 <= 1'd1; + liteethudpipcore_liteethmac_liteethmacdepacketizer_next_state <= 2'd2; + end else begin + liteethudpipcore_liteethmac_liteethmacdepacketizer_next_state <= 2'd3; + end + end + end + end + 2'd2: begin + ethcore_mac_depacketizer_source_valid <= (ethcore_mac_depacketizer_sink_valid | ethcore_mac_depacketizer_sink_d_last); + ethcore_mac_depacketizer_source_last <= (ethcore_mac_depacketizer_sink_last | ethcore_mac_depacketizer_sink_d_last); + ethcore_mac_depacketizer_sink_ready <= ethcore_mac_depacketizer_source_ready; + ethcore_mac_depacketizer_source_payload_data <= ethcore_mac_depacketizer_sink_d_payload_data[7:0]; + ethcore_mac_depacketizer_source_payload_data[7] <= ethcore_mac_depacketizer_sink_payload_data; + if (ethcore_mac_depacketizer_fsm_from_idle) begin + ethcore_mac_depacketizer_source_valid <= ethcore_mac_depacketizer_sink_d_last; + ethcore_mac_depacketizer_sink_ready <= 1'd1; + if (ethcore_mac_depacketizer_sink_valid) begin + ethcore_mac_depacketizer_fsm_from_idle_liteethmacdepacketizer_next_value1 <= 1'd0; + ethcore_mac_depacketizer_fsm_from_idle_liteethmacdepacketizer_next_value_ce1 <= 1'd1; + ethcore_mac_depacketizer_sr_shift_leftover <= 1'd1; + end + end + if ((ethcore_mac_depacketizer_source_valid & ethcore_mac_depacketizer_source_ready)) begin + if (ethcore_mac_depacketizer_source_last) begin + liteethudpipcore_liteethmac_liteethmacdepacketizer_next_state <= 1'd0; + end + end + end + 2'd3: begin + ethcore_mac_depacketizer_source_valid <= (ethcore_mac_depacketizer_sink_valid | ethcore_mac_depacketizer_sink_d_last); + ethcore_mac_depacketizer_source_last <= (ethcore_mac_depacketizer_sink_last | ethcore_mac_depacketizer_sink_d_last); + ethcore_mac_depacketizer_sink_ready <= ethcore_mac_depacketizer_source_ready; + ethcore_mac_depacketizer_source_payload_data <= ethcore_mac_depacketizer_sink_payload_data; + if ((ethcore_mac_depacketizer_source_valid & ethcore_mac_depacketizer_source_ready)) begin + if (ethcore_mac_depacketizer_source_last) begin + liteethudpipcore_liteethmac_liteethmacdepacketizer_next_state <= 1'd0; + end + end + end + default: begin + ethcore_mac_depacketizer_sink_ready <= 1'd1; + ethcore_mac_depacketizer_count_liteethmacdepacketizer_next_value0 <= 1'd1; + ethcore_mac_depacketizer_count_liteethmacdepacketizer_next_value_ce0 <= 1'd1; + if (ethcore_mac_depacketizer_sink_valid) begin + ethcore_mac_depacketizer_sr_shift <= 1'd1; + ethcore_mac_depacketizer_fsm_from_idle_liteethmacdepacketizer_next_value1 <= 1'd1; + ethcore_mac_depacketizer_fsm_from_idle_liteethmacdepacketizer_next_value_ce1 <= 1'd1; + if (1'd0) begin + if (1'd0) begin + liteethudpipcore_liteethmac_liteethmacdepacketizer_next_state <= 2'd2; + end else begin + liteethudpipcore_liteethmac_liteethmacdepacketizer_next_state <= 2'd3; + end + end else begin + liteethudpipcore_liteethmac_liteethmacdepacketizer_next_state <= 1'd1; + end + end + end + endcase +end +assign ethcore_arp_table_sink_valid = ethcore_arp_rx_source_source_valid; +assign ethcore_arp_rx_source_source_ready = ethcore_arp_table_sink_ready; +assign ethcore_arp_table_sink_first = ethcore_arp_rx_source_source_first; +assign ethcore_arp_table_sink_last = ethcore_arp_rx_source_source_last; +assign ethcore_arp_table_sink_payload_reply = ethcore_arp_rx_source_source_payload_reply; +assign ethcore_arp_table_sink_payload_request = ethcore_arp_rx_source_source_payload_request; +assign ethcore_arp_table_sink_payload_ip_address = ethcore_arp_rx_source_source_payload_ip_address; +assign ethcore_arp_table_sink_payload_mac_address = ethcore_arp_rx_source_source_payload_mac_address; +assign ethcore_arp_tx_sink_sink_valid = ethcore_arp_table_source_valid; +assign ethcore_arp_table_source_ready = ethcore_arp_tx_sink_sink_ready; +assign ethcore_arp_tx_sink_sink_first = ethcore_arp_table_source_first; +assign ethcore_arp_tx_sink_sink_last = ethcore_arp_table_source_last; +assign ethcore_arp_tx_sink_sink_payload_reply = ethcore_arp_table_source_payload_reply; +assign ethcore_arp_tx_sink_sink_payload_request = ethcore_arp_table_source_payload_request; +assign ethcore_arp_tx_sink_sink_payload_ip_address = ethcore_arp_table_source_payload_ip_address; +assign ethcore_arp_tx_sink_sink_payload_mac_address = ethcore_arp_table_source_payload_mac_address; +assign ethcore_arp_mac_port_sink_valid = ethcore_arp_tx_source_source_valid; +assign ethcore_arp_tx_source_source_ready = ethcore_arp_mac_port_sink_ready; +assign ethcore_arp_mac_port_sink_first = ethcore_arp_tx_source_source_first; +assign ethcore_arp_mac_port_sink_last = ethcore_arp_tx_source_source_last; +assign ethcore_arp_mac_port_sink_payload_ethernet_type = ethcore_arp_tx_source_source_payload_ethernet_type; +assign ethcore_arp_mac_port_sink_payload_sender_mac = ethcore_arp_tx_source_source_payload_sender_mac; +assign ethcore_arp_mac_port_sink_payload_target_mac = ethcore_arp_tx_source_source_payload_target_mac; +assign ethcore_arp_mac_port_sink_payload_data = ethcore_arp_tx_source_source_payload_data; +assign ethcore_arp_mac_port_sink_payload_last_be = ethcore_arp_tx_source_source_payload_last_be; +assign ethcore_arp_mac_port_sink_payload_error = ethcore_arp_tx_source_source_payload_error; +assign ethcore_arp_rx_sink_sink_valid = ethcore_arp_mac_port_source_valid; +assign ethcore_arp_mac_port_source_ready = ethcore_arp_rx_sink_sink_ready; +assign ethcore_arp_rx_sink_sink_first = ethcore_arp_mac_port_source_first; +assign ethcore_arp_rx_sink_sink_last = ethcore_arp_mac_port_source_last; +assign ethcore_arp_rx_sink_sink_payload_ethernet_type = ethcore_arp_mac_port_source_payload_ethernet_type; +assign ethcore_arp_rx_sink_sink_payload_sender_mac = ethcore_arp_mac_port_source_payload_sender_mac; +assign ethcore_arp_rx_sink_sink_payload_target_mac = ethcore_arp_mac_port_source_payload_target_mac; +assign ethcore_arp_rx_sink_sink_payload_data = ethcore_arp_mac_port_source_payload_data; +assign ethcore_arp_rx_sink_sink_payload_last_be = ethcore_arp_mac_port_source_payload_last_be; +assign ethcore_arp_rx_sink_sink_payload_error = ethcore_arp_mac_port_source_payload_error; +assign ethcore_arp_tx_packetizer_sink_last = (ethcore_arp_tx_counter == 6'd45); +assign ethcore_arp_tx_packetizer_sink_param_hwtype = 1'd1; +assign ethcore_arp_tx_packetizer_sink_param_proto = 12'd2048; +assign ethcore_arp_tx_packetizer_sink_param_hwsize = 3'd6; +assign ethcore_arp_tx_packetizer_sink_param_protosize = 3'd4; +assign ethcore_arp_tx_packetizer_sink_param_sender_mac = 45'd18566422200320; +assign ethcore_arp_tx_packetizer_sink_param_sender_ip = 32'd3232235826; +always @(*) begin + ethcore_arp_tx_packetizer_sink_param_target_mac <= 48'd0; + ethcore_arp_tx_packetizer_sink_param_opcode <= 16'd0; + ethcore_arp_tx_packetizer_sink_param_target_ip <= 32'd0; + if (ethcore_arp_tx_sink_sink_payload_reply) begin + ethcore_arp_tx_packetizer_sink_param_opcode <= 2'd2; + ethcore_arp_tx_packetizer_sink_param_target_mac <= ethcore_arp_tx_sink_sink_payload_mac_address; + ethcore_arp_tx_packetizer_sink_param_target_ip <= ethcore_arp_tx_sink_sink_payload_ip_address; + end else begin + if (ethcore_arp_tx_sink_sink_payload_request) begin + ethcore_arp_tx_packetizer_sink_param_opcode <= 1'd1; + ethcore_arp_tx_packetizer_sink_param_target_mac <= 48'd281474976710655; + ethcore_arp_tx_packetizer_sink_param_target_ip <= ethcore_arp_tx_sink_sink_payload_ip_address; + end + end +end +always @(*) begin + ethcore_arp_tx_packetizer_header <= 224'd0; + ethcore_arp_tx_packetizer_header[39:32] <= {ethcore_arp_tx_packetizer_sink_param_hwsize[7:0]}; + ethcore_arp_tx_packetizer_header[15:0] <= {ethcore_arp_tx_packetizer_sink_param_hwtype[7:0], ethcore_arp_tx_packetizer_sink_param_hwtype[15:8]}; + ethcore_arp_tx_packetizer_header[63:48] <= {ethcore_arp_tx_packetizer_sink_param_opcode[7:0], ethcore_arp_tx_packetizer_sink_param_opcode[15:8]}; + ethcore_arp_tx_packetizer_header[31:16] <= {ethcore_arp_tx_packetizer_sink_param_proto[7:0], ethcore_arp_tx_packetizer_sink_param_proto[15:8]}; + ethcore_arp_tx_packetizer_header[47:40] <= {ethcore_arp_tx_packetizer_sink_param_protosize[7:0]}; + ethcore_arp_tx_packetizer_header[143:112] <= {ethcore_arp_tx_packetizer_sink_param_sender_ip[7:0], ethcore_arp_tx_packetizer_sink_param_sender_ip[15:8], ethcore_arp_tx_packetizer_sink_param_sender_ip[23:16], ethcore_arp_tx_packetizer_sink_param_sender_ip[31:24]}; + ethcore_arp_tx_packetizer_header[111:64] <= {ethcore_arp_tx_packetizer_sink_param_sender_mac[7:0], ethcore_arp_tx_packetizer_sink_param_sender_mac[15:8], ethcore_arp_tx_packetizer_sink_param_sender_mac[23:16], ethcore_arp_tx_packetizer_sink_param_sender_mac[31:24], ethcore_arp_tx_packetizer_sink_param_sender_mac[39:32], ethcore_arp_tx_packetizer_sink_param_sender_mac[47:40]}; + ethcore_arp_tx_packetizer_header[223:192] <= {ethcore_arp_tx_packetizer_sink_param_target_ip[7:0], ethcore_arp_tx_packetizer_sink_param_target_ip[15:8], ethcore_arp_tx_packetizer_sink_param_target_ip[23:16], ethcore_arp_tx_packetizer_sink_param_target_ip[31:24]}; + ethcore_arp_tx_packetizer_header[191:144] <= {ethcore_arp_tx_packetizer_sink_param_target_mac[7:0], ethcore_arp_tx_packetizer_sink_param_target_mac[15:8], ethcore_arp_tx_packetizer_sink_param_target_mac[23:16], ethcore_arp_tx_packetizer_sink_param_target_mac[31:24], ethcore_arp_tx_packetizer_sink_param_target_mac[39:32], ethcore_arp_tx_packetizer_sink_param_target_mac[47:40]}; +end +assign ethcore_arp_tx_packetizer_source_payload_error = ethcore_arp_tx_packetizer_sink_payload_error; +always @(*) begin + ethcore_arp_tx_packetizer_source_payload_data <= 8'd0; + ethcore_arp_tx_packetizer_fsm_from_idle_liteetharp_liteetharppacketizer_next_value1 <= 1'd0; + ethcore_arp_tx_packetizer_fsm_from_idle_liteetharp_liteetharppacketizer_next_value_ce1 <= 1'd0; + ethcore_arp_tx_packetizer_sr_load <= 1'd0; + ethcore_arp_tx_packetizer_sr_shift <= 1'd0; + ethcore_arp_tx_packetizer_source_valid <= 1'd0; + ethcore_arp_tx_packetizer_sink_ready <= 1'd0; + ethcore_arp_tx_packetizer_source_last <= 1'd0; + liteethudpipcore_liteetharptx_liteetharppacketizer_next_state <= 2'd0; + ethcore_arp_tx_packetizer_count_liteetharp_liteetharppacketizer_next_value0 <= 5'd0; + ethcore_arp_tx_packetizer_count_liteetharp_liteetharppacketizer_next_value_ce0 <= 1'd0; + liteethudpipcore_liteetharptx_liteetharppacketizer_next_state <= liteethudpipcore_liteetharptx_liteetharppacketizer_state; + case (liteethudpipcore_liteetharptx_liteetharppacketizer_state) + 1'd1: begin + ethcore_arp_tx_packetizer_source_valid <= 1'd1; + ethcore_arp_tx_packetizer_source_last <= 1'd0; + ethcore_arp_tx_packetizer_source_payload_data <= ethcore_arp_tx_packetizer_sr[223:8]; + if ((ethcore_arp_tx_packetizer_source_valid & ethcore_arp_tx_packetizer_source_ready)) begin + ethcore_arp_tx_packetizer_sr_shift <= 1'd1; + if ((ethcore_arp_tx_packetizer_count == 5'd27)) begin + ethcore_arp_tx_packetizer_sr_shift <= 1'd0; + if (1'd0) begin + liteethudpipcore_liteetharptx_liteetharppacketizer_next_state <= 2'd3; + ethcore_arp_tx_packetizer_count_liteetharp_liteetharppacketizer_next_value0 <= (ethcore_arp_tx_packetizer_count + 1'd1); + ethcore_arp_tx_packetizer_count_liteetharp_liteetharppacketizer_next_value_ce0 <= 1'd1; + end else begin + liteethudpipcore_liteetharptx_liteetharppacketizer_next_state <= 2'd2; + end + end else begin + ethcore_arp_tx_packetizer_count_liteetharp_liteetharppacketizer_next_value0 <= (ethcore_arp_tx_packetizer_count + 1'd1); + ethcore_arp_tx_packetizer_count_liteetharp_liteetharppacketizer_next_value_ce0 <= 1'd1; + end + end + end + 2'd2: begin + ethcore_arp_tx_packetizer_source_valid <= ethcore_arp_tx_packetizer_sink_valid; + ethcore_arp_tx_packetizer_source_last <= ethcore_arp_tx_packetizer_sink_last; + ethcore_arp_tx_packetizer_source_payload_data <= ethcore_arp_tx_packetizer_sink_payload_data; + if ((ethcore_arp_tx_packetizer_source_valid & ethcore_arp_tx_packetizer_source_ready)) begin + ethcore_arp_tx_packetizer_sink_ready <= 1'd1; + if (ethcore_arp_tx_packetizer_source_last) begin + liteethudpipcore_liteetharptx_liteetharppacketizer_next_state <= 1'd0; + end + end + end + 2'd3: begin + ethcore_arp_tx_packetizer_source_valid <= (ethcore_arp_tx_packetizer_sink_valid | ethcore_arp_tx_packetizer_sink_d_last); + ethcore_arp_tx_packetizer_source_last <= ethcore_arp_tx_packetizer_sink_d_last; + if (ethcore_arp_tx_packetizer_fsm_from_idle) begin + ethcore_arp_tx_packetizer_source_payload_data[0] <= ethcore_arp_tx_packetizer_sr[223:16]; + end else begin + ethcore_arp_tx_packetizer_source_payload_data[0] <= ethcore_arp_tx_packetizer_sink_d_payload_data[7]; + end + ethcore_arp_tx_packetizer_source_payload_data[7:0] <= ethcore_arp_tx_packetizer_sink_payload_data; + if ((ethcore_arp_tx_packetizer_source_valid & ethcore_arp_tx_packetizer_source_ready)) begin + ethcore_arp_tx_packetizer_sink_ready <= (~ethcore_arp_tx_packetizer_source_last); + ethcore_arp_tx_packetizer_fsm_from_idle_liteetharp_liteetharppacketizer_next_value1 <= 1'd0; + ethcore_arp_tx_packetizer_fsm_from_idle_liteetharp_liteetharppacketizer_next_value_ce1 <= 1'd1; + if (ethcore_arp_tx_packetizer_source_last) begin + liteethudpipcore_liteetharptx_liteetharppacketizer_next_state <= 1'd0; + end + end + end + default: begin + ethcore_arp_tx_packetizer_sink_ready <= 1'd1; + ethcore_arp_tx_packetizer_count_liteetharp_liteetharppacketizer_next_value0 <= 1'd1; + ethcore_arp_tx_packetizer_count_liteetharp_liteetharppacketizer_next_value_ce0 <= 1'd1; + if (ethcore_arp_tx_packetizer_sink_valid) begin + ethcore_arp_tx_packetizer_sink_ready <= 1'd0; + ethcore_arp_tx_packetizer_source_valid <= 1'd1; + ethcore_arp_tx_packetizer_source_last <= 1'd0; + ethcore_arp_tx_packetizer_source_payload_data <= ethcore_arp_tx_packetizer_header[7:0]; + if ((ethcore_arp_tx_packetizer_source_valid & ethcore_arp_tx_packetizer_source_ready)) begin + ethcore_arp_tx_packetizer_sr_load <= 1'd1; + ethcore_arp_tx_packetizer_fsm_from_idle_liteetharp_liteetharppacketizer_next_value1 <= 1'd1; + ethcore_arp_tx_packetizer_fsm_from_idle_liteetharp_liteetharppacketizer_next_value_ce1 <= 1'd1; + if (1'd0) begin + if (1'd0) begin + liteethudpipcore_liteetharptx_liteetharppacketizer_next_state <= 2'd3; + end else begin + liteethudpipcore_liteetharptx_liteetharppacketizer_next_state <= 2'd2; + end + end else begin + liteethudpipcore_liteetharptx_liteetharppacketizer_next_state <= 1'd1; + end + end + end + end + endcase +end +always @(*) begin + ethcore_arp_tx_source_source_first <= 1'd0; + ethcore_arp_tx_source_source_last <= 1'd0; + ethcore_arp_tx_source_source_payload_ethernet_type <= 16'd0; + ethcore_arp_tx_source_source_payload_sender_mac <= 48'd0; + liteethudpipcore_liteetharptx_fsm_next_state <= 1'd0; + ethcore_arp_tx_source_source_payload_target_mac <= 48'd0; + ethcore_arp_tx_counter_liteetharp_fsm_next_value <= 6'd0; + ethcore_arp_tx_source_source_payload_data <= 8'd0; + ethcore_arp_tx_counter_liteetharp_fsm_next_value_ce <= 1'd0; + ethcore_arp_tx_source_source_payload_last_be <= 1'd0; + ethcore_arp_tx_sink_sink_ready <= 1'd0; + ethcore_arp_tx_source_source_payload_error <= 1'd0; + ethcore_arp_tx_packetizer_sink_valid <= 1'd0; + ethcore_arp_tx_packetizer_source_ready <= 1'd0; + ethcore_arp_tx_source_source_valid <= 1'd0; + liteethudpipcore_liteetharptx_fsm_next_state <= liteethudpipcore_liteetharptx_fsm_state; + case (liteethudpipcore_liteetharptx_fsm_state) + 1'd1: begin + ethcore_arp_tx_packetizer_sink_valid <= 1'd1; + ethcore_arp_tx_source_source_valid <= ethcore_arp_tx_packetizer_source_valid; + ethcore_arp_tx_packetizer_source_ready <= ethcore_arp_tx_source_source_ready; + ethcore_arp_tx_source_source_first <= ethcore_arp_tx_packetizer_source_first; + ethcore_arp_tx_source_source_last <= ethcore_arp_tx_packetizer_source_last; + ethcore_arp_tx_source_source_payload_ethernet_type <= ethcore_arp_tx_packetizer_source_payload_ethernet_type; + ethcore_arp_tx_source_source_payload_sender_mac <= ethcore_arp_tx_packetizer_source_payload_sender_mac; + ethcore_arp_tx_source_source_payload_target_mac <= ethcore_arp_tx_packetizer_source_payload_target_mac; + ethcore_arp_tx_source_source_payload_data <= ethcore_arp_tx_packetizer_source_payload_data; + ethcore_arp_tx_source_source_payload_last_be <= ethcore_arp_tx_packetizer_source_payload_last_be; + ethcore_arp_tx_source_source_payload_error <= ethcore_arp_tx_packetizer_source_payload_error; + ethcore_arp_tx_source_source_payload_target_mac <= ethcore_arp_tx_packetizer_sink_param_target_mac; + ethcore_arp_tx_source_source_payload_sender_mac <= 45'd18566422200320; + ethcore_arp_tx_source_source_payload_ethernet_type <= 12'd2054; + if ((ethcore_arp_tx_source_source_valid & ethcore_arp_tx_source_source_ready)) begin + ethcore_arp_tx_counter_liteetharp_fsm_next_value <= (ethcore_arp_tx_counter + 1'd1); + ethcore_arp_tx_counter_liteetharp_fsm_next_value_ce <= 1'd1; + if (ethcore_arp_tx_source_source_last) begin + ethcore_arp_tx_sink_sink_ready <= 1'd1; + liteethudpipcore_liteetharptx_fsm_next_state <= 1'd0; + end + end + end + default: begin + ethcore_arp_tx_sink_sink_ready <= 1'd1; + ethcore_arp_tx_counter_liteetharp_fsm_next_value <= 1'd0; + ethcore_arp_tx_counter_liteetharp_fsm_next_value_ce <= 1'd1; + if (ethcore_arp_tx_sink_sink_valid) begin + ethcore_arp_tx_sink_sink_ready <= 1'd0; + liteethudpipcore_liteetharptx_fsm_next_state <= 1'd1; + end + end + endcase +end +assign ethcore_arp_rx_depacketizer_sink_valid = ethcore_arp_rx_sink_sink_valid; +assign ethcore_arp_rx_sink_sink_ready = ethcore_arp_rx_depacketizer_sink_ready; +assign ethcore_arp_rx_depacketizer_sink_first = ethcore_arp_rx_sink_sink_first; +assign ethcore_arp_rx_depacketizer_sink_last = ethcore_arp_rx_sink_sink_last; +assign ethcore_arp_rx_depacketizer_sink_payload_ethernet_type = ethcore_arp_rx_sink_sink_payload_ethernet_type; +assign ethcore_arp_rx_depacketizer_sink_payload_sender_mac = ethcore_arp_rx_sink_sink_payload_sender_mac; +assign ethcore_arp_rx_depacketizer_sink_payload_target_mac = ethcore_arp_rx_sink_sink_payload_target_mac; +assign ethcore_arp_rx_depacketizer_sink_payload_data = ethcore_arp_rx_sink_sink_payload_data; +assign ethcore_arp_rx_depacketizer_sink_payload_last_be = ethcore_arp_rx_sink_sink_payload_last_be; +assign ethcore_arp_rx_depacketizer_sink_payload_error = ethcore_arp_rx_sink_sink_payload_error; +always @(*) begin + ethcore_arp_rx_request <= 1'd0; + ethcore_arp_rx_reply <= 1'd0; + case (ethcore_arp_rx_depacketizer_source_param_opcode) + 1'd1: begin + ethcore_arp_rx_request <= 1'd1; + end + 2'd2: begin + ethcore_arp_rx_reply <= 1'd1; + end + default: begin + end + endcase +end +assign ethcore_arp_rx_source_source_payload_ip_address = ethcore_arp_rx_depacketizer_source_param_sender_ip; +assign ethcore_arp_rx_source_source_payload_mac_address = ethcore_arp_rx_depacketizer_source_param_sender_mac; +assign ethcore_arp_rx_depacketizer_header = ethcore_arp_rx_depacketizer_sr; +assign ethcore_arp_rx_depacketizer_source_param_hwsize = {rhs_slice_proxy14[7:0]}; +assign ethcore_arp_rx_depacketizer_source_param_hwtype = {rhs_slice_proxy16[7:0], rhs_slice_proxy15[15:8]}; +assign ethcore_arp_rx_depacketizer_source_param_opcode = {rhs_slice_proxy18[7:0], rhs_slice_proxy17[15:8]}; +assign ethcore_arp_rx_depacketizer_source_param_proto = {rhs_slice_proxy20[7:0], rhs_slice_proxy19[15:8]}; +assign ethcore_arp_rx_depacketizer_source_param_protosize = {rhs_slice_proxy21[7:0]}; +assign ethcore_arp_rx_depacketizer_source_param_sender_ip = {rhs_slice_proxy25[7:0], rhs_slice_proxy24[15:8], rhs_slice_proxy23[23:16], rhs_slice_proxy22[31:24]}; +assign ethcore_arp_rx_depacketizer_source_param_sender_mac = {rhs_slice_proxy31[7:0], rhs_slice_proxy30[15:8], rhs_slice_proxy29[23:16], rhs_slice_proxy28[31:24], rhs_slice_proxy27[39:32], rhs_slice_proxy26[47:40]}; +assign ethcore_arp_rx_depacketizer_source_param_target_ip = {rhs_slice_proxy35[7:0], rhs_slice_proxy34[15:8], rhs_slice_proxy33[23:16], rhs_slice_proxy32[31:24]}; +assign ethcore_arp_rx_depacketizer_source_param_target_mac = {rhs_slice_proxy41[7:0], rhs_slice_proxy40[15:8], rhs_slice_proxy39[23:16], rhs_slice_proxy38[31:24], rhs_slice_proxy37[39:32], rhs_slice_proxy36[47:40]}; +assign ethcore_arp_rx_depacketizer_source_payload_error = ethcore_arp_rx_depacketizer_sink_payload_error; +always @(*) begin + ethcore_arp_rx_depacketizer_count_liteetharp_next_value0 <= 5'd0; + ethcore_arp_rx_depacketizer_count_liteetharp_next_value_ce0 <= 1'd0; + ethcore_arp_rx_depacketizer_fsm_from_idle_liteetharp_next_value1 <= 1'd0; + ethcore_arp_rx_depacketizer_fsm_from_idle_liteetharp_next_value_ce1 <= 1'd0; + ethcore_arp_rx_depacketizer_source_valid <= 1'd0; + ethcore_arp_rx_depacketizer_sr_shift <= 1'd0; + ethcore_arp_rx_depacketizer_sr_shift_leftover <= 1'd0; + ethcore_arp_rx_depacketizer_source_last <= 1'd0; + ethcore_arp_rx_depacketizer_source_payload_data <= 8'd0; + ethcore_arp_rx_depacketizer_sink_ready <= 1'd0; + liteethudpipcore_liteetharprx_liteetharpdepacketizer_next_state <= 2'd0; + liteethudpipcore_liteetharprx_liteetharpdepacketizer_next_state <= liteethudpipcore_liteetharprx_liteetharpdepacketizer_state; + case (liteethudpipcore_liteetharprx_liteetharpdepacketizer_state) + 1'd1: begin + ethcore_arp_rx_depacketizer_sink_ready <= 1'd1; + if (ethcore_arp_rx_depacketizer_sink_valid) begin + ethcore_arp_rx_depacketizer_count_liteetharp_next_value0 <= (ethcore_arp_rx_depacketizer_count + 1'd1); + ethcore_arp_rx_depacketizer_count_liteetharp_next_value_ce0 <= 1'd1; + ethcore_arp_rx_depacketizer_sr_shift <= 1'd1; + if ((ethcore_arp_rx_depacketizer_count == 5'd27)) begin + if (1'd0) begin + ethcore_arp_rx_depacketizer_count_liteetharp_next_value0 <= (ethcore_arp_rx_depacketizer_count + 1'd1); + ethcore_arp_rx_depacketizer_count_liteetharp_next_value_ce0 <= 1'd1; + liteethudpipcore_liteetharprx_liteetharpdepacketizer_next_state <= 2'd2; + end else begin + liteethudpipcore_liteetharprx_liteetharpdepacketizer_next_state <= 2'd3; + end + end + end + end + 2'd2: begin + ethcore_arp_rx_depacketizer_source_valid <= (ethcore_arp_rx_depacketizer_sink_valid | ethcore_arp_rx_depacketizer_sink_d_last); + ethcore_arp_rx_depacketizer_source_last <= (ethcore_arp_rx_depacketizer_sink_last | ethcore_arp_rx_depacketizer_sink_d_last); + ethcore_arp_rx_depacketizer_sink_ready <= ethcore_arp_rx_depacketizer_source_ready; + ethcore_arp_rx_depacketizer_source_payload_data <= ethcore_arp_rx_depacketizer_sink_d_payload_data[7:0]; + ethcore_arp_rx_depacketizer_source_payload_data[7] <= ethcore_arp_rx_depacketizer_sink_payload_data; + if (ethcore_arp_rx_depacketizer_fsm_from_idle) begin + ethcore_arp_rx_depacketizer_source_valid <= ethcore_arp_rx_depacketizer_sink_d_last; + ethcore_arp_rx_depacketizer_sink_ready <= 1'd1; + if (ethcore_arp_rx_depacketizer_sink_valid) begin + ethcore_arp_rx_depacketizer_fsm_from_idle_liteetharp_next_value1 <= 1'd0; + ethcore_arp_rx_depacketizer_fsm_from_idle_liteetharp_next_value_ce1 <= 1'd1; + ethcore_arp_rx_depacketizer_sr_shift_leftover <= 1'd1; + end + end + if ((ethcore_arp_rx_depacketizer_source_valid & ethcore_arp_rx_depacketizer_source_ready)) begin + if (ethcore_arp_rx_depacketizer_source_last) begin + liteethudpipcore_liteetharprx_liteetharpdepacketizer_next_state <= 1'd0; + end + end + end + 2'd3: begin + ethcore_arp_rx_depacketizer_source_valid <= (ethcore_arp_rx_depacketizer_sink_valid | ethcore_arp_rx_depacketizer_sink_d_last); + ethcore_arp_rx_depacketizer_source_last <= (ethcore_arp_rx_depacketizer_sink_last | ethcore_arp_rx_depacketizer_sink_d_last); + ethcore_arp_rx_depacketizer_sink_ready <= ethcore_arp_rx_depacketizer_source_ready; + ethcore_arp_rx_depacketizer_source_payload_data <= ethcore_arp_rx_depacketizer_sink_payload_data; + if ((ethcore_arp_rx_depacketizer_source_valid & ethcore_arp_rx_depacketizer_source_ready)) begin + if (ethcore_arp_rx_depacketizer_source_last) begin + liteethudpipcore_liteetharprx_liteetharpdepacketizer_next_state <= 1'd0; + end + end + end + default: begin + ethcore_arp_rx_depacketizer_sink_ready <= 1'd1; + ethcore_arp_rx_depacketizer_count_liteetharp_next_value0 <= 1'd1; + ethcore_arp_rx_depacketizer_count_liteetharp_next_value_ce0 <= 1'd1; + if (ethcore_arp_rx_depacketizer_sink_valid) begin + ethcore_arp_rx_depacketizer_sr_shift <= 1'd1; + ethcore_arp_rx_depacketizer_fsm_from_idle_liteetharp_next_value1 <= 1'd1; + ethcore_arp_rx_depacketizer_fsm_from_idle_liteetharp_next_value_ce1 <= 1'd1; + if (1'd0) begin + if (1'd0) begin + liteethudpipcore_liteetharprx_liteetharpdepacketizer_next_state <= 2'd2; + end else begin + liteethudpipcore_liteetharprx_liteetharpdepacketizer_next_state <= 2'd3; + end + end else begin + liteethudpipcore_liteetharprx_liteetharpdepacketizer_next_state <= 1'd1; + end + end + end + endcase +end +always @(*) begin + ethcore_arp_rx_source_source_payload_reply <= 1'd0; + ethcore_arp_rx_source_source_payload_request <= 1'd0; + ethcore_arp_rx_source_source_valid <= 1'd0; + liteethudpipcore_liteetharprx_fsm_next_state <= 2'd0; + ethcore_arp_rx_depacketizer_source_ready <= 1'd0; + liteethudpipcore_liteetharprx_fsm_next_state <= liteethudpipcore_liteetharprx_fsm_state; + case (liteethudpipcore_liteetharprx_fsm_state) + 1'd1: begin + if (ethcore_arp_rx_valid) begin + ethcore_arp_rx_source_source_valid <= 1'd1; + ethcore_arp_rx_source_source_payload_reply <= ethcore_arp_rx_reply; + ethcore_arp_rx_source_source_payload_request <= ethcore_arp_rx_request; + end + liteethudpipcore_liteetharprx_fsm_next_state <= 2'd2; + end + 2'd2: begin + ethcore_arp_rx_depacketizer_source_ready <= 1'd1; + if ((ethcore_arp_rx_depacketizer_source_valid & ethcore_arp_rx_depacketizer_source_last)) begin + liteethudpipcore_liteetharprx_fsm_next_state <= 1'd0; + end + end + default: begin + ethcore_arp_rx_depacketizer_source_ready <= 1'd1; + if (ethcore_arp_rx_depacketizer_source_valid) begin + ethcore_arp_rx_depacketizer_source_ready <= 1'd0; + liteethudpipcore_liteetharprx_fsm_next_state <= 1'd1; + end + end + endcase +end +assign ethcore_arp_table_request_timer_wait = (ethcore_arp_table_request_pending & (~ethcore_arp_table_request_counter_ce)); +assign ethcore_arp_table_cached_timer_wait = (~ethcore_arp_table_update); +assign ethcore_arp_table_response_payload_mac_address = ethcore_arp_table_cached_mac_address; +assign ethcore_arp_table_request_timer_done = (ethcore_arp_table_request_timer_count == 1'd0); +assign ethcore_arp_table_cached_timer_done = (ethcore_arp_table_cached_timer_count == 1'd0); +always @(*) begin + ethcore_arp_table_source_valid <= 1'd0; + ethcore_arp_table_request_counter_reset <= 1'd0; + ethcore_arp_table_response_payload_failed <= 1'd0; + ethcore_arp_table_request_counter_ce <= 1'd0; + ethcore_arp_table_source_payload_reply <= 1'd0; + ethcore_arp_table_request_pending_clr <= 1'd0; + ethcore_arp_table_source_payload_request <= 1'd0; + ethcore_arp_table_update <= 1'd0; + ethcore_arp_table_source_payload_ip_address <= 32'd0; + ethcore_arp_table_request_pending_set <= 1'd0; + ethcore_arp_table_source_payload_mac_address <= 48'd0; + ethcore_arp_table_request_ip_address_reset <= 1'd0; + ethcore_arp_table_request_ready <= 1'd0; + ethcore_arp_table_request_ip_address_update <= 1'd0; + liteethudpipcore_next_state <= 3'd0; + ethcore_arp_table_response_valid <= 1'd0; + if ((ethcore_arp_table_request_counter == 3'd7)) begin + ethcore_arp_table_response_payload_failed <= 1'd1; + ethcore_arp_table_request_counter_reset <= 1'd1; + ethcore_arp_table_request_pending_clr <= 1'd1; + end + liteethudpipcore_next_state <= liteethudpipcore_state; + case (liteethudpipcore_state) + 1'd1: begin + ethcore_arp_table_source_valid <= 1'd1; + ethcore_arp_table_source_payload_reply <= 1'd1; + ethcore_arp_table_source_payload_ip_address <= ethcore_arp_table_sink_payload_ip_address; + ethcore_arp_table_source_payload_mac_address <= ethcore_arp_table_sink_payload_mac_address; + if (ethcore_arp_table_source_ready) begin + liteethudpipcore_next_state <= 1'd0; + end + end + 2'd2: begin + ethcore_arp_table_request_pending_clr <= 1'd1; + ethcore_arp_table_update <= 1'd1; + liteethudpipcore_next_state <= 2'd3; + end + 2'd3: begin + if (ethcore_arp_table_cached_valid) begin + if ((ethcore_arp_table_request_ip_address == ethcore_arp_table_cached_ip_address)) begin + ethcore_arp_table_request_ip_address_reset <= 1'd1; + liteethudpipcore_next_state <= 3'd5; + end else begin + if ((ethcore_arp_table_request_payload_ip_address == ethcore_arp_table_cached_ip_address)) begin + ethcore_arp_table_request_ready <= ethcore_arp_table_request_valid; + liteethudpipcore_next_state <= 3'd5; + end else begin + ethcore_arp_table_request_ip_address_update <= ethcore_arp_table_request_valid; + liteethudpipcore_next_state <= 3'd4; + end + end + end else begin + ethcore_arp_table_request_ip_address_update <= ethcore_arp_table_request_valid; + liteethudpipcore_next_state <= 3'd4; + end + end + 3'd4: begin + ethcore_arp_table_source_valid <= 1'd1; + ethcore_arp_table_source_payload_request <= 1'd1; + ethcore_arp_table_source_payload_ip_address <= ethcore_arp_table_request_ip_address; + if (ethcore_arp_table_source_ready) begin + ethcore_arp_table_request_counter_reset <= ethcore_arp_table_request_valid; + ethcore_arp_table_request_counter_ce <= 1'd1; + ethcore_arp_table_request_pending_set <= 1'd1; + ethcore_arp_table_request_ready <= 1'd1; + liteethudpipcore_next_state <= 1'd0; + end + end + 3'd5: begin + ethcore_arp_table_response_valid <= 1'd1; + if (ethcore_arp_table_response_ready) begin + liteethudpipcore_next_state <= 1'd0; + end + end + default: begin + if ((ethcore_arp_table_sink_valid & ethcore_arp_table_sink_payload_request)) begin + liteethudpipcore_next_state <= 1'd1; + end else begin + if (((ethcore_arp_table_sink_valid & ethcore_arp_table_sink_payload_reply) & ethcore_arp_table_request_pending)) begin + liteethudpipcore_next_state <= 2'd2; + end else begin + if ((ethcore_arp_table_request_counter == 3'd7)) begin + liteethudpipcore_next_state <= 3'd5; + end else begin + if ((ethcore_arp_table_request_valid | (ethcore_arp_table_request_pending & ethcore_arp_table_request_timer_done))) begin + liteethudpipcore_next_state <= 2'd3; + end + end + end + end + end + endcase +end +assign ethcore_ip_mac_port_sink_valid = ethcore_ip_tx_source_source_valid; +assign ethcore_ip_tx_source_source_ready = ethcore_ip_mac_port_sink_ready; +assign ethcore_ip_mac_port_sink_first = ethcore_ip_tx_source_source_first; +assign ethcore_ip_mac_port_sink_last = ethcore_ip_tx_source_source_last; +assign ethcore_ip_mac_port_sink_payload_ethernet_type = ethcore_ip_tx_source_source_payload_ethernet_type; +assign ethcore_ip_mac_port_sink_payload_sender_mac = ethcore_ip_tx_source_source_payload_sender_mac; +assign ethcore_ip_mac_port_sink_payload_target_mac = ethcore_ip_tx_source_source_payload_target_mac; +assign ethcore_ip_mac_port_sink_payload_data = ethcore_ip_tx_source_source_payload_data; +assign ethcore_ip_mac_port_sink_payload_last_be = ethcore_ip_tx_source_source_payload_last_be; +assign ethcore_ip_mac_port_sink_payload_error = ethcore_ip_tx_source_source_payload_error; +assign ethcore_ip_rx_sink_sink_valid = ethcore_ip_mac_port_source_valid; +assign ethcore_ip_mac_port_source_ready = ethcore_ip_rx_sink_sink_ready; +assign ethcore_ip_rx_sink_sink_first = ethcore_ip_mac_port_source_first; +assign ethcore_ip_rx_sink_sink_last = ethcore_ip_mac_port_source_last; +assign ethcore_ip_rx_sink_sink_payload_ethernet_type = ethcore_ip_mac_port_source_payload_ethernet_type; +assign ethcore_ip_rx_sink_sink_payload_sender_mac = ethcore_ip_mac_port_source_payload_sender_mac; +assign ethcore_ip_rx_sink_sink_payload_target_mac = ethcore_ip_mac_port_source_payload_target_mac; +assign ethcore_ip_rx_sink_sink_payload_data = ethcore_ip_mac_port_source_payload_data; +assign ethcore_ip_rx_sink_sink_payload_last_be = ethcore_ip_mac_port_source_payload_last_be; +assign ethcore_ip_rx_sink_sink_payload_error = ethcore_ip_mac_port_source_payload_error; +assign ethcore_ip_tx_sink_sink_valid = ethcore_ip_crossbar_source_valid; +assign ethcore_ip_crossbar_source_ready = ethcore_ip_tx_sink_sink_ready; +assign ethcore_ip_tx_sink_sink_first = ethcore_ip_crossbar_source_first; +assign ethcore_ip_tx_sink_sink_last = ethcore_ip_crossbar_source_last; +assign ethcore_ip_tx_sink_sink_payload_data = ethcore_ip_crossbar_source_payload_data; +assign ethcore_ip_tx_sink_sink_payload_error = ethcore_ip_crossbar_source_payload_error; +assign ethcore_ip_tx_sink_sink_param_length = ethcore_ip_crossbar_source_param_length; +assign ethcore_ip_tx_sink_sink_param_protocol = ethcore_ip_crossbar_source_param_protocol; +assign ethcore_ip_tx_sink_sink_param_ip_address = ethcore_ip_crossbar_source_param_ip_address; +assign ethcore_ip_crossbar_sink_valid = ethcore_ip_rx_source_source_valid; +assign ethcore_ip_rx_source_source_ready = ethcore_ip_crossbar_sink_ready; +assign ethcore_ip_crossbar_sink_first = ethcore_ip_rx_source_source_first; +assign ethcore_ip_crossbar_sink_last = ethcore_ip_rx_source_source_last; +assign ethcore_ip_crossbar_sink_payload_data = ethcore_ip_rx_source_source_payload_data; +assign ethcore_ip_crossbar_sink_payload_error = ethcore_ip_rx_source_source_payload_error; +assign ethcore_ip_crossbar_sink_param_length = ethcore_ip_rx_source_source_param_length; +assign ethcore_ip_crossbar_sink_param_protocol = ethcore_ip_rx_source_source_param_protocol; +assign ethcore_ip_crossbar_sink_param_ip_address = ethcore_ip_rx_source_source_param_ip_address; +assign ethcore_ip_tx_ce = ethcore_ip_tx_sink_sink_valid; +assign ethcore_ip_tx_reset = ((ethcore_ip_tx_source_source_valid & ethcore_ip_tx_source_source_last) & ethcore_ip_tx_source_source_ready); +assign ethcore_ip_tx_packetizer_sink_valid = (ethcore_ip_tx_sink_sink_valid & ethcore_ip_tx_liteethipv4checksum_done); +assign ethcore_ip_tx_packetizer_sink_last = ethcore_ip_tx_sink_sink_last; +assign ethcore_ip_tx_sink_sink_ready = (ethcore_ip_tx_packetizer_sink_ready & ethcore_ip_tx_liteethipv4checksum_done); +assign ethcore_ip_tx_packetizer_sink_param_target_ip = ethcore_ip_tx_sink_sink_param_ip_address; +assign ethcore_ip_tx_packetizer_sink_param_protocol = ethcore_ip_tx_sink_sink_param_protocol; +assign ethcore_ip_tx_packetizer_sink_param_total_length = (5'd20 + ethcore_ip_tx_sink_sink_param_length); +assign ethcore_ip_tx_packetizer_sink_param_version = 3'd4; +assign ethcore_ip_tx_packetizer_sink_param_ihl = 3'd5; +assign ethcore_ip_tx_packetizer_sink_param_identification = 1'd0; +assign ethcore_ip_tx_packetizer_sink_param_ttl = 8'd128; +assign ethcore_ip_tx_packetizer_sink_param_sender_ip = 32'd3232235826; +assign ethcore_ip_tx_packetizer_sink_payload_data = ethcore_ip_tx_sink_sink_payload_data; +assign ethcore_ip_tx_liteethipv4checksum_header = ethcore_ip_tx_packetizer_header; +assign ethcore_ip_tx_packetizer_sink_param_checksum = ethcore_ip_tx_liteethipv4checksum_value; +assign ethcore_arp_table_request_payload_ip_address = ethcore_ip_tx_sink_sink_param_ip_address; +assign ethcore_ip_tx_liteethipv4checksum_s_next0 = (ethcore_ip_tx_liteethipv4checksum_r + ethcore_ip_tx_liteethipv4checksum_header[15:0]); +assign ethcore_ip_tx_liteethipv4checksum_s_next1 = (ethcore_ip_tx_liteethipv4checksum_r_next0 + ethcore_ip_tx_liteethipv4checksum_header[31:16]); +assign ethcore_ip_tx_liteethipv4checksum_s_next2 = (ethcore_ip_tx_liteethipv4checksum_r_next1 + ethcore_ip_tx_liteethipv4checksum_header[47:32]); +assign ethcore_ip_tx_liteethipv4checksum_s_next3 = (ethcore_ip_tx_liteethipv4checksum_r_next2 + ethcore_ip_tx_liteethipv4checksum_header[63:48]); +assign ethcore_ip_tx_liteethipv4checksum_s_next4 = (ethcore_ip_tx_liteethipv4checksum_r_next3 + ethcore_ip_tx_liteethipv4checksum_header[79:64]); +assign ethcore_ip_tx_liteethipv4checksum_s_next5 = (ethcore_ip_tx_liteethipv4checksum_r_next4 + ethcore_ip_tx_liteethipv4checksum_header[111:96]); +assign ethcore_ip_tx_liteethipv4checksum_s_next6 = (ethcore_ip_tx_liteethipv4checksum_r_next5 + ethcore_ip_tx_liteethipv4checksum_header[127:112]); +assign ethcore_ip_tx_liteethipv4checksum_s_next7 = (ethcore_ip_tx_liteethipv4checksum_r_next6 + ethcore_ip_tx_liteethipv4checksum_header[143:128]); +assign ethcore_ip_tx_liteethipv4checksum_s_next8 = (ethcore_ip_tx_liteethipv4checksum_r_next7 + ethcore_ip_tx_liteethipv4checksum_header[159:144]); +assign ethcore_ip_tx_liteethipv4checksum_value = (~{ethcore_ip_tx_liteethipv4checksum_r_next8[7:0], ethcore_ip_tx_liteethipv4checksum_r_next8[15:8]}); +assign ethcore_ip_tx_liteethipv4checksum_counter_ce = (~ethcore_ip_tx_liteethipv4checksum_done); +assign ethcore_ip_tx_liteethipv4checksum_done = (ethcore_ip_tx_liteethipv4checksum_counter == 4'd9); +always @(*) begin + ethcore_ip_tx_packetizer_header <= 160'd0; + ethcore_ip_tx_packetizer_header[95:80] <= {ethcore_ip_tx_packetizer_sink_param_checksum[7:0], ethcore_ip_tx_packetizer_sink_param_checksum[15:8]}; + ethcore_ip_tx_packetizer_header[47:32] <= {ethcore_ip_tx_packetizer_sink_param_identification[7:0], ethcore_ip_tx_packetizer_sink_param_identification[15:8]}; + ethcore_ip_tx_packetizer_header[3:0] <= {ethcore_ip_tx_packetizer_sink_param_ihl[3:0]}; + ethcore_ip_tx_packetizer_header[79:72] <= {ethcore_ip_tx_packetizer_sink_param_protocol[7:0]}; + ethcore_ip_tx_packetizer_header[127:96] <= {ethcore_ip_tx_packetizer_sink_param_sender_ip[7:0], ethcore_ip_tx_packetizer_sink_param_sender_ip[15:8], ethcore_ip_tx_packetizer_sink_param_sender_ip[23:16], ethcore_ip_tx_packetizer_sink_param_sender_ip[31:24]}; + ethcore_ip_tx_packetizer_header[159:128] <= {ethcore_ip_tx_packetizer_sink_param_target_ip[7:0], ethcore_ip_tx_packetizer_sink_param_target_ip[15:8], ethcore_ip_tx_packetizer_sink_param_target_ip[23:16], ethcore_ip_tx_packetizer_sink_param_target_ip[31:24]}; + ethcore_ip_tx_packetizer_header[31:16] <= {ethcore_ip_tx_packetizer_sink_param_total_length[7:0], ethcore_ip_tx_packetizer_sink_param_total_length[15:8]}; + ethcore_ip_tx_packetizer_header[71:64] <= {ethcore_ip_tx_packetizer_sink_param_ttl[7:0]}; + ethcore_ip_tx_packetizer_header[7:4] <= {ethcore_ip_tx_packetizer_sink_param_version[3:0]}; +end +assign ethcore_ip_tx_packetizer_source_payload_error = ethcore_ip_tx_packetizer_sink_payload_error; +always @(*) begin + ethcore_ip_tx_packetizer_sink_ready <= 1'd0; + ethcore_ip_tx_packetizer_source_last <= 1'd0; + ethcore_ip_tx_packetizer_fsm_from_idle_liteethip_liteethipv4packetizer_next_value1 <= 1'd0; + ethcore_ip_tx_packetizer_fsm_from_idle_liteethip_liteethipv4packetizer_next_value_ce1 <= 1'd0; + ethcore_ip_tx_packetizer_source_payload_data <= 8'd0; + ethcore_ip_tx_packetizer_count_liteethip_liteethipv4packetizer_next_value_ce0 <= 1'd0; + ethcore_ip_tx_packetizer_sr_load <= 1'd0; + ethcore_ip_tx_packetizer_sr_shift <= 1'd0; + liteethudpipcore_liteethip_liteethiptx_liteethipv4packetizer_next_state <= 2'd0; + ethcore_ip_tx_packetizer_count_liteethip_liteethipv4packetizer_next_value0 <= 5'd0; + ethcore_ip_tx_packetizer_source_valid <= 1'd0; + liteethudpipcore_liteethip_liteethiptx_liteethipv4packetizer_next_state <= liteethudpipcore_liteethip_liteethiptx_liteethipv4packetizer_state; + case (liteethudpipcore_liteethip_liteethiptx_liteethipv4packetizer_state) + 1'd1: begin + ethcore_ip_tx_packetizer_source_valid <= 1'd1; + ethcore_ip_tx_packetizer_source_last <= 1'd0; + ethcore_ip_tx_packetizer_source_payload_data <= ethcore_ip_tx_packetizer_sr[159:8]; + if ((ethcore_ip_tx_packetizer_source_valid & ethcore_ip_tx_packetizer_source_ready)) begin + ethcore_ip_tx_packetizer_sr_shift <= 1'd1; + if ((ethcore_ip_tx_packetizer_count == 5'd19)) begin + ethcore_ip_tx_packetizer_sr_shift <= 1'd0; + if (1'd0) begin + liteethudpipcore_liteethip_liteethiptx_liteethipv4packetizer_next_state <= 2'd3; + ethcore_ip_tx_packetizer_count_liteethip_liteethipv4packetizer_next_value0 <= (ethcore_ip_tx_packetizer_count + 1'd1); + ethcore_ip_tx_packetizer_count_liteethip_liteethipv4packetizer_next_value_ce0 <= 1'd1; + end else begin + liteethudpipcore_liteethip_liteethiptx_liteethipv4packetizer_next_state <= 2'd2; + end + end else begin + ethcore_ip_tx_packetizer_count_liteethip_liteethipv4packetizer_next_value0 <= (ethcore_ip_tx_packetizer_count + 1'd1); + ethcore_ip_tx_packetizer_count_liteethip_liteethipv4packetizer_next_value_ce0 <= 1'd1; + end + end + end + 2'd2: begin + ethcore_ip_tx_packetizer_source_valid <= ethcore_ip_tx_packetizer_sink_valid; + ethcore_ip_tx_packetizer_source_last <= ethcore_ip_tx_packetizer_sink_last; + ethcore_ip_tx_packetizer_source_payload_data <= ethcore_ip_tx_packetizer_sink_payload_data; + if ((ethcore_ip_tx_packetizer_source_valid & ethcore_ip_tx_packetizer_source_ready)) begin + ethcore_ip_tx_packetizer_sink_ready <= 1'd1; + if (ethcore_ip_tx_packetizer_source_last) begin + liteethudpipcore_liteethip_liteethiptx_liteethipv4packetizer_next_state <= 1'd0; + end + end + end + 2'd3: begin + ethcore_ip_tx_packetizer_source_valid <= (ethcore_ip_tx_packetizer_sink_valid | ethcore_ip_tx_packetizer_sink_d_last); + ethcore_ip_tx_packetizer_source_last <= ethcore_ip_tx_packetizer_sink_d_last; + if (ethcore_ip_tx_packetizer_fsm_from_idle) begin + ethcore_ip_tx_packetizer_source_payload_data[0] <= ethcore_ip_tx_packetizer_sr[159:16]; + end else begin + ethcore_ip_tx_packetizer_source_payload_data[0] <= ethcore_ip_tx_packetizer_sink_d_payload_data[7]; + end + ethcore_ip_tx_packetizer_source_payload_data[7:0] <= ethcore_ip_tx_packetizer_sink_payload_data; + if ((ethcore_ip_tx_packetizer_source_valid & ethcore_ip_tx_packetizer_source_ready)) begin + ethcore_ip_tx_packetizer_sink_ready <= (~ethcore_ip_tx_packetizer_source_last); + ethcore_ip_tx_packetizer_fsm_from_idle_liteethip_liteethipv4packetizer_next_value1 <= 1'd0; + ethcore_ip_tx_packetizer_fsm_from_idle_liteethip_liteethipv4packetizer_next_value_ce1 <= 1'd1; + if (ethcore_ip_tx_packetizer_source_last) begin + liteethudpipcore_liteethip_liteethiptx_liteethipv4packetizer_next_state <= 1'd0; + end + end + end + default: begin + ethcore_ip_tx_packetizer_sink_ready <= 1'd1; + ethcore_ip_tx_packetizer_count_liteethip_liteethipv4packetizer_next_value0 <= 1'd1; + ethcore_ip_tx_packetizer_count_liteethip_liteethipv4packetizer_next_value_ce0 <= 1'd1; + if (ethcore_ip_tx_packetizer_sink_valid) begin + ethcore_ip_tx_packetizer_sink_ready <= 1'd0; + ethcore_ip_tx_packetizer_source_valid <= 1'd1; + ethcore_ip_tx_packetizer_source_last <= 1'd0; + ethcore_ip_tx_packetizer_source_payload_data <= ethcore_ip_tx_packetizer_header[7:0]; + if ((ethcore_ip_tx_packetizer_source_valid & ethcore_ip_tx_packetizer_source_ready)) begin + ethcore_ip_tx_packetizer_sr_load <= 1'd1; + ethcore_ip_tx_packetizer_fsm_from_idle_liteethip_liteethipv4packetizer_next_value1 <= 1'd1; + ethcore_ip_tx_packetizer_fsm_from_idle_liteethip_liteethipv4packetizer_next_value_ce1 <= 1'd1; + if (1'd0) begin + if (1'd0) begin + liteethudpipcore_liteethip_liteethiptx_liteethipv4packetizer_next_state <= 2'd3; + end else begin + liteethudpipcore_liteethip_liteethiptx_liteethipv4packetizer_next_state <= 2'd2; + end + end else begin + liteethudpipcore_liteethip_liteethiptx_liteethipv4packetizer_next_state <= 1'd1; + end + end + end + end + endcase +end +always @(*) begin + ethcore_ip_tx_source_source_payload_sender_mac <= 48'd0; + ethcore_ip_tx_source_source_payload_target_mac <= 48'd0; + ethcore_ip_tx_source_source_payload_data <= 8'd0; + ethcore_ip_tx_packetizer_source_ready <= 1'd0; + ethcore_ip_tx_source_source_payload_last_be <= 1'd0; + ethcore_ip_tx_source_source_payload_error <= 1'd0; + ethcore_ip_tx_target_unreachable <= 1'd0; + ethcore_arp_table_request_valid <= 1'd0; + ethcore_arp_table_response_ready <= 1'd0; + liteethudpipcore_liteethip_liteethiptx_fsm_next_state <= 3'd0; + ethcore_ip_tx_target_mac_liteethip_fsm_next_value <= 48'd0; + ethcore_ip_tx_target_mac_liteethip_fsm_next_value_ce <= 1'd0; + ethcore_ip_tx_source_source_valid <= 1'd0; + ethcore_ip_tx_source_source_first <= 1'd0; + ethcore_ip_tx_source_source_last <= 1'd0; + ethcore_ip_tx_source_source_payload_ethernet_type <= 16'd0; + liteethudpipcore_liteethip_liteethiptx_fsm_next_state <= liteethudpipcore_liteethip_liteethiptx_fsm_state; + case (liteethudpipcore_liteethip_liteethiptx_fsm_state) + 1'd1: begin + ethcore_arp_table_request_valid <= 1'd1; + if ((ethcore_arp_table_request_valid & ethcore_arp_table_request_ready)) begin + liteethudpipcore_liteethip_liteethiptx_fsm_next_state <= 2'd2; + end + end + 2'd2: begin + if (ethcore_arp_table_response_valid) begin + ethcore_ip_tx_target_mac_liteethip_fsm_next_value <= ethcore_arp_table_response_payload_mac_address; + ethcore_ip_tx_target_mac_liteethip_fsm_next_value_ce <= 1'd1; + ethcore_arp_table_response_ready <= 1'd1; + if (ethcore_arp_table_response_payload_failed) begin + ethcore_ip_tx_target_unreachable <= 1'd1; + liteethudpipcore_liteethip_liteethiptx_fsm_next_state <= 3'd4; + end else begin + liteethudpipcore_liteethip_liteethiptx_fsm_next_state <= 2'd3; + end + end + end + 2'd3: begin + ethcore_ip_tx_source_source_valid <= ethcore_ip_tx_packetizer_source_valid; + ethcore_ip_tx_packetizer_source_ready <= ethcore_ip_tx_source_source_ready; + ethcore_ip_tx_source_source_first <= ethcore_ip_tx_packetizer_source_first; + ethcore_ip_tx_source_source_last <= ethcore_ip_tx_packetizer_source_last; + ethcore_ip_tx_source_source_payload_ethernet_type <= ethcore_ip_tx_packetizer_source_payload_ethernet_type; + ethcore_ip_tx_source_source_payload_sender_mac <= ethcore_ip_tx_packetizer_source_payload_sender_mac; + ethcore_ip_tx_source_source_payload_target_mac <= ethcore_ip_tx_packetizer_source_payload_target_mac; + ethcore_ip_tx_source_source_payload_data <= ethcore_ip_tx_packetizer_source_payload_data; + ethcore_ip_tx_source_source_payload_last_be <= ethcore_ip_tx_packetizer_source_payload_last_be; + ethcore_ip_tx_source_source_payload_error <= ethcore_ip_tx_packetizer_source_payload_error; + ethcore_ip_tx_source_source_payload_ethernet_type <= 12'd2048; + ethcore_ip_tx_source_source_payload_target_mac <= ethcore_ip_tx_target_mac; + ethcore_ip_tx_source_source_payload_sender_mac <= 45'd18566422200320; + if (((ethcore_ip_tx_source_source_valid & ethcore_ip_tx_source_source_last) & ethcore_ip_tx_source_source_ready)) begin + liteethudpipcore_liteethip_liteethiptx_fsm_next_state <= 1'd0; + end + end + 3'd4: begin + ethcore_ip_tx_packetizer_source_ready <= 1'd1; + if (((ethcore_ip_tx_packetizer_source_valid & ethcore_ip_tx_packetizer_source_last) & ethcore_ip_tx_packetizer_source_ready)) begin + liteethudpipcore_liteethip_liteethiptx_fsm_next_state <= 1'd0; + end + end + default: begin + ethcore_ip_tx_packetizer_source_ready <= 1'd1; + if (ethcore_ip_tx_packetizer_source_valid) begin + ethcore_ip_tx_packetizer_source_ready <= 1'd0; + if ((ethcore_ip_tx_sink_sink_param_ip_address[31:28] == 4'd14)) begin + ethcore_ip_tx_target_mac_liteethip_fsm_next_value <= {24'd65630, 1'd0, ethcore_ip_tx_sink_sink_param_ip_address[22:0]}; + ethcore_ip_tx_target_mac_liteethip_fsm_next_value_ce <= 1'd1; + liteethudpipcore_liteethip_liteethiptx_fsm_next_state <= 2'd3; + end else begin + liteethudpipcore_liteethip_liteethiptx_fsm_next_state <= 1'd1; + end + end + end + endcase +end +assign ethcore_ip_rx_depacketizer_sink_valid = ethcore_ip_rx_sink_sink_valid; +assign ethcore_ip_rx_sink_sink_ready = ethcore_ip_rx_depacketizer_sink_ready; +assign ethcore_ip_rx_depacketizer_sink_first = ethcore_ip_rx_sink_sink_first; +assign ethcore_ip_rx_depacketizer_sink_last = ethcore_ip_rx_sink_sink_last; +assign ethcore_ip_rx_depacketizer_sink_payload_ethernet_type = ethcore_ip_rx_sink_sink_payload_ethernet_type; +assign ethcore_ip_rx_depacketizer_sink_payload_sender_mac = ethcore_ip_rx_sink_sink_payload_sender_mac; +assign ethcore_ip_rx_depacketizer_sink_payload_target_mac = ethcore_ip_rx_sink_sink_payload_target_mac; +assign ethcore_ip_rx_depacketizer_sink_payload_data = ethcore_ip_rx_sink_sink_payload_data; +assign ethcore_ip_rx_depacketizer_sink_payload_last_be = ethcore_ip_rx_sink_sink_payload_last_be; +assign ethcore_ip_rx_depacketizer_sink_payload_error = ethcore_ip_rx_sink_sink_payload_error; +assign ethcore_ip_rx_liteethipv4checksum_header = ethcore_ip_rx_depacketizer_header; +assign ethcore_ip_rx_reset = (~ethcore_ip_rx_depacketizer_source_valid); +assign ethcore_ip_rx_ce = 1'd1; +assign ethcore_ip_rx_source_source_last = ethcore_ip_rx_depacketizer_source_last; +assign ethcore_ip_rx_source_source_param_length = (ethcore_ip_rx_depacketizer_source_param_total_length - 5'd20); +assign ethcore_ip_rx_source_source_param_protocol = ethcore_ip_rx_depacketizer_source_param_protocol; +assign ethcore_ip_rx_source_source_param_ip_address = ethcore_ip_rx_depacketizer_source_param_sender_ip; +assign ethcore_ip_rx_source_source_payload_data = ethcore_ip_rx_depacketizer_source_payload_data; +assign ethcore_ip_rx_source_source_payload_error = ethcore_ip_rx_depacketizer_source_payload_error; +assign ethcore_ip_rx_depacketizer_header = ethcore_ip_rx_depacketizer_sr; +assign ethcore_ip_rx_depacketizer_source_param_checksum = {rhs_slice_proxy43[7:0], rhs_slice_proxy42[15:8]}; +assign ethcore_ip_rx_depacketizer_source_param_identification = {rhs_slice_proxy45[7:0], rhs_slice_proxy44[15:8]}; +assign ethcore_ip_rx_depacketizer_source_param_ihl = {rhs_slice_proxy46[3:0]}; +assign ethcore_ip_rx_depacketizer_source_param_protocol = {rhs_slice_proxy47[7:0]}; +assign ethcore_ip_rx_depacketizer_source_param_sender_ip = {rhs_slice_proxy51[7:0], rhs_slice_proxy50[15:8], rhs_slice_proxy49[23:16], rhs_slice_proxy48[31:24]}; +assign ethcore_ip_rx_depacketizer_source_param_target_ip = {rhs_slice_proxy55[7:0], rhs_slice_proxy54[15:8], rhs_slice_proxy53[23:16], rhs_slice_proxy52[31:24]}; +assign ethcore_ip_rx_depacketizer_source_param_total_length = {rhs_slice_proxy57[7:0], rhs_slice_proxy56[15:8]}; +assign ethcore_ip_rx_depacketizer_source_param_ttl = {rhs_slice_proxy58[7:0]}; +assign ethcore_ip_rx_depacketizer_source_param_version = {rhs_slice_proxy59[3:0]}; +assign ethcore_ip_rx_depacketizer_source_payload_error = ethcore_ip_rx_depacketizer_sink_payload_error; +always @(*) begin + ethcore_ip_rx_depacketizer_sink_ready <= 1'd0; + liteethudpipcore_liteethip_liteethiprx_liteethipv4depacketizer_next_state <= 2'd0; + ethcore_ip_rx_depacketizer_count_liteethip_next_value0 <= 5'd0; + ethcore_ip_rx_depacketizer_count_liteethip_next_value_ce0 <= 1'd0; + ethcore_ip_rx_depacketizer_fsm_from_idle_liteethip_next_value1 <= 1'd0; + ethcore_ip_rx_depacketizer_fsm_from_idle_liteethip_next_value_ce1 <= 1'd0; + ethcore_ip_rx_depacketizer_source_valid <= 1'd0; + ethcore_ip_rx_depacketizer_sr_shift <= 1'd0; + ethcore_ip_rx_depacketizer_sr_shift_leftover <= 1'd0; + ethcore_ip_rx_depacketizer_source_last <= 1'd0; + ethcore_ip_rx_depacketizer_source_payload_data <= 8'd0; + liteethudpipcore_liteethip_liteethiprx_liteethipv4depacketizer_next_state <= liteethudpipcore_liteethip_liteethiprx_liteethipv4depacketizer_state; + case (liteethudpipcore_liteethip_liteethiprx_liteethipv4depacketizer_state) + 1'd1: begin + ethcore_ip_rx_depacketizer_sink_ready <= 1'd1; + if (ethcore_ip_rx_depacketizer_sink_valid) begin + ethcore_ip_rx_depacketizer_count_liteethip_next_value0 <= (ethcore_ip_rx_depacketizer_count + 1'd1); + ethcore_ip_rx_depacketizer_count_liteethip_next_value_ce0 <= 1'd1; + ethcore_ip_rx_depacketizer_sr_shift <= 1'd1; + if ((ethcore_ip_rx_depacketizer_count == 5'd19)) begin + if (1'd0) begin + ethcore_ip_rx_depacketizer_count_liteethip_next_value0 <= (ethcore_ip_rx_depacketizer_count + 1'd1); + ethcore_ip_rx_depacketizer_count_liteethip_next_value_ce0 <= 1'd1; + liteethudpipcore_liteethip_liteethiprx_liteethipv4depacketizer_next_state <= 2'd2; + end else begin + liteethudpipcore_liteethip_liteethiprx_liteethipv4depacketizer_next_state <= 2'd3; + end + end + end + end + 2'd2: begin + ethcore_ip_rx_depacketizer_source_valid <= (ethcore_ip_rx_depacketizer_sink_valid | ethcore_ip_rx_depacketizer_sink_d_last); + ethcore_ip_rx_depacketizer_source_last <= (ethcore_ip_rx_depacketizer_sink_last | ethcore_ip_rx_depacketizer_sink_d_last); + ethcore_ip_rx_depacketizer_sink_ready <= ethcore_ip_rx_depacketizer_source_ready; + ethcore_ip_rx_depacketizer_source_payload_data <= ethcore_ip_rx_depacketizer_sink_d_payload_data[7:0]; + ethcore_ip_rx_depacketizer_source_payload_data[7] <= ethcore_ip_rx_depacketizer_sink_payload_data; + if (ethcore_ip_rx_depacketizer_fsm_from_idle) begin + ethcore_ip_rx_depacketizer_source_valid <= ethcore_ip_rx_depacketizer_sink_d_last; + ethcore_ip_rx_depacketizer_sink_ready <= 1'd1; + if (ethcore_ip_rx_depacketizer_sink_valid) begin + ethcore_ip_rx_depacketizer_fsm_from_idle_liteethip_next_value1 <= 1'd0; + ethcore_ip_rx_depacketizer_fsm_from_idle_liteethip_next_value_ce1 <= 1'd1; + ethcore_ip_rx_depacketizer_sr_shift_leftover <= 1'd1; + end + end + if ((ethcore_ip_rx_depacketizer_source_valid & ethcore_ip_rx_depacketizer_source_ready)) begin + if (ethcore_ip_rx_depacketizer_source_last) begin + liteethudpipcore_liteethip_liteethiprx_liteethipv4depacketizer_next_state <= 1'd0; + end + end + end + 2'd3: begin + ethcore_ip_rx_depacketizer_source_valid <= (ethcore_ip_rx_depacketizer_sink_valid | ethcore_ip_rx_depacketizer_sink_d_last); + ethcore_ip_rx_depacketizer_source_last <= (ethcore_ip_rx_depacketizer_sink_last | ethcore_ip_rx_depacketizer_sink_d_last); + ethcore_ip_rx_depacketizer_sink_ready <= ethcore_ip_rx_depacketizer_source_ready; + ethcore_ip_rx_depacketizer_source_payload_data <= ethcore_ip_rx_depacketizer_sink_payload_data; + if ((ethcore_ip_rx_depacketizer_source_valid & ethcore_ip_rx_depacketizer_source_ready)) begin + if (ethcore_ip_rx_depacketizer_source_last) begin + liteethudpipcore_liteethip_liteethiprx_liteethipv4depacketizer_next_state <= 1'd0; + end + end + end + default: begin + ethcore_ip_rx_depacketizer_sink_ready <= 1'd1; + ethcore_ip_rx_depacketizer_count_liteethip_next_value0 <= 1'd1; + ethcore_ip_rx_depacketizer_count_liteethip_next_value_ce0 <= 1'd1; + if (ethcore_ip_rx_depacketizer_sink_valid) begin + ethcore_ip_rx_depacketizer_sr_shift <= 1'd1; + ethcore_ip_rx_depacketizer_fsm_from_idle_liteethip_next_value1 <= 1'd1; + ethcore_ip_rx_depacketizer_fsm_from_idle_liteethip_next_value_ce1 <= 1'd1; + if (1'd0) begin + if (1'd0) begin + liteethudpipcore_liteethip_liteethiprx_liteethipv4depacketizer_next_state <= 2'd2; + end else begin + liteethudpipcore_liteethip_liteethiprx_liteethipv4depacketizer_next_state <= 2'd3; + end + end else begin + liteethudpipcore_liteethip_liteethiprx_liteethipv4depacketizer_next_state <= 1'd1; + end + end + end + endcase +end +assign ethcore_ip_rx_liteethipv4checksum_s_next0 = (ethcore_ip_rx_liteethipv4checksum_r + ethcore_ip_rx_liteethipv4checksum_header[15:0]); +assign ethcore_ip_rx_liteethipv4checksum_s_next1 = (ethcore_ip_rx_liteethipv4checksum_r_next0 + ethcore_ip_rx_liteethipv4checksum_header[31:16]); +assign ethcore_ip_rx_liteethipv4checksum_s_next2 = (ethcore_ip_rx_liteethipv4checksum_r_next1 + ethcore_ip_rx_liteethipv4checksum_header[47:32]); +assign ethcore_ip_rx_liteethipv4checksum_s_next3 = (ethcore_ip_rx_liteethipv4checksum_r_next2 + ethcore_ip_rx_liteethipv4checksum_header[63:48]); +assign ethcore_ip_rx_liteethipv4checksum_s_next4 = (ethcore_ip_rx_liteethipv4checksum_r_next3 + ethcore_ip_rx_liteethipv4checksum_header[79:64]); +assign ethcore_ip_rx_liteethipv4checksum_s_next5 = (ethcore_ip_rx_liteethipv4checksum_r_next4 + ethcore_ip_rx_liteethipv4checksum_header[95:80]); +assign ethcore_ip_rx_liteethipv4checksum_s_next6 = (ethcore_ip_rx_liteethipv4checksum_r_next5 + ethcore_ip_rx_liteethipv4checksum_header[111:96]); +assign ethcore_ip_rx_liteethipv4checksum_s_next7 = (ethcore_ip_rx_liteethipv4checksum_r_next6 + ethcore_ip_rx_liteethipv4checksum_header[127:112]); +assign ethcore_ip_rx_liteethipv4checksum_s_next8 = (ethcore_ip_rx_liteethipv4checksum_r_next7 + ethcore_ip_rx_liteethipv4checksum_header[143:128]); +assign ethcore_ip_rx_liteethipv4checksum_s_next9 = (ethcore_ip_rx_liteethipv4checksum_r_next8 + ethcore_ip_rx_liteethipv4checksum_header[159:144]); +assign ethcore_ip_rx_liteethipv4checksum_value = (~{ethcore_ip_rx_liteethipv4checksum_r_next9[7:0], ethcore_ip_rx_liteethipv4checksum_r_next9[15:8]}); +assign ethcore_ip_rx_liteethipv4checksum_counter_ce = (~ethcore_ip_rx_liteethipv4checksum_done); +assign ethcore_ip_rx_liteethipv4checksum_done = (ethcore_ip_rx_liteethipv4checksum_counter == 4'd11); +always @(*) begin + ethcore_ip_rx_depacketizer_source_ready <= 1'd0; + liteethudpipcore_liteethip_liteethiprx_fsm_next_state <= 2'd0; + ethcore_ip_rx_source_source_valid <= 1'd0; + liteethudpipcore_liteethip_liteethiprx_fsm_next_state <= liteethudpipcore_liteethip_liteethiprx_fsm_state; + case (liteethudpipcore_liteethip_liteethiprx_fsm_state) + 1'd1: begin + if (ethcore_ip_rx_liteethipv4checksum_done) begin + if (ethcore_ip_rx_valid) begin + liteethudpipcore_liteethip_liteethiprx_fsm_next_state <= 2'd2; + end else begin + liteethudpipcore_liteethip_liteethiprx_fsm_next_state <= 2'd3; + end + end + end + 2'd2: begin + ethcore_ip_rx_source_source_valid <= ethcore_ip_rx_depacketizer_source_valid; + ethcore_ip_rx_depacketizer_source_ready <= ethcore_ip_rx_source_source_ready; + if (((ethcore_ip_rx_source_source_valid & ethcore_ip_rx_source_source_last) & ethcore_ip_rx_source_source_ready)) begin + liteethudpipcore_liteethip_liteethiprx_fsm_next_state <= 1'd0; + end + end + 2'd3: begin + ethcore_ip_rx_depacketizer_source_ready <= 1'd1; + if (((ethcore_ip_rx_depacketizer_source_valid & ethcore_ip_rx_depacketizer_source_last) & ethcore_ip_rx_depacketizer_source_ready)) begin + liteethudpipcore_liteethip_liteethiprx_fsm_next_state <= 1'd0; + end + end + default: begin + ethcore_ip_rx_depacketizer_source_ready <= 1'd1; + if (ethcore_ip_rx_depacketizer_source_valid) begin + ethcore_ip_rx_depacketizer_source_ready <= 1'd0; + liteethudpipcore_liteethip_liteethiprx_fsm_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + liteethudpipcore_liteethip_sel0 <= 2'd0; + case (ethcore_ip_crossbar_sink_param_protocol) + 1'd1: begin + liteethudpipcore_liteethip_sel0 <= 1'd1; + end + 5'd17: begin + liteethudpipcore_liteethip_sel0 <= 2'd2; + end + default: begin + liteethudpipcore_liteethip_sel0 <= 1'd0; + end + endcase +end +always @(*) begin + liteethudpipcore_liteethip_request <= 2'd0; + liteethudpipcore_liteethip_request[0] <= liteethudpipcore_liteethip_status0_ongoing0; + liteethudpipcore_liteethip_request[1] <= liteethudpipcore_liteethip_status1_ongoing0; +end +always @(*) begin + ethcore_ip_crossbar_source_param_protocol <= 8'd0; + ethcore_ip_crossbar_source_param_ip_address <= 32'd0; + ethcore_ip_port_sink_ready <= 1'd0; + ethcore_icmp_sink_ready <= 1'd0; + ethcore_ip_crossbar_source_valid <= 1'd0; + ethcore_ip_crossbar_source_first <= 1'd0; + ethcore_ip_crossbar_source_last <= 1'd0; + ethcore_ip_crossbar_source_payload_data <= 8'd0; + ethcore_ip_crossbar_source_payload_error <= 1'd0; + ethcore_ip_crossbar_source_param_length <= 16'd0; + case (liteethudpipcore_liteethip_grant) + 1'd0: begin + ethcore_ip_crossbar_source_valid <= ethcore_icmp_sink_valid; + ethcore_icmp_sink_ready <= ethcore_ip_crossbar_source_ready; + ethcore_ip_crossbar_source_first <= ethcore_icmp_sink_first; + ethcore_ip_crossbar_source_last <= ethcore_icmp_sink_last; + ethcore_ip_crossbar_source_payload_data <= ethcore_icmp_sink_payload_data; + ethcore_ip_crossbar_source_payload_error <= ethcore_icmp_sink_payload_error; + ethcore_ip_crossbar_source_param_length <= ethcore_icmp_sink_param_length; + ethcore_ip_crossbar_source_param_protocol <= ethcore_icmp_sink_param_protocol; + ethcore_ip_crossbar_source_param_ip_address <= ethcore_icmp_sink_param_ip_address; + end + 1'd1: begin + ethcore_ip_crossbar_source_valid <= ethcore_ip_port_sink_valid; + ethcore_ip_port_sink_ready <= ethcore_ip_crossbar_source_ready; + ethcore_ip_crossbar_source_first <= ethcore_ip_port_sink_first; + ethcore_ip_crossbar_source_last <= ethcore_ip_port_sink_last; + ethcore_ip_crossbar_source_payload_data <= ethcore_ip_port_sink_payload_data; + ethcore_ip_crossbar_source_payload_error <= ethcore_ip_port_sink_payload_error; + ethcore_ip_crossbar_source_param_length <= ethcore_ip_port_sink_param_length; + ethcore_ip_crossbar_source_param_protocol <= ethcore_ip_port_sink_param_protocol; + ethcore_ip_crossbar_source_param_ip_address <= ethcore_ip_port_sink_param_ip_address; + end + endcase +end +always @(*) begin + liteethudpipcore_liteethip_status0_last <= 1'd0; + if (ethcore_icmp_sink_valid) begin + liteethudpipcore_liteethip_status0_last <= (ethcore_icmp_sink_last & ethcore_icmp_sink_ready); + end +end +assign liteethudpipcore_liteethip_status0_ongoing0 = ((ethcore_icmp_sink_valid | liteethudpipcore_liteethip_status0_ongoing1) & (~liteethudpipcore_liteethip_status0_last)); +always @(*) begin + liteethudpipcore_liteethip_status1_last <= 1'd0; + if (ethcore_ip_port_sink_valid) begin + liteethudpipcore_liteethip_status1_last <= (ethcore_ip_port_sink_last & ethcore_ip_port_sink_ready); + end +end +assign liteethudpipcore_liteethip_status1_ongoing0 = ((ethcore_ip_port_sink_valid | liteethudpipcore_liteethip_status1_ongoing1) & (~liteethudpipcore_liteethip_status1_last)); +always @(*) begin + liteethudpipcore_liteethip_sel1 <= 2'd0; + if (liteethudpipcore_liteethip_first) begin + liteethudpipcore_liteethip_sel1 <= liteethudpipcore_liteethip_sel0; + end else begin + liteethudpipcore_liteethip_sel1 <= liteethudpipcore_liteethip_sel_ongoing; + end +end +always @(*) begin + ethcore_ip_crossbar_sink_ready <= 1'd0; + ethcore_ip_port_source_valid <= 1'd0; + ethcore_ip_port_source_first <= 1'd0; + ethcore_ip_port_source_last <= 1'd0; + ethcore_ip_port_source_payload_data <= 8'd0; + ethcore_ip_port_source_payload_error <= 1'd0; + ethcore_ip_port_source_param_length <= 16'd0; + ethcore_ip_port_source_param_protocol <= 8'd0; + ethcore_ip_port_source_param_ip_address <= 32'd0; + ethcore_icmp_source_valid <= 1'd0; + ethcore_icmp_source_first <= 1'd0; + ethcore_icmp_source_last <= 1'd0; + ethcore_icmp_source_payload_data <= 8'd0; + ethcore_icmp_source_payload_error <= 1'd0; + ethcore_icmp_source_param_length <= 16'd0; + ethcore_icmp_source_param_protocol <= 8'd0; + ethcore_icmp_source_param_ip_address <= 32'd0; + case (liteethudpipcore_liteethip_sel1) + 1'd1: begin + ethcore_icmp_source_valid <= ethcore_ip_crossbar_sink_valid; + ethcore_ip_crossbar_sink_ready <= ethcore_icmp_source_ready; + ethcore_icmp_source_first <= ethcore_ip_crossbar_sink_first; + ethcore_icmp_source_last <= ethcore_ip_crossbar_sink_last; + ethcore_icmp_source_payload_data <= ethcore_ip_crossbar_sink_payload_data; + ethcore_icmp_source_payload_error <= ethcore_ip_crossbar_sink_payload_error; + ethcore_icmp_source_param_length <= ethcore_ip_crossbar_sink_param_length; + ethcore_icmp_source_param_protocol <= ethcore_ip_crossbar_sink_param_protocol; + ethcore_icmp_source_param_ip_address <= ethcore_ip_crossbar_sink_param_ip_address; + end + 2'd2: begin + ethcore_ip_port_source_valid <= ethcore_ip_crossbar_sink_valid; + ethcore_ip_crossbar_sink_ready <= ethcore_ip_port_source_ready; + ethcore_ip_port_source_first <= ethcore_ip_crossbar_sink_first; + ethcore_ip_port_source_last <= ethcore_ip_crossbar_sink_last; + ethcore_ip_port_source_payload_data <= ethcore_ip_crossbar_sink_payload_data; + ethcore_ip_port_source_payload_error <= ethcore_ip_crossbar_sink_payload_error; + ethcore_ip_port_source_param_length <= ethcore_ip_crossbar_sink_param_length; + ethcore_ip_port_source_param_protocol <= ethcore_ip_crossbar_sink_param_protocol; + ethcore_ip_port_source_param_ip_address <= ethcore_ip_crossbar_sink_param_ip_address; + end + default: begin + ethcore_ip_crossbar_sink_ready <= 1'd1; + end + endcase +end +always @(*) begin + liteethudpipcore_liteethip_last <= 1'd0; + if (ethcore_ip_crossbar_sink_valid) begin + liteethudpipcore_liteethip_last <= (ethcore_ip_crossbar_sink_last & ethcore_ip_crossbar_sink_ready); + end +end +assign liteethudpipcore_liteethip_ongoing0 = ((ethcore_ip_crossbar_sink_valid | liteethudpipcore_liteethip_ongoing1) & (~liteethudpipcore_liteethip_last)); +assign ethcore_icmp_echo_sink_sink_valid = ethcore_icmp_rx_source_source_valid; +assign ethcore_icmp_rx_source_source_ready = ethcore_icmp_echo_sink_sink_ready; +assign ethcore_icmp_echo_sink_sink_first = ethcore_icmp_rx_source_source_first; +assign ethcore_icmp_echo_sink_sink_last = ethcore_icmp_rx_source_source_last; +assign ethcore_icmp_echo_sink_sink_payload_data = ethcore_icmp_rx_source_source_payload_data; +assign ethcore_icmp_echo_sink_sink_payload_error = ethcore_icmp_rx_source_source_payload_error; +assign ethcore_icmp_echo_sink_sink_param_checksum = ethcore_icmp_rx_source_source_param_checksum; +assign ethcore_icmp_echo_sink_sink_param_code = ethcore_icmp_rx_source_source_param_code; +assign ethcore_icmp_echo_sink_sink_param_msgtype = ethcore_icmp_rx_source_source_param_msgtype; +assign ethcore_icmp_echo_sink_sink_param_quench = ethcore_icmp_rx_source_source_param_quench; +assign ethcore_icmp_echo_sink_sink_param_ip_address = ethcore_icmp_rx_source_source_param_ip_address; +assign ethcore_icmp_echo_sink_sink_param_length = ethcore_icmp_rx_source_source_param_length; +assign ethcore_icmp_tx_sink_sink_valid = ethcore_icmp_echo_source_source_valid; +assign ethcore_icmp_echo_source_source_ready = ethcore_icmp_tx_sink_sink_ready; +assign ethcore_icmp_tx_sink_sink_first = ethcore_icmp_echo_source_source_first; +assign ethcore_icmp_tx_sink_sink_last = ethcore_icmp_echo_source_source_last; +assign ethcore_icmp_tx_sink_sink_payload_data = ethcore_icmp_echo_source_source_payload_data; +assign ethcore_icmp_tx_sink_sink_payload_error = ethcore_icmp_echo_source_source_payload_error; +assign ethcore_icmp_tx_sink_sink_param_checksum = ethcore_icmp_echo_source_source_param_checksum; +assign ethcore_icmp_tx_sink_sink_param_code = ethcore_icmp_echo_source_source_param_code; +assign ethcore_icmp_tx_sink_sink_param_msgtype = ethcore_icmp_echo_source_source_param_msgtype; +assign ethcore_icmp_tx_sink_sink_param_quench = ethcore_icmp_echo_source_source_param_quench; +assign ethcore_icmp_tx_sink_sink_param_ip_address = ethcore_icmp_echo_source_source_param_ip_address; +assign ethcore_icmp_tx_sink_sink_param_length = ethcore_icmp_echo_source_source_param_length; +assign ethcore_icmp_sink_valid = ethcore_icmp_tx_source_source_valid; +assign ethcore_icmp_tx_source_source_ready = ethcore_icmp_sink_ready; +assign ethcore_icmp_sink_first = ethcore_icmp_tx_source_source_first; +assign ethcore_icmp_sink_last = ethcore_icmp_tx_source_source_last; +assign ethcore_icmp_sink_payload_data = ethcore_icmp_tx_source_source_payload_data; +assign ethcore_icmp_sink_payload_error = ethcore_icmp_tx_source_source_payload_error; +assign ethcore_icmp_sink_param_length = ethcore_icmp_tx_source_source_param_length; +assign ethcore_icmp_sink_param_protocol = ethcore_icmp_tx_source_source_param_protocol; +assign ethcore_icmp_sink_param_ip_address = ethcore_icmp_tx_source_source_param_ip_address; +assign ethcore_icmp_rx_sink_sink_valid = ethcore_icmp_source_valid; +assign ethcore_icmp_source_ready = ethcore_icmp_rx_sink_sink_ready; +assign ethcore_icmp_rx_sink_sink_first = ethcore_icmp_source_first; +assign ethcore_icmp_rx_sink_sink_last = ethcore_icmp_source_last; +assign ethcore_icmp_rx_sink_sink_payload_data = ethcore_icmp_source_payload_data; +assign ethcore_icmp_rx_sink_sink_payload_error = ethcore_icmp_source_payload_error; +assign ethcore_icmp_rx_sink_sink_param_length = ethcore_icmp_source_param_length; +assign ethcore_icmp_rx_sink_sink_param_protocol = ethcore_icmp_source_param_protocol; +assign ethcore_icmp_rx_sink_sink_param_ip_address = ethcore_icmp_source_param_ip_address; +assign ethcore_icmp_tx_packetizer_sink_valid = ethcore_icmp_tx_sink_sink_valid; +assign ethcore_icmp_tx_packetizer_sink_last = ethcore_icmp_tx_sink_sink_last; +assign ethcore_icmp_tx_sink_sink_ready = ethcore_icmp_tx_packetizer_sink_ready; +assign ethcore_icmp_tx_packetizer_sink_param_msgtype = ethcore_icmp_tx_sink_sink_param_msgtype; +assign ethcore_icmp_tx_packetizer_sink_param_code = ethcore_icmp_tx_sink_sink_param_code; +assign ethcore_icmp_tx_packetizer_sink_param_checksum = ethcore_icmp_tx_sink_sink_param_checksum; +assign ethcore_icmp_tx_packetizer_sink_param_quench = ethcore_icmp_tx_sink_sink_param_quench; +assign ethcore_icmp_tx_packetizer_sink_payload_data = ethcore_icmp_tx_sink_sink_payload_data; +always @(*) begin + ethcore_icmp_tx_packetizer_header <= 64'd0; + ethcore_icmp_tx_packetizer_header[31:16] <= {ethcore_icmp_tx_packetizer_sink_param_checksum[7:0], ethcore_icmp_tx_packetizer_sink_param_checksum[15:8]}; + ethcore_icmp_tx_packetizer_header[15:8] <= {ethcore_icmp_tx_packetizer_sink_param_code[7:0]}; + ethcore_icmp_tx_packetizer_header[7:0] <= {ethcore_icmp_tx_packetizer_sink_param_msgtype[7:0]}; + ethcore_icmp_tx_packetizer_header[63:32] <= {ethcore_icmp_tx_packetizer_sink_param_quench[7:0], ethcore_icmp_tx_packetizer_sink_param_quench[15:8], ethcore_icmp_tx_packetizer_sink_param_quench[23:16], ethcore_icmp_tx_packetizer_sink_param_quench[31:24]}; +end +assign ethcore_icmp_tx_packetizer_source_payload_error = ethcore_icmp_tx_packetizer_sink_payload_error; +always @(*) begin + ethcore_icmp_tx_packetizer_count_liteethicmptx_next_value_ce0 <= 1'd0; + ethcore_icmp_tx_packetizer_sink_ready <= 1'd0; + ethcore_icmp_tx_packetizer_fsm_from_idle_liteethicmptx_next_value1 <= 1'd0; + ethcore_icmp_tx_packetizer_fsm_from_idle_liteethicmptx_next_value_ce1 <= 1'd0; + ethcore_icmp_tx_packetizer_sr_load <= 1'd0; + ethcore_icmp_tx_packetizer_sr_shift <= 1'd0; + ethcore_icmp_tx_packetizer_source_valid <= 1'd0; + liteethudpipcore_liteethicmptx_liteethicmppacketizer_next_state <= 2'd0; + ethcore_icmp_tx_packetizer_source_last <= 1'd0; + ethcore_icmp_tx_packetizer_source_payload_data <= 8'd0; + ethcore_icmp_tx_packetizer_count_liteethicmptx_next_value0 <= 3'd0; + liteethudpipcore_liteethicmptx_liteethicmppacketizer_next_state <= liteethudpipcore_liteethicmptx_liteethicmppacketizer_state; + case (liteethudpipcore_liteethicmptx_liteethicmppacketizer_state) + 1'd1: begin + ethcore_icmp_tx_packetizer_source_valid <= 1'd1; + ethcore_icmp_tx_packetizer_source_last <= 1'd0; + ethcore_icmp_tx_packetizer_source_payload_data <= ethcore_icmp_tx_packetizer_sr[63:8]; + if ((ethcore_icmp_tx_packetizer_source_valid & ethcore_icmp_tx_packetizer_source_ready)) begin + ethcore_icmp_tx_packetizer_sr_shift <= 1'd1; + if ((ethcore_icmp_tx_packetizer_count == 3'd7)) begin + ethcore_icmp_tx_packetizer_sr_shift <= 1'd0; + if (1'd0) begin + liteethudpipcore_liteethicmptx_liteethicmppacketizer_next_state <= 2'd3; + ethcore_icmp_tx_packetizer_count_liteethicmptx_next_value0 <= (ethcore_icmp_tx_packetizer_count + 1'd1); + ethcore_icmp_tx_packetizer_count_liteethicmptx_next_value_ce0 <= 1'd1; + end else begin + liteethudpipcore_liteethicmptx_liteethicmppacketizer_next_state <= 2'd2; + end + end else begin + ethcore_icmp_tx_packetizer_count_liteethicmptx_next_value0 <= (ethcore_icmp_tx_packetizer_count + 1'd1); + ethcore_icmp_tx_packetizer_count_liteethicmptx_next_value_ce0 <= 1'd1; + end + end + end + 2'd2: begin + ethcore_icmp_tx_packetizer_source_valid <= ethcore_icmp_tx_packetizer_sink_valid; + ethcore_icmp_tx_packetizer_source_last <= ethcore_icmp_tx_packetizer_sink_last; + ethcore_icmp_tx_packetizer_source_payload_data <= ethcore_icmp_tx_packetizer_sink_payload_data; + if ((ethcore_icmp_tx_packetizer_source_valid & ethcore_icmp_tx_packetizer_source_ready)) begin + ethcore_icmp_tx_packetizer_sink_ready <= 1'd1; + if (ethcore_icmp_tx_packetizer_source_last) begin + liteethudpipcore_liteethicmptx_liteethicmppacketizer_next_state <= 1'd0; + end + end + end + 2'd3: begin + ethcore_icmp_tx_packetizer_source_valid <= (ethcore_icmp_tx_packetizer_sink_valid | ethcore_icmp_tx_packetizer_sink_d_last); + ethcore_icmp_tx_packetizer_source_last <= ethcore_icmp_tx_packetizer_sink_d_last; + if (ethcore_icmp_tx_packetizer_fsm_from_idle) begin + ethcore_icmp_tx_packetizer_source_payload_data[0] <= ethcore_icmp_tx_packetizer_sr[63:16]; + end else begin + ethcore_icmp_tx_packetizer_source_payload_data[0] <= ethcore_icmp_tx_packetizer_sink_d_payload_data[7]; + end + ethcore_icmp_tx_packetizer_source_payload_data[7:0] <= ethcore_icmp_tx_packetizer_sink_payload_data; + if ((ethcore_icmp_tx_packetizer_source_valid & ethcore_icmp_tx_packetizer_source_ready)) begin + ethcore_icmp_tx_packetizer_sink_ready <= (~ethcore_icmp_tx_packetizer_source_last); + ethcore_icmp_tx_packetizer_fsm_from_idle_liteethicmptx_next_value1 <= 1'd0; + ethcore_icmp_tx_packetizer_fsm_from_idle_liteethicmptx_next_value_ce1 <= 1'd1; + if (ethcore_icmp_tx_packetizer_source_last) begin + liteethudpipcore_liteethicmptx_liteethicmppacketizer_next_state <= 1'd0; + end + end + end + default: begin + ethcore_icmp_tx_packetizer_sink_ready <= 1'd1; + ethcore_icmp_tx_packetizer_count_liteethicmptx_next_value0 <= 1'd1; + ethcore_icmp_tx_packetizer_count_liteethicmptx_next_value_ce0 <= 1'd1; + if (ethcore_icmp_tx_packetizer_sink_valid) begin + ethcore_icmp_tx_packetizer_sink_ready <= 1'd0; + ethcore_icmp_tx_packetizer_source_valid <= 1'd1; + ethcore_icmp_tx_packetizer_source_last <= 1'd0; + ethcore_icmp_tx_packetizer_source_payload_data <= ethcore_icmp_tx_packetizer_header[7:0]; + if ((ethcore_icmp_tx_packetizer_source_valid & ethcore_icmp_tx_packetizer_source_ready)) begin + ethcore_icmp_tx_packetizer_sr_load <= 1'd1; + ethcore_icmp_tx_packetizer_fsm_from_idle_liteethicmptx_next_value1 <= 1'd1; + ethcore_icmp_tx_packetizer_fsm_from_idle_liteethicmptx_next_value_ce1 <= 1'd1; + if (1'd0) begin + if (1'd0) begin + liteethudpipcore_liteethicmptx_liteethicmppacketizer_next_state <= 2'd3; + end else begin + liteethudpipcore_liteethicmptx_liteethicmppacketizer_next_state <= 2'd2; + end + end else begin + liteethudpipcore_liteethicmptx_liteethicmppacketizer_next_state <= 1'd1; + end + end + end + end + endcase +end +always @(*) begin + liteethudpipcore_liteethicmptx_fsm_next_state <= 1'd0; + ethcore_icmp_tx_source_source_valid <= 1'd0; + ethcore_icmp_tx_source_source_first <= 1'd0; + ethcore_icmp_tx_source_source_last <= 1'd0; + ethcore_icmp_tx_source_source_payload_data <= 8'd0; + ethcore_icmp_tx_packetizer_source_ready <= 1'd0; + ethcore_icmp_tx_source_source_payload_error <= 1'd0; + ethcore_icmp_tx_source_source_param_length <= 16'd0; + ethcore_icmp_tx_source_source_param_protocol <= 8'd0; + ethcore_icmp_tx_source_source_param_ip_address <= 32'd0; + liteethudpipcore_liteethicmptx_fsm_next_state <= liteethudpipcore_liteethicmptx_fsm_state; + case (liteethudpipcore_liteethicmptx_fsm_state) + 1'd1: begin + ethcore_icmp_tx_source_source_valid <= ethcore_icmp_tx_packetizer_source_valid; + ethcore_icmp_tx_packetizer_source_ready <= ethcore_icmp_tx_source_source_ready; + ethcore_icmp_tx_source_source_first <= ethcore_icmp_tx_packetizer_source_first; + ethcore_icmp_tx_source_source_last <= ethcore_icmp_tx_packetizer_source_last; + ethcore_icmp_tx_source_source_payload_data <= ethcore_icmp_tx_packetizer_source_payload_data; + ethcore_icmp_tx_source_source_payload_error <= ethcore_icmp_tx_packetizer_source_payload_error; + ethcore_icmp_tx_source_source_param_length <= ethcore_icmp_tx_packetizer_source_param_length; + ethcore_icmp_tx_source_source_param_protocol <= ethcore_icmp_tx_packetizer_source_param_protocol; + ethcore_icmp_tx_source_source_param_ip_address <= ethcore_icmp_tx_packetizer_source_param_ip_address; + ethcore_icmp_tx_source_source_param_length <= (ethcore_icmp_tx_sink_sink_param_length + 4'd8); + ethcore_icmp_tx_source_source_param_protocol <= 1'd1; + ethcore_icmp_tx_source_source_param_ip_address <= ethcore_icmp_tx_sink_sink_param_ip_address; + if (((ethcore_icmp_tx_source_source_valid & ethcore_icmp_tx_source_source_last) & ethcore_icmp_tx_source_source_ready)) begin + liteethudpipcore_liteethicmptx_fsm_next_state <= 1'd0; + end + end + default: begin + ethcore_icmp_tx_packetizer_source_ready <= 1'd1; + if (ethcore_icmp_tx_packetizer_source_valid) begin + ethcore_icmp_tx_packetizer_source_ready <= 1'd0; + liteethudpipcore_liteethicmptx_fsm_next_state <= 1'd1; + end + end + endcase +end +assign ethcore_icmp_rx_depacketizer_sink_valid = ethcore_icmp_rx_sink_sink_valid; +assign ethcore_icmp_rx_sink_sink_ready = ethcore_icmp_rx_depacketizer_sink_ready; +assign ethcore_icmp_rx_depacketizer_sink_first = ethcore_icmp_rx_sink_sink_first; +assign ethcore_icmp_rx_depacketizer_sink_last = ethcore_icmp_rx_sink_sink_last; +assign ethcore_icmp_rx_depacketizer_sink_payload_data = ethcore_icmp_rx_sink_sink_payload_data; +assign ethcore_icmp_rx_depacketizer_sink_payload_error = ethcore_icmp_rx_sink_sink_payload_error; +assign ethcore_icmp_rx_depacketizer_sink_param_length = ethcore_icmp_rx_sink_sink_param_length; +assign ethcore_icmp_rx_depacketizer_sink_param_protocol = ethcore_icmp_rx_sink_sink_param_protocol; +assign ethcore_icmp_rx_depacketizer_sink_param_ip_address = ethcore_icmp_rx_sink_sink_param_ip_address; +assign ethcore_icmp_rx_source_source_last = ethcore_icmp_rx_depacketizer_source_last; +assign ethcore_icmp_rx_source_source_param_msgtype = ethcore_icmp_rx_depacketizer_source_param_msgtype; +assign ethcore_icmp_rx_source_source_param_code = ethcore_icmp_rx_depacketizer_source_param_code; +assign ethcore_icmp_rx_source_source_param_checksum = ethcore_icmp_rx_depacketizer_source_param_checksum; +assign ethcore_icmp_rx_source_source_param_quench = ethcore_icmp_rx_depacketizer_source_param_quench; +assign ethcore_icmp_rx_source_source_param_ip_address = ethcore_icmp_rx_sink_sink_param_ip_address; +assign ethcore_icmp_rx_source_source_param_length = (ethcore_icmp_rx_sink_sink_param_length - 4'd8); +assign ethcore_icmp_rx_source_source_payload_data = ethcore_icmp_rx_depacketizer_source_payload_data; +assign ethcore_icmp_rx_source_source_payload_error = ethcore_icmp_rx_depacketizer_source_payload_error; +assign ethcore_icmp_rx_depacketizer_header = ethcore_icmp_rx_depacketizer_sr; +assign ethcore_icmp_rx_depacketizer_source_param_checksum = {rhs_slice_proxy61[7:0], rhs_slice_proxy60[15:8]}; +assign ethcore_icmp_rx_depacketizer_source_param_code = {rhs_slice_proxy62[7:0]}; +assign ethcore_icmp_rx_depacketizer_source_param_msgtype = {rhs_slice_proxy63[7:0]}; +assign ethcore_icmp_rx_depacketizer_source_param_quench = {rhs_slice_proxy67[7:0], rhs_slice_proxy66[15:8], rhs_slice_proxy65[23:16], rhs_slice_proxy64[31:24]}; +assign ethcore_icmp_rx_depacketizer_source_payload_error = ethcore_icmp_rx_depacketizer_sink_payload_error; +always @(*) begin + ethcore_icmp_rx_depacketizer_source_last <= 1'd0; + ethcore_icmp_rx_depacketizer_fsm_from_idle_liteethicmprx_next_value1 <= 1'd0; + ethcore_icmp_rx_depacketizer_source_payload_data <= 8'd0; + ethcore_icmp_rx_depacketizer_fsm_from_idle_liteethicmprx_next_value_ce1 <= 1'd0; + ethcore_icmp_rx_depacketizer_sink_ready <= 1'd0; + ethcore_icmp_rx_depacketizer_source_valid <= 1'd0; + ethcore_icmp_rx_depacketizer_sr_shift <= 1'd0; + ethcore_icmp_rx_depacketizer_sr_shift_leftover <= 1'd0; + liteethudpipcore_liteethicmprx_liteethicmpdepacketizer_next_state <= 2'd0; + ethcore_icmp_rx_depacketizer_count_liteethicmprx_next_value0 <= 3'd0; + ethcore_icmp_rx_depacketizer_count_liteethicmprx_next_value_ce0 <= 1'd0; + liteethudpipcore_liteethicmprx_liteethicmpdepacketizer_next_state <= liteethudpipcore_liteethicmprx_liteethicmpdepacketizer_state; + case (liteethudpipcore_liteethicmprx_liteethicmpdepacketizer_state) + 1'd1: begin + ethcore_icmp_rx_depacketizer_sink_ready <= 1'd1; + if (ethcore_icmp_rx_depacketizer_sink_valid) begin + ethcore_icmp_rx_depacketizer_count_liteethicmprx_next_value0 <= (ethcore_icmp_rx_depacketizer_count + 1'd1); + ethcore_icmp_rx_depacketizer_count_liteethicmprx_next_value_ce0 <= 1'd1; + ethcore_icmp_rx_depacketizer_sr_shift <= 1'd1; + if ((ethcore_icmp_rx_depacketizer_count == 3'd7)) begin + if (1'd0) begin + ethcore_icmp_rx_depacketizer_count_liteethicmprx_next_value0 <= (ethcore_icmp_rx_depacketizer_count + 1'd1); + ethcore_icmp_rx_depacketizer_count_liteethicmprx_next_value_ce0 <= 1'd1; + liteethudpipcore_liteethicmprx_liteethicmpdepacketizer_next_state <= 2'd2; + end else begin + liteethudpipcore_liteethicmprx_liteethicmpdepacketizer_next_state <= 2'd3; + end + end + end + end + 2'd2: begin + ethcore_icmp_rx_depacketizer_source_valid <= (ethcore_icmp_rx_depacketizer_sink_valid | ethcore_icmp_rx_depacketizer_sink_d_last); + ethcore_icmp_rx_depacketizer_source_last <= (ethcore_icmp_rx_depacketizer_sink_last | ethcore_icmp_rx_depacketizer_sink_d_last); + ethcore_icmp_rx_depacketizer_sink_ready <= ethcore_icmp_rx_depacketizer_source_ready; + ethcore_icmp_rx_depacketizer_source_payload_data <= ethcore_icmp_rx_depacketizer_sink_d_payload_data[7:0]; + ethcore_icmp_rx_depacketizer_source_payload_data[7] <= ethcore_icmp_rx_depacketizer_sink_payload_data; + if (ethcore_icmp_rx_depacketizer_fsm_from_idle) begin + ethcore_icmp_rx_depacketizer_source_valid <= ethcore_icmp_rx_depacketizer_sink_d_last; + ethcore_icmp_rx_depacketizer_sink_ready <= 1'd1; + if (ethcore_icmp_rx_depacketizer_sink_valid) begin + ethcore_icmp_rx_depacketizer_fsm_from_idle_liteethicmprx_next_value1 <= 1'd0; + ethcore_icmp_rx_depacketizer_fsm_from_idle_liteethicmprx_next_value_ce1 <= 1'd1; + ethcore_icmp_rx_depacketizer_sr_shift_leftover <= 1'd1; + end + end + if ((ethcore_icmp_rx_depacketizer_source_valid & ethcore_icmp_rx_depacketizer_source_ready)) begin + if (ethcore_icmp_rx_depacketizer_source_last) begin + liteethudpipcore_liteethicmprx_liteethicmpdepacketizer_next_state <= 1'd0; + end + end + end + 2'd3: begin + ethcore_icmp_rx_depacketizer_source_valid <= (ethcore_icmp_rx_depacketizer_sink_valid | ethcore_icmp_rx_depacketizer_sink_d_last); + ethcore_icmp_rx_depacketizer_source_last <= (ethcore_icmp_rx_depacketizer_sink_last | ethcore_icmp_rx_depacketizer_sink_d_last); + ethcore_icmp_rx_depacketizer_sink_ready <= ethcore_icmp_rx_depacketizer_source_ready; + ethcore_icmp_rx_depacketizer_source_payload_data <= ethcore_icmp_rx_depacketizer_sink_payload_data; + if ((ethcore_icmp_rx_depacketizer_source_valid & ethcore_icmp_rx_depacketizer_source_ready)) begin + if (ethcore_icmp_rx_depacketizer_source_last) begin + liteethudpipcore_liteethicmprx_liteethicmpdepacketizer_next_state <= 1'd0; + end + end + end + default: begin + ethcore_icmp_rx_depacketizer_sink_ready <= 1'd1; + ethcore_icmp_rx_depacketizer_count_liteethicmprx_next_value0 <= 1'd1; + ethcore_icmp_rx_depacketizer_count_liteethicmprx_next_value_ce0 <= 1'd1; + if (ethcore_icmp_rx_depacketizer_sink_valid) begin + ethcore_icmp_rx_depacketizer_sr_shift <= 1'd1; + ethcore_icmp_rx_depacketizer_fsm_from_idle_liteethicmprx_next_value1 <= 1'd1; + ethcore_icmp_rx_depacketizer_fsm_from_idle_liteethicmprx_next_value_ce1 <= 1'd1; + if (1'd0) begin + if (1'd0) begin + liteethudpipcore_liteethicmprx_liteethicmpdepacketizer_next_state <= 2'd2; + end else begin + liteethudpipcore_liteethicmprx_liteethicmpdepacketizer_next_state <= 2'd3; + end + end else begin + liteethudpipcore_liteethicmprx_liteethicmpdepacketizer_next_state <= 1'd1; + end + end + end + endcase +end +always @(*) begin + ethcore_icmp_rx_source_source_valid <= 1'd0; + ethcore_icmp_rx_depacketizer_source_ready <= 1'd0; + liteethudpipcore_liteethicmprx_fsm_next_state <= 2'd0; + liteethudpipcore_liteethicmprx_fsm_next_state <= liteethudpipcore_liteethicmprx_fsm_state; + case (liteethudpipcore_liteethicmprx_fsm_state) + 1'd1: begin + if (ethcore_icmp_rx_valid) begin + liteethudpipcore_liteethicmprx_fsm_next_state <= 2'd2; + end else begin + liteethudpipcore_liteethicmprx_fsm_next_state <= 2'd3; + end + end + 2'd2: begin + ethcore_icmp_rx_source_source_valid <= ethcore_icmp_rx_depacketizer_source_valid; + ethcore_icmp_rx_depacketizer_source_ready <= ethcore_icmp_rx_source_source_ready; + if (((ethcore_icmp_rx_source_source_valid & ethcore_icmp_rx_source_source_last) & ethcore_icmp_rx_source_source_ready)) begin + liteethudpipcore_liteethicmprx_fsm_next_state <= 1'd0; + end + end + 2'd3: begin + ethcore_icmp_rx_depacketizer_source_ready <= 1'd1; + if (((ethcore_icmp_rx_depacketizer_source_valid & ethcore_icmp_rx_depacketizer_source_last) & ethcore_icmp_rx_depacketizer_source_ready)) begin + liteethudpipcore_liteethicmprx_fsm_next_state <= 1'd0; + end + end + default: begin + ethcore_icmp_rx_depacketizer_source_ready <= 1'd1; + if (ethcore_icmp_rx_depacketizer_source_valid) begin + ethcore_icmp_rx_depacketizer_source_ready <= 1'd0; + liteethudpipcore_liteethicmprx_fsm_next_state <= 1'd1; + end + end + endcase +end +assign ethcore_icmp_echo_buffer_sink_valid = ethcore_icmp_echo_sink_sink_valid; +assign ethcore_icmp_echo_sink_sink_ready = ethcore_icmp_echo_buffer_sink_ready; +assign ethcore_icmp_echo_buffer_sink_first = ethcore_icmp_echo_sink_sink_first; +assign ethcore_icmp_echo_buffer_sink_last = ethcore_icmp_echo_sink_sink_last; +assign ethcore_icmp_echo_buffer_sink_payload_data = ethcore_icmp_echo_sink_sink_payload_data; +assign ethcore_icmp_echo_buffer_sink_payload_error = ethcore_icmp_echo_sink_sink_payload_error; +assign ethcore_icmp_echo_buffer_sink_param_checksum = ethcore_icmp_echo_sink_sink_param_checksum; +assign ethcore_icmp_echo_buffer_sink_param_code = ethcore_icmp_echo_sink_sink_param_code; +assign ethcore_icmp_echo_buffer_sink_param_msgtype = ethcore_icmp_echo_sink_sink_param_msgtype; +assign ethcore_icmp_echo_buffer_sink_param_quench = ethcore_icmp_echo_sink_sink_param_quench; +assign ethcore_icmp_echo_buffer_sink_param_ip_address = ethcore_icmp_echo_sink_sink_param_ip_address; +assign ethcore_icmp_echo_buffer_sink_param_length = ethcore_icmp_echo_sink_sink_param_length; +assign ethcore_icmp_echo_source_source_valid = ethcore_icmp_echo_buffer_source_valid; +assign ethcore_icmp_echo_buffer_source_ready = ethcore_icmp_echo_source_source_ready; +assign ethcore_icmp_echo_source_source_first = ethcore_icmp_echo_buffer_source_first; +assign ethcore_icmp_echo_source_source_last = ethcore_icmp_echo_buffer_source_last; +assign ethcore_icmp_echo_source_source_payload_data = ethcore_icmp_echo_buffer_source_payload_data; +assign ethcore_icmp_echo_source_source_payload_error = ethcore_icmp_echo_buffer_source_payload_error; +assign ethcore_icmp_echo_source_source_param_code = ethcore_icmp_echo_buffer_source_param_code; +assign ethcore_icmp_echo_source_source_param_quench = ethcore_icmp_echo_buffer_source_param_quench; +assign ethcore_icmp_echo_source_source_param_ip_address = ethcore_icmp_echo_buffer_source_param_ip_address; +assign ethcore_icmp_echo_source_source_param_length = ethcore_icmp_echo_buffer_source_param_length; +always @(*) begin + ethcore_icmp_echo_source_source_param_msgtype <= 8'd0; + ethcore_icmp_echo_source_source_param_msgtype <= ethcore_icmp_echo_buffer_source_param_msgtype; + ethcore_icmp_echo_source_source_param_msgtype <= 1'd0; +end +always @(*) begin + ethcore_icmp_echo_source_source_param_checksum <= 16'd0; + ethcore_icmp_echo_source_source_param_checksum <= ethcore_icmp_echo_buffer_source_param_checksum; + ethcore_icmp_echo_source_source_param_checksum <= ((ethcore_icmp_echo_buffer_source_param_checksum + 12'd2048) + (ethcore_icmp_echo_buffer_source_param_checksum >= 16'd63488)); +end +assign ethcore_icmp_echo_buffer_syncfifo_din = {ethcore_icmp_echo_buffer_fifo_in_last, ethcore_icmp_echo_buffer_fifo_in_first, ethcore_icmp_echo_buffer_fifo_in_param_length, ethcore_icmp_echo_buffer_fifo_in_param_ip_address, ethcore_icmp_echo_buffer_fifo_in_param_quench, ethcore_icmp_echo_buffer_fifo_in_param_msgtype, ethcore_icmp_echo_buffer_fifo_in_param_code, ethcore_icmp_echo_buffer_fifo_in_param_checksum, ethcore_icmp_echo_buffer_fifo_in_payload_error, ethcore_icmp_echo_buffer_fifo_in_payload_data}; +assign {ethcore_icmp_echo_buffer_fifo_out_last, ethcore_icmp_echo_buffer_fifo_out_first, ethcore_icmp_echo_buffer_fifo_out_param_length, ethcore_icmp_echo_buffer_fifo_out_param_ip_address, ethcore_icmp_echo_buffer_fifo_out_param_quench, ethcore_icmp_echo_buffer_fifo_out_param_msgtype, ethcore_icmp_echo_buffer_fifo_out_param_code, ethcore_icmp_echo_buffer_fifo_out_param_checksum, ethcore_icmp_echo_buffer_fifo_out_payload_error, ethcore_icmp_echo_buffer_fifo_out_payload_data} = ethcore_icmp_echo_buffer_syncfifo_dout; +assign ethcore_icmp_echo_buffer_sink_ready = ethcore_icmp_echo_buffer_syncfifo_writable; +assign ethcore_icmp_echo_buffer_syncfifo_we = ethcore_icmp_echo_buffer_sink_valid; +assign ethcore_icmp_echo_buffer_fifo_in_first = ethcore_icmp_echo_buffer_sink_first; +assign ethcore_icmp_echo_buffer_fifo_in_last = ethcore_icmp_echo_buffer_sink_last; +assign ethcore_icmp_echo_buffer_fifo_in_payload_data = ethcore_icmp_echo_buffer_sink_payload_data; +assign ethcore_icmp_echo_buffer_fifo_in_payload_error = ethcore_icmp_echo_buffer_sink_payload_error; +assign ethcore_icmp_echo_buffer_fifo_in_param_checksum = ethcore_icmp_echo_buffer_sink_param_checksum; +assign ethcore_icmp_echo_buffer_fifo_in_param_code = ethcore_icmp_echo_buffer_sink_param_code; +assign ethcore_icmp_echo_buffer_fifo_in_param_msgtype = ethcore_icmp_echo_buffer_sink_param_msgtype; +assign ethcore_icmp_echo_buffer_fifo_in_param_quench = ethcore_icmp_echo_buffer_sink_param_quench; +assign ethcore_icmp_echo_buffer_fifo_in_param_ip_address = ethcore_icmp_echo_buffer_sink_param_ip_address; +assign ethcore_icmp_echo_buffer_fifo_in_param_length = ethcore_icmp_echo_buffer_sink_param_length; +assign ethcore_icmp_echo_buffer_source_valid = ethcore_icmp_echo_buffer_readable; +assign ethcore_icmp_echo_buffer_source_first = ethcore_icmp_echo_buffer_fifo_out_first; +assign ethcore_icmp_echo_buffer_source_last = ethcore_icmp_echo_buffer_fifo_out_last; +assign ethcore_icmp_echo_buffer_source_payload_data = ethcore_icmp_echo_buffer_fifo_out_payload_data; +assign ethcore_icmp_echo_buffer_source_payload_error = ethcore_icmp_echo_buffer_fifo_out_payload_error; +assign ethcore_icmp_echo_buffer_source_param_checksum = ethcore_icmp_echo_buffer_fifo_out_param_checksum; +assign ethcore_icmp_echo_buffer_source_param_code = ethcore_icmp_echo_buffer_fifo_out_param_code; +assign ethcore_icmp_echo_buffer_source_param_msgtype = ethcore_icmp_echo_buffer_fifo_out_param_msgtype; +assign ethcore_icmp_echo_buffer_source_param_quench = ethcore_icmp_echo_buffer_fifo_out_param_quench; +assign ethcore_icmp_echo_buffer_source_param_ip_address = ethcore_icmp_echo_buffer_fifo_out_param_ip_address; +assign ethcore_icmp_echo_buffer_source_param_length = ethcore_icmp_echo_buffer_fifo_out_param_length; +assign ethcore_icmp_echo_buffer_re = ethcore_icmp_echo_buffer_source_ready; +assign ethcore_icmp_echo_buffer_syncfifo_re = (ethcore_icmp_echo_buffer_syncfifo_readable & ((~ethcore_icmp_echo_buffer_readable) | ethcore_icmp_echo_buffer_re)); +assign ethcore_icmp_echo_buffer_level1 = (ethcore_icmp_echo_buffer_level0 + ethcore_icmp_echo_buffer_readable); +always @(*) begin + ethcore_icmp_echo_buffer_wrport_adr <= 7'd0; + if (ethcore_icmp_echo_buffer_replace) begin + ethcore_icmp_echo_buffer_wrport_adr <= (ethcore_icmp_echo_buffer_produce - 1'd1); + end else begin + ethcore_icmp_echo_buffer_wrport_adr <= ethcore_icmp_echo_buffer_produce; + end +end +assign ethcore_icmp_echo_buffer_wrport_dat_w = ethcore_icmp_echo_buffer_syncfifo_din; +assign ethcore_icmp_echo_buffer_wrport_we = (ethcore_icmp_echo_buffer_syncfifo_we & (ethcore_icmp_echo_buffer_syncfifo_writable | ethcore_icmp_echo_buffer_replace)); +assign ethcore_icmp_echo_buffer_do_read = (ethcore_icmp_echo_buffer_syncfifo_readable & ethcore_icmp_echo_buffer_syncfifo_re); +assign ethcore_icmp_echo_buffer_rdport_adr = ethcore_icmp_echo_buffer_consume; +assign ethcore_icmp_echo_buffer_syncfifo_dout = ethcore_icmp_echo_buffer_rdport_dat_r; +assign ethcore_icmp_echo_buffer_rdport_re = ethcore_icmp_echo_buffer_do_read; +assign ethcore_icmp_echo_buffer_syncfifo_writable = (ethcore_icmp_echo_buffer_level0 != 8'd128); +assign ethcore_icmp_echo_buffer_syncfifo_readable = (ethcore_icmp_echo_buffer_level0 != 1'd0); +assign ethcore_ip_port_sink_valid = ethcore_tx_source_source_valid; +assign ethcore_tx_source_source_ready = ethcore_ip_port_sink_ready; +assign ethcore_ip_port_sink_first = ethcore_tx_source_source_first; +assign ethcore_ip_port_sink_last = ethcore_tx_source_source_last; +assign ethcore_ip_port_sink_payload_data = ethcore_tx_source_source_payload_data; +assign ethcore_ip_port_sink_payload_error = ethcore_tx_source_source_payload_error; +assign ethcore_ip_port_sink_param_length = ethcore_tx_source_source_param_length; +assign ethcore_ip_port_sink_param_protocol = ethcore_tx_source_source_param_protocol; +assign ethcore_ip_port_sink_param_ip_address = ethcore_tx_source_source_param_ip_address; +assign ethcore_rx_sink_sink_valid = ethcore_ip_port_source_valid; +assign ethcore_ip_port_source_ready = ethcore_rx_sink_sink_ready; +assign ethcore_rx_sink_sink_first = ethcore_ip_port_source_first; +assign ethcore_rx_sink_sink_last = ethcore_ip_port_source_last; +assign ethcore_rx_sink_sink_payload_data = ethcore_ip_port_source_payload_data; +assign ethcore_rx_sink_sink_payload_error = ethcore_ip_port_source_payload_error; +assign ethcore_rx_sink_sink_param_length = ethcore_ip_port_source_param_length; +assign ethcore_rx_sink_sink_param_protocol = ethcore_ip_port_source_param_protocol; +assign ethcore_rx_sink_sink_param_ip_address = ethcore_ip_port_source_param_ip_address; +assign ethcore_tx_sink_sink_valid = ethcore_crossbar_source_valid; +assign ethcore_crossbar_source_ready = ethcore_tx_sink_sink_ready; +assign ethcore_tx_sink_sink_first = ethcore_crossbar_source_first; +assign ethcore_tx_sink_sink_last = ethcore_crossbar_source_last; +assign ethcore_tx_sink_sink_payload_data = ethcore_crossbar_source_payload_data; +assign ethcore_tx_sink_sink_payload_error = ethcore_crossbar_source_payload_error; +assign ethcore_tx_sink_sink_param_src_port = ethcore_crossbar_source_param_src_port; +assign ethcore_tx_sink_sink_param_dst_port = ethcore_crossbar_source_param_dst_port; +assign ethcore_tx_sink_sink_param_ip_address = ethcore_crossbar_source_param_ip_address; +assign ethcore_tx_sink_sink_param_length = ethcore_crossbar_source_param_length; +assign ethcore_crossbar_sink_valid = ethcore_rx_source_source_valid; +assign ethcore_rx_source_source_ready = ethcore_crossbar_sink_ready; +assign ethcore_crossbar_sink_first = ethcore_rx_source_source_first; +assign ethcore_crossbar_sink_last = ethcore_rx_source_source_last; +assign ethcore_crossbar_sink_payload_data = ethcore_rx_source_source_payload_data; +assign ethcore_crossbar_sink_payload_error = ethcore_rx_source_source_payload_error; +assign ethcore_crossbar_sink_param_src_port = ethcore_rx_source_source_param_src_port; +assign ethcore_crossbar_sink_param_dst_port = ethcore_rx_source_source_param_dst_port; +assign ethcore_crossbar_sink_param_ip_address = ethcore_rx_source_source_param_ip_address; +assign ethcore_crossbar_sink_param_length = ethcore_rx_source_source_param_length; +assign ethcore_tx_packetizer_sink_valid = ethcore_tx_sink_sink_valid; +assign ethcore_tx_packetizer_sink_last = ethcore_tx_sink_sink_last; +assign ethcore_tx_sink_sink_ready = ethcore_tx_packetizer_sink_ready; +assign ethcore_tx_packetizer_sink_param_src_port = ethcore_tx_sink_sink_param_src_port; +assign ethcore_tx_packetizer_sink_param_dst_port = ethcore_tx_sink_sink_param_dst_port; +assign ethcore_tx_packetizer_sink_param_length = (ethcore_tx_sink_sink_param_length + 4'd8); +assign ethcore_tx_packetizer_sink_param_checksum = 1'd0; +assign ethcore_tx_packetizer_sink_payload_data = ethcore_tx_sink_sink_payload_data; +always @(*) begin + ethcore_tx_packetizer_header <= 64'd0; + ethcore_tx_packetizer_header[63:48] <= {ethcore_tx_packetizer_sink_param_checksum[7:0], ethcore_tx_packetizer_sink_param_checksum[15:8]}; + ethcore_tx_packetizer_header[31:16] <= {ethcore_tx_packetizer_sink_param_dst_port[7:0], ethcore_tx_packetizer_sink_param_dst_port[15:8]}; + ethcore_tx_packetizer_header[47:32] <= {ethcore_tx_packetizer_sink_param_length[7:0], ethcore_tx_packetizer_sink_param_length[15:8]}; + ethcore_tx_packetizer_header[15:0] <= {ethcore_tx_packetizer_sink_param_src_port[7:0], ethcore_tx_packetizer_sink_param_src_port[15:8]}; +end +assign ethcore_tx_packetizer_source_payload_error = ethcore_tx_packetizer_sink_payload_error; +always @(*) begin + ethcore_tx_packetizer_sr_load <= 1'd0; + ethcore_tx_packetizer_sr_shift <= 1'd0; + ethcore_tx_packetizer_fsm_from_idle_liteethudptx_next_value1 <= 1'd0; + ethcore_tx_packetizer_fsm_from_idle_liteethudptx_next_value_ce1 <= 1'd0; + ethcore_tx_packetizer_source_valid <= 1'd0; + ethcore_tx_packetizer_source_last <= 1'd0; + ethcore_tx_packetizer_source_payload_data <= 8'd0; + ethcore_tx_packetizer_sink_ready <= 1'd0; + liteethudpipcore_liteethudp_liteethudptx_liteethudppacketizer_next_state <= 2'd0; + ethcore_tx_packetizer_count_liteethudptx_next_value0 <= 3'd0; + ethcore_tx_packetizer_count_liteethudptx_next_value_ce0 <= 1'd0; + liteethudpipcore_liteethudp_liteethudptx_liteethudppacketizer_next_state <= liteethudpipcore_liteethudp_liteethudptx_liteethudppacketizer_state; + case (liteethudpipcore_liteethudp_liteethudptx_liteethudppacketizer_state) + 1'd1: begin + ethcore_tx_packetizer_source_valid <= 1'd1; + ethcore_tx_packetizer_source_last <= 1'd0; + ethcore_tx_packetizer_source_payload_data <= ethcore_tx_packetizer_sr[63:8]; + if ((ethcore_tx_packetizer_source_valid & ethcore_tx_packetizer_source_ready)) begin + ethcore_tx_packetizer_sr_shift <= 1'd1; + if ((ethcore_tx_packetizer_count == 3'd7)) begin + ethcore_tx_packetizer_sr_shift <= 1'd0; + if (1'd0) begin + liteethudpipcore_liteethudp_liteethudptx_liteethudppacketizer_next_state <= 2'd3; + ethcore_tx_packetizer_count_liteethudptx_next_value0 <= (ethcore_tx_packetizer_count + 1'd1); + ethcore_tx_packetizer_count_liteethudptx_next_value_ce0 <= 1'd1; + end else begin + liteethudpipcore_liteethudp_liteethudptx_liteethudppacketizer_next_state <= 2'd2; + end + end else begin + ethcore_tx_packetizer_count_liteethudptx_next_value0 <= (ethcore_tx_packetizer_count + 1'd1); + ethcore_tx_packetizer_count_liteethudptx_next_value_ce0 <= 1'd1; + end + end + end + 2'd2: begin + ethcore_tx_packetizer_source_valid <= ethcore_tx_packetizer_sink_valid; + ethcore_tx_packetizer_source_last <= ethcore_tx_packetizer_sink_last; + ethcore_tx_packetizer_source_payload_data <= ethcore_tx_packetizer_sink_payload_data; + if ((ethcore_tx_packetizer_source_valid & ethcore_tx_packetizer_source_ready)) begin + ethcore_tx_packetizer_sink_ready <= 1'd1; + if (ethcore_tx_packetizer_source_last) begin + liteethudpipcore_liteethudp_liteethudptx_liteethudppacketizer_next_state <= 1'd0; + end + end + end + 2'd3: begin + ethcore_tx_packetizer_source_valid <= (ethcore_tx_packetizer_sink_valid | ethcore_tx_packetizer_sink_d_last); + ethcore_tx_packetizer_source_last <= ethcore_tx_packetizer_sink_d_last; + if (ethcore_tx_packetizer_fsm_from_idle) begin + ethcore_tx_packetizer_source_payload_data[0] <= ethcore_tx_packetizer_sr[63:16]; + end else begin + ethcore_tx_packetizer_source_payload_data[0] <= ethcore_tx_packetizer_sink_d_payload_data[7]; + end + ethcore_tx_packetizer_source_payload_data[7:0] <= ethcore_tx_packetizer_sink_payload_data; + if ((ethcore_tx_packetizer_source_valid & ethcore_tx_packetizer_source_ready)) begin + ethcore_tx_packetizer_sink_ready <= (~ethcore_tx_packetizer_source_last); + ethcore_tx_packetizer_fsm_from_idle_liteethudptx_next_value1 <= 1'd0; + ethcore_tx_packetizer_fsm_from_idle_liteethudptx_next_value_ce1 <= 1'd1; + if (ethcore_tx_packetizer_source_last) begin + liteethudpipcore_liteethudp_liteethudptx_liteethudppacketizer_next_state <= 1'd0; + end + end + end + default: begin + ethcore_tx_packetizer_sink_ready <= 1'd1; + ethcore_tx_packetizer_count_liteethudptx_next_value0 <= 1'd1; + ethcore_tx_packetizer_count_liteethudptx_next_value_ce0 <= 1'd1; + if (ethcore_tx_packetizer_sink_valid) begin + ethcore_tx_packetizer_sink_ready <= 1'd0; + ethcore_tx_packetizer_source_valid <= 1'd1; + ethcore_tx_packetizer_source_last <= 1'd0; + ethcore_tx_packetizer_source_payload_data <= ethcore_tx_packetizer_header[7:0]; + if ((ethcore_tx_packetizer_source_valid & ethcore_tx_packetizer_source_ready)) begin + ethcore_tx_packetizer_sr_load <= 1'd1; + ethcore_tx_packetizer_fsm_from_idle_liteethudptx_next_value1 <= 1'd1; + ethcore_tx_packetizer_fsm_from_idle_liteethudptx_next_value_ce1 <= 1'd1; + if (1'd0) begin + if (1'd0) begin + liteethudpipcore_liteethudp_liteethudptx_liteethudppacketizer_next_state <= 2'd3; + end else begin + liteethudpipcore_liteethudp_liteethudptx_liteethudppacketizer_next_state <= 2'd2; + end + end else begin + liteethudpipcore_liteethudp_liteethudptx_liteethudppacketizer_next_state <= 1'd1; + end + end + end + end + endcase +end +always @(*) begin + ethcore_tx_source_source_valid <= 1'd0; + ethcore_tx_source_source_first <= 1'd0; + liteethudpipcore_liteethudp_liteethudptx_fsm_next_state <= 1'd0; + ethcore_tx_source_source_last <= 1'd0; + ethcore_tx_packetizer_source_ready <= 1'd0; + ethcore_tx_source_source_payload_data <= 8'd0; + ethcore_tx_source_source_payload_error <= 1'd0; + ethcore_tx_source_source_param_length <= 16'd0; + ethcore_tx_source_source_param_protocol <= 8'd0; + ethcore_tx_source_source_param_ip_address <= 32'd0; + liteethudpipcore_liteethudp_liteethudptx_fsm_next_state <= liteethudpipcore_liteethudp_liteethudptx_fsm_state; + case (liteethudpipcore_liteethudp_liteethudptx_fsm_state) + 1'd1: begin + ethcore_tx_source_source_valid <= ethcore_tx_packetizer_source_valid; + ethcore_tx_packetizer_source_ready <= ethcore_tx_source_source_ready; + ethcore_tx_source_source_first <= ethcore_tx_packetizer_source_first; + ethcore_tx_source_source_last <= ethcore_tx_packetizer_source_last; + ethcore_tx_source_source_payload_data <= ethcore_tx_packetizer_source_payload_data; + ethcore_tx_source_source_payload_error <= ethcore_tx_packetizer_source_payload_error; + ethcore_tx_source_source_param_length <= ethcore_tx_packetizer_source_param_length; + ethcore_tx_source_source_param_protocol <= ethcore_tx_packetizer_source_param_protocol; + ethcore_tx_source_source_param_ip_address <= ethcore_tx_packetizer_source_param_ip_address; + ethcore_tx_source_source_param_length <= ethcore_tx_packetizer_sink_param_length; + ethcore_tx_source_source_param_protocol <= 5'd17; + ethcore_tx_source_source_param_ip_address <= ethcore_tx_sink_sink_param_ip_address; + if (((ethcore_tx_source_source_valid & ethcore_tx_source_source_last) & ethcore_tx_source_source_ready)) begin + liteethudpipcore_liteethudp_liteethudptx_fsm_next_state <= 1'd0; + end + end + default: begin + ethcore_tx_packetizer_source_ready <= 1'd1; + if (ethcore_tx_packetizer_source_valid) begin + ethcore_tx_packetizer_source_ready <= 1'd0; + liteethudpipcore_liteethudp_liteethudptx_fsm_next_state <= 1'd1; + end + end + endcase +end +assign ethcore_rx_depacketizer_sink_valid = ethcore_rx_sink_sink_valid; +assign ethcore_rx_sink_sink_ready = ethcore_rx_depacketizer_sink_ready; +assign ethcore_rx_depacketizer_sink_first = ethcore_rx_sink_sink_first; +assign ethcore_rx_depacketizer_sink_last = ethcore_rx_sink_sink_last; +assign ethcore_rx_depacketizer_sink_payload_data = ethcore_rx_sink_sink_payload_data; +assign ethcore_rx_depacketizer_sink_payload_error = ethcore_rx_sink_sink_payload_error; +assign ethcore_rx_depacketizer_sink_param_length = ethcore_rx_sink_sink_param_length; +assign ethcore_rx_depacketizer_sink_param_protocol = ethcore_rx_sink_sink_param_protocol; +assign ethcore_rx_depacketizer_sink_param_ip_address = ethcore_rx_sink_sink_param_ip_address; +assign ethcore_rx_source_source_last = ethcore_rx_depacketizer_source_last; +assign ethcore_rx_source_source_param_src_port = ethcore_rx_depacketizer_source_param_src_port; +assign ethcore_rx_source_source_param_dst_port = ethcore_rx_depacketizer_source_param_dst_port; +assign ethcore_rx_source_source_param_ip_address = ethcore_rx_sink_sink_param_ip_address; +assign ethcore_rx_source_source_param_length = (ethcore_rx_depacketizer_source_param_length - 4'd8); +assign ethcore_rx_source_source_payload_data = ethcore_rx_depacketizer_source_payload_data; +assign ethcore_rx_source_source_payload_error = ethcore_rx_depacketizer_source_payload_error; +assign ethcore_rx_depacketizer_header = ethcore_rx_depacketizer_sr; +assign ethcore_rx_depacketizer_source_param_checksum = {rhs_slice_proxy69[7:0], rhs_slice_proxy68[15:8]}; +assign ethcore_rx_depacketizer_source_param_dst_port = {rhs_slice_proxy71[7:0], rhs_slice_proxy70[15:8]}; +assign ethcore_rx_depacketizer_source_param_length = {rhs_slice_proxy73[7:0], rhs_slice_proxy72[15:8]}; +assign ethcore_rx_depacketizer_source_param_src_port = {rhs_slice_proxy75[7:0], rhs_slice_proxy74[15:8]}; +assign ethcore_rx_depacketizer_source_payload_error = ethcore_rx_depacketizer_sink_payload_error; +always @(*) begin + ethcore_rx_depacketizer_fsm_from_idle_liteethudprx_next_value_ce1 <= 1'd0; + ethcore_rx_depacketizer_sr_shift <= 1'd0; + ethcore_rx_depacketizer_sr_shift_leftover <= 1'd0; + ethcore_rx_depacketizer_source_valid <= 1'd0; + ethcore_rx_depacketizer_source_last <= 1'd0; + ethcore_rx_depacketizer_source_payload_data <= 8'd0; + liteethudpipcore_liteethudp_liteethudprx_liteethudpdepacketizer_next_state <= 2'd0; + ethcore_rx_depacketizer_count_liteethudprx_next_value0 <= 3'd0; + ethcore_rx_depacketizer_count_liteethudprx_next_value_ce0 <= 1'd0; + ethcore_rx_depacketizer_sink_ready <= 1'd0; + ethcore_rx_depacketizer_fsm_from_idle_liteethudprx_next_value1 <= 1'd0; + liteethudpipcore_liteethudp_liteethudprx_liteethudpdepacketizer_next_state <= liteethudpipcore_liteethudp_liteethudprx_liteethudpdepacketizer_state; + case (liteethudpipcore_liteethudp_liteethudprx_liteethudpdepacketizer_state) + 1'd1: begin + ethcore_rx_depacketizer_sink_ready <= 1'd1; + if (ethcore_rx_depacketizer_sink_valid) begin + ethcore_rx_depacketizer_count_liteethudprx_next_value0 <= (ethcore_rx_depacketizer_count + 1'd1); + ethcore_rx_depacketizer_count_liteethudprx_next_value_ce0 <= 1'd1; + ethcore_rx_depacketizer_sr_shift <= 1'd1; + if ((ethcore_rx_depacketizer_count == 3'd7)) begin + if (1'd0) begin + ethcore_rx_depacketizer_count_liteethudprx_next_value0 <= (ethcore_rx_depacketizer_count + 1'd1); + ethcore_rx_depacketizer_count_liteethudprx_next_value_ce0 <= 1'd1; + liteethudpipcore_liteethudp_liteethudprx_liteethudpdepacketizer_next_state <= 2'd2; + end else begin + liteethudpipcore_liteethudp_liteethudprx_liteethudpdepacketizer_next_state <= 2'd3; + end + end + end + end + 2'd2: begin + ethcore_rx_depacketizer_source_valid <= (ethcore_rx_depacketizer_sink_valid | ethcore_rx_depacketizer_sink_d_last); + ethcore_rx_depacketizer_source_last <= (ethcore_rx_depacketizer_sink_last | ethcore_rx_depacketizer_sink_d_last); + ethcore_rx_depacketizer_sink_ready <= ethcore_rx_depacketizer_source_ready; + ethcore_rx_depacketizer_source_payload_data <= ethcore_rx_depacketizer_sink_d_payload_data[7:0]; + ethcore_rx_depacketizer_source_payload_data[7] <= ethcore_rx_depacketizer_sink_payload_data; + if (ethcore_rx_depacketizer_fsm_from_idle) begin + ethcore_rx_depacketizer_source_valid <= ethcore_rx_depacketizer_sink_d_last; + ethcore_rx_depacketizer_sink_ready <= 1'd1; + if (ethcore_rx_depacketizer_sink_valid) begin + ethcore_rx_depacketizer_fsm_from_idle_liteethudprx_next_value1 <= 1'd0; + ethcore_rx_depacketizer_fsm_from_idle_liteethudprx_next_value_ce1 <= 1'd1; + ethcore_rx_depacketizer_sr_shift_leftover <= 1'd1; + end + end + if ((ethcore_rx_depacketizer_source_valid & ethcore_rx_depacketizer_source_ready)) begin + if (ethcore_rx_depacketizer_source_last) begin + liteethudpipcore_liteethudp_liteethudprx_liteethudpdepacketizer_next_state <= 1'd0; + end + end + end + 2'd3: begin + ethcore_rx_depacketizer_source_valid <= (ethcore_rx_depacketizer_sink_valid | ethcore_rx_depacketizer_sink_d_last); + ethcore_rx_depacketizer_source_last <= (ethcore_rx_depacketizer_sink_last | ethcore_rx_depacketizer_sink_d_last); + ethcore_rx_depacketizer_sink_ready <= ethcore_rx_depacketizer_source_ready; + ethcore_rx_depacketizer_source_payload_data <= ethcore_rx_depacketizer_sink_payload_data; + if ((ethcore_rx_depacketizer_source_valid & ethcore_rx_depacketizer_source_ready)) begin + if (ethcore_rx_depacketizer_source_last) begin + liteethudpipcore_liteethudp_liteethudprx_liteethudpdepacketizer_next_state <= 1'd0; + end + end + end + default: begin + ethcore_rx_depacketizer_sink_ready <= 1'd1; + ethcore_rx_depacketizer_count_liteethudprx_next_value0 <= 1'd1; + ethcore_rx_depacketizer_count_liteethudprx_next_value_ce0 <= 1'd1; + if (ethcore_rx_depacketizer_sink_valid) begin + ethcore_rx_depacketizer_sr_shift <= 1'd1; + ethcore_rx_depacketizer_fsm_from_idle_liteethudprx_next_value1 <= 1'd1; + ethcore_rx_depacketizer_fsm_from_idle_liteethudprx_next_value_ce1 <= 1'd1; + if (1'd0) begin + if (1'd0) begin + liteethudpipcore_liteethudp_liteethudprx_liteethudpdepacketizer_next_state <= 2'd2; + end else begin + liteethudpipcore_liteethudp_liteethudprx_liteethudpdepacketizer_next_state <= 2'd3; + end + end else begin + liteethudpipcore_liteethudp_liteethudprx_liteethudpdepacketizer_next_state <= 1'd1; + end + end + end + endcase +end +always @(*) begin + liteethudpipcore_liteethudp_liteethudprx_fsm_next_state <= 2'd0; + ethcore_rx_source_source_valid <= 1'd0; + ethcore_rx_depacketizer_source_ready <= 1'd0; + liteethudpipcore_liteethudp_liteethudprx_fsm_next_state <= liteethudpipcore_liteethudp_liteethudprx_fsm_state; + case (liteethudpipcore_liteethudp_liteethudprx_fsm_state) + 1'd1: begin + if (ethcore_rx_valid) begin + liteethudpipcore_liteethudp_liteethudprx_fsm_next_state <= 2'd2; + end else begin + liteethudpipcore_liteethudp_liteethudprx_fsm_next_state <= 2'd3; + end + end + 2'd2: begin + ethcore_rx_source_source_valid <= ethcore_rx_depacketizer_source_valid; + ethcore_rx_depacketizer_source_ready <= ethcore_rx_source_source_ready; + if (((ethcore_rx_source_source_valid & ethcore_rx_source_source_last) & ethcore_rx_source_source_ready)) begin + liteethudpipcore_liteethudp_liteethudprx_fsm_next_state <= 1'd0; + end + end + 2'd3: begin + ethcore_rx_depacketizer_source_ready <= 1'd1; + if (((ethcore_rx_depacketizer_source_valid & ethcore_rx_depacketizer_source_last) & ethcore_rx_depacketizer_source_ready)) begin + liteethudpipcore_liteethudp_liteethudprx_fsm_next_state <= 1'd0; + end + end + default: begin + ethcore_rx_depacketizer_source_ready <= 1'd1; + if (ethcore_rx_depacketizer_source_valid) begin + ethcore_rx_depacketizer_source_ready <= 1'd0; + liteethudpipcore_liteethudp_liteethudprx_fsm_next_state <= 1'd1; + end + end + endcase +end +assign etherbone_tx_converter_sink_valid = etherbone_user_port_sink_valid; +assign etherbone_user_port_sink_ready = etherbone_tx_converter_sink_ready; +assign etherbone_tx_converter_sink_first = etherbone_user_port_sink_first; +assign etherbone_tx_converter_sink_last = etherbone_user_port_sink_last; +assign etherbone_tx_converter_sink_payload_data = etherbone_user_port_sink_payload_data; +assign etherbone_tx_converter_sink_payload_error = etherbone_user_port_sink_payload_error; +assign etherbone_tx_converter_sink_param_src_port = etherbone_user_port_sink_param_src_port; +assign etherbone_tx_converter_sink_param_dst_port = etherbone_user_port_sink_param_dst_port; +assign etherbone_tx_converter_sink_param_ip_address = etherbone_user_port_sink_param_ip_address; +assign etherbone_tx_converter_sink_param_length = etherbone_user_port_sink_param_length; +assign etherbone_internal_port_sink_valid = etherbone_tx_converter_source_valid; +assign etherbone_tx_converter_source_ready = etherbone_internal_port_sink_ready; +assign etherbone_internal_port_sink_first = etherbone_tx_converter_source_first; +assign etherbone_internal_port_sink_last = etherbone_tx_converter_source_last; +assign etherbone_internal_port_sink_payload_data = etherbone_tx_converter_source_payload_data; +assign etherbone_internal_port_sink_payload_error = etherbone_tx_converter_source_payload_error; +assign etherbone_internal_port_sink_param_src_port = etherbone_tx_converter_source_param_src_port; +assign etherbone_internal_port_sink_param_dst_port = etherbone_tx_converter_source_param_dst_port; +assign etherbone_internal_port_sink_param_ip_address = etherbone_tx_converter_source_param_ip_address; +assign etherbone_internal_port_sink_param_length = etherbone_tx_converter_source_param_length; +assign etherbone_rx_converter_sink_valid = etherbone_internal_port_source_valid; +assign etherbone_internal_port_source_ready = etherbone_rx_converter_sink_ready; +assign etherbone_rx_converter_sink_first = etherbone_internal_port_source_first; +assign etherbone_rx_converter_sink_last = etherbone_internal_port_source_last; +assign etherbone_rx_converter_sink_payload_data = etherbone_internal_port_source_payload_data; +assign etherbone_rx_converter_sink_payload_error = etherbone_internal_port_source_payload_error; +assign etherbone_rx_converter_sink_param_src_port = etherbone_internal_port_source_param_src_port; +assign etherbone_rx_converter_sink_param_dst_port = etherbone_internal_port_source_param_dst_port; +assign etherbone_rx_converter_sink_param_ip_address = etherbone_internal_port_source_param_ip_address; +assign etherbone_rx_converter_sink_param_length = etherbone_internal_port_source_param_length; +assign etherbone_user_port_source_valid = etherbone_rx_converter_source_valid; +assign etherbone_rx_converter_source_ready = etherbone_user_port_source_ready; +assign etherbone_user_port_source_first = etherbone_rx_converter_source_first; +assign etherbone_user_port_source_last = etherbone_rx_converter_source_last; +assign etherbone_user_port_source_payload_data = etherbone_rx_converter_source_payload_data; +assign etherbone_user_port_source_payload_error = etherbone_rx_converter_source_payload_error; +assign etherbone_user_port_source_param_src_port = etherbone_rx_converter_source_param_src_port; +assign etherbone_user_port_source_param_dst_port = etherbone_rx_converter_source_param_dst_port; +assign etherbone_user_port_source_param_ip_address = etherbone_rx_converter_source_param_ip_address; +assign etherbone_user_port_source_param_length = etherbone_rx_converter_source_param_length; +always @(*) begin + liteethudpipcore_liteethudp_sel <= 1'd0; + case (ethcore_crossbar_sink_param_dst_port) + 11'd1234: begin + liteethudpipcore_liteethudp_sel <= 1'd1; + end + default: begin + liteethudpipcore_liteethudp_sel <= 1'd0; + end + endcase +end +assign etherbone_tx_converter_converter_sink_valid = etherbone_tx_converter_sink_valid; +assign etherbone_tx_converter_converter_sink_first = etherbone_tx_converter_sink_first; +assign etherbone_tx_converter_converter_sink_last = etherbone_tx_converter_sink_last; +assign etherbone_tx_converter_sink_ready = etherbone_tx_converter_converter_sink_ready; +always @(*) begin + etherbone_tx_converter_converter_sink_payload_data <= 36'd0; + etherbone_tx_converter_converter_sink_payload_data[7:0] <= etherbone_tx_converter_sink_payload_data[7:0]; + etherbone_tx_converter_converter_sink_payload_data[8] <= etherbone_tx_converter_sink_payload_error[0]; + etherbone_tx_converter_converter_sink_payload_data[16:9] <= etherbone_tx_converter_sink_payload_data[15:8]; + etherbone_tx_converter_converter_sink_payload_data[17] <= etherbone_tx_converter_sink_payload_error[1]; + etherbone_tx_converter_converter_sink_payload_data[25:18] <= etherbone_tx_converter_sink_payload_data[23:16]; + etherbone_tx_converter_converter_sink_payload_data[26] <= etherbone_tx_converter_sink_payload_error[2]; + etherbone_tx_converter_converter_sink_payload_data[34:27] <= etherbone_tx_converter_sink_payload_data[31:24]; + etherbone_tx_converter_converter_sink_payload_data[35] <= etherbone_tx_converter_sink_payload_error[3]; +end +assign etherbone_tx_converter_source_valid = etherbone_tx_converter_source_source_valid; +assign etherbone_tx_converter_source_first = etherbone_tx_converter_source_source_first; +assign etherbone_tx_converter_source_last = etherbone_tx_converter_source_source_last; +assign etherbone_tx_converter_source_source_ready = etherbone_tx_converter_source_ready; +assign {etherbone_tx_converter_source_payload_error, etherbone_tx_converter_source_payload_data} = etherbone_tx_converter_source_source_payload_data; +assign etherbone_tx_converter_source_param_src_port = etherbone_tx_converter_sink_param_src_port; +assign etherbone_tx_converter_source_param_dst_port = etherbone_tx_converter_sink_param_dst_port; +assign etherbone_tx_converter_source_param_ip_address = etherbone_tx_converter_sink_param_ip_address; +assign etherbone_tx_converter_source_param_length = etherbone_tx_converter_sink_param_length; +assign etherbone_tx_converter_source_source_valid = etherbone_tx_converter_converter_source_valid; +assign etherbone_tx_converter_converter_source_ready = etherbone_tx_converter_source_source_ready; +assign etherbone_tx_converter_source_source_first = etherbone_tx_converter_converter_source_first; +assign etherbone_tx_converter_source_source_last = etherbone_tx_converter_converter_source_last; +assign etherbone_tx_converter_source_source_payload_data = etherbone_tx_converter_converter_source_payload_data; +assign etherbone_tx_converter_converter_first = (etherbone_tx_converter_converter_mux == 1'd0); +assign etherbone_tx_converter_converter_last = (etherbone_tx_converter_converter_mux == 2'd3); +assign etherbone_tx_converter_converter_source_valid = etherbone_tx_converter_converter_sink_valid; +assign etherbone_tx_converter_converter_source_first = (etherbone_tx_converter_converter_sink_first & etherbone_tx_converter_converter_first); +assign etherbone_tx_converter_converter_source_last = (etherbone_tx_converter_converter_sink_last & etherbone_tx_converter_converter_last); +assign etherbone_tx_converter_converter_sink_ready = (etherbone_tx_converter_converter_last & etherbone_tx_converter_converter_source_ready); +always @(*) begin + etherbone_tx_converter_converter_source_payload_data <= 9'd0; + case (etherbone_tx_converter_converter_mux) + 1'd0: begin + etherbone_tx_converter_converter_source_payload_data <= etherbone_tx_converter_converter_sink_payload_data[8:0]; + end + 1'd1: begin + etherbone_tx_converter_converter_source_payload_data <= etherbone_tx_converter_converter_sink_payload_data[17:9]; + end + 2'd2: begin + etherbone_tx_converter_converter_source_payload_data <= etherbone_tx_converter_converter_sink_payload_data[26:18]; + end + default: begin + etherbone_tx_converter_converter_source_payload_data <= etherbone_tx_converter_converter_sink_payload_data[35:27]; + end + endcase +end +assign etherbone_tx_converter_converter_source_payload_valid_token_count = etherbone_tx_converter_converter_last; +assign etherbone_rx_converter_converter_sink_valid = etherbone_rx_converter_sink_valid; +assign etherbone_rx_converter_converter_sink_first = etherbone_rx_converter_sink_first; +assign etherbone_rx_converter_converter_sink_last = etherbone_rx_converter_sink_last; +assign etherbone_rx_converter_sink_ready = etherbone_rx_converter_converter_sink_ready; +assign etherbone_rx_converter_converter_sink_payload_data = {etherbone_rx_converter_sink_payload_error, etherbone_rx_converter_sink_payload_data}; +assign etherbone_rx_converter_source_valid = etherbone_rx_converter_source_source_valid; +assign etherbone_rx_converter_source_first = etherbone_rx_converter_source_source_first; +assign etherbone_rx_converter_source_last = etherbone_rx_converter_source_source_last; +assign etherbone_rx_converter_source_source_ready = etherbone_rx_converter_source_ready; +always @(*) begin + etherbone_rx_converter_source_payload_data <= 32'd0; + etherbone_rx_converter_source_payload_data[7:0] <= etherbone_rx_converter_source_source_payload_data[7:0]; + etherbone_rx_converter_source_payload_data[15:8] <= etherbone_rx_converter_source_source_payload_data[16:9]; + etherbone_rx_converter_source_payload_data[23:16] <= etherbone_rx_converter_source_source_payload_data[25:18]; + etherbone_rx_converter_source_payload_data[31:24] <= etherbone_rx_converter_source_source_payload_data[34:27]; +end +always @(*) begin + etherbone_rx_converter_source_payload_error <= 4'd0; + etherbone_rx_converter_source_payload_error[0] <= etherbone_rx_converter_source_source_payload_data[8]; + etherbone_rx_converter_source_payload_error[1] <= etherbone_rx_converter_source_source_payload_data[17]; + etherbone_rx_converter_source_payload_error[2] <= etherbone_rx_converter_source_source_payload_data[26]; + etherbone_rx_converter_source_payload_error[3] <= etherbone_rx_converter_source_source_payload_data[35]; +end +assign etherbone_rx_converter_source_source_valid = etherbone_rx_converter_converter_source_valid; +assign etherbone_rx_converter_converter_source_ready = etherbone_rx_converter_source_source_ready; +assign etherbone_rx_converter_source_source_first = etherbone_rx_converter_converter_source_first; +assign etherbone_rx_converter_source_source_last = etherbone_rx_converter_converter_source_last; +assign etherbone_rx_converter_source_source_payload_data = etherbone_rx_converter_converter_source_payload_data; +assign etherbone_rx_converter_converter_sink_ready = ((~etherbone_rx_converter_converter_strobe_all) | etherbone_rx_converter_converter_source_ready); +assign etherbone_rx_converter_converter_source_valid = etherbone_rx_converter_converter_strobe_all; +assign etherbone_rx_converter_converter_load_part = (etherbone_rx_converter_converter_sink_valid & etherbone_rx_converter_converter_sink_ready); +assign ethcore_crossbar_source_valid = etherbone_internal_port_sink_valid; +assign etherbone_internal_port_sink_ready = ethcore_crossbar_source_ready; +assign ethcore_crossbar_source_first = etherbone_internal_port_sink_first; +assign ethcore_crossbar_source_last = etherbone_internal_port_sink_last; +assign ethcore_crossbar_source_payload_data = etherbone_internal_port_sink_payload_data; +assign ethcore_crossbar_source_payload_error = etherbone_internal_port_sink_payload_error; +assign ethcore_crossbar_source_param_src_port = etherbone_internal_port_sink_param_src_port; +assign ethcore_crossbar_source_param_dst_port = etherbone_internal_port_sink_param_dst_port; +assign ethcore_crossbar_source_param_ip_address = etherbone_internal_port_sink_param_ip_address; +assign ethcore_crossbar_source_param_length = etherbone_internal_port_sink_param_length; +assign etherbone_internal_port_source_valid = ethcore_crossbar_sink_valid; +assign ethcore_crossbar_sink_ready = etherbone_internal_port_source_ready; +assign etherbone_internal_port_source_first = ethcore_crossbar_sink_first; +assign etherbone_internal_port_source_last = ethcore_crossbar_sink_last; +assign etherbone_internal_port_source_payload_data = ethcore_crossbar_sink_payload_data; +assign etherbone_internal_port_source_payload_error = ethcore_crossbar_sink_payload_error; +assign etherbone_internal_port_source_param_src_port = ethcore_crossbar_sink_param_src_port; +assign etherbone_internal_port_source_param_dst_port = ethcore_crossbar_sink_param_dst_port; +assign etherbone_internal_port_source_param_ip_address = ethcore_crossbar_sink_param_ip_address; +assign etherbone_internal_port_source_param_length = ethcore_crossbar_sink_param_length; +assign etherbone_dispatcher_sel0 = (~etherbone_rx_source_source_param_pf); +assign etherbone_liteethetherbonewishbonemaster_sink_valid = etherbone_record_receiver_source_source_valid; +assign etherbone_record_receiver_source_source_ready = etherbone_liteethetherbonewishbonemaster_sink_ready; +assign etherbone_liteethetherbonewishbonemaster_sink_first = etherbone_record_receiver_source_source_first; +assign etherbone_liteethetherbonewishbonemaster_sink_last = etherbone_record_receiver_source_source_last; +assign etherbone_liteethetherbonewishbonemaster_sink_payload_addr = etherbone_record_receiver_source_source_payload_addr; +assign etherbone_liteethetherbonewishbonemaster_sink_payload_data = etherbone_record_receiver_source_source_payload_data; +assign etherbone_liteethetherbonewishbonemaster_sink_param_we = etherbone_record_receiver_source_source_param_we; +assign etherbone_liteethetherbonewishbonemaster_sink_param_count = etherbone_record_receiver_source_source_param_count; +assign etherbone_liteethetherbonewishbonemaster_sink_param_base_addr = etherbone_record_receiver_source_source_param_base_addr; +assign etherbone_liteethetherbonewishbonemaster_sink_param_be = etherbone_record_receiver_source_source_param_be; +assign etherbone_record_sender_sink_sink_valid = etherbone_liteethetherbonewishbonemaster_source_valid; +assign etherbone_liteethetherbonewishbonemaster_source_ready = etherbone_record_sender_sink_sink_ready; +assign etherbone_record_sender_sink_sink_first = etherbone_liteethetherbonewishbonemaster_source_first; +assign etherbone_record_sender_sink_sink_last = etherbone_liteethetherbonewishbonemaster_source_last; +assign etherbone_record_sender_sink_sink_payload_addr = etherbone_liteethetherbonewishbonemaster_source_payload_addr; +assign etherbone_record_sender_sink_sink_payload_data = etherbone_liteethetherbonewishbonemaster_source_payload_data; +assign etherbone_record_sender_sink_sink_param_we = etherbone_liteethetherbonewishbonemaster_source_param_we; +assign etherbone_record_sender_sink_sink_param_count = etherbone_liteethetherbonewishbonemaster_source_param_count; +assign etherbone_record_sender_sink_sink_param_base_addr = etherbone_liteethetherbonewishbonemaster_source_param_base_addr; +assign etherbone_record_sender_sink_sink_param_be = etherbone_liteethetherbonewishbonemaster_source_param_be; +assign etherbone_user_port_sink_valid = etherbone_tx_source_source_valid; +assign etherbone_tx_source_source_ready = etherbone_user_port_sink_ready; +assign etherbone_user_port_sink_first = etherbone_tx_source_source_first; +assign etherbone_user_port_sink_last = etherbone_tx_source_source_last; +assign etherbone_user_port_sink_payload_data = etherbone_tx_source_source_payload_data; +assign etherbone_user_port_sink_payload_error = etherbone_tx_source_source_payload_error; +assign etherbone_user_port_sink_param_src_port = etherbone_tx_source_source_param_src_port; +assign etherbone_user_port_sink_param_dst_port = etherbone_tx_source_source_param_dst_port; +assign etherbone_user_port_sink_param_ip_address = etherbone_tx_source_source_param_ip_address; +assign etherbone_user_port_sink_param_length = etherbone_tx_source_source_param_length; +assign etherbone_rx_sink_sink_valid = etherbone_user_port_source_valid; +assign etherbone_user_port_source_ready = etherbone_rx_sink_sink_ready; +assign etherbone_rx_sink_sink_first = etherbone_user_port_source_first; +assign etherbone_rx_sink_sink_last = etherbone_user_port_source_last; +assign etherbone_rx_sink_sink_payload_data = etherbone_user_port_source_payload_data; +assign etherbone_rx_sink_sink_payload_error = etherbone_user_port_source_payload_error; +assign etherbone_rx_sink_sink_param_src_port = etherbone_user_port_source_param_src_port; +assign etherbone_rx_sink_sink_param_dst_port = etherbone_user_port_source_param_dst_port; +assign etherbone_rx_sink_sink_param_ip_address = etherbone_user_port_source_param_ip_address; +assign etherbone_rx_sink_sink_param_length = etherbone_user_port_source_param_length; +assign etherbone_tx_packetizer_sink_valid = etherbone_tx_sink_sink_valid; +assign etherbone_tx_packetizer_sink_last = etherbone_tx_sink_sink_last; +assign etherbone_tx_sink_sink_ready = etherbone_tx_packetizer_sink_ready; +assign etherbone_tx_packetizer_sink_param_magic = 15'd20079; +assign etherbone_tx_packetizer_sink_param_port_size = 3'd4; +assign etherbone_tx_packetizer_sink_param_addr_size = 3'd4; +assign etherbone_tx_packetizer_sink_param_pf = etherbone_tx_sink_sink_param_pf; +assign etherbone_tx_packetizer_sink_param_pr = etherbone_tx_sink_sink_param_pr; +assign etherbone_tx_packetizer_sink_param_nr = etherbone_tx_sink_sink_param_nr; +assign etherbone_tx_packetizer_sink_param_version = 1'd1; +assign etherbone_tx_packetizer_sink_payload_data = etherbone_tx_sink_sink_payload_data; +always @(*) begin + etherbone_tx_packetizer_header <= 64'd0; + etherbone_tx_packetizer_header[31:28] <= {etherbone_tx_packetizer_sink_param_addr_size[3:0]}; + etherbone_tx_packetizer_header[15:0] <= {etherbone_tx_packetizer_sink_param_magic[7:0], etherbone_tx_packetizer_sink_param_magic[15:8]}; + etherbone_tx_packetizer_header[18] <= {etherbone_tx_packetizer_sink_param_nr}; + etherbone_tx_packetizer_header[16] <= {etherbone_tx_packetizer_sink_param_pf}; + etherbone_tx_packetizer_header[27:24] <= {etherbone_tx_packetizer_sink_param_port_size[3:0]}; + etherbone_tx_packetizer_header[17] <= {etherbone_tx_packetizer_sink_param_pr}; + etherbone_tx_packetizer_header[23:20] <= {etherbone_tx_packetizer_sink_param_version[3:0]}; +end +assign etherbone_tx_packetizer_source_payload_error = etherbone_tx_packetizer_sink_payload_error; +always @(*) begin + etherbone_tx_packetizer_source_payload_data <= 32'd0; + etherbone_tx_packetizer_count_liteethetherbonepackettx_next_value_ce0 <= 1'd0; + etherbone_tx_packetizer_fsm_from_idle_liteethetherbonepackettx_next_value1 <= 1'd0; + etherbone_tx_packetizer_sr_load <= 1'd0; + etherbone_tx_packetizer_fsm_from_idle_liteethetherbonepackettx_next_value_ce1 <= 1'd0; + etherbone_tx_packetizer_sr_shift <= 1'd0; + etherbone_tx_packetizer_source_valid <= 1'd0; + etherbone_tx_packetizer_source_last <= 1'd0; + etherbone_tx_packetizer_sink_ready <= 1'd0; + liteethetherbonepackettx_liteethetherbonepacketpacketizer_next_state <= 2'd0; + etherbone_tx_packetizer_count_liteethetherbonepackettx_next_value0 <= 1'd0; + liteethetherbonepackettx_liteethetherbonepacketpacketizer_next_state <= liteethetherbonepackettx_liteethetherbonepacketpacketizer_state; + case (liteethetherbonepackettx_liteethetherbonepacketpacketizer_state) + 1'd1: begin + etherbone_tx_packetizer_source_valid <= 1'd1; + etherbone_tx_packetizer_source_last <= 1'd0; + etherbone_tx_packetizer_source_payload_data <= etherbone_tx_packetizer_sr[63:32]; + if ((etherbone_tx_packetizer_source_valid & etherbone_tx_packetizer_source_ready)) begin + etherbone_tx_packetizer_sr_shift <= 1'd1; + if ((etherbone_tx_packetizer_count == 1'd1)) begin + etherbone_tx_packetizer_sr_shift <= 1'd0; + if (1'd0) begin + liteethetherbonepackettx_liteethetherbonepacketpacketizer_next_state <= 2'd3; + etherbone_tx_packetizer_count_liteethetherbonepackettx_next_value0 <= (etherbone_tx_packetizer_count + 1'd1); + etherbone_tx_packetizer_count_liteethetherbonepackettx_next_value_ce0 <= 1'd1; + end else begin + liteethetherbonepackettx_liteethetherbonepacketpacketizer_next_state <= 2'd2; + end + end else begin + etherbone_tx_packetizer_count_liteethetherbonepackettx_next_value0 <= (etherbone_tx_packetizer_count + 1'd1); + etherbone_tx_packetizer_count_liteethetherbonepackettx_next_value_ce0 <= 1'd1; + end + end + end + 2'd2: begin + etherbone_tx_packetizer_source_valid <= etherbone_tx_packetizer_sink_valid; + etherbone_tx_packetizer_source_last <= etherbone_tx_packetizer_sink_last; + etherbone_tx_packetizer_source_payload_data <= etherbone_tx_packetizer_sink_payload_data; + if ((etherbone_tx_packetizer_source_valid & etherbone_tx_packetizer_source_ready)) begin + etherbone_tx_packetizer_sink_ready <= 1'd1; + if (etherbone_tx_packetizer_source_last) begin + liteethetherbonepackettx_liteethetherbonepacketpacketizer_next_state <= 1'd0; + end + end + end + 2'd3: begin + etherbone_tx_packetizer_source_valid <= (etherbone_tx_packetizer_sink_valid | etherbone_tx_packetizer_sink_d_last); + etherbone_tx_packetizer_source_last <= etherbone_tx_packetizer_sink_d_last; + if (etherbone_tx_packetizer_fsm_from_idle) begin + etherbone_tx_packetizer_source_payload_data[0] <= etherbone_tx_packetizer_sr[63]; + end else begin + etherbone_tx_packetizer_source_payload_data[0] <= etherbone_tx_packetizer_sink_d_payload_data[31]; + end + etherbone_tx_packetizer_source_payload_data[31:0] <= etherbone_tx_packetizer_sink_payload_data; + if ((etherbone_tx_packetizer_source_valid & etherbone_tx_packetizer_source_ready)) begin + etherbone_tx_packetizer_sink_ready <= (~etherbone_tx_packetizer_source_last); + etherbone_tx_packetizer_fsm_from_idle_liteethetherbonepackettx_next_value1 <= 1'd0; + etherbone_tx_packetizer_fsm_from_idle_liteethetherbonepackettx_next_value_ce1 <= 1'd1; + if (etherbone_tx_packetizer_source_last) begin + liteethetherbonepackettx_liteethetherbonepacketpacketizer_next_state <= 1'd0; + end + end + end + default: begin + etherbone_tx_packetizer_sink_ready <= 1'd1; + etherbone_tx_packetizer_count_liteethetherbonepackettx_next_value0 <= 1'd1; + etherbone_tx_packetizer_count_liteethetherbonepackettx_next_value_ce0 <= 1'd1; + if (etherbone_tx_packetizer_sink_valid) begin + etherbone_tx_packetizer_sink_ready <= 1'd0; + etherbone_tx_packetizer_source_valid <= 1'd1; + etherbone_tx_packetizer_source_last <= 1'd0; + etherbone_tx_packetizer_source_payload_data <= etherbone_tx_packetizer_header[31:0]; + if ((etherbone_tx_packetizer_source_valid & etherbone_tx_packetizer_source_ready)) begin + etherbone_tx_packetizer_sr_load <= 1'd1; + etherbone_tx_packetizer_fsm_from_idle_liteethetherbonepackettx_next_value1 <= 1'd1; + etherbone_tx_packetizer_fsm_from_idle_liteethetherbonepackettx_next_value_ce1 <= 1'd1; + if (1'd0) begin + if (1'd0) begin + liteethetherbonepackettx_liteethetherbonepacketpacketizer_next_state <= 2'd3; + end else begin + liteethetherbonepackettx_liteethetherbonepacketpacketizer_next_state <= 2'd2; + end + end else begin + liteethetherbonepackettx_liteethetherbonepacketpacketizer_next_state <= 1'd1; + end + end + end + end + endcase +end +always @(*) begin + etherbone_tx_source_source_valid <= 1'd0; + etherbone_tx_source_source_first <= 1'd0; + etherbone_tx_source_source_last <= 1'd0; + etherbone_tx_source_source_payload_data <= 32'd0; + liteethetherbonepackettx_fsm_next_state <= 1'd0; + etherbone_tx_source_source_payload_error <= 4'd0; + etherbone_tx_source_source_param_src_port <= 16'd0; + etherbone_tx_source_source_param_dst_port <= 16'd0; + etherbone_tx_packetizer_source_ready <= 1'd0; + etherbone_tx_source_source_param_ip_address <= 32'd0; + etherbone_tx_source_source_param_length <= 16'd0; + liteethetherbonepackettx_fsm_next_state <= liteethetherbonepackettx_fsm_state; + case (liteethetherbonepackettx_fsm_state) + 1'd1: begin + etherbone_tx_source_source_valid <= etherbone_tx_packetizer_source_valid; + etherbone_tx_packetizer_source_ready <= etherbone_tx_source_source_ready; + etherbone_tx_source_source_first <= etherbone_tx_packetizer_source_first; + etherbone_tx_source_source_last <= etherbone_tx_packetizer_source_last; + etherbone_tx_source_source_payload_data <= etherbone_tx_packetizer_source_payload_data; + etherbone_tx_source_source_payload_error <= etherbone_tx_packetizer_source_payload_error; + etherbone_tx_source_source_param_src_port <= etherbone_tx_packetizer_source_param_src_port; + etherbone_tx_source_source_param_dst_port <= etherbone_tx_packetizer_source_param_dst_port; + etherbone_tx_source_source_param_ip_address <= etherbone_tx_packetizer_source_param_ip_address; + etherbone_tx_source_source_param_length <= etherbone_tx_packetizer_source_param_length; + etherbone_tx_source_source_param_src_port <= 11'd1234; + etherbone_tx_source_source_param_dst_port <= 11'd1234; + etherbone_tx_source_source_param_ip_address <= etherbone_tx_sink_sink_param_ip_address; + etherbone_tx_source_source_param_length <= (etherbone_tx_sink_sink_param_length + 4'd8); + if (((etherbone_tx_source_source_valid & etherbone_tx_source_source_last) & etherbone_tx_source_source_ready)) begin + liteethetherbonepackettx_fsm_next_state <= 1'd0; + end + end + default: begin + etherbone_tx_packetizer_source_ready <= 1'd1; + if (etherbone_tx_packetizer_source_valid) begin + etherbone_tx_packetizer_source_ready <= 1'd0; + liteethetherbonepackettx_fsm_next_state <= 1'd1; + end + end + endcase +end +assign etherbone_rx_depacketizer_sink_valid = etherbone_rx_sink_sink_valid; +assign etherbone_rx_sink_sink_ready = etherbone_rx_depacketizer_sink_ready; +assign etherbone_rx_depacketizer_sink_first = etherbone_rx_sink_sink_first; +assign etherbone_rx_depacketizer_sink_last = etherbone_rx_sink_sink_last; +assign etherbone_rx_depacketizer_sink_payload_data = etherbone_rx_sink_sink_payload_data; +assign etherbone_rx_depacketizer_sink_payload_error = etherbone_rx_sink_sink_payload_error; +assign etherbone_rx_depacketizer_sink_param_src_port = etherbone_rx_sink_sink_param_src_port; +assign etherbone_rx_depacketizer_sink_param_dst_port = etherbone_rx_sink_sink_param_dst_port; +assign etherbone_rx_depacketizer_sink_param_ip_address = etherbone_rx_sink_sink_param_ip_address; +assign etherbone_rx_depacketizer_sink_param_length = etherbone_rx_sink_sink_param_length; +assign etherbone_rx_source_source_last = etherbone_rx_depacketizer_source_last; +assign etherbone_rx_source_source_param_pf = etherbone_rx_depacketizer_source_param_pf; +assign etherbone_rx_source_source_param_pr = etherbone_rx_depacketizer_source_param_pr; +assign etherbone_rx_source_source_param_nr = etherbone_rx_depacketizer_source_param_nr; +assign etherbone_rx_source_source_payload_data = etherbone_rx_depacketizer_source_payload_data; +assign etherbone_rx_source_source_param_src_port = etherbone_rx_sink_sink_param_src_port; +assign etherbone_rx_source_source_param_dst_port = etherbone_rx_sink_sink_param_dst_port; +assign etherbone_rx_source_source_param_ip_address = etherbone_rx_sink_sink_param_ip_address; +assign etherbone_rx_source_source_param_length = (etherbone_rx_sink_sink_param_length - 4'd8); +assign etherbone_rx_depacketizer_header = etherbone_rx_depacketizer_sr; +assign etherbone_rx_depacketizer_source_param_addr_size = {rhs_slice_proxy76[3:0]}; +assign etherbone_rx_depacketizer_source_param_magic = {rhs_slice_proxy78[7:0], rhs_slice_proxy77[15:8]}; +assign etherbone_rx_depacketizer_source_param_nr = {rhs_slice_proxy79}; +assign etherbone_rx_depacketizer_source_param_pf = {rhs_slice_proxy80}; +assign etherbone_rx_depacketizer_source_param_port_size = {rhs_slice_proxy81[3:0]}; +assign etherbone_rx_depacketizer_source_param_pr = {rhs_slice_proxy82}; +assign etherbone_rx_depacketizer_source_param_version = {rhs_slice_proxy83[3:0]}; +assign etherbone_rx_depacketizer_source_payload_error = etherbone_rx_depacketizer_sink_payload_error; +always @(*) begin + etherbone_rx_depacketizer_sink_ready <= 1'd0; + etherbone_rx_depacketizer_fsm_from_idle_liteethetherbonepacketrx_next_value1 <= 1'd0; + etherbone_rx_depacketizer_fsm_from_idle_liteethetherbonepacketrx_next_value_ce1 <= 1'd0; + etherbone_rx_depacketizer_sr_shift <= 1'd0; + etherbone_rx_depacketizer_source_valid <= 1'd0; + etherbone_rx_depacketizer_sr_shift_leftover <= 1'd0; + etherbone_rx_depacketizer_source_last <= 1'd0; + liteethetherbonepacketrx_liteethetherbonepacketdepacketizer_next_state <= 2'd0; + etherbone_rx_depacketizer_source_payload_data <= 32'd0; + etherbone_rx_depacketizer_count_liteethetherbonepacketrx_next_value0 <= 1'd0; + etherbone_rx_depacketizer_count_liteethetherbonepacketrx_next_value_ce0 <= 1'd0; + liteethetherbonepacketrx_liteethetherbonepacketdepacketizer_next_state <= liteethetherbonepacketrx_liteethetherbonepacketdepacketizer_state; + case (liteethetherbonepacketrx_liteethetherbonepacketdepacketizer_state) + 1'd1: begin + etherbone_rx_depacketizer_sink_ready <= 1'd1; + if (etherbone_rx_depacketizer_sink_valid) begin + etherbone_rx_depacketizer_count_liteethetherbonepacketrx_next_value0 <= (etherbone_rx_depacketizer_count + 1'd1); + etherbone_rx_depacketizer_count_liteethetherbonepacketrx_next_value_ce0 <= 1'd1; + etherbone_rx_depacketizer_sr_shift <= 1'd1; + if ((etherbone_rx_depacketizer_count == 1'd1)) begin + if (1'd0) begin + etherbone_rx_depacketizer_count_liteethetherbonepacketrx_next_value0 <= (etherbone_rx_depacketizer_count + 1'd1); + etherbone_rx_depacketizer_count_liteethetherbonepacketrx_next_value_ce0 <= 1'd1; + liteethetherbonepacketrx_liteethetherbonepacketdepacketizer_next_state <= 2'd2; + end else begin + liteethetherbonepacketrx_liteethetherbonepacketdepacketizer_next_state <= 2'd3; + end + end + end + end + 2'd2: begin + etherbone_rx_depacketizer_source_valid <= (etherbone_rx_depacketizer_sink_valid | etherbone_rx_depacketizer_sink_d_last); + etherbone_rx_depacketizer_source_last <= (etherbone_rx_depacketizer_sink_last | etherbone_rx_depacketizer_sink_d_last); + etherbone_rx_depacketizer_sink_ready <= etherbone_rx_depacketizer_source_ready; + etherbone_rx_depacketizer_source_payload_data <= etherbone_rx_depacketizer_sink_d_payload_data[31:0]; + etherbone_rx_depacketizer_source_payload_data[31] <= etherbone_rx_depacketizer_sink_payload_data; + if (etherbone_rx_depacketizer_fsm_from_idle) begin + etherbone_rx_depacketizer_source_valid <= etherbone_rx_depacketizer_sink_d_last; + etherbone_rx_depacketizer_sink_ready <= 1'd1; + if (etherbone_rx_depacketizer_sink_valid) begin + etherbone_rx_depacketizer_fsm_from_idle_liteethetherbonepacketrx_next_value1 <= 1'd0; + etherbone_rx_depacketizer_fsm_from_idle_liteethetherbonepacketrx_next_value_ce1 <= 1'd1; + etherbone_rx_depacketizer_sr_shift_leftover <= 1'd1; + end + end + if ((etherbone_rx_depacketizer_source_valid & etherbone_rx_depacketizer_source_ready)) begin + if (etherbone_rx_depacketizer_source_last) begin + liteethetherbonepacketrx_liteethetherbonepacketdepacketizer_next_state <= 1'd0; + end + end + end + 2'd3: begin + etherbone_rx_depacketizer_source_valid <= (etherbone_rx_depacketizer_sink_valid | etherbone_rx_depacketizer_sink_d_last); + etherbone_rx_depacketizer_source_last <= (etherbone_rx_depacketizer_sink_last | etherbone_rx_depacketizer_sink_d_last); + etherbone_rx_depacketizer_sink_ready <= etherbone_rx_depacketizer_source_ready; + etherbone_rx_depacketizer_source_payload_data <= etherbone_rx_depacketizer_sink_payload_data; + if ((etherbone_rx_depacketizer_source_valid & etherbone_rx_depacketizer_source_ready)) begin + if (etherbone_rx_depacketizer_source_last) begin + liteethetherbonepacketrx_liteethetherbonepacketdepacketizer_next_state <= 1'd0; + end + end + end + default: begin + etherbone_rx_depacketizer_sink_ready <= 1'd1; + etherbone_rx_depacketizer_count_liteethetherbonepacketrx_next_value0 <= 1'd1; + etherbone_rx_depacketizer_count_liteethetherbonepacketrx_next_value_ce0 <= 1'd1; + if (etherbone_rx_depacketizer_sink_valid) begin + etherbone_rx_depacketizer_sr_shift <= 1'd1; + etherbone_rx_depacketizer_fsm_from_idle_liteethetherbonepacketrx_next_value1 <= 1'd1; + etherbone_rx_depacketizer_fsm_from_idle_liteethetherbonepacketrx_next_value_ce1 <= 1'd1; + if (1'd0) begin + if (1'd0) begin + liteethetherbonepacketrx_liteethetherbonepacketdepacketizer_next_state <= 2'd2; + end else begin + liteethetherbonepacketrx_liteethetherbonepacketdepacketizer_next_state <= 2'd3; + end + end else begin + liteethetherbonepacketrx_liteethetherbonepacketdepacketizer_next_state <= 1'd1; + end + end + end + endcase +end +always @(*) begin + liteethetherbonepacketrx_fsm_next_state <= 2'd0; + etherbone_rx_source_source_valid <= 1'd0; + etherbone_rx_depacketizer_source_ready <= 1'd0; + liteethetherbonepacketrx_fsm_next_state <= liteethetherbonepacketrx_fsm_state; + case (liteethetherbonepacketrx_fsm_state) + 1'd1: begin + if (etherbone_rx_valid) begin + liteethetherbonepacketrx_fsm_next_state <= 2'd2; + end else begin + liteethetherbonepacketrx_fsm_next_state <= 2'd3; + end + end + 2'd2: begin + etherbone_rx_source_source_valid <= etherbone_rx_depacketizer_source_valid; + etherbone_rx_depacketizer_source_ready <= etherbone_rx_source_source_ready; + if (((etherbone_rx_source_source_valid & etherbone_rx_source_source_last) & etherbone_rx_source_source_ready)) begin + liteethetherbonepacketrx_fsm_next_state <= 1'd0; + end + end + 2'd3: begin + etherbone_rx_depacketizer_source_ready <= 1'd1; + if (((etherbone_rx_depacketizer_source_valid & etherbone_rx_depacketizer_source_last) & etherbone_rx_depacketizer_source_ready)) begin + liteethetherbonepacketrx_fsm_next_state <= 1'd0; + end + end + default: begin + etherbone_rx_depacketizer_source_ready <= 1'd1; + if (etherbone_rx_depacketizer_source_valid) begin + etherbone_rx_depacketizer_source_ready <= 1'd0; + liteethetherbonepacketrx_fsm_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + etherbone_probe_source_param_pr <= 1'd0; + etherbone_probe_source_param_src_port <= 16'd0; + etherbone_probe_source_param_dst_port <= 16'd0; + etherbone_probe_source_param_ip_address <= 32'd0; + etherbone_probe_source_param_length <= 16'd0; + etherbone_probe_sink_ready <= 1'd0; + liteethetherboneprobe_next_state <= 1'd0; + etherbone_probe_source_valid <= 1'd0; + etherbone_probe_source_first <= 1'd0; + etherbone_probe_source_last <= 1'd0; + etherbone_probe_source_payload_data <= 32'd0; + etherbone_probe_source_payload_error <= 4'd0; + etherbone_probe_source_param_addr_size <= 4'd0; + etherbone_probe_source_param_nr <= 1'd0; + etherbone_probe_source_param_pf <= 1'd0; + etherbone_probe_source_param_port_size <= 4'd0; + liteethetherboneprobe_next_state <= liteethetherboneprobe_state; + case (liteethetherboneprobe_state) + 1'd1: begin + etherbone_probe_source_valid <= etherbone_probe_sink_valid; + etherbone_probe_sink_ready <= etherbone_probe_source_ready; + etherbone_probe_source_first <= etherbone_probe_sink_first; + etherbone_probe_source_last <= etherbone_probe_sink_last; + etherbone_probe_source_payload_data <= etherbone_probe_sink_payload_data; + etherbone_probe_source_payload_error <= etherbone_probe_sink_payload_error; + etherbone_probe_source_param_addr_size <= etherbone_probe_sink_param_addr_size; + etherbone_probe_source_param_nr <= etherbone_probe_sink_param_nr; + etherbone_probe_source_param_pf <= etherbone_probe_sink_param_pf; + etherbone_probe_source_param_port_size <= etherbone_probe_sink_param_port_size; + etherbone_probe_source_param_pr <= etherbone_probe_sink_param_pr; + etherbone_probe_source_param_src_port <= etherbone_probe_sink_param_src_port; + etherbone_probe_source_param_dst_port <= etherbone_probe_sink_param_dst_port; + etherbone_probe_source_param_ip_address <= etherbone_probe_sink_param_ip_address; + etherbone_probe_source_param_length <= etherbone_probe_sink_param_length; + etherbone_probe_source_param_pf <= 1'd0; + etherbone_probe_source_param_pr <= 1'd1; + if (((etherbone_probe_source_valid & etherbone_probe_source_last) & etherbone_probe_source_ready)) begin + liteethetherboneprobe_next_state <= 1'd0; + end + end + default: begin + etherbone_probe_sink_ready <= 1'd1; + if (etherbone_probe_sink_valid) begin + etherbone_probe_sink_ready <= 1'd0; + liteethetherboneprobe_next_state <= 1'd1; + end + end + endcase +end +assign etherbone_record_depacketizer_sink_valid = etherbone_record_sink_sink_valid; +assign etherbone_record_sink_sink_ready = etherbone_record_depacketizer_sink_ready; +assign etherbone_record_depacketizer_sink_first = etherbone_record_sink_sink_first; +assign etherbone_record_depacketizer_sink_last = etherbone_record_sink_sink_last; +assign etherbone_record_depacketizer_sink_payload_data = etherbone_record_sink_sink_payload_data; +assign etherbone_record_depacketizer_sink_payload_error = etherbone_record_sink_sink_payload_error; +assign etherbone_record_depacketizer_sink_param_addr_size = etherbone_record_sink_sink_param_addr_size; +assign etherbone_record_depacketizer_sink_param_nr = etherbone_record_sink_sink_param_nr; +assign etherbone_record_depacketizer_sink_param_pf = etherbone_record_sink_sink_param_pf; +assign etherbone_record_depacketizer_sink_param_port_size = etherbone_record_sink_sink_param_port_size; +assign etherbone_record_depacketizer_sink_param_pr = etherbone_record_sink_sink_param_pr; +assign etherbone_record_depacketizer_sink_param_src_port = etherbone_record_sink_sink_param_src_port; +assign etherbone_record_depacketizer_sink_param_dst_port = etherbone_record_sink_sink_param_dst_port; +assign etherbone_record_depacketizer_sink_param_ip_address = etherbone_record_sink_sink_param_ip_address; +assign etherbone_record_depacketizer_sink_param_length = etherbone_record_sink_sink_param_length; +assign etherbone_record_receiver_sink_sink_valid = etherbone_record_depacketizer_source_valid; +assign etherbone_record_depacketizer_source_ready = etherbone_record_receiver_sink_sink_ready; +assign etherbone_record_receiver_sink_sink_first = etherbone_record_depacketizer_source_first; +assign etherbone_record_receiver_sink_sink_last = etherbone_record_depacketizer_source_last; +assign etherbone_record_receiver_sink_sink_payload_error = etherbone_record_depacketizer_source_payload_error; +assign etherbone_record_receiver_sink_sink_param_bca = etherbone_record_depacketizer_source_param_bca; +assign etherbone_record_receiver_sink_sink_param_byte_enable = etherbone_record_depacketizer_source_param_byte_enable; +assign etherbone_record_receiver_sink_sink_param_cyc = etherbone_record_depacketizer_source_param_cyc; +assign etherbone_record_receiver_sink_sink_param_rca = etherbone_record_depacketizer_source_param_rca; +assign etherbone_record_receiver_sink_sink_param_rcount = etherbone_record_depacketizer_source_param_rcount; +assign etherbone_record_receiver_sink_sink_param_rff = etherbone_record_depacketizer_source_param_rff; +assign etherbone_record_receiver_sink_sink_param_wca = etherbone_record_depacketizer_source_param_wca; +assign etherbone_record_receiver_sink_sink_param_wcount = etherbone_record_depacketizer_source_param_wcount; +assign etherbone_record_receiver_sink_sink_param_wff = etherbone_record_depacketizer_source_param_wff; +always @(*) begin + etherbone_record_receiver_sink_sink_payload_data <= 32'd0; + etherbone_record_receiver_sink_sink_payload_data <= etherbone_record_depacketizer_source_payload_data; + etherbone_record_receiver_sink_sink_payload_data <= {etherbone_record_depacketizer_source_payload_data[7:0], etherbone_record_depacketizer_source_payload_data[15:8], etherbone_record_depacketizer_source_payload_data[23:16], etherbone_record_depacketizer_source_payload_data[31:24]}; +end +assign etherbone_record_packetizer_sink_valid = etherbone_record_sender_source_source_valid; +assign etherbone_record_sender_source_source_ready = etherbone_record_packetizer_sink_ready; +assign etherbone_record_packetizer_sink_first = etherbone_record_sender_source_source_first; +assign etherbone_record_packetizer_sink_last = etherbone_record_sender_source_source_last; +assign etherbone_record_packetizer_sink_payload_error = etherbone_record_sender_source_source_payload_error; +assign etherbone_record_packetizer_sink_param_bca = etherbone_record_sender_source_source_param_bca; +assign etherbone_record_packetizer_sink_param_byte_enable = etherbone_record_sender_source_source_param_byte_enable; +assign etherbone_record_packetizer_sink_param_cyc = etherbone_record_sender_source_source_param_cyc; +assign etherbone_record_packetizer_sink_param_rca = etherbone_record_sender_source_source_param_rca; +assign etherbone_record_packetizer_sink_param_rcount = etherbone_record_sender_source_source_param_rcount; +assign etherbone_record_packetizer_sink_param_rff = etherbone_record_sender_source_source_param_rff; +assign etherbone_record_packetizer_sink_param_wca = etherbone_record_sender_source_source_param_wca; +assign etherbone_record_packetizer_sink_param_wcount = etherbone_record_sender_source_source_param_wcount; +assign etherbone_record_packetizer_sink_param_wff = etherbone_record_sender_source_source_param_wff; +assign etherbone_record_source_source_valid = etherbone_record_packetizer_source_valid; +assign etherbone_record_packetizer_source_ready = etherbone_record_source_source_ready; +assign etherbone_record_source_source_first = etherbone_record_packetizer_source_first; +assign etherbone_record_source_source_last = etherbone_record_packetizer_source_last; +assign etherbone_record_source_source_payload_data = etherbone_record_packetizer_source_payload_data; +assign etherbone_record_source_source_payload_error = etherbone_record_packetizer_source_payload_error; +assign etherbone_record_source_source_param_addr_size = etherbone_record_packetizer_source_param_addr_size; +assign etherbone_record_source_source_param_nr = etherbone_record_packetizer_source_param_nr; +assign etherbone_record_source_source_param_pf = etherbone_record_packetizer_source_param_pf; +assign etherbone_record_source_source_param_port_size = etherbone_record_packetizer_source_param_port_size; +assign etherbone_record_source_source_param_pr = etherbone_record_packetizer_source_param_pr; +assign etherbone_record_source_source_param_src_port = etherbone_record_packetizer_source_param_src_port; +assign etherbone_record_source_source_param_dst_port = etherbone_record_packetizer_source_param_dst_port; +always @(*) begin + etherbone_record_source_source_param_length <= 16'd0; + etherbone_record_source_source_param_length <= etherbone_record_packetizer_source_param_length; + etherbone_record_source_source_param_length <= ((((3'd4 + ((etherbone_record_sender_source_source_param_wcount != 1'd0) * 3'd4)) + (etherbone_record_sender_source_source_param_wcount * 3'd4)) + ((etherbone_record_sender_source_source_param_rcount != 1'd0) * 3'd4)) + (etherbone_record_sender_source_source_param_rcount * 3'd4)); +end +always @(*) begin + etherbone_record_source_source_param_ip_address <= 32'd0; + etherbone_record_source_source_param_ip_address <= etherbone_record_packetizer_source_param_ip_address; + etherbone_record_source_source_param_ip_address <= etherbone_record_last_ip_address; +end +always @(*) begin + etherbone_record_packetizer_sink_payload_data <= 32'd0; + etherbone_record_packetizer_sink_payload_data <= etherbone_record_sender_source_source_payload_data; + etherbone_record_packetizer_sink_payload_data <= {etherbone_record_sender_source_source_payload_data[7:0], etherbone_record_sender_source_source_payload_data[15:8], etherbone_record_sender_source_source_payload_data[23:16], etherbone_record_sender_source_source_payload_data[31:24]}; +end +assign etherbone_record_depacketizer_header = etherbone_record_depacketizer_sr; +assign etherbone_record_depacketizer_source_param_bca = {rhs_slice_proxy84}; +assign etherbone_record_depacketizer_source_param_byte_enable = {rhs_slice_proxy85[7:0]}; +assign etherbone_record_depacketizer_source_param_cyc = {rhs_slice_proxy86}; +assign etherbone_record_depacketizer_source_param_rca = {rhs_slice_proxy87}; +assign etherbone_record_depacketizer_source_param_rcount = {rhs_slice_proxy88[7:0]}; +assign etherbone_record_depacketizer_source_param_rff = {rhs_slice_proxy89}; +assign etherbone_record_depacketizer_source_param_wca = {rhs_slice_proxy90}; +assign etherbone_record_depacketizer_source_param_wcount = {rhs_slice_proxy91[7:0]}; +assign etherbone_record_depacketizer_source_param_wff = {rhs_slice_proxy92}; +assign etherbone_record_depacketizer_source_payload_error = etherbone_record_depacketizer_sink_payload_error; +always @(*) begin + liteethetherbonerecorddepacketizer_next_state <= 2'd0; + etherbone_record_depacketizer_count_liteethetherbonerecorddepacketizer_next_value0 <= 1'd0; + etherbone_record_depacketizer_count_liteethetherbonerecorddepacketizer_next_value_ce0 <= 1'd0; + etherbone_record_depacketizer_source_valid <= 1'd0; + etherbone_record_depacketizer_sr_shift <= 1'd0; + etherbone_record_depacketizer_fsm_from_idle_liteethetherbonerecorddepacketizer_next_value1 <= 1'd0; + etherbone_record_depacketizer_sink_ready <= 1'd0; + etherbone_record_depacketizer_fsm_from_idle_liteethetherbonerecorddepacketizer_next_value_ce1 <= 1'd0; + etherbone_record_depacketizer_source_last <= 1'd0; + etherbone_record_depacketizer_source_payload_data <= 32'd0; + etherbone_record_depacketizer_sr_shift_leftover <= 1'd0; + liteethetherbonerecorddepacketizer_next_state <= liteethetherbonerecorddepacketizer_state; + case (liteethetherbonerecorddepacketizer_state) + 1'd1: begin + etherbone_record_depacketizer_sink_ready <= 1'd1; + if (etherbone_record_depacketizer_sink_valid) begin + etherbone_record_depacketizer_count_liteethetherbonerecorddepacketizer_next_value0 <= (etherbone_record_depacketizer_count + 1'd1); + etherbone_record_depacketizer_count_liteethetherbonerecorddepacketizer_next_value_ce0 <= 1'd1; + etherbone_record_depacketizer_sr_shift <= 1'd1; + if ((etherbone_record_depacketizer_count == 1'd0)) begin + if (1'd0) begin + etherbone_record_depacketizer_count_liteethetherbonerecorddepacketizer_next_value0 <= (etherbone_record_depacketizer_count + 1'd1); + etherbone_record_depacketizer_count_liteethetherbonerecorddepacketizer_next_value_ce0 <= 1'd1; + liteethetherbonerecorddepacketizer_next_state <= 2'd2; + end else begin + liteethetherbonerecorddepacketizer_next_state <= 2'd3; + end + end + end + end + 2'd2: begin + etherbone_record_depacketizer_source_valid <= (etherbone_record_depacketizer_sink_valid | etherbone_record_depacketizer_sink_d_last); + etherbone_record_depacketizer_source_last <= (etherbone_record_depacketizer_sink_last | etherbone_record_depacketizer_sink_d_last); + etherbone_record_depacketizer_sink_ready <= etherbone_record_depacketizer_source_ready; + etherbone_record_depacketizer_source_payload_data <= etherbone_record_depacketizer_sink_d_payload_data[31:0]; + etherbone_record_depacketizer_source_payload_data[31] <= etherbone_record_depacketizer_sink_payload_data; + if (etherbone_record_depacketizer_fsm_from_idle) begin + etherbone_record_depacketizer_source_valid <= etherbone_record_depacketizer_sink_d_last; + etherbone_record_depacketizer_sink_ready <= 1'd1; + if (etherbone_record_depacketizer_sink_valid) begin + etherbone_record_depacketizer_fsm_from_idle_liteethetherbonerecorddepacketizer_next_value1 <= 1'd0; + etherbone_record_depacketizer_fsm_from_idle_liteethetherbonerecorddepacketizer_next_value_ce1 <= 1'd1; + etherbone_record_depacketizer_sr_shift_leftover <= 1'd1; + end + end + if ((etherbone_record_depacketizer_source_valid & etherbone_record_depacketizer_source_ready)) begin + if (etherbone_record_depacketizer_source_last) begin + liteethetherbonerecorddepacketizer_next_state <= 1'd0; + end + end + end + 2'd3: begin + etherbone_record_depacketizer_source_valid <= (etherbone_record_depacketizer_sink_valid | etherbone_record_depacketizer_sink_d_last); + etherbone_record_depacketizer_source_last <= (etherbone_record_depacketizer_sink_last | etherbone_record_depacketizer_sink_d_last); + etherbone_record_depacketizer_sink_ready <= etherbone_record_depacketizer_source_ready; + etherbone_record_depacketizer_source_payload_data <= etherbone_record_depacketizer_sink_payload_data; + if ((etherbone_record_depacketizer_source_valid & etherbone_record_depacketizer_source_ready)) begin + if (etherbone_record_depacketizer_source_last) begin + liteethetherbonerecorddepacketizer_next_state <= 1'd0; + end + end + end + default: begin + etherbone_record_depacketizer_sink_ready <= 1'd1; + etherbone_record_depacketizer_count_liteethetherbonerecorddepacketizer_next_value0 <= 1'd1; + etherbone_record_depacketizer_count_liteethetherbonerecorddepacketizer_next_value_ce0 <= 1'd1; + if (etherbone_record_depacketizer_sink_valid) begin + etherbone_record_depacketizer_sr_shift <= 1'd1; + etherbone_record_depacketizer_fsm_from_idle_liteethetherbonerecorddepacketizer_next_value1 <= 1'd1; + etherbone_record_depacketizer_fsm_from_idle_liteethetherbonerecorddepacketizer_next_value_ce1 <= 1'd1; + if (1'd1) begin + if (1'd0) begin + liteethetherbonerecorddepacketizer_next_state <= 2'd2; + end else begin + liteethetherbonerecorddepacketizer_next_state <= 2'd3; + end + end else begin + liteethetherbonerecorddepacketizer_next_state <= 1'd1; + end + end + end + endcase +end +assign etherbone_record_receiver_fifo_sink_valid = etherbone_record_receiver_sink_sink_valid; +assign etherbone_record_receiver_sink_sink_ready = etherbone_record_receiver_fifo_sink_ready; +assign etherbone_record_receiver_fifo_sink_first = etherbone_record_receiver_sink_sink_first; +assign etherbone_record_receiver_fifo_sink_last = etherbone_record_receiver_sink_sink_last; +assign etherbone_record_receiver_fifo_sink_payload_data = etherbone_record_receiver_sink_sink_payload_data; +assign etherbone_record_receiver_fifo_sink_payload_error = etherbone_record_receiver_sink_sink_payload_error; +assign etherbone_record_receiver_fifo_sink_param_bca = etherbone_record_receiver_sink_sink_param_bca; +assign etherbone_record_receiver_fifo_sink_param_byte_enable = etherbone_record_receiver_sink_sink_param_byte_enable; +assign etherbone_record_receiver_fifo_sink_param_cyc = etherbone_record_receiver_sink_sink_param_cyc; +assign etherbone_record_receiver_fifo_sink_param_rca = etherbone_record_receiver_sink_sink_param_rca; +assign etherbone_record_receiver_fifo_sink_param_rcount = etherbone_record_receiver_sink_sink_param_rcount; +assign etherbone_record_receiver_fifo_sink_param_rff = etherbone_record_receiver_sink_sink_param_rff; +assign etherbone_record_receiver_fifo_sink_param_wca = etherbone_record_receiver_sink_sink_param_wca; +assign etherbone_record_receiver_fifo_sink_param_wcount = etherbone_record_receiver_sink_sink_param_wcount; +assign etherbone_record_receiver_fifo_sink_param_wff = etherbone_record_receiver_sink_sink_param_wff; +assign etherbone_record_receiver_fifo_syncfifo_din = {etherbone_record_receiver_fifo_fifo_in_last, etherbone_record_receiver_fifo_fifo_in_first, etherbone_record_receiver_fifo_fifo_in_param_wff, etherbone_record_receiver_fifo_fifo_in_param_wcount, etherbone_record_receiver_fifo_fifo_in_param_wca, etherbone_record_receiver_fifo_fifo_in_param_rff, etherbone_record_receiver_fifo_fifo_in_param_rcount, etherbone_record_receiver_fifo_fifo_in_param_rca, etherbone_record_receiver_fifo_fifo_in_param_cyc, etherbone_record_receiver_fifo_fifo_in_param_byte_enable, etherbone_record_receiver_fifo_fifo_in_param_bca, etherbone_record_receiver_fifo_fifo_in_payload_error, etherbone_record_receiver_fifo_fifo_in_payload_data}; +assign {etherbone_record_receiver_fifo_fifo_out_last, etherbone_record_receiver_fifo_fifo_out_first, etherbone_record_receiver_fifo_fifo_out_param_wff, etherbone_record_receiver_fifo_fifo_out_param_wcount, etherbone_record_receiver_fifo_fifo_out_param_wca, etherbone_record_receiver_fifo_fifo_out_param_rff, etherbone_record_receiver_fifo_fifo_out_param_rcount, etherbone_record_receiver_fifo_fifo_out_param_rca, etherbone_record_receiver_fifo_fifo_out_param_cyc, etherbone_record_receiver_fifo_fifo_out_param_byte_enable, etherbone_record_receiver_fifo_fifo_out_param_bca, etherbone_record_receiver_fifo_fifo_out_payload_error, etherbone_record_receiver_fifo_fifo_out_payload_data} = etherbone_record_receiver_fifo_syncfifo_dout; +assign etherbone_record_receiver_fifo_sink_ready = etherbone_record_receiver_fifo_syncfifo_writable; +assign etherbone_record_receiver_fifo_syncfifo_we = etherbone_record_receiver_fifo_sink_valid; +assign etherbone_record_receiver_fifo_fifo_in_first = etherbone_record_receiver_fifo_sink_first; +assign etherbone_record_receiver_fifo_fifo_in_last = etherbone_record_receiver_fifo_sink_last; +assign etherbone_record_receiver_fifo_fifo_in_payload_data = etherbone_record_receiver_fifo_sink_payload_data; +assign etherbone_record_receiver_fifo_fifo_in_payload_error = etherbone_record_receiver_fifo_sink_payload_error; +assign etherbone_record_receiver_fifo_fifo_in_param_bca = etherbone_record_receiver_fifo_sink_param_bca; +assign etherbone_record_receiver_fifo_fifo_in_param_byte_enable = etherbone_record_receiver_fifo_sink_param_byte_enable; +assign etherbone_record_receiver_fifo_fifo_in_param_cyc = etherbone_record_receiver_fifo_sink_param_cyc; +assign etherbone_record_receiver_fifo_fifo_in_param_rca = etherbone_record_receiver_fifo_sink_param_rca; +assign etherbone_record_receiver_fifo_fifo_in_param_rcount = etherbone_record_receiver_fifo_sink_param_rcount; +assign etherbone_record_receiver_fifo_fifo_in_param_rff = etherbone_record_receiver_fifo_sink_param_rff; +assign etherbone_record_receiver_fifo_fifo_in_param_wca = etherbone_record_receiver_fifo_sink_param_wca; +assign etherbone_record_receiver_fifo_fifo_in_param_wcount = etherbone_record_receiver_fifo_sink_param_wcount; +assign etherbone_record_receiver_fifo_fifo_in_param_wff = etherbone_record_receiver_fifo_sink_param_wff; +assign etherbone_record_receiver_fifo_source_valid = etherbone_record_receiver_fifo_readable; +assign etherbone_record_receiver_fifo_source_first = etherbone_record_receiver_fifo_fifo_out_first; +assign etherbone_record_receiver_fifo_source_last = etherbone_record_receiver_fifo_fifo_out_last; +assign etherbone_record_receiver_fifo_source_payload_data = etherbone_record_receiver_fifo_fifo_out_payload_data; +assign etherbone_record_receiver_fifo_source_payload_error = etherbone_record_receiver_fifo_fifo_out_payload_error; +assign etherbone_record_receiver_fifo_source_param_bca = etherbone_record_receiver_fifo_fifo_out_param_bca; +assign etherbone_record_receiver_fifo_source_param_byte_enable = etherbone_record_receiver_fifo_fifo_out_param_byte_enable; +assign etherbone_record_receiver_fifo_source_param_cyc = etherbone_record_receiver_fifo_fifo_out_param_cyc; +assign etherbone_record_receiver_fifo_source_param_rca = etherbone_record_receiver_fifo_fifo_out_param_rca; +assign etherbone_record_receiver_fifo_source_param_rcount = etherbone_record_receiver_fifo_fifo_out_param_rcount; +assign etherbone_record_receiver_fifo_source_param_rff = etherbone_record_receiver_fifo_fifo_out_param_rff; +assign etherbone_record_receiver_fifo_source_param_wca = etherbone_record_receiver_fifo_fifo_out_param_wca; +assign etherbone_record_receiver_fifo_source_param_wcount = etherbone_record_receiver_fifo_fifo_out_param_wcount; +assign etherbone_record_receiver_fifo_source_param_wff = etherbone_record_receiver_fifo_fifo_out_param_wff; +assign etherbone_record_receiver_fifo_re = etherbone_record_receiver_fifo_source_ready; +assign etherbone_record_receiver_fifo_syncfifo_re = (etherbone_record_receiver_fifo_syncfifo_readable & ((~etherbone_record_receiver_fifo_readable) | etherbone_record_receiver_fifo_re)); +assign etherbone_record_receiver_fifo_level1 = (etherbone_record_receiver_fifo_level0 + etherbone_record_receiver_fifo_readable); +always @(*) begin + etherbone_record_receiver_fifo_wrport_adr <= 2'd0; + if (etherbone_record_receiver_fifo_replace) begin + etherbone_record_receiver_fifo_wrport_adr <= (etherbone_record_receiver_fifo_produce - 1'd1); + end else begin + etherbone_record_receiver_fifo_wrport_adr <= etherbone_record_receiver_fifo_produce; + end +end +assign etherbone_record_receiver_fifo_wrport_dat_w = etherbone_record_receiver_fifo_syncfifo_din; +assign etherbone_record_receiver_fifo_wrport_we = (etherbone_record_receiver_fifo_syncfifo_we & (etherbone_record_receiver_fifo_syncfifo_writable | etherbone_record_receiver_fifo_replace)); +assign etherbone_record_receiver_fifo_do_read = (etherbone_record_receiver_fifo_syncfifo_readable & etherbone_record_receiver_fifo_syncfifo_re); +assign etherbone_record_receiver_fifo_rdport_adr = etherbone_record_receiver_fifo_consume; +assign etherbone_record_receiver_fifo_syncfifo_dout = etherbone_record_receiver_fifo_rdport_dat_r; +assign etherbone_record_receiver_fifo_rdport_re = etherbone_record_receiver_fifo_do_read; +assign etherbone_record_receiver_fifo_syncfifo_writable = (etherbone_record_receiver_fifo_level0 != 3'd4); +assign etherbone_record_receiver_fifo_syncfifo_readable = (etherbone_record_receiver_fifo_level0 != 1'd0); +always @(*) begin + etherbone_record_receiver_base_addr_update <= 1'd0; + etherbone_record_receiver_source_source_valid <= 1'd0; + etherbone_record_receiver_counter_reset <= 1'd0; + etherbone_record_receiver_counter_ce <= 1'd0; + etherbone_record_receiver_source_source_last <= 1'd0; + etherbone_record_receiver_source_source_payload_addr <= 32'd0; + etherbone_record_receiver_source_source_payload_data <= 32'd0; + etherbone_record_receiver_source_source_param_we <= 1'd0; + liteethetherbonerecordreceiver_next_state <= 2'd0; + etherbone_record_receiver_source_source_param_count <= 8'd0; + etherbone_record_receiver_source_source_param_base_addr <= 32'd0; + etherbone_record_receiver_source_source_param_be <= 4'd0; + etherbone_record_receiver_fifo_source_ready <= 1'd0; + liteethetherbonerecordreceiver_next_state <= liteethetherbonerecordreceiver_state; + case (liteethetherbonerecordreceiver_state) + 1'd1: begin + etherbone_record_receiver_source_source_valid <= etherbone_record_receiver_fifo_source_valid; + etherbone_record_receiver_source_source_last <= (etherbone_record_receiver_counter == (etherbone_record_receiver_fifo_source_param_wcount - 1'd1)); + etherbone_record_receiver_source_source_param_count <= etherbone_record_receiver_fifo_source_param_wcount; + etherbone_record_receiver_source_source_param_be <= etherbone_record_receiver_fifo_source_param_byte_enable; + etherbone_record_receiver_source_source_payload_addr <= (etherbone_record_receiver_base_addr[31:2] + etherbone_record_receiver_counter); + etherbone_record_receiver_source_source_param_we <= 1'd1; + etherbone_record_receiver_source_source_payload_data <= etherbone_record_receiver_fifo_source_payload_data; + etherbone_record_receiver_fifo_source_ready <= etherbone_record_receiver_source_source_ready; + if ((etherbone_record_receiver_source_source_valid & etherbone_record_receiver_source_source_ready)) begin + etherbone_record_receiver_counter_ce <= 1'd1; + if (etherbone_record_receiver_source_source_last) begin + if (etherbone_record_receiver_fifo_source_param_rcount) begin + liteethetherbonerecordreceiver_next_state <= 2'd2; + end else begin + liteethetherbonerecordreceiver_next_state <= 1'd0; + end + end + end + end + 2'd2: begin + etherbone_record_receiver_counter_reset <= 1'd1; + if (etherbone_record_receiver_fifo_source_valid) begin + etherbone_record_receiver_base_addr_update <= 1'd1; + liteethetherbonerecordreceiver_next_state <= 2'd3; + end + end + 2'd3: begin + etherbone_record_receiver_source_source_valid <= etherbone_record_receiver_fifo_source_valid; + etherbone_record_receiver_source_source_last <= (etherbone_record_receiver_counter == (etherbone_record_receiver_fifo_source_param_rcount - 1'd1)); + etherbone_record_receiver_source_source_param_count <= etherbone_record_receiver_fifo_source_param_rcount; + etherbone_record_receiver_source_source_param_base_addr <= etherbone_record_receiver_base_addr; + etherbone_record_receiver_source_source_payload_addr <= etherbone_record_receiver_fifo_source_payload_data[31:2]; + etherbone_record_receiver_fifo_source_ready <= etherbone_record_receiver_source_source_ready; + if ((etherbone_record_receiver_source_source_valid & etherbone_record_receiver_source_source_ready)) begin + etherbone_record_receiver_counter_ce <= 1'd1; + if (etherbone_record_receiver_source_source_last) begin + liteethetherbonerecordreceiver_next_state <= 1'd0; + end + end + end + default: begin + etherbone_record_receiver_fifo_source_ready <= 1'd1; + etherbone_record_receiver_counter_reset <= 1'd1; + if (etherbone_record_receiver_fifo_source_valid) begin + etherbone_record_receiver_base_addr_update <= 1'd1; + if (etherbone_record_receiver_fifo_source_param_wcount) begin + liteethetherbonerecordreceiver_next_state <= 1'd1; + end else begin + if (etherbone_record_receiver_fifo_source_param_rcount) begin + liteethetherbonerecordreceiver_next_state <= 2'd3; + end + end + end + end + endcase +end +assign etherbone_record_sender_fifo_sink_valid = etherbone_record_sender_sink_sink_valid; +assign etherbone_record_sender_sink_sink_ready = etherbone_record_sender_fifo_sink_ready; +assign etherbone_record_sender_fifo_sink_first = etherbone_record_sender_sink_sink_first; +assign etherbone_record_sender_fifo_sink_last = etherbone_record_sender_sink_sink_last; +assign etherbone_record_sender_fifo_sink_payload_addr = etherbone_record_sender_sink_sink_payload_addr; +assign etherbone_record_sender_fifo_sink_payload_data = etherbone_record_sender_sink_sink_payload_data; +assign etherbone_record_sender_fifo_sink_param_we = etherbone_record_sender_sink_sink_param_we; +assign etherbone_record_sender_fifo_sink_param_count = etherbone_record_sender_sink_sink_param_count; +assign etherbone_record_sender_fifo_sink_param_base_addr = etherbone_record_sender_sink_sink_param_base_addr; +assign etherbone_record_sender_fifo_sink_param_be = etherbone_record_sender_sink_sink_param_be; +assign etherbone_record_sender_fifo_syncfifo_din = {etherbone_record_sender_fifo_fifo_in_last, etherbone_record_sender_fifo_fifo_in_first, etherbone_record_sender_fifo_fifo_in_param_be, etherbone_record_sender_fifo_fifo_in_param_base_addr, etherbone_record_sender_fifo_fifo_in_param_count, etherbone_record_sender_fifo_fifo_in_param_we, etherbone_record_sender_fifo_fifo_in_payload_data, etherbone_record_sender_fifo_fifo_in_payload_addr}; +assign {etherbone_record_sender_fifo_fifo_out_last, etherbone_record_sender_fifo_fifo_out_first, etherbone_record_sender_fifo_fifo_out_param_be, etherbone_record_sender_fifo_fifo_out_param_base_addr, etherbone_record_sender_fifo_fifo_out_param_count, etherbone_record_sender_fifo_fifo_out_param_we, etherbone_record_sender_fifo_fifo_out_payload_data, etherbone_record_sender_fifo_fifo_out_payload_addr} = etherbone_record_sender_fifo_syncfifo_dout; +assign etherbone_record_sender_fifo_sink_ready = etherbone_record_sender_fifo_syncfifo_writable; +assign etherbone_record_sender_fifo_syncfifo_we = etherbone_record_sender_fifo_sink_valid; +assign etherbone_record_sender_fifo_fifo_in_first = etherbone_record_sender_fifo_sink_first; +assign etherbone_record_sender_fifo_fifo_in_last = etherbone_record_sender_fifo_sink_last; +assign etherbone_record_sender_fifo_fifo_in_payload_addr = etherbone_record_sender_fifo_sink_payload_addr; +assign etherbone_record_sender_fifo_fifo_in_payload_data = etherbone_record_sender_fifo_sink_payload_data; +assign etherbone_record_sender_fifo_fifo_in_param_we = etherbone_record_sender_fifo_sink_param_we; +assign etherbone_record_sender_fifo_fifo_in_param_count = etherbone_record_sender_fifo_sink_param_count; +assign etherbone_record_sender_fifo_fifo_in_param_base_addr = etherbone_record_sender_fifo_sink_param_base_addr; +assign etherbone_record_sender_fifo_fifo_in_param_be = etherbone_record_sender_fifo_sink_param_be; +assign etherbone_record_sender_fifo_source_valid = etherbone_record_sender_fifo_readable; +assign etherbone_record_sender_fifo_source_first = etherbone_record_sender_fifo_fifo_out_first; +assign etherbone_record_sender_fifo_source_last = etherbone_record_sender_fifo_fifo_out_last; +assign etherbone_record_sender_fifo_source_payload_addr = etherbone_record_sender_fifo_fifo_out_payload_addr; +assign etherbone_record_sender_fifo_source_payload_data = etherbone_record_sender_fifo_fifo_out_payload_data; +assign etherbone_record_sender_fifo_source_param_we = etherbone_record_sender_fifo_fifo_out_param_we; +assign etherbone_record_sender_fifo_source_param_count = etherbone_record_sender_fifo_fifo_out_param_count; +assign etherbone_record_sender_fifo_source_param_base_addr = etherbone_record_sender_fifo_fifo_out_param_base_addr; +assign etherbone_record_sender_fifo_source_param_be = etherbone_record_sender_fifo_fifo_out_param_be; +assign etherbone_record_sender_fifo_re = etherbone_record_sender_fifo_source_ready; +assign etherbone_record_sender_fifo_syncfifo_re = (etherbone_record_sender_fifo_syncfifo_readable & ((~etherbone_record_sender_fifo_readable) | etherbone_record_sender_fifo_re)); +assign etherbone_record_sender_fifo_level1 = (etherbone_record_sender_fifo_level0 + etherbone_record_sender_fifo_readable); +always @(*) begin + etherbone_record_sender_fifo_wrport_adr <= 2'd0; + if (etherbone_record_sender_fifo_replace) begin + etherbone_record_sender_fifo_wrport_adr <= (etherbone_record_sender_fifo_produce - 1'd1); + end else begin + etherbone_record_sender_fifo_wrport_adr <= etherbone_record_sender_fifo_produce; + end +end +assign etherbone_record_sender_fifo_wrport_dat_w = etherbone_record_sender_fifo_syncfifo_din; +assign etherbone_record_sender_fifo_wrport_we = (etherbone_record_sender_fifo_syncfifo_we & (etherbone_record_sender_fifo_syncfifo_writable | etherbone_record_sender_fifo_replace)); +assign etherbone_record_sender_fifo_do_read = (etherbone_record_sender_fifo_syncfifo_readable & etherbone_record_sender_fifo_syncfifo_re); +assign etherbone_record_sender_fifo_rdport_adr = etherbone_record_sender_fifo_consume; +assign etherbone_record_sender_fifo_syncfifo_dout = etherbone_record_sender_fifo_rdport_dat_r; +assign etherbone_record_sender_fifo_rdport_re = etherbone_record_sender_fifo_do_read; +assign etherbone_record_sender_fifo_syncfifo_writable = (etherbone_record_sender_fifo_level0 != 3'd4); +assign etherbone_record_sender_fifo_syncfifo_readable = (etherbone_record_sender_fifo_level0 != 1'd0); +always @(*) begin + etherbone_record_sender_fifo_source_ready <= 1'd0; + etherbone_record_sender_source_source_last <= 1'd0; + etherbone_record_sender_data_sel <= 1'd0; + liteethetherbonerecordsender_next_state <= 2'd0; + etherbone_record_sender_source_source_valid <= 1'd0; + liteethetherbonerecordsender_next_state <= liteethetherbonerecordsender_state; + case (liteethetherbonerecordsender_state) + 1'd1: begin + etherbone_record_sender_source_source_valid <= 1'd1; + etherbone_record_sender_source_source_last <= 1'd0; + if (etherbone_record_sender_source_source_ready) begin + etherbone_record_sender_data_sel <= 1'd1; + liteethetherbonerecordsender_next_state <= 2'd2; + end + end + 2'd2: begin + etherbone_record_sender_source_source_valid <= 1'd1; + etherbone_record_sender_source_source_last <= etherbone_record_sender_fifo_source_last; + etherbone_record_sender_data_sel <= 1'd1; + if ((etherbone_record_sender_source_source_valid & etherbone_record_sender_source_source_ready)) begin + etherbone_record_sender_fifo_source_ready <= 1'd1; + if (etherbone_record_sender_source_source_last) begin + liteethetherbonerecordsender_next_state <= 1'd0; + end + end + end + default: begin + etherbone_record_sender_fifo_source_ready <= 1'd1; + if (etherbone_record_sender_fifo_source_valid) begin + etherbone_record_sender_fifo_source_ready <= 1'd0; + liteethetherbonerecordsender_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + etherbone_record_packetizer_header <= 32'd0; + etherbone_record_packetizer_header[0] <= {etherbone_record_packetizer_sink_param_bca}; + etherbone_record_packetizer_header[15:8] <= {etherbone_record_packetizer_sink_param_byte_enable[7:0]}; + etherbone_record_packetizer_header[4] <= {etherbone_record_packetizer_sink_param_cyc}; + etherbone_record_packetizer_header[1] <= {etherbone_record_packetizer_sink_param_rca}; + etherbone_record_packetizer_header[31:24] <= {etherbone_record_packetizer_sink_param_rcount[7:0]}; + etherbone_record_packetizer_header[2] <= {etherbone_record_packetizer_sink_param_rff}; + etherbone_record_packetizer_header[5] <= {etherbone_record_packetizer_sink_param_wca}; + etherbone_record_packetizer_header[23:16] <= {etherbone_record_packetizer_sink_param_wcount[7:0]}; + etherbone_record_packetizer_header[6] <= {etherbone_record_packetizer_sink_param_wff}; +end +assign etherbone_record_packetizer_source_payload_error = etherbone_record_packetizer_sink_payload_error; +always @(*) begin + etherbone_record_packetizer_source_valid <= 1'd0; + etherbone_record_packetizer_fsm_from_idle_liteethetherbonerecordpacketizer_next_value1 <= 1'd0; + etherbone_record_packetizer_sr_load <= 1'd0; + etherbone_record_packetizer_fsm_from_idle_liteethetherbonerecordpacketizer_next_value_ce1 <= 1'd0; + etherbone_record_packetizer_sink_ready <= 1'd0; + etherbone_record_packetizer_sr_shift <= 1'd0; + etherbone_record_packetizer_source_last <= 1'd0; + etherbone_record_packetizer_source_payload_data <= 32'd0; + liteethetherbonerecordpacketizer_next_state <= 2'd0; + etherbone_record_packetizer_count_liteethetherbonerecordpacketizer_next_value0 <= 1'd0; + etherbone_record_packetizer_count_liteethetherbonerecordpacketizer_next_value_ce0 <= 1'd0; + liteethetherbonerecordpacketizer_next_state <= liteethetherbonerecordpacketizer_state; + case (liteethetherbonerecordpacketizer_state) + 1'd1: begin + etherbone_record_packetizer_source_valid <= 1'd1; + etherbone_record_packetizer_source_last <= 1'd0; + etherbone_record_packetizer_source_payload_data <= etherbone_record_packetizer_sr[31]; + if ((etherbone_record_packetizer_source_valid & etherbone_record_packetizer_source_ready)) begin + etherbone_record_packetizer_sr_shift <= 1'd1; + if ((etherbone_record_packetizer_count == 1'd0)) begin + etherbone_record_packetizer_sr_shift <= 1'd0; + if (1'd0) begin + liteethetherbonerecordpacketizer_next_state <= 2'd3; + etherbone_record_packetizer_count_liteethetherbonerecordpacketizer_next_value0 <= (etherbone_record_packetizer_count + 1'd1); + etherbone_record_packetizer_count_liteethetherbonerecordpacketizer_next_value_ce0 <= 1'd1; + end else begin + liteethetherbonerecordpacketizer_next_state <= 2'd2; + end + end else begin + etherbone_record_packetizer_count_liteethetherbonerecordpacketizer_next_value0 <= (etherbone_record_packetizer_count + 1'd1); + etherbone_record_packetizer_count_liteethetherbonerecordpacketizer_next_value_ce0 <= 1'd1; + end + end + end + 2'd2: begin + etherbone_record_packetizer_source_valid <= etherbone_record_packetizer_sink_valid; + etherbone_record_packetizer_source_last <= etherbone_record_packetizer_sink_last; + etherbone_record_packetizer_source_payload_data <= etherbone_record_packetizer_sink_payload_data; + if ((etherbone_record_packetizer_source_valid & etherbone_record_packetizer_source_ready)) begin + etherbone_record_packetizer_sink_ready <= 1'd1; + if (etherbone_record_packetizer_source_last) begin + liteethetherbonerecordpacketizer_next_state <= 1'd0; + end + end + end + 2'd3: begin + etherbone_record_packetizer_source_valid <= (etherbone_record_packetizer_sink_valid | etherbone_record_packetizer_sink_d_last); + etherbone_record_packetizer_source_last <= etherbone_record_packetizer_sink_d_last; + if (etherbone_record_packetizer_fsm_from_idle) begin + etherbone_record_packetizer_source_payload_data[0] <= etherbone_record_packetizer_sr[31]; + end else begin + etherbone_record_packetizer_source_payload_data[0] <= etherbone_record_packetizer_sink_d_payload_data[31]; + end + etherbone_record_packetizer_source_payload_data[31:0] <= etherbone_record_packetizer_sink_payload_data; + if ((etherbone_record_packetizer_source_valid & etherbone_record_packetizer_source_ready)) begin + etherbone_record_packetizer_sink_ready <= (~etherbone_record_packetizer_source_last); + etherbone_record_packetizer_fsm_from_idle_liteethetherbonerecordpacketizer_next_value1 <= 1'd0; + etherbone_record_packetizer_fsm_from_idle_liteethetherbonerecordpacketizer_next_value_ce1 <= 1'd1; + if (etherbone_record_packetizer_source_last) begin + liteethetherbonerecordpacketizer_next_state <= 1'd0; + end + end + end + default: begin + etherbone_record_packetizer_sink_ready <= 1'd1; + etherbone_record_packetizer_count_liteethetherbonerecordpacketizer_next_value0 <= 1'd1; + etherbone_record_packetizer_count_liteethetherbonerecordpacketizer_next_value_ce0 <= 1'd1; + if (etherbone_record_packetizer_sink_valid) begin + etherbone_record_packetizer_sink_ready <= 1'd0; + etherbone_record_packetizer_source_valid <= 1'd1; + etherbone_record_packetizer_source_last <= 1'd0; + etherbone_record_packetizer_source_payload_data <= etherbone_record_packetizer_header[31:0]; + if ((etherbone_record_packetizer_source_valid & etherbone_record_packetizer_source_ready)) begin + etherbone_record_packetizer_sr_load <= 1'd1; + etherbone_record_packetizer_fsm_from_idle_liteethetherbonerecordpacketizer_next_value1 <= 1'd1; + etherbone_record_packetizer_fsm_from_idle_liteethetherbonerecordpacketizer_next_value_ce1 <= 1'd1; + if (1'd1) begin + if (1'd0) begin + liteethetherbonerecordpacketizer_next_state <= 2'd3; + end else begin + liteethetherbonerecordpacketizer_next_state <= 2'd2; + end + end else begin + liteethetherbonerecordpacketizer_next_state <= 1'd1; + end + end + end + end + endcase +end +always @(*) begin + etherbone_dispatcher_sel1 <= 1'd0; + if (etherbone_dispatcher_first) begin + etherbone_dispatcher_sel1 <= etherbone_dispatcher_sel0; + end else begin + etherbone_dispatcher_sel1 <= etherbone_dispatcher_sel_ongoing; + end +end +always @(*) begin + etherbone_probe_sink_valid <= 1'd0; + etherbone_record_sink_sink_valid <= 1'd0; + etherbone_probe_sink_first <= 1'd0; + etherbone_record_sink_sink_first <= 1'd0; + etherbone_probe_sink_last <= 1'd0; + etherbone_record_sink_sink_last <= 1'd0; + etherbone_probe_sink_payload_data <= 32'd0; + etherbone_record_sink_sink_payload_data <= 32'd0; + etherbone_probe_sink_payload_error <= 4'd0; + etherbone_record_sink_sink_payload_error <= 4'd0; + etherbone_probe_sink_param_addr_size <= 4'd0; + etherbone_record_sink_sink_param_addr_size <= 4'd0; + etherbone_probe_sink_param_nr <= 1'd0; + etherbone_record_sink_sink_param_nr <= 1'd0; + etherbone_probe_sink_param_pf <= 1'd0; + etherbone_record_sink_sink_param_pf <= 1'd0; + etherbone_probe_sink_param_port_size <= 4'd0; + etherbone_record_sink_sink_param_port_size <= 4'd0; + etherbone_probe_sink_param_pr <= 1'd0; + etherbone_record_sink_sink_param_pr <= 1'd0; + etherbone_rx_source_source_ready <= 1'd0; + etherbone_record_sink_sink_param_src_port <= 16'd0; + etherbone_probe_sink_param_src_port <= 16'd0; + etherbone_record_sink_sink_param_dst_port <= 16'd0; + etherbone_probe_sink_param_dst_port <= 16'd0; + etherbone_record_sink_sink_param_ip_address <= 32'd0; + etherbone_probe_sink_param_ip_address <= 32'd0; + etherbone_record_sink_sink_param_length <= 16'd0; + etherbone_probe_sink_param_length <= 16'd0; + case (etherbone_dispatcher_sel1) + 1'd0: begin + etherbone_probe_sink_valid <= etherbone_rx_source_source_valid; + etherbone_rx_source_source_ready <= etherbone_probe_sink_ready; + etherbone_probe_sink_first <= etherbone_rx_source_source_first; + etherbone_probe_sink_last <= etherbone_rx_source_source_last; + etherbone_probe_sink_payload_data <= etherbone_rx_source_source_payload_data; + etherbone_probe_sink_payload_error <= etherbone_rx_source_source_payload_error; + etherbone_probe_sink_param_addr_size <= etherbone_rx_source_source_param_addr_size; + etherbone_probe_sink_param_nr <= etherbone_rx_source_source_param_nr; + etherbone_probe_sink_param_pf <= etherbone_rx_source_source_param_pf; + etherbone_probe_sink_param_port_size <= etherbone_rx_source_source_param_port_size; + etherbone_probe_sink_param_pr <= etherbone_rx_source_source_param_pr; + etherbone_probe_sink_param_src_port <= etherbone_rx_source_source_param_src_port; + etherbone_probe_sink_param_dst_port <= etherbone_rx_source_source_param_dst_port; + etherbone_probe_sink_param_ip_address <= etherbone_rx_source_source_param_ip_address; + etherbone_probe_sink_param_length <= etherbone_rx_source_source_param_length; + end + 1'd1: begin + etherbone_record_sink_sink_valid <= etherbone_rx_source_source_valid; + etherbone_rx_source_source_ready <= etherbone_record_sink_sink_ready; + etherbone_record_sink_sink_first <= etherbone_rx_source_source_first; + etherbone_record_sink_sink_last <= etherbone_rx_source_source_last; + etherbone_record_sink_sink_payload_data <= etherbone_rx_source_source_payload_data; + etherbone_record_sink_sink_payload_error <= etherbone_rx_source_source_payload_error; + etherbone_record_sink_sink_param_addr_size <= etherbone_rx_source_source_param_addr_size; + etherbone_record_sink_sink_param_nr <= etherbone_rx_source_source_param_nr; + etherbone_record_sink_sink_param_pf <= etherbone_rx_source_source_param_pf; + etherbone_record_sink_sink_param_port_size <= etherbone_rx_source_source_param_port_size; + etherbone_record_sink_sink_param_pr <= etherbone_rx_source_source_param_pr; + etherbone_record_sink_sink_param_src_port <= etherbone_rx_source_source_param_src_port; + etherbone_record_sink_sink_param_dst_port <= etherbone_rx_source_source_param_dst_port; + etherbone_record_sink_sink_param_ip_address <= etherbone_rx_source_source_param_ip_address; + etherbone_record_sink_sink_param_length <= etherbone_rx_source_source_param_length; + end + default: begin + etherbone_rx_source_source_ready <= 1'd1; + end + endcase +end +always @(*) begin + etherbone_dispatcher_last <= 1'd0; + if (etherbone_rx_source_source_valid) begin + etherbone_dispatcher_last <= (etherbone_rx_source_source_last & etherbone_rx_source_source_ready); + end +end +assign etherbone_dispatcher_ongoing0 = ((etherbone_rx_source_source_valid | etherbone_dispatcher_ongoing1) & (~etherbone_dispatcher_last)); +always @(*) begin + etherbone_request <= 2'd0; + etherbone_request[0] <= etherbone_status0_ongoing0; + etherbone_request[1] <= etherbone_status1_ongoing0; +end +always @(*) begin + etherbone_tx_sink_sink_valid <= 1'd0; + etherbone_tx_sink_sink_first <= 1'd0; + etherbone_tx_sink_sink_last <= 1'd0; + etherbone_tx_sink_sink_payload_data <= 32'd0; + etherbone_tx_sink_sink_payload_error <= 4'd0; + etherbone_tx_sink_sink_param_addr_size <= 4'd0; + etherbone_tx_sink_sink_param_nr <= 1'd0; + etherbone_tx_sink_sink_param_pf <= 1'd0; + etherbone_tx_sink_sink_param_port_size <= 4'd0; + etherbone_tx_sink_sink_param_pr <= 1'd0; + etherbone_tx_sink_sink_param_src_port <= 16'd0; + etherbone_tx_sink_sink_param_dst_port <= 16'd0; + etherbone_tx_sink_sink_param_ip_address <= 32'd0; + etherbone_tx_sink_sink_param_length <= 16'd0; + etherbone_probe_source_ready <= 1'd0; + etherbone_record_source_source_ready <= 1'd0; + case (etherbone_grant) + 1'd0: begin + etherbone_tx_sink_sink_valid <= etherbone_probe_source_valid; + etherbone_probe_source_ready <= etherbone_tx_sink_sink_ready; + etherbone_tx_sink_sink_first <= etherbone_probe_source_first; + etherbone_tx_sink_sink_last <= etherbone_probe_source_last; + etherbone_tx_sink_sink_payload_data <= etherbone_probe_source_payload_data; + etherbone_tx_sink_sink_payload_error <= etherbone_probe_source_payload_error; + etherbone_tx_sink_sink_param_addr_size <= etherbone_probe_source_param_addr_size; + etherbone_tx_sink_sink_param_nr <= etherbone_probe_source_param_nr; + etherbone_tx_sink_sink_param_pf <= etherbone_probe_source_param_pf; + etherbone_tx_sink_sink_param_port_size <= etherbone_probe_source_param_port_size; + etherbone_tx_sink_sink_param_pr <= etherbone_probe_source_param_pr; + etherbone_tx_sink_sink_param_src_port <= etherbone_probe_source_param_src_port; + etherbone_tx_sink_sink_param_dst_port <= etherbone_probe_source_param_dst_port; + etherbone_tx_sink_sink_param_ip_address <= etherbone_probe_source_param_ip_address; + etherbone_tx_sink_sink_param_length <= etherbone_probe_source_param_length; + end + 1'd1: begin + etherbone_tx_sink_sink_valid <= etherbone_record_source_source_valid; + etherbone_record_source_source_ready <= etherbone_tx_sink_sink_ready; + etherbone_tx_sink_sink_first <= etherbone_record_source_source_first; + etherbone_tx_sink_sink_last <= etherbone_record_source_source_last; + etherbone_tx_sink_sink_payload_data <= etherbone_record_source_source_payload_data; + etherbone_tx_sink_sink_payload_error <= etherbone_record_source_source_payload_error; + etherbone_tx_sink_sink_param_addr_size <= etherbone_record_source_source_param_addr_size; + etherbone_tx_sink_sink_param_nr <= etherbone_record_source_source_param_nr; + etherbone_tx_sink_sink_param_pf <= etherbone_record_source_source_param_pf; + etherbone_tx_sink_sink_param_port_size <= etherbone_record_source_source_param_port_size; + etherbone_tx_sink_sink_param_pr <= etherbone_record_source_source_param_pr; + etherbone_tx_sink_sink_param_src_port <= etherbone_record_source_source_param_src_port; + etherbone_tx_sink_sink_param_dst_port <= etherbone_record_source_source_param_dst_port; + etherbone_tx_sink_sink_param_ip_address <= etherbone_record_source_source_param_ip_address; + etherbone_tx_sink_sink_param_length <= etherbone_record_source_source_param_length; + end + endcase +end +always @(*) begin + etherbone_status0_last <= 1'd0; + if (etherbone_probe_source_valid) begin + etherbone_status0_last <= (etherbone_probe_source_last & etherbone_probe_source_ready); + end +end +assign etherbone_status0_ongoing0 = ((etherbone_probe_source_valid | etherbone_status0_ongoing1) & (~etherbone_status0_last)); +always @(*) begin + etherbone_status1_last <= 1'd0; + if (etherbone_record_source_source_valid) begin + etherbone_status1_last <= (etherbone_record_source_source_last & etherbone_record_source_source_ready); + end +end +assign etherbone_status1_ongoing0 = ((etherbone_record_source_source_valid | etherbone_status1_ongoing1) & (~etherbone_status1_last)); +always @(*) begin + etherbone_liteethetherbonewishbonemaster_bus_stb <= 1'd0; + etherbone_liteethetherbonewishbonemaster_source_valid <= 1'd0; + etherbone_liteethetherbonewishbonemaster_bus_we <= 1'd0; + etherbone_liteethetherbonewishbonemaster_source_last <= 1'd0; + liteethetherbonewishbonemaster_next_state <= 2'd0; + etherbone_liteethetherbonewishbonemaster_data_update <= 1'd0; + etherbone_liteethetherbonewishbonemaster_sink_ready <= 1'd0; + etherbone_liteethetherbonewishbonemaster_bus_adr <= 30'd0; + etherbone_liteethetherbonewishbonemaster_bus_dat_w <= 32'd0; + etherbone_liteethetherbonewishbonemaster_bus_sel <= 4'd0; + etherbone_liteethetherbonewishbonemaster_bus_cyc <= 1'd0; + liteethetherbonewishbonemaster_next_state <= liteethetherbonewishbonemaster_state; + case (liteethetherbonewishbonemaster_state) + 1'd1: begin + etherbone_liteethetherbonewishbonemaster_bus_adr <= etherbone_liteethetherbonewishbonemaster_sink_payload_addr; + etherbone_liteethetherbonewishbonemaster_bus_dat_w <= etherbone_liteethetherbonewishbonemaster_sink_payload_data; + etherbone_liteethetherbonewishbonemaster_bus_sel <= etherbone_liteethetherbonewishbonemaster_sink_param_be; + etherbone_liteethetherbonewishbonemaster_bus_stb <= etherbone_liteethetherbonewishbonemaster_sink_valid; + etherbone_liteethetherbonewishbonemaster_bus_we <= 1'd1; + etherbone_liteethetherbonewishbonemaster_bus_cyc <= 1'd1; + if ((etherbone_liteethetherbonewishbonemaster_bus_stb & etherbone_liteethetherbonewishbonemaster_bus_ack)) begin + etherbone_liteethetherbonewishbonemaster_sink_ready <= 1'd1; + if (etherbone_liteethetherbonewishbonemaster_sink_last) begin + liteethetherbonewishbonemaster_next_state <= 1'd0; + end + end + end + 2'd2: begin + etherbone_liteethetherbonewishbonemaster_bus_adr <= etherbone_liteethetherbonewishbonemaster_sink_payload_addr; + etherbone_liteethetherbonewishbonemaster_bus_sel <= etherbone_liteethetherbonewishbonemaster_sink_param_be; + etherbone_liteethetherbonewishbonemaster_bus_stb <= etherbone_liteethetherbonewishbonemaster_sink_valid; + etherbone_liteethetherbonewishbonemaster_bus_cyc <= 1'd1; + if ((etherbone_liteethetherbonewishbonemaster_bus_stb & etherbone_liteethetherbonewishbonemaster_bus_ack)) begin + etherbone_liteethetherbonewishbonemaster_data_update <= 1'd1; + liteethetherbonewishbonemaster_next_state <= 2'd3; + end + end + 2'd3: begin + etherbone_liteethetherbonewishbonemaster_source_valid <= etherbone_liteethetherbonewishbonemaster_sink_valid; + etherbone_liteethetherbonewishbonemaster_source_last <= etherbone_liteethetherbonewishbonemaster_sink_last; + if ((etherbone_liteethetherbonewishbonemaster_source_valid & etherbone_liteethetherbonewishbonemaster_source_ready)) begin + etherbone_liteethetherbonewishbonemaster_sink_ready <= 1'd1; + if (etherbone_liteethetherbonewishbonemaster_source_last) begin + liteethetherbonewishbonemaster_next_state <= 1'd0; + end else begin + liteethetherbonewishbonemaster_next_state <= 2'd2; + end + end + end + default: begin + etherbone_liteethetherbonewishbonemaster_sink_ready <= 1'd1; + if (etherbone_liteethetherbonewishbonemaster_sink_valid) begin + etherbone_liteethetherbonewishbonemaster_sink_ready <= 1'd0; + if (etherbone_liteethetherbonewishbonemaster_sink_param_we) begin + liteethetherbonewishbonemaster_next_state <= 1'd1; + end else begin + liteethetherbonewishbonemaster_next_state <= 2'd2; + end + end + end + endcase +end +assign s7pciephy_pcie_rst_n = pcie_x1_rst_n; +assign s7pciephy_tx_datapath_sink_sink_valid = s7pciephy_sink_sink_valid; +assign s7pciephy_sink_sink_ready = s7pciephy_tx_datapath_sink_sink_ready; +assign s7pciephy_tx_datapath_sink_sink_first = s7pciephy_sink_sink_first; +assign s7pciephy_tx_datapath_sink_sink_last = s7pciephy_sink_sink_last; +assign s7pciephy_tx_datapath_sink_sink_payload_dat = s7pciephy_sink_sink_payload_dat; +assign s7pciephy_tx_datapath_sink_sink_payload_be = s7pciephy_sink_sink_payload_be; +assign s7pciephy_source_source_valid = s7pciephy_rx_datapath_source_source_valid; +assign s7pciephy_rx_datapath_source_source_ready = s7pciephy_source_source_ready; +assign s7pciephy_source_source_first = s7pciephy_rx_datapath_source_source_first; +assign s7pciephy_source_source_last = s7pciephy_rx_datapath_source_source_last; +assign s7pciephy_source_source_payload_dat = s7pciephy_rx_datapath_source_source_payload_dat; +assign s7pciephy_source_source_payload_be = s7pciephy_rx_datapath_source_source_payload_be; +assign s7pciephy_msi_cdc_sink_valid = s7pciephy_msi_valid; +assign s7pciephy_msi_ready = s7pciephy_msi_cdc_sink_ready; +assign s7pciephy_msi_cdc_sink_first = s7pciephy_msi_first; +assign s7pciephy_msi_cdc_sink_last = s7pciephy_msi_last; +assign s7pciephy_msi_cdc_sink_payload_dat = s7pciephy_msi_payload_dat; +assign s7pciephy_rx_datapath_sink_sink_first = 1'd0; +assign s7pciephy_rx_datapath_sink_sink_last = s7pciephy_m_axis_rx_tlast; +assign s7pciephy_tx_datapath_pipe_valid_sink_valid = s7pciephy_tx_datapath_sink_sink_valid; +assign s7pciephy_tx_datapath_sink_sink_ready = s7pciephy_tx_datapath_pipe_valid_sink_ready; +assign s7pciephy_tx_datapath_pipe_valid_sink_first = s7pciephy_tx_datapath_sink_sink_first; +assign s7pciephy_tx_datapath_pipe_valid_sink_last = s7pciephy_tx_datapath_sink_sink_last; +assign s7pciephy_tx_datapath_pipe_valid_sink_payload_dat = s7pciephy_tx_datapath_sink_sink_payload_dat; +assign s7pciephy_tx_datapath_pipe_valid_sink_payload_be = s7pciephy_tx_datapath_sink_sink_payload_be; +assign s7pciephy_tx_datapath_cdc_sink_valid = s7pciephy_tx_datapath_pipe_valid_source_valid; +assign s7pciephy_tx_datapath_pipe_valid_source_ready = s7pciephy_tx_datapath_cdc_sink_ready; +assign s7pciephy_tx_datapath_cdc_sink_first = s7pciephy_tx_datapath_pipe_valid_source_first; +assign s7pciephy_tx_datapath_cdc_sink_last = s7pciephy_tx_datapath_pipe_valid_source_last; +assign s7pciephy_tx_datapath_cdc_sink_payload_dat = s7pciephy_tx_datapath_pipe_valid_source_payload_dat; +assign s7pciephy_tx_datapath_cdc_sink_payload_be = s7pciephy_tx_datapath_pipe_valid_source_payload_be; +assign s7pciephy_tx_datapath_converter_sink_valid = s7pciephy_tx_datapath_cdc_source_valid; +assign s7pciephy_tx_datapath_cdc_source_ready = s7pciephy_tx_datapath_converter_sink_ready; +assign s7pciephy_tx_datapath_converter_sink_first = s7pciephy_tx_datapath_cdc_source_first; +assign s7pciephy_tx_datapath_converter_sink_last = s7pciephy_tx_datapath_cdc_source_last; +assign s7pciephy_tx_datapath_converter_sink_payload_dat = s7pciephy_tx_datapath_cdc_source_payload_dat; +assign s7pciephy_tx_datapath_converter_sink_payload_be = s7pciephy_tx_datapath_cdc_source_payload_be; +assign s7pciephy_tx_datapath_pipe_ready_sink_valid = s7pciephy_tx_datapath_converter_source_valid; +assign s7pciephy_tx_datapath_converter_source_ready = s7pciephy_tx_datapath_pipe_ready_sink_ready; +assign s7pciephy_tx_datapath_pipe_ready_sink_first = s7pciephy_tx_datapath_converter_source_first; +assign s7pciephy_tx_datapath_pipe_ready_sink_last = s7pciephy_tx_datapath_converter_source_last; +assign s7pciephy_tx_datapath_pipe_ready_sink_payload_dat = s7pciephy_tx_datapath_converter_source_payload_dat; +assign s7pciephy_tx_datapath_pipe_ready_sink_payload_be = s7pciephy_tx_datapath_converter_source_payload_be; +assign s7pciephy_tx_datapath_source_source_valid = s7pciephy_tx_datapath_pipe_ready_source_valid; +assign s7pciephy_tx_datapath_pipe_ready_source_ready = s7pciephy_tx_datapath_source_source_ready; +assign s7pciephy_tx_datapath_source_source_first = s7pciephy_tx_datapath_pipe_ready_source_first; +assign s7pciephy_tx_datapath_source_source_last = s7pciephy_tx_datapath_pipe_ready_source_last; +assign s7pciephy_tx_datapath_source_source_payload_dat = s7pciephy_tx_datapath_pipe_ready_source_payload_dat; +assign s7pciephy_tx_datapath_source_source_payload_be = s7pciephy_tx_datapath_pipe_ready_source_payload_be; +assign s7pciephy_tx_datapath_pipe_valid_sink_ready = ((~s7pciephy_tx_datapath_pipe_valid_source_valid) | s7pciephy_tx_datapath_pipe_valid_source_ready); +assign s7pciephy_tx_datapath_cdc_asyncfifo_din = {s7pciephy_tx_datapath_cdc_fifo_in_last, s7pciephy_tx_datapath_cdc_fifo_in_first, s7pciephy_tx_datapath_cdc_fifo_in_payload_be, s7pciephy_tx_datapath_cdc_fifo_in_payload_dat}; +assign {s7pciephy_tx_datapath_cdc_fifo_out_last, s7pciephy_tx_datapath_cdc_fifo_out_first, s7pciephy_tx_datapath_cdc_fifo_out_payload_be, s7pciephy_tx_datapath_cdc_fifo_out_payload_dat} = s7pciephy_tx_datapath_cdc_asyncfifo_dout; +assign s7pciephy_tx_datapath_cdc_sink_ready = s7pciephy_tx_datapath_cdc_asyncfifo_writable; +assign s7pciephy_tx_datapath_cdc_asyncfifo_we = s7pciephy_tx_datapath_cdc_sink_valid; +assign s7pciephy_tx_datapath_cdc_fifo_in_first = s7pciephy_tx_datapath_cdc_sink_first; +assign s7pciephy_tx_datapath_cdc_fifo_in_last = s7pciephy_tx_datapath_cdc_sink_last; +assign s7pciephy_tx_datapath_cdc_fifo_in_payload_dat = s7pciephy_tx_datapath_cdc_sink_payload_dat; +assign s7pciephy_tx_datapath_cdc_fifo_in_payload_be = s7pciephy_tx_datapath_cdc_sink_payload_be; +assign s7pciephy_tx_datapath_cdc_source_valid = s7pciephy_tx_datapath_cdc_asyncfifo_readable; +assign s7pciephy_tx_datapath_cdc_source_first = s7pciephy_tx_datapath_cdc_fifo_out_first; +assign s7pciephy_tx_datapath_cdc_source_last = s7pciephy_tx_datapath_cdc_fifo_out_last; +assign s7pciephy_tx_datapath_cdc_source_payload_dat = s7pciephy_tx_datapath_cdc_fifo_out_payload_dat; +assign s7pciephy_tx_datapath_cdc_source_payload_be = s7pciephy_tx_datapath_cdc_fifo_out_payload_be; +assign s7pciephy_tx_datapath_cdc_asyncfifo_re = s7pciephy_tx_datapath_cdc_source_ready; +assign s7pciephy_tx_datapath_cdc_graycounter0_ce = (s7pciephy_tx_datapath_cdc_asyncfifo_writable & s7pciephy_tx_datapath_cdc_asyncfifo_we); +assign s7pciephy_tx_datapath_cdc_graycounter1_ce = (s7pciephy_tx_datapath_cdc_asyncfifo_readable & s7pciephy_tx_datapath_cdc_asyncfifo_re); +assign s7pciephy_tx_datapath_cdc_asyncfifo_writable = (((s7pciephy_tx_datapath_cdc_graycounter0_q[2] == s7pciephy_tx_datapath_cdc_consume_wdomain[2]) | (s7pciephy_tx_datapath_cdc_graycounter0_q[1] == s7pciephy_tx_datapath_cdc_consume_wdomain[1])) | (s7pciephy_tx_datapath_cdc_graycounter0_q[0] != s7pciephy_tx_datapath_cdc_consume_wdomain[0])); +assign s7pciephy_tx_datapath_cdc_asyncfifo_readable = (s7pciephy_tx_datapath_cdc_graycounter1_q != s7pciephy_tx_datapath_cdc_produce_rdomain); +assign s7pciephy_tx_datapath_cdc_wrport_adr = s7pciephy_tx_datapath_cdc_graycounter0_q_binary[1:0]; +assign s7pciephy_tx_datapath_cdc_wrport_dat_w = s7pciephy_tx_datapath_cdc_asyncfifo_din; +assign s7pciephy_tx_datapath_cdc_wrport_we = s7pciephy_tx_datapath_cdc_graycounter0_ce; +assign s7pciephy_tx_datapath_cdc_rdport_adr = s7pciephy_tx_datapath_cdc_graycounter1_q_next_binary[1:0]; +assign s7pciephy_tx_datapath_cdc_asyncfifo_dout = s7pciephy_tx_datapath_cdc_rdport_dat_r; +always @(*) begin + s7pciephy_tx_datapath_cdc_graycounter0_q_next_binary <= 3'd0; + if (s7pciephy_tx_datapath_cdc_graycounter0_ce) begin + s7pciephy_tx_datapath_cdc_graycounter0_q_next_binary <= (s7pciephy_tx_datapath_cdc_graycounter0_q_binary + 1'd1); + end else begin + s7pciephy_tx_datapath_cdc_graycounter0_q_next_binary <= s7pciephy_tx_datapath_cdc_graycounter0_q_binary; + end +end +assign s7pciephy_tx_datapath_cdc_graycounter0_q_next = (s7pciephy_tx_datapath_cdc_graycounter0_q_next_binary ^ s7pciephy_tx_datapath_cdc_graycounter0_q_next_binary[2:1]); +always @(*) begin + s7pciephy_tx_datapath_cdc_graycounter1_q_next_binary <= 3'd0; + if (s7pciephy_tx_datapath_cdc_graycounter1_ce) begin + s7pciephy_tx_datapath_cdc_graycounter1_q_next_binary <= (s7pciephy_tx_datapath_cdc_graycounter1_q_binary + 1'd1); + end else begin + s7pciephy_tx_datapath_cdc_graycounter1_q_next_binary <= s7pciephy_tx_datapath_cdc_graycounter1_q_binary; + end +end +assign s7pciephy_tx_datapath_cdc_graycounter1_q_next = (s7pciephy_tx_datapath_cdc_graycounter1_q_next_binary ^ s7pciephy_tx_datapath_cdc_graycounter1_q_next_binary[2:1]); +assign s7pciephy_tx_datapath_converter_converter_sink_valid = s7pciephy_tx_datapath_converter_sink_valid; +assign s7pciephy_tx_datapath_converter_converter_sink_first = s7pciephy_tx_datapath_converter_sink_first; +assign s7pciephy_tx_datapath_converter_converter_sink_last = s7pciephy_tx_datapath_converter_sink_last; +assign s7pciephy_tx_datapath_converter_sink_ready = s7pciephy_tx_datapath_converter_converter_sink_ready; +assign s7pciephy_tx_datapath_converter_converter_sink_payload_data = {s7pciephy_tx_datapath_converter_sink_payload_be, s7pciephy_tx_datapath_converter_sink_payload_dat}; +assign s7pciephy_tx_datapath_converter_source_valid = s7pciephy_tx_datapath_converter_source_source_valid; +assign s7pciephy_tx_datapath_converter_source_first = s7pciephy_tx_datapath_converter_source_source_first; +assign s7pciephy_tx_datapath_converter_source_last = s7pciephy_tx_datapath_converter_source_source_last; +assign s7pciephy_tx_datapath_converter_source_source_ready = s7pciephy_tx_datapath_converter_source_ready; +assign {s7pciephy_tx_datapath_converter_source_payload_be, s7pciephy_tx_datapath_converter_source_payload_dat} = s7pciephy_tx_datapath_converter_source_source_payload_data; +assign s7pciephy_tx_datapath_converter_source_source_valid = s7pciephy_tx_datapath_converter_converter_source_valid; +assign s7pciephy_tx_datapath_converter_converter_source_ready = s7pciephy_tx_datapath_converter_source_source_ready; +assign s7pciephy_tx_datapath_converter_source_source_first = s7pciephy_tx_datapath_converter_converter_source_first; +assign s7pciephy_tx_datapath_converter_source_source_last = s7pciephy_tx_datapath_converter_converter_source_last; +assign s7pciephy_tx_datapath_converter_source_source_payload_data = s7pciephy_tx_datapath_converter_converter_source_payload_data; +assign s7pciephy_tx_datapath_converter_converter_source_valid = s7pciephy_tx_datapath_converter_converter_sink_valid; +assign s7pciephy_tx_datapath_converter_converter_sink_ready = s7pciephy_tx_datapath_converter_converter_source_ready; +assign s7pciephy_tx_datapath_converter_converter_source_first = s7pciephy_tx_datapath_converter_converter_sink_first; +assign s7pciephy_tx_datapath_converter_converter_source_last = s7pciephy_tx_datapath_converter_converter_sink_last; +assign s7pciephy_tx_datapath_converter_converter_source_payload_data = s7pciephy_tx_datapath_converter_converter_sink_payload_data; +assign s7pciephy_tx_datapath_converter_converter_source_payload_valid_token_count = 1'd1; +assign s7pciephy_tx_datapath_pipe_ready_sink_ready = (~s7pciephy_tx_datapath_pipe_ready_valid); +always @(*) begin + s7pciephy_tx_datapath_pipe_ready_source_payload_be <= 8'd0; + s7pciephy_tx_datapath_pipe_ready_source_valid <= 1'd0; + s7pciephy_tx_datapath_pipe_ready_source_first <= 1'd0; + s7pciephy_tx_datapath_pipe_ready_source_last <= 1'd0; + s7pciephy_tx_datapath_pipe_ready_source_payload_dat <= 64'd0; + if (s7pciephy_tx_datapath_pipe_ready_valid) begin + s7pciephy_tx_datapath_pipe_ready_source_valid <= s7pciephy_tx_datapath_pipe_ready_sink_d_valid; + s7pciephy_tx_datapath_pipe_ready_source_first <= s7pciephy_tx_datapath_pipe_ready_sink_d_first; + s7pciephy_tx_datapath_pipe_ready_source_last <= s7pciephy_tx_datapath_pipe_ready_sink_d_last; + s7pciephy_tx_datapath_pipe_ready_source_payload_dat <= s7pciephy_tx_datapath_pipe_ready_sink_d_payload_dat; + s7pciephy_tx_datapath_pipe_ready_source_payload_be <= s7pciephy_tx_datapath_pipe_ready_sink_d_payload_be; + end else begin + s7pciephy_tx_datapath_pipe_ready_source_valid <= s7pciephy_tx_datapath_pipe_ready_sink_valid; + s7pciephy_tx_datapath_pipe_ready_source_first <= s7pciephy_tx_datapath_pipe_ready_sink_first; + s7pciephy_tx_datapath_pipe_ready_source_last <= s7pciephy_tx_datapath_pipe_ready_sink_last; + s7pciephy_tx_datapath_pipe_ready_source_payload_dat <= s7pciephy_tx_datapath_pipe_ready_sink_payload_dat; + s7pciephy_tx_datapath_pipe_ready_source_payload_be <= s7pciephy_tx_datapath_pipe_ready_sink_payload_be; + end +end +assign s7pciephy_rx_datapath_pipe_ready_sink_valid = s7pciephy_rx_datapath_sink_sink_valid; +assign s7pciephy_rx_datapath_sink_sink_ready = s7pciephy_rx_datapath_pipe_ready_sink_ready; +assign s7pciephy_rx_datapath_pipe_ready_sink_first = s7pciephy_rx_datapath_sink_sink_first; +assign s7pciephy_rx_datapath_pipe_ready_sink_last = s7pciephy_rx_datapath_sink_sink_last; +assign s7pciephy_rx_datapath_pipe_ready_sink_payload_dat = s7pciephy_rx_datapath_sink_sink_payload_dat; +assign s7pciephy_rx_datapath_pipe_ready_sink_payload_be = s7pciephy_rx_datapath_sink_sink_payload_be; +assign s7pciephy_rx_datapath_converter_sink_valid = s7pciephy_rx_datapath_pipe_ready_source_valid; +assign s7pciephy_rx_datapath_pipe_ready_source_ready = s7pciephy_rx_datapath_converter_sink_ready; +assign s7pciephy_rx_datapath_converter_sink_first = s7pciephy_rx_datapath_pipe_ready_source_first; +assign s7pciephy_rx_datapath_converter_sink_last = s7pciephy_rx_datapath_pipe_ready_source_last; +assign s7pciephy_rx_datapath_converter_sink_payload_dat = s7pciephy_rx_datapath_pipe_ready_source_payload_dat; +assign s7pciephy_rx_datapath_converter_sink_payload_be = s7pciephy_rx_datapath_pipe_ready_source_payload_be; +assign s7pciephy_rx_datapath_cdc_sink_valid = s7pciephy_rx_datapath_converter_source_valid; +assign s7pciephy_rx_datapath_converter_source_ready = s7pciephy_rx_datapath_cdc_sink_ready; +assign s7pciephy_rx_datapath_cdc_sink_first = s7pciephy_rx_datapath_converter_source_first; +assign s7pciephy_rx_datapath_cdc_sink_last = s7pciephy_rx_datapath_converter_source_last; +assign s7pciephy_rx_datapath_cdc_sink_payload_dat = s7pciephy_rx_datapath_converter_source_payload_dat; +assign s7pciephy_rx_datapath_cdc_sink_payload_be = s7pciephy_rx_datapath_converter_source_payload_be; +assign s7pciephy_rx_datapath_pipe_valid_sink_valid = s7pciephy_rx_datapath_cdc_source_valid; +assign s7pciephy_rx_datapath_cdc_source_ready = s7pciephy_rx_datapath_pipe_valid_sink_ready; +assign s7pciephy_rx_datapath_pipe_valid_sink_first = s7pciephy_rx_datapath_cdc_source_first; +assign s7pciephy_rx_datapath_pipe_valid_sink_last = s7pciephy_rx_datapath_cdc_source_last; +assign s7pciephy_rx_datapath_pipe_valid_sink_payload_dat = s7pciephy_rx_datapath_cdc_source_payload_dat; +assign s7pciephy_rx_datapath_pipe_valid_sink_payload_be = s7pciephy_rx_datapath_cdc_source_payload_be; +assign s7pciephy_rx_datapath_source_source_valid = s7pciephy_rx_datapath_pipe_valid_source_valid; +assign s7pciephy_rx_datapath_pipe_valid_source_ready = s7pciephy_rx_datapath_source_source_ready; +assign s7pciephy_rx_datapath_source_source_first = s7pciephy_rx_datapath_pipe_valid_source_first; +assign s7pciephy_rx_datapath_source_source_last = s7pciephy_rx_datapath_pipe_valid_source_last; +assign s7pciephy_rx_datapath_source_source_payload_dat = s7pciephy_rx_datapath_pipe_valid_source_payload_dat; +assign s7pciephy_rx_datapath_source_source_payload_be = s7pciephy_rx_datapath_pipe_valid_source_payload_be; +assign s7pciephy_rx_datapath_pipe_ready_sink_ready = (~s7pciephy_rx_datapath_pipe_ready_valid); +always @(*) begin + s7pciephy_rx_datapath_pipe_ready_source_first <= 1'd0; + s7pciephy_rx_datapath_pipe_ready_source_last <= 1'd0; + s7pciephy_rx_datapath_pipe_ready_source_payload_dat <= 64'd0; + s7pciephy_rx_datapath_pipe_ready_source_payload_be <= 8'd0; + s7pciephy_rx_datapath_pipe_ready_source_valid <= 1'd0; + if (s7pciephy_rx_datapath_pipe_ready_valid) begin + s7pciephy_rx_datapath_pipe_ready_source_valid <= s7pciephy_rx_datapath_pipe_ready_sink_d_valid; + s7pciephy_rx_datapath_pipe_ready_source_first <= s7pciephy_rx_datapath_pipe_ready_sink_d_first; + s7pciephy_rx_datapath_pipe_ready_source_last <= s7pciephy_rx_datapath_pipe_ready_sink_d_last; + s7pciephy_rx_datapath_pipe_ready_source_payload_dat <= s7pciephy_rx_datapath_pipe_ready_sink_d_payload_dat; + s7pciephy_rx_datapath_pipe_ready_source_payload_be <= s7pciephy_rx_datapath_pipe_ready_sink_d_payload_be; + end else begin + s7pciephy_rx_datapath_pipe_ready_source_valid <= s7pciephy_rx_datapath_pipe_ready_sink_valid; + s7pciephy_rx_datapath_pipe_ready_source_first <= s7pciephy_rx_datapath_pipe_ready_sink_first; + s7pciephy_rx_datapath_pipe_ready_source_last <= s7pciephy_rx_datapath_pipe_ready_sink_last; + s7pciephy_rx_datapath_pipe_ready_source_payload_dat <= s7pciephy_rx_datapath_pipe_ready_sink_payload_dat; + s7pciephy_rx_datapath_pipe_ready_source_payload_be <= s7pciephy_rx_datapath_pipe_ready_sink_payload_be; + end +end +assign s7pciephy_rx_datapath_converter_converter_sink_valid = s7pciephy_rx_datapath_converter_sink_valid; +assign s7pciephy_rx_datapath_converter_converter_sink_first = s7pciephy_rx_datapath_converter_sink_first; +assign s7pciephy_rx_datapath_converter_converter_sink_last = s7pciephy_rx_datapath_converter_sink_last; +assign s7pciephy_rx_datapath_converter_sink_ready = s7pciephy_rx_datapath_converter_converter_sink_ready; +assign s7pciephy_rx_datapath_converter_converter_sink_payload_data = {s7pciephy_rx_datapath_converter_sink_payload_be, s7pciephy_rx_datapath_converter_sink_payload_dat}; +assign s7pciephy_rx_datapath_converter_source_valid = s7pciephy_rx_datapath_converter_source_source_valid; +assign s7pciephy_rx_datapath_converter_source_first = s7pciephy_rx_datapath_converter_source_source_first; +assign s7pciephy_rx_datapath_converter_source_last = s7pciephy_rx_datapath_converter_source_source_last; +assign s7pciephy_rx_datapath_converter_source_source_ready = s7pciephy_rx_datapath_converter_source_ready; +assign {s7pciephy_rx_datapath_converter_source_payload_be, s7pciephy_rx_datapath_converter_source_payload_dat} = s7pciephy_rx_datapath_converter_source_source_payload_data; +assign s7pciephy_rx_datapath_converter_source_source_valid = s7pciephy_rx_datapath_converter_converter_source_valid; +assign s7pciephy_rx_datapath_converter_converter_source_ready = s7pciephy_rx_datapath_converter_source_source_ready; +assign s7pciephy_rx_datapath_converter_source_source_first = s7pciephy_rx_datapath_converter_converter_source_first; +assign s7pciephy_rx_datapath_converter_source_source_last = s7pciephy_rx_datapath_converter_converter_source_last; +assign s7pciephy_rx_datapath_converter_source_source_payload_data = s7pciephy_rx_datapath_converter_converter_source_payload_data; +assign s7pciephy_rx_datapath_converter_converter_source_valid = s7pciephy_rx_datapath_converter_converter_sink_valid; +assign s7pciephy_rx_datapath_converter_converter_sink_ready = s7pciephy_rx_datapath_converter_converter_source_ready; +assign s7pciephy_rx_datapath_converter_converter_source_first = s7pciephy_rx_datapath_converter_converter_sink_first; +assign s7pciephy_rx_datapath_converter_converter_source_last = s7pciephy_rx_datapath_converter_converter_sink_last; +assign s7pciephy_rx_datapath_converter_converter_source_payload_data = s7pciephy_rx_datapath_converter_converter_sink_payload_data; +assign s7pciephy_rx_datapath_converter_converter_source_payload_valid_token_count = 1'd1; +assign s7pciephy_rx_datapath_cdc_asyncfifo_din = {s7pciephy_rx_datapath_cdc_fifo_in_last, s7pciephy_rx_datapath_cdc_fifo_in_first, s7pciephy_rx_datapath_cdc_fifo_in_payload_be, s7pciephy_rx_datapath_cdc_fifo_in_payload_dat}; +assign {s7pciephy_rx_datapath_cdc_fifo_out_last, s7pciephy_rx_datapath_cdc_fifo_out_first, s7pciephy_rx_datapath_cdc_fifo_out_payload_be, s7pciephy_rx_datapath_cdc_fifo_out_payload_dat} = s7pciephy_rx_datapath_cdc_asyncfifo_dout; +assign s7pciephy_rx_datapath_cdc_sink_ready = s7pciephy_rx_datapath_cdc_asyncfifo_writable; +assign s7pciephy_rx_datapath_cdc_asyncfifo_we = s7pciephy_rx_datapath_cdc_sink_valid; +assign s7pciephy_rx_datapath_cdc_fifo_in_first = s7pciephy_rx_datapath_cdc_sink_first; +assign s7pciephy_rx_datapath_cdc_fifo_in_last = s7pciephy_rx_datapath_cdc_sink_last; +assign s7pciephy_rx_datapath_cdc_fifo_in_payload_dat = s7pciephy_rx_datapath_cdc_sink_payload_dat; +assign s7pciephy_rx_datapath_cdc_fifo_in_payload_be = s7pciephy_rx_datapath_cdc_sink_payload_be; +assign s7pciephy_rx_datapath_cdc_source_valid = s7pciephy_rx_datapath_cdc_asyncfifo_readable; +assign s7pciephy_rx_datapath_cdc_source_first = s7pciephy_rx_datapath_cdc_fifo_out_first; +assign s7pciephy_rx_datapath_cdc_source_last = s7pciephy_rx_datapath_cdc_fifo_out_last; +assign s7pciephy_rx_datapath_cdc_source_payload_dat = s7pciephy_rx_datapath_cdc_fifo_out_payload_dat; +assign s7pciephy_rx_datapath_cdc_source_payload_be = s7pciephy_rx_datapath_cdc_fifo_out_payload_be; +assign s7pciephy_rx_datapath_cdc_asyncfifo_re = s7pciephy_rx_datapath_cdc_source_ready; +assign s7pciephy_rx_datapath_cdc_graycounter0_ce = (s7pciephy_rx_datapath_cdc_asyncfifo_writable & s7pciephy_rx_datapath_cdc_asyncfifo_we); +assign s7pciephy_rx_datapath_cdc_graycounter1_ce = (s7pciephy_rx_datapath_cdc_asyncfifo_readable & s7pciephy_rx_datapath_cdc_asyncfifo_re); +assign s7pciephy_rx_datapath_cdc_asyncfifo_writable = (((s7pciephy_rx_datapath_cdc_graycounter0_q[2] == s7pciephy_rx_datapath_cdc_consume_wdomain[2]) | (s7pciephy_rx_datapath_cdc_graycounter0_q[1] == s7pciephy_rx_datapath_cdc_consume_wdomain[1])) | (s7pciephy_rx_datapath_cdc_graycounter0_q[0] != s7pciephy_rx_datapath_cdc_consume_wdomain[0])); +assign s7pciephy_rx_datapath_cdc_asyncfifo_readable = (s7pciephy_rx_datapath_cdc_graycounter1_q != s7pciephy_rx_datapath_cdc_produce_rdomain); +assign s7pciephy_rx_datapath_cdc_wrport_adr = s7pciephy_rx_datapath_cdc_graycounter0_q_binary[1:0]; +assign s7pciephy_rx_datapath_cdc_wrport_dat_w = s7pciephy_rx_datapath_cdc_asyncfifo_din; +assign s7pciephy_rx_datapath_cdc_wrport_we = s7pciephy_rx_datapath_cdc_graycounter0_ce; +assign s7pciephy_rx_datapath_cdc_rdport_adr = s7pciephy_rx_datapath_cdc_graycounter1_q_next_binary[1:0]; +assign s7pciephy_rx_datapath_cdc_asyncfifo_dout = s7pciephy_rx_datapath_cdc_rdport_dat_r; +always @(*) begin + s7pciephy_rx_datapath_cdc_graycounter0_q_next_binary <= 3'd0; + if (s7pciephy_rx_datapath_cdc_graycounter0_ce) begin + s7pciephy_rx_datapath_cdc_graycounter0_q_next_binary <= (s7pciephy_rx_datapath_cdc_graycounter0_q_binary + 1'd1); + end else begin + s7pciephy_rx_datapath_cdc_graycounter0_q_next_binary <= s7pciephy_rx_datapath_cdc_graycounter0_q_binary; + end +end +assign s7pciephy_rx_datapath_cdc_graycounter0_q_next = (s7pciephy_rx_datapath_cdc_graycounter0_q_next_binary ^ s7pciephy_rx_datapath_cdc_graycounter0_q_next_binary[2:1]); +always @(*) begin + s7pciephy_rx_datapath_cdc_graycounter1_q_next_binary <= 3'd0; + if (s7pciephy_rx_datapath_cdc_graycounter1_ce) begin + s7pciephy_rx_datapath_cdc_graycounter1_q_next_binary <= (s7pciephy_rx_datapath_cdc_graycounter1_q_binary + 1'd1); + end else begin + s7pciephy_rx_datapath_cdc_graycounter1_q_next_binary <= s7pciephy_rx_datapath_cdc_graycounter1_q_binary; + end +end +assign s7pciephy_rx_datapath_cdc_graycounter1_q_next = (s7pciephy_rx_datapath_cdc_graycounter1_q_next_binary ^ s7pciephy_rx_datapath_cdc_graycounter1_q_next_binary[2:1]); +assign s7pciephy_rx_datapath_pipe_valid_sink_ready = ((~s7pciephy_rx_datapath_pipe_valid_source_valid) | s7pciephy_rx_datapath_pipe_valid_source_ready); +assign s7pciephy_msi_cdc_asyncfifo_din = {s7pciephy_msi_cdc_fifo_in_last, s7pciephy_msi_cdc_fifo_in_first, s7pciephy_msi_cdc_fifo_in_payload_dat}; +assign {s7pciephy_msi_cdc_fifo_out_last, s7pciephy_msi_cdc_fifo_out_first, s7pciephy_msi_cdc_fifo_out_payload_dat} = s7pciephy_msi_cdc_asyncfifo_dout; +assign s7pciephy_msi_cdc_sink_ready = s7pciephy_msi_cdc_asyncfifo_writable; +assign s7pciephy_msi_cdc_asyncfifo_we = s7pciephy_msi_cdc_sink_valid; +assign s7pciephy_msi_cdc_fifo_in_first = s7pciephy_msi_cdc_sink_first; +assign s7pciephy_msi_cdc_fifo_in_last = s7pciephy_msi_cdc_sink_last; +assign s7pciephy_msi_cdc_fifo_in_payload_dat = s7pciephy_msi_cdc_sink_payload_dat; +assign s7pciephy_msi_cdc_source_valid = s7pciephy_msi_cdc_asyncfifo_readable; +assign s7pciephy_msi_cdc_source_first = s7pciephy_msi_cdc_fifo_out_first; +assign s7pciephy_msi_cdc_source_last = s7pciephy_msi_cdc_fifo_out_last; +assign s7pciephy_msi_cdc_source_payload_dat = s7pciephy_msi_cdc_fifo_out_payload_dat; +assign s7pciephy_msi_cdc_asyncfifo_re = s7pciephy_msi_cdc_source_ready; +assign s7pciephy_msi_cdc_graycounter0_ce = (s7pciephy_msi_cdc_asyncfifo_writable & s7pciephy_msi_cdc_asyncfifo_we); +assign s7pciephy_msi_cdc_graycounter1_ce = (s7pciephy_msi_cdc_asyncfifo_readable & s7pciephy_msi_cdc_asyncfifo_re); +assign s7pciephy_msi_cdc_asyncfifo_writable = (((s7pciephy_msi_cdc_graycounter0_q[2] == s7pciephy_msi_cdc_consume_wdomain[2]) | (s7pciephy_msi_cdc_graycounter0_q[1] == s7pciephy_msi_cdc_consume_wdomain[1])) | (s7pciephy_msi_cdc_graycounter0_q[0] != s7pciephy_msi_cdc_consume_wdomain[0])); +assign s7pciephy_msi_cdc_asyncfifo_readable = (s7pciephy_msi_cdc_graycounter1_q != s7pciephy_msi_cdc_produce_rdomain); +assign s7pciephy_msi_cdc_wrport_adr = s7pciephy_msi_cdc_graycounter0_q_binary[1:0]; +assign s7pciephy_msi_cdc_wrport_dat_w = s7pciephy_msi_cdc_asyncfifo_din; +assign s7pciephy_msi_cdc_wrport_we = s7pciephy_msi_cdc_graycounter0_ce; +assign s7pciephy_msi_cdc_rdport_adr = s7pciephy_msi_cdc_graycounter1_q_next_binary[1:0]; +assign s7pciephy_msi_cdc_asyncfifo_dout = s7pciephy_msi_cdc_rdport_dat_r; +always @(*) begin + s7pciephy_msi_cdc_graycounter0_q_next_binary <= 3'd0; + if (s7pciephy_msi_cdc_graycounter0_ce) begin + s7pciephy_msi_cdc_graycounter0_q_next_binary <= (s7pciephy_msi_cdc_graycounter0_q_binary + 1'd1); + end else begin + s7pciephy_msi_cdc_graycounter0_q_next_binary <= s7pciephy_msi_cdc_graycounter0_q_binary; + end +end +assign s7pciephy_msi_cdc_graycounter0_q_next = (s7pciephy_msi_cdc_graycounter0_q_next_binary ^ s7pciephy_msi_cdc_graycounter0_q_next_binary[2:1]); +always @(*) begin + s7pciephy_msi_cdc_graycounter1_q_next_binary <= 3'd0; + if (s7pciephy_msi_cdc_graycounter1_ce) begin + s7pciephy_msi_cdc_graycounter1_q_next_binary <= (s7pciephy_msi_cdc_graycounter1_q_binary + 1'd1); + end else begin + s7pciephy_msi_cdc_graycounter1_q_next_binary <= s7pciephy_msi_cdc_graycounter1_q_binary; + end +end +assign s7pciephy_msi_cdc_graycounter1_q_next = (s7pciephy_msi_cdc_graycounter1_q_next_binary ^ s7pciephy_msi_cdc_graycounter1_q_next_binary[2:1]); +assign depacketizer_sink_sink_valid = s7pciephy_source_source_valid; +assign s7pciephy_source_source_ready = depacketizer_sink_sink_ready; +assign depacketizer_sink_sink_first = s7pciephy_source_source_first; +assign depacketizer_sink_sink_last = s7pciephy_source_source_last; +assign depacketizer_sink_sink_payload_dat = s7pciephy_source_source_payload_dat; +assign depacketizer_sink_sink_payload_be = s7pciephy_source_source_payload_be; +assign s7pciephy_sink_sink_valid = packetizer_source_source_valid; +assign packetizer_source_source_ready = s7pciephy_sink_sink_ready; +assign s7pciephy_sink_sink_first = packetizer_source_source_first; +assign s7pciephy_sink_sink_last = packetizer_source_source_last; +assign s7pciephy_sink_sink_payload_dat = packetizer_source_source_payload_dat; +assign s7pciephy_sink_sink_payload_be = packetizer_source_source_payload_be; +assign slave_source_valid = depacketizer_req_source_valid; +assign depacketizer_req_source_ready = slave_source_ready; +assign slave_source_first = depacketizer_req_source_first; +assign slave_source_last = depacketizer_req_source_last; +assign slave_source_payload_we = depacketizer_req_source_payload_we; +assign slave_source_payload_adr = depacketizer_req_source_payload_adr; +assign slave_source_payload_len = depacketizer_req_source_payload_len; +assign slave_source_payload_req_id = depacketizer_req_source_payload_req_id; +assign slave_source_payload_tag = depacketizer_req_source_payload_tag; +assign slave_source_payload_dat = depacketizer_req_source_payload_dat; +assign slave_source_payload_channel = depacketizer_req_source_payload_channel; +assign slave_source_payload_user_id = depacketizer_req_source_payload_user_id; +assign packetizer_cmp_sink_valid = slave_sink_valid; +assign slave_sink_ready = packetizer_cmp_sink_ready; +assign packetizer_cmp_sink_first = slave_sink_first; +assign packetizer_cmp_sink_last = slave_sink_last; +assign packetizer_cmp_sink_payload_adr = slave_sink_payload_adr; +assign packetizer_cmp_sink_payload_len = slave_sink_payload_len; +assign packetizer_cmp_sink_payload_end = slave_sink_payload_end; +assign packetizer_cmp_sink_payload_req_id = slave_sink_payload_req_id; +assign packetizer_cmp_sink_payload_cmp_id = slave_sink_payload_cmp_id; +assign packetizer_cmp_sink_payload_err = slave_sink_payload_err; +assign packetizer_cmp_sink_payload_tag = slave_sink_payload_tag; +assign packetizer_cmp_sink_payload_dat = slave_sink_payload_dat; +assign packetizer_cmp_sink_payload_channel = slave_sink_payload_channel; +assign packetizer_cmp_sink_payload_user_id = slave_sink_payload_user_id; +assign packetizer_req_sink_valid = master_sink_valid; +assign master_sink_ready = packetizer_req_sink_ready; +assign packetizer_req_sink_first = master_sink_first; +assign packetizer_req_sink_last = master_sink_last; +assign packetizer_req_sink_payload_we = master_sink_payload_we; +assign packetizer_req_sink_payload_adr = master_sink_payload_adr; +assign packetizer_req_sink_payload_len = master_sink_payload_len; +assign packetizer_req_sink_payload_req_id = master_sink_payload_req_id; +assign packetizer_req_sink_payload_tag = master_sink_payload_tag; +assign packetizer_req_sink_payload_dat = master_sink_payload_dat; +assign packetizer_req_sink_payload_channel = master_sink_payload_channel; +assign packetizer_req_sink_payload_user_id = master_sink_payload_user_id; +assign master_source_valid = depacketizer_cmp_source_valid; +assign depacketizer_cmp_source_ready = master_source_ready; +assign master_source_first = depacketizer_cmp_source_first; +assign master_source_last = depacketizer_cmp_source_last; +assign master_source_payload_adr = depacketizer_cmp_source_payload_adr; +assign master_source_payload_len = depacketizer_cmp_source_payload_len; +assign master_source_payload_end = depacketizer_cmp_source_payload_end; +assign master_source_payload_req_id = depacketizer_cmp_source_payload_req_id; +assign master_source_payload_cmp_id = depacketizer_cmp_source_payload_cmp_id; +assign master_source_payload_err = depacketizer_cmp_source_payload_err; +assign master_source_payload_tag = depacketizer_cmp_source_payload_tag; +assign master_source_payload_dat = depacketizer_cmp_source_payload_dat; +assign master_source_payload_channel = depacketizer_cmp_source_payload_channel; +assign master_source_payload_user_id = depacketizer_cmp_source_payload_user_id; +assign depacketizer_header_extracter_sink_valid = depacketizer_sink_sink_valid; +assign depacketizer_sink_sink_ready = depacketizer_header_extracter_sink_ready; +assign depacketizer_header_extracter_sink_first = depacketizer_sink_sink_first; +assign depacketizer_header_extracter_sink_last = depacketizer_sink_sink_last; +assign depacketizer_header_extracter_sink_payload_dat = depacketizer_sink_sink_payload_dat; +assign depacketizer_header_extracter_sink_payload_be = depacketizer_sink_sink_payload_be; +assign depacketizer_dispatch_source_valid = depacketizer_header_extracter_source_valid; +assign depacketizer_header_extracter_source_ready = depacketizer_dispatch_source_ready; +assign depacketizer_dispatch_source_first = depacketizer_header_extracter_source_first; +assign depacketizer_dispatch_source_last = depacketizer_header_extracter_source_last; +assign depacketizer_dispatch_source_payload_dat = depacketizer_header_extracter_source_payload_dat; +assign depacketizer_dispatch_source_payload_be = depacketizer_header_extracter_source_payload_be; +assign depacketizer_dispatch_source_payload_fmt = depacketizer_header_extracter_source_payload_header[30:29]; +assign depacketizer_dispatch_source_payload_type = depacketizer_header_extracter_source_payload_header[28:24]; +always @(*) begin + depacketizer_dispatcher_sel0 <= 1'd0; + if ((({depacketizer_dispatch_source_payload_fmt, depacketizer_dispatch_source_payload_type} == 1'd0) | ({depacketizer_dispatch_source_payload_fmt, depacketizer_dispatch_source_payload_type} == 7'd64))) begin + depacketizer_dispatcher_sel0 <= 1'd0; + end else begin + if ((({depacketizer_dispatch_source_payload_fmt, depacketizer_dispatch_source_payload_type} == 7'd74) | ({depacketizer_dispatch_source_payload_fmt, depacketizer_dispatch_source_payload_type} == 4'd10))) begin + depacketizer_dispatcher_sel0 <= 1'd1; + end + end +end +assign depacketizer_tlp_req_valid = depacketizer_endpoint0_valid; +assign depacketizer_endpoint0_ready = depacketizer_tlp_req_ready; +assign depacketizer_tlp_req_first = depacketizer_endpoint0_first; +assign depacketizer_tlp_req_last = depacketizer_endpoint0_last; +assign depacketizer_tlp_req_payload_dat = depacketizer_endpoint0_payload_dat; +assign depacketizer_tlp_req_payload_be = depacketizer_endpoint0_payload_be; +assign depacketizer_tlp_req_payload_address = depacketizer_header_extracter_source_payload_header[95:64]; +assign depacketizer_tlp_req_payload_attr = depacketizer_header_extracter_source_payload_header[13:12]; +assign depacketizer_tlp_req_payload_ep = depacketizer_header_extracter_source_payload_header[14]; +assign depacketizer_tlp_req_payload_first_be = depacketizer_header_extracter_source_payload_header[35:32]; +always @(*) begin + depacketizer_tlp_req_payload_fmt <= 2'd0; + depacketizer_tlp_req_payload_fmt <= depacketizer_endpoint0_payload_fmt; + depacketizer_tlp_req_payload_fmt <= depacketizer_header_extracter_source_payload_header[30:29]; +end +assign depacketizer_tlp_req_payload_last_be = depacketizer_header_extracter_source_payload_header[39:36]; +assign depacketizer_tlp_req_payload_length = depacketizer_header_extracter_source_payload_header[9:0]; +assign depacketizer_tlp_req_payload_requester_id = depacketizer_header_extracter_source_payload_header[63:48]; +assign depacketizer_tlp_req_payload_tag = depacketizer_header_extracter_source_payload_header[47:40]; +assign depacketizer_tlp_req_payload_tc = depacketizer_header_extracter_source_payload_header[22:20]; +assign depacketizer_tlp_req_payload_td = depacketizer_header_extracter_source_payload_header[15]; +always @(*) begin + depacketizer_tlp_req_payload_type <= 5'd0; + depacketizer_tlp_req_payload_type <= depacketizer_endpoint0_payload_type; + depacketizer_tlp_req_payload_type <= depacketizer_header_extracter_source_payload_header[28:24]; +end +assign depacketizer_req_source_valid = depacketizer_tlp_req_valid; +assign depacketizer_req_source_payload_we = (depacketizer_tlp_req_valid & ({depacketizer_tlp_req_payload_fmt, depacketizer_tlp_req_payload_type} == 7'd64)); +assign depacketizer_tlp_req_ready = depacketizer_req_source_ready; +assign depacketizer_req_source_first = depacketizer_tlp_req_first; +assign depacketizer_req_source_last = depacketizer_tlp_req_last; +assign depacketizer_req_source_payload_adr = ($signed({1'd0, depacketizer_tlp_req_payload_address}) & -33'd4294836225); +assign depacketizer_req_source_payload_len = depacketizer_tlp_req_payload_length; +assign depacketizer_req_source_payload_req_id = depacketizer_tlp_req_payload_requester_id; +assign depacketizer_req_source_payload_tag = depacketizer_tlp_req_payload_tag; +assign depacketizer_req_source_payload_dat = depacketizer_tlp_req_payload_dat; +assign depacketizer_tlp_cmp_valid = depacketizer_endpoint1_valid; +assign depacketizer_endpoint1_ready = depacketizer_tlp_cmp_ready; +assign depacketizer_tlp_cmp_first = depacketizer_endpoint1_first; +assign depacketizer_tlp_cmp_last = depacketizer_endpoint1_last; +assign depacketizer_tlp_cmp_payload_dat = depacketizer_endpoint1_payload_dat; +assign depacketizer_tlp_cmp_payload_be = depacketizer_endpoint1_payload_be; +assign depacketizer_tlp_cmp_payload_attr = depacketizer_header_extracter_source_payload_header[13:12]; +assign depacketizer_tlp_cmp_payload_bcm = depacketizer_header_extracter_source_payload_header[44]; +assign depacketizer_tlp_cmp_payload_byte_count = depacketizer_header_extracter_source_payload_header[43:32]; +assign depacketizer_tlp_cmp_payload_completer_id = depacketizer_header_extracter_source_payload_header[63:48]; +assign depacketizer_tlp_cmp_payload_ep = depacketizer_header_extracter_source_payload_header[14]; +always @(*) begin + depacketizer_tlp_cmp_payload_fmt <= 2'd0; + depacketizer_tlp_cmp_payload_fmt <= depacketizer_endpoint1_payload_fmt; + depacketizer_tlp_cmp_payload_fmt <= depacketizer_header_extracter_source_payload_header[30:29]; +end +assign depacketizer_tlp_cmp_payload_length = depacketizer_header_extracter_source_payload_header[9:0]; +assign depacketizer_tlp_cmp_payload_lower_address = depacketizer_header_extracter_source_payload_header[70:64]; +assign depacketizer_tlp_cmp_payload_requester_id = depacketizer_header_extracter_source_payload_header[95:80]; +assign depacketizer_tlp_cmp_payload_status = depacketizer_header_extracter_source_payload_header[47:45]; +assign depacketizer_tlp_cmp_payload_tag = depacketizer_header_extracter_source_payload_header[79:72]; +assign depacketizer_tlp_cmp_payload_tc = depacketizer_header_extracter_source_payload_header[22:20]; +assign depacketizer_tlp_cmp_payload_td = depacketizer_header_extracter_source_payload_header[15]; +always @(*) begin + depacketizer_tlp_cmp_payload_type <= 5'd0; + depacketizer_tlp_cmp_payload_type <= depacketizer_endpoint1_payload_type; + depacketizer_tlp_cmp_payload_type <= depacketizer_header_extracter_source_payload_header[28:24]; +end +assign depacketizer_cmp_source_valid = depacketizer_tlp_cmp_valid; +assign depacketizer_tlp_cmp_ready = depacketizer_cmp_source_ready; +assign depacketizer_cmp_source_first = depacketizer_tlp_cmp_first; +assign depacketizer_cmp_source_last = depacketizer_tlp_cmp_last; +assign depacketizer_cmp_source_payload_len = depacketizer_tlp_cmp_payload_length; +assign depacketizer_cmp_source_payload_end = (depacketizer_tlp_cmp_payload_length == depacketizer_tlp_cmp_payload_byte_count[11:2]); +assign depacketizer_cmp_source_payload_adr = depacketizer_tlp_cmp_payload_lower_address; +assign depacketizer_cmp_source_payload_req_id = depacketizer_tlp_cmp_payload_requester_id; +assign depacketizer_cmp_source_payload_cmp_id = depacketizer_tlp_cmp_payload_completer_id; +assign depacketizer_cmp_source_payload_err = (depacketizer_tlp_cmp_payload_status != 1'd0); +assign depacketizer_cmp_source_payload_tag = depacketizer_tlp_cmp_payload_tag; +assign depacketizer_cmp_source_payload_dat = depacketizer_tlp_cmp_payload_dat; +always @(*) begin + depacketizer_header_extracter_source_payload_dat <= 64'd0; + depacketizer_header_extracter_source_payload_dat[31:0] <= {rhs_slice_proxy96[7:0], rhs_slice_proxy95[15:8], rhs_slice_proxy94[23:16], rhs_slice_proxy93[31:24]}; + depacketizer_header_extracter_source_payload_dat[63:32] <= {rhs_slice_proxy100[7:0], rhs_slice_proxy99[15:8], rhs_slice_proxy98[23:16], rhs_slice_proxy97[31:24]}; +end +always @(*) begin + depacketizer_header_extracter_source_payload_be <= 8'd0; + depacketizer_header_extracter_source_payload_be[3:0] <= {rhs_slice_proxy104[0], rhs_slice_proxy103[1], rhs_slice_proxy102[2], rhs_slice_proxy101[3]}; + depacketizer_header_extracter_source_payload_be[7:4] <= {rhs_slice_proxy108[0], rhs_slice_proxy107[1], rhs_slice_proxy106[2], rhs_slice_proxy105[3]}; +end +always @(*) begin + litepcietlpdepacketizer_next_state <= 2'd0; + depacketizer_header_extracter_source_first <= 1'd0; + depacketizer_header_extracter_first_litepcietlpdepacketizer_next_value0 <= 1'd0; + depacketizer_header_extracter_source_last <= 1'd0; + depacketizer_header_extracter_first_litepcietlpdepacketizer_next_value_ce0 <= 1'd0; + depacketizer_header_extracter_last_litepcietlpdepacketizer_next_value1 <= 1'd0; + depacketizer_header_extracter_last_litepcietlpdepacketizer_next_value_ce1 <= 1'd0; + depacketizer_header_extracter_count_litepcietlpdepacketizer_next_value2 <= 1'd0; + depacketizer_header_extracter_count_litepcietlpdepacketizer_next_value_ce2 <= 1'd0; + litepcietlpdepacketizer_next_value0 <= 32'd0; + litepcietlpdepacketizer_next_value_ce0 <= 1'd0; + litepcietlpdepacketizer_next_value1 <= 32'd0; + litepcietlpdepacketizer_next_value_ce1 <= 1'd0; + litepcietlpdepacketizer_next_value2 <= 32'd0; + litepcietlpdepacketizer_next_value_ce2 <= 1'd0; + litepcietlpdepacketizer_next_value3 <= 32'd0; + litepcietlpdepacketizer_next_value_ce3 <= 1'd0; + depacketizer_header_extracter_sink_ready <= 1'd0; + depacketizer_header_extracter_source_valid <= 1'd0; + litepcietlpdepacketizer_next_state <= litepcietlpdepacketizer_state; + case (litepcietlpdepacketizer_state) + 1'd1: begin + depacketizer_header_extracter_sink_ready <= 1'd1; + if (depacketizer_header_extracter_sink_valid) begin + depacketizer_header_extracter_count_litepcietlpdepacketizer_next_value2 <= (depacketizer_header_extracter_count + 1'd1); + depacketizer_header_extracter_count_litepcietlpdepacketizer_next_value_ce2 <= 1'd1; + litepcietlpdepacketizer_next_value0 <= depacketizer_header_extracter_source_payload_header[95:64]; + litepcietlpdepacketizer_next_value_ce0 <= 1'd1; + litepcietlpdepacketizer_next_value1 <= depacketizer_header_extracter_source_payload_header[127:96]; + litepcietlpdepacketizer_next_value_ce1 <= 1'd1; + litepcietlpdepacketizer_next_value2 <= depacketizer_header_extracter_sink_payload_dat[31:0]; + litepcietlpdepacketizer_next_value_ce2 <= 1'd1; + litepcietlpdepacketizer_next_value3 <= depacketizer_header_extracter_sink_payload_dat[63:32]; + litepcietlpdepacketizer_next_value_ce3 <= 1'd1; + if (depacketizer_header_extracter_count) begin + if (depacketizer_header_extracter_sink_last) begin + depacketizer_header_extracter_last_litepcietlpdepacketizer_next_value1 <= 1'd1; + depacketizer_header_extracter_last_litepcietlpdepacketizer_next_value_ce1 <= 1'd1; + end + litepcietlpdepacketizer_next_state <= 2'd2; + end + end + end + 2'd2: begin + depacketizer_header_extracter_source_valid <= (depacketizer_header_extracter_sink_valid | depacketizer_header_extracter_last); + depacketizer_header_extracter_source_first <= depacketizer_header_extracter_first; + depacketizer_header_extracter_source_last <= (depacketizer_header_extracter_sink_last | depacketizer_header_extracter_last); + if ((depacketizer_header_extracter_source_valid & depacketizer_header_extracter_source_ready)) begin + depacketizer_header_extracter_first_litepcietlpdepacketizer_next_value0 <= 1'd0; + depacketizer_header_extracter_first_litepcietlpdepacketizer_next_value_ce0 <= 1'd1; + depacketizer_header_extracter_sink_ready <= (1'd1 & (~depacketizer_header_extracter_last)); + if (depacketizer_header_extracter_source_last) begin + litepcietlpdepacketizer_next_state <= 1'd0; + end + end + end + default: begin + depacketizer_header_extracter_first_litepcietlpdepacketizer_next_value0 <= 1'd1; + depacketizer_header_extracter_first_litepcietlpdepacketizer_next_value_ce0 <= 1'd1; + depacketizer_header_extracter_last_litepcietlpdepacketizer_next_value1 <= 1'd0; + depacketizer_header_extracter_last_litepcietlpdepacketizer_next_value_ce1 <= 1'd1; + depacketizer_header_extracter_count_litepcietlpdepacketizer_next_value2 <= 1'd0; + depacketizer_header_extracter_count_litepcietlpdepacketizer_next_value_ce2 <= 1'd1; + if (depacketizer_header_extracter_sink_valid) begin + litepcietlpdepacketizer_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + depacketizer_dispatcher_sel1 <= 1'd0; + if (depacketizer_dispatcher_first) begin + depacketizer_dispatcher_sel1 <= depacketizer_dispatcher_sel0; + end else begin + depacketizer_dispatcher_sel1 <= depacketizer_dispatcher_sel_ongoing; + end +end +always @(*) begin + depacketizer_endpoint0_payload_dat <= 64'd0; + depacketizer_endpoint0_payload_be <= 8'd0; + depacketizer_endpoint1_valid <= 1'd0; + depacketizer_dispatch_source_ready <= 1'd0; + depacketizer_endpoint1_first <= 1'd0; + depacketizer_endpoint1_last <= 1'd0; + depacketizer_endpoint1_payload_fmt <= 2'd0; + depacketizer_endpoint1_payload_type <= 5'd0; + depacketizer_endpoint1_payload_dat <= 64'd0; + depacketizer_endpoint1_payload_be <= 8'd0; + depacketizer_endpoint0_valid <= 1'd0; + depacketizer_endpoint0_first <= 1'd0; + depacketizer_endpoint0_last <= 1'd0; + depacketizer_endpoint0_payload_fmt <= 2'd0; + depacketizer_endpoint0_payload_type <= 5'd0; + case (depacketizer_dispatcher_sel1) + 1'd0: begin + depacketizer_endpoint0_valid <= depacketizer_dispatch_source_valid; + depacketizer_dispatch_source_ready <= depacketizer_endpoint0_ready; + depacketizer_endpoint0_first <= depacketizer_dispatch_source_first; + depacketizer_endpoint0_last <= depacketizer_dispatch_source_last; + depacketizer_endpoint0_payload_fmt <= depacketizer_dispatch_source_payload_fmt; + depacketizer_endpoint0_payload_type <= depacketizer_dispatch_source_payload_type; + depacketizer_endpoint0_payload_dat <= depacketizer_dispatch_source_payload_dat; + depacketizer_endpoint0_payload_be <= depacketizer_dispatch_source_payload_be; + end + 1'd1: begin + depacketizer_endpoint1_valid <= depacketizer_dispatch_source_valid; + depacketizer_dispatch_source_ready <= depacketizer_endpoint1_ready; + depacketizer_endpoint1_first <= depacketizer_dispatch_source_first; + depacketizer_endpoint1_last <= depacketizer_dispatch_source_last; + depacketizer_endpoint1_payload_fmt <= depacketizer_dispatch_source_payload_fmt; + depacketizer_endpoint1_payload_type <= depacketizer_dispatch_source_payload_type; + depacketizer_endpoint1_payload_dat <= depacketizer_dispatch_source_payload_dat; + depacketizer_endpoint1_payload_be <= depacketizer_dispatch_source_payload_be; + end + default: begin + depacketizer_dispatch_source_ready <= 1'd1; + end + endcase +end +always @(*) begin + depacketizer_dispatcher_last <= 1'd0; + if (depacketizer_dispatch_source_valid) begin + depacketizer_dispatcher_last <= (depacketizer_dispatch_source_last & depacketizer_dispatch_source_ready); + end +end +assign depacketizer_dispatcher_ongoing0 = ((depacketizer_dispatch_source_valid | depacketizer_dispatcher_ongoing1) & (~depacketizer_dispatcher_last)); +assign packetizer_tlp_req_valid = packetizer_req_sink_valid; +assign packetizer_req_sink_ready = packetizer_tlp_req_ready; +assign packetizer_tlp_req_first = packetizer_req_sink_first; +assign packetizer_tlp_req_last = packetizer_req_sink_last; +always @(*) begin + packetizer_tlp_req_payload_type <= 5'd0; + packetizer_tlp_req_payload_fmt <= 2'd0; + if (packetizer_req_sink_payload_we) begin + {packetizer_tlp_req_payload_fmt, packetizer_tlp_req_payload_type} <= 7'd64; + end else begin + {packetizer_tlp_req_payload_fmt, packetizer_tlp_req_payload_type} <= 1'd0; + end +end +assign packetizer_tlp_req_payload_tc = 1'd0; +assign packetizer_tlp_req_payload_td = 1'd0; +assign packetizer_tlp_req_payload_ep = 1'd0; +assign packetizer_tlp_req_payload_attr = 1'd0; +assign packetizer_tlp_req_payload_length = packetizer_req_sink_payload_len; +assign packetizer_tlp_req_payload_requester_id = packetizer_req_sink_payload_req_id; +assign packetizer_tlp_req_payload_tag = packetizer_req_sink_payload_tag; +always @(*) begin + packetizer_tlp_req_payload_last_be <= 4'd0; + if ((packetizer_req_sink_payload_len > 1'd1)) begin + packetizer_tlp_req_payload_last_be <= 4'd15; + end else begin + packetizer_tlp_req_payload_last_be <= 1'd0; + end +end +assign packetizer_tlp_req_payload_first_be = 4'd15; +assign packetizer_tlp_req_payload_address = packetizer_req_sink_payload_adr; +assign packetizer_tlp_req_payload_dat = packetizer_req_sink_payload_dat; +always @(*) begin + packetizer_tlp_req_payload_be <= 8'd0; + if (packetizer_req_sink_payload_we) begin + packetizer_tlp_req_payload_be <= 8'd255; + end else begin + packetizer_tlp_req_payload_be <= 1'd0; + end +end +assign packetizer_tlp_raw_req_valid = packetizer_tlp_req_valid; +assign packetizer_tlp_req_ready = packetizer_tlp_raw_req_ready; +assign packetizer_tlp_raw_req_first = packetizer_tlp_req_first; +assign packetizer_tlp_raw_req_last = packetizer_tlp_req_last; +always @(*) begin + packetizer_tlp_raw_req_payload_header <= 128'd0; + packetizer_tlp_raw_req_payload_header[95:64] <= packetizer_tlp_req_payload_address; + packetizer_tlp_raw_req_payload_header[13:12] <= packetizer_tlp_req_payload_attr; + packetizer_tlp_raw_req_payload_header[14] <= packetizer_tlp_req_payload_ep; + packetizer_tlp_raw_req_payload_header[35:32] <= packetizer_tlp_req_payload_first_be; + packetizer_tlp_raw_req_payload_header[30:29] <= packetizer_tlp_req_payload_fmt; + packetizer_tlp_raw_req_payload_header[39:36] <= packetizer_tlp_req_payload_last_be; + packetizer_tlp_raw_req_payload_header[9:0] <= packetizer_tlp_req_payload_length; + packetizer_tlp_raw_req_payload_header[63:48] <= packetizer_tlp_req_payload_requester_id; + packetizer_tlp_raw_req_payload_header[47:40] <= packetizer_tlp_req_payload_tag; + packetizer_tlp_raw_req_payload_header[22:20] <= packetizer_tlp_req_payload_tc; + packetizer_tlp_raw_req_payload_header[15] <= packetizer_tlp_req_payload_td; + packetizer_tlp_raw_req_payload_header[28:24] <= packetizer_tlp_req_payload_type; +end +assign packetizer_tlp_raw_req_payload_dat = packetizer_tlp_req_payload_dat; +assign packetizer_tlp_raw_req_payload_be = packetizer_tlp_req_payload_be; +assign packetizer_tlp_cmp_valid = packetizer_cmp_sink_valid; +assign packetizer_cmp_sink_ready = packetizer_tlp_cmp_ready; +assign packetizer_tlp_cmp_first = packetizer_cmp_sink_first; +assign packetizer_tlp_cmp_last = packetizer_cmp_sink_last; +assign packetizer_tlp_cmp_payload_tc = 1'd0; +assign packetizer_tlp_cmp_payload_td = 1'd0; +assign packetizer_tlp_cmp_payload_ep = 1'd0; +assign packetizer_tlp_cmp_payload_attr = 1'd0; +assign packetizer_tlp_cmp_payload_length = packetizer_cmp_sink_payload_len; +assign packetizer_tlp_cmp_payload_completer_id = packetizer_cmp_sink_payload_cmp_id; +always @(*) begin + packetizer_tlp_cmp_payload_status <= 3'd0; + packetizer_tlp_cmp_payload_type <= 5'd0; + packetizer_tlp_cmp_payload_fmt <= 2'd0; + if (packetizer_cmp_sink_payload_err) begin + {packetizer_tlp_cmp_payload_fmt, packetizer_tlp_cmp_payload_type} <= 4'd10; + packetizer_tlp_cmp_payload_status <= 1'd1; + end else begin + {packetizer_tlp_cmp_payload_fmt, packetizer_tlp_cmp_payload_type} <= 7'd74; + packetizer_tlp_cmp_payload_status <= 1'd0; + end +end +assign packetizer_tlp_cmp_payload_bcm = 1'd0; +assign packetizer_tlp_cmp_payload_byte_count = (packetizer_cmp_sink_payload_len * 3'd4); +assign packetizer_tlp_cmp_payload_requester_id = packetizer_cmp_sink_payload_req_id; +assign packetizer_tlp_cmp_payload_tag = packetizer_cmp_sink_payload_tag; +assign packetizer_tlp_cmp_payload_lower_address = packetizer_cmp_sink_payload_adr; +assign packetizer_tlp_cmp_payload_dat = packetizer_cmp_sink_payload_dat; +always @(*) begin + packetizer_tlp_cmp_payload_be <= 8'd0; + if ((packetizer_cmp_sink_last & packetizer_cmp_sink_first)) begin + packetizer_tlp_cmp_payload_be <= 4'd15; + end else begin + packetizer_tlp_cmp_payload_be <= 8'd255; + end +end +assign packetizer_tlp_raw_cmp_valid = packetizer_tlp_cmp_valid; +assign packetizer_tlp_cmp_ready = packetizer_tlp_raw_cmp_ready; +assign packetizer_tlp_raw_cmp_first = packetizer_tlp_cmp_first; +assign packetizer_tlp_raw_cmp_last = packetizer_tlp_cmp_last; +always @(*) begin + packetizer_tlp_raw_cmp_payload_header <= 128'd0; + packetizer_tlp_raw_cmp_payload_header[13:12] <= packetizer_tlp_cmp_payload_attr; + packetizer_tlp_raw_cmp_payload_header[44] <= packetizer_tlp_cmp_payload_bcm; + packetizer_tlp_raw_cmp_payload_header[43:32] <= packetizer_tlp_cmp_payload_byte_count; + packetizer_tlp_raw_cmp_payload_header[63:48] <= packetizer_tlp_cmp_payload_completer_id; + packetizer_tlp_raw_cmp_payload_header[14] <= packetizer_tlp_cmp_payload_ep; + packetizer_tlp_raw_cmp_payload_header[30:29] <= packetizer_tlp_cmp_payload_fmt; + packetizer_tlp_raw_cmp_payload_header[9:0] <= packetizer_tlp_cmp_payload_length; + packetizer_tlp_raw_cmp_payload_header[70:64] <= packetizer_tlp_cmp_payload_lower_address; + packetizer_tlp_raw_cmp_payload_header[95:80] <= packetizer_tlp_cmp_payload_requester_id; + packetizer_tlp_raw_cmp_payload_header[47:45] <= packetizer_tlp_cmp_payload_status; + packetizer_tlp_raw_cmp_payload_header[79:72] <= packetizer_tlp_cmp_payload_tag; + packetizer_tlp_raw_cmp_payload_header[22:20] <= packetizer_tlp_cmp_payload_tc; + packetizer_tlp_raw_cmp_payload_header[15] <= packetizer_tlp_cmp_payload_td; + packetizer_tlp_raw_cmp_payload_header[28:24] <= packetizer_tlp_cmp_payload_type; +end +assign packetizer_tlp_raw_cmp_payload_dat = packetizer_tlp_cmp_payload_dat; +assign packetizer_tlp_raw_cmp_payload_be = packetizer_tlp_cmp_payload_be; +assign packetizer_header_inserter_sink_valid = packetizer_tlp_raw_valid; +assign packetizer_tlp_raw_ready = packetizer_header_inserter_sink_ready; +assign packetizer_header_inserter_sink_first = packetizer_tlp_raw_first; +assign packetizer_header_inserter_sink_last = packetizer_tlp_raw_last; +assign packetizer_header_inserter_sink_payload_header = packetizer_tlp_raw_payload_header; +assign packetizer_header_inserter_sink_payload_dat = packetizer_tlp_raw_payload_dat; +assign packetizer_header_inserter_sink_payload_be = packetizer_tlp_raw_payload_be; +assign packetizer_source_source_valid = packetizer_header_inserter_source_valid; +assign packetizer_header_inserter_source_ready = packetizer_source_source_ready; +assign packetizer_source_source_first = packetizer_header_inserter_source_first; +assign packetizer_source_source_last = packetizer_header_inserter_source_last; +assign packetizer_source_source_payload_dat = packetizer_header_inserter_source_payload_dat; +assign packetizer_source_source_payload_be = packetizer_header_inserter_source_payload_be; +always @(*) begin + packetizer_request <= 2'd0; + packetizer_request[0] <= packetizer_status0_ongoing0; + packetizer_request[1] <= packetizer_status1_ongoing0; +end +always @(*) begin + packetizer_tlp_raw_req_ready <= 1'd0; + packetizer_tlp_raw_valid <= 1'd0; + packetizer_tlp_raw_first <= 1'd0; + packetizer_tlp_raw_last <= 1'd0; + packetizer_tlp_raw_cmp_ready <= 1'd0; + packetizer_tlp_raw_payload_header <= 128'd0; + packetizer_tlp_raw_payload_dat <= 64'd0; + packetizer_tlp_raw_payload_be <= 8'd0; + case (packetizer_grant) + 1'd0: begin + packetizer_tlp_raw_valid <= packetizer_tlp_raw_req_valid; + packetizer_tlp_raw_req_ready <= packetizer_tlp_raw_ready; + packetizer_tlp_raw_first <= packetizer_tlp_raw_req_first; + packetizer_tlp_raw_last <= packetizer_tlp_raw_req_last; + packetizer_tlp_raw_payload_header <= packetizer_tlp_raw_req_payload_header; + packetizer_tlp_raw_payload_dat <= packetizer_tlp_raw_req_payload_dat; + packetizer_tlp_raw_payload_be <= packetizer_tlp_raw_req_payload_be; + end + 1'd1: begin + packetizer_tlp_raw_valid <= packetizer_tlp_raw_cmp_valid; + packetizer_tlp_raw_cmp_ready <= packetizer_tlp_raw_ready; + packetizer_tlp_raw_first <= packetizer_tlp_raw_cmp_first; + packetizer_tlp_raw_last <= packetizer_tlp_raw_cmp_last; + packetizer_tlp_raw_payload_header <= packetizer_tlp_raw_cmp_payload_header; + packetizer_tlp_raw_payload_dat <= packetizer_tlp_raw_cmp_payload_dat; + packetizer_tlp_raw_payload_be <= packetizer_tlp_raw_cmp_payload_be; + end + endcase +end +always @(*) begin + packetizer_status0_last <= 1'd0; + if (packetizer_tlp_raw_req_valid) begin + packetizer_status0_last <= (packetizer_tlp_raw_req_last & packetizer_tlp_raw_req_ready); + end +end +assign packetizer_status0_ongoing0 = ((packetizer_tlp_raw_req_valid | packetizer_status0_ongoing1) & (~packetizer_status0_last)); +always @(*) begin + packetizer_status1_last <= 1'd0; + if (packetizer_tlp_raw_cmp_valid) begin + packetizer_status1_last <= (packetizer_tlp_raw_cmp_last & packetizer_tlp_raw_cmp_ready); + end +end +assign packetizer_status1_ongoing0 = ((packetizer_tlp_raw_cmp_valid | packetizer_status1_ongoing1) & (~packetizer_status1_last)); +always @(*) begin + packetizer_header_inserter_source_valid <= 1'd0; + packetizer_header_inserter_source_first <= 1'd0; + packetizer_header_inserter_sink_ready <= 1'd0; + packetizer_header_inserter_source_last <= 1'd0; + packetizer_header_inserter_source_payload_dat <= 64'd0; + packetizer_header_inserter_source_payload_be <= 8'd0; + litepcietlppacketizer_next_state <= 2'd0; + litepcietlppacketizer_next_state <= litepcietlppacketizer_state; + case (litepcietlppacketizer_state) + 1'd1: begin + packetizer_header_inserter_source_valid <= 1'd1; + packetizer_header_inserter_source_last <= packetizer_header_inserter_sink_last; + packetizer_header_inserter_source_payload_dat[31:0] <= packetizer_header_inserter_sink_payload_header[95:64]; + packetizer_header_inserter_source_payload_be[3:0] <= 4'd15; + packetizer_header_inserter_source_payload_dat[63:32] <= {cases_slice_proxy3[7:0], cases_slice_proxy2[15:8], cases_slice_proxy1[23:16], cases_slice_proxy0[31:24]}; + packetizer_header_inserter_source_payload_be[7:4] <= {cases_slice_proxy7[0], cases_slice_proxy6[1], cases_slice_proxy5[2], cases_slice_proxy4[3]}; + if ((packetizer_header_inserter_source_valid & packetizer_header_inserter_source_ready)) begin + packetizer_header_inserter_sink_ready <= 1'd1; + if (packetizer_header_inserter_source_last) begin + litepcietlppacketizer_next_state <= 1'd0; + end else begin + litepcietlppacketizer_next_state <= 2'd2; + end + end + end + 2'd2: begin + packetizer_header_inserter_source_valid <= (packetizer_header_inserter_sink_valid | packetizer_header_inserter_last); + packetizer_header_inserter_source_last <= packetizer_header_inserter_last; + packetizer_header_inserter_source_payload_dat[31:0] <= {cases_slice_proxy11[7:0], cases_slice_proxy10[15:8], cases_slice_proxy9[23:16], cases_slice_proxy8[31:24]}; + packetizer_header_inserter_source_payload_be[3:0] <= 4'd15; + packetizer_header_inserter_source_payload_dat[63:32] <= {cases_slice_proxy15[7:0], cases_slice_proxy14[15:8], cases_slice_proxy13[23:16], cases_slice_proxy12[31:24]}; + if (packetizer_header_inserter_last) begin + packetizer_header_inserter_source_payload_be[7:4] <= 1'd0; + end else begin + packetizer_header_inserter_source_payload_be[7:4] <= 4'd15; + end + if ((packetizer_header_inserter_source_valid & packetizer_header_inserter_source_ready)) begin + packetizer_header_inserter_sink_ready <= (~packetizer_header_inserter_last); + if (packetizer_header_inserter_source_last) begin + litepcietlppacketizer_next_state <= 1'd0; + end + end + end + default: begin + packetizer_header_inserter_sink_ready <= 1'd1; + if (packetizer_header_inserter_sink_first) begin + packetizer_header_inserter_sink_ready <= 1'd0; + packetizer_header_inserter_source_valid <= packetizer_header_inserter_sink_valid; + packetizer_header_inserter_source_first <= packetizer_header_inserter_sink_first; + packetizer_header_inserter_source_last <= 1'd0; + packetizer_header_inserter_source_payload_dat[31:0] <= packetizer_header_inserter_sink_payload_header[31:0]; + packetizer_header_inserter_source_payload_be[3:0] <= 4'd15; + packetizer_header_inserter_source_payload_dat[63:32] <= packetizer_header_inserter_sink_payload_header[63:32]; + packetizer_header_inserter_source_payload_be[7:4] <= 4'd15; + if ((packetizer_header_inserter_source_valid & packetizer_header_inserter_source_ready)) begin + litepcietlppacketizer_next_state <= 1'd1; + end + end + end + endcase +end +assign sel = 1'd1; +always @(*) begin + dispatcher0_sel0 <= 2'd0; + dispatcher0_sel0[0] <= (master_in_source_payload_channel == 1'd1); + dispatcher0_sel0[1] <= (master_in_source_payload_channel == 2'd3); +end +always @(*) begin + dispatcher1_sel0 <= 2'd0; + dispatcher1_sel0[0] <= (source_payload_channel == 1'd0); + dispatcher1_sel0[1] <= (source_payload_channel == 2'd2); +end +assign master_out_source_valid = master_source_valid; +assign master_source_ready = master_out_source_ready; +assign master_out_source_first = master_source_first; +assign master_out_source_last = master_source_last; +assign master_out_source_payload_adr = master_source_payload_adr; +assign master_out_source_payload_len = master_source_payload_len; +assign master_out_source_payload_end = master_source_payload_end; +assign master_out_source_payload_req_id = master_source_payload_req_id; +assign master_out_source_payload_cmp_id = master_source_payload_cmp_id; +assign master_out_source_payload_err = master_source_payload_err; +assign master_out_source_payload_tag = master_source_payload_tag; +assign master_out_source_payload_dat = master_source_payload_dat; +assign master_out_source_payload_channel = master_source_payload_channel; +assign master_out_source_payload_user_id = master_source_payload_user_id; +assign pcie_bridge_source_valid = slave_source_valid; +assign slave_source_ready = pcie_bridge_source_ready; +assign pcie_bridge_source_first = slave_source_first; +assign pcie_bridge_source_last = slave_source_last; +assign pcie_bridge_source_payload_we = slave_source_payload_we; +assign pcie_bridge_source_payload_adr = slave_source_payload_adr; +assign pcie_bridge_source_payload_len = slave_source_payload_len; +assign pcie_bridge_source_payload_req_id = slave_source_payload_req_id; +assign pcie_bridge_source_payload_tag = slave_source_payload_tag; +assign pcie_bridge_source_payload_dat = slave_source_payload_dat; +assign pcie_bridge_source_payload_channel = slave_source_payload_channel; +assign pcie_bridge_source_payload_user_id = slave_source_payload_user_id; +assign slave_sink_valid = pcie_bridge_sink_valid; +assign pcie_bridge_sink_ready = slave_sink_ready; +assign slave_sink_first = pcie_bridge_sink_first; +assign slave_sink_last = pcie_bridge_sink_last; +assign slave_sink_payload_adr = pcie_bridge_sink_payload_adr; +assign slave_sink_payload_len = pcie_bridge_sink_payload_len; +assign slave_sink_payload_end = pcie_bridge_sink_payload_end; +assign slave_sink_payload_req_id = pcie_bridge_sink_payload_req_id; +assign slave_sink_payload_cmp_id = pcie_bridge_sink_payload_cmp_id; +assign slave_sink_payload_err = pcie_bridge_sink_payload_err; +assign slave_sink_payload_tag = pcie_bridge_sink_payload_tag; +assign slave_sink_payload_dat = pcie_bridge_sink_payload_dat; +assign slave_sink_payload_channel = pcie_bridge_sink_payload_channel; +assign slave_sink_payload_user_id = pcie_bridge_sink_payload_user_id; +assign master_out_sink_first = master_in_sink_first; +assign master_out_sink_last = master_in_sink_last; +assign master_out_sink_payload_we = master_in_sink_payload_we; +assign master_out_sink_payload_adr = master_in_sink_payload_adr; +assign master_out_sink_payload_len = master_in_sink_payload_len; +assign master_out_sink_payload_req_id = master_in_sink_payload_req_id; +assign master_out_sink_payload_dat = master_in_sink_payload_dat; +assign master_out_sink_payload_channel = master_in_sink_payload_channel; +assign master_out_sink_payload_user_id = master_in_sink_payload_user_id; +assign requests_queue_sink_payload_tag = tags_queue_source_payload_tag; +assign requests_queue_sink_payload_channel = master_in_sink_payload_channel; +assign requests_queue_sink_payload_user_id = master_in_sink_payload_user_id; +always @(*) begin + syncfifo2_sink_valid <= 1'd0; + syncfifo0_sink_valid <= 1'd0; + syncfifo2_sink_first <= 1'd0; + syncfifo0_sink_first <= 1'd0; + syncfifo2_sink_last <= 1'd0; + syncfifo0_sink_last <= 1'd0; + syncfifo2_sink_payload_adr <= 32'd0; + syncfifo0_sink_payload_adr <= 32'd0; + syncfifo2_sink_payload_len <= 10'd0; + syncfifo0_sink_payload_len <= 10'd0; + syncfifo2_sink_payload_end <= 1'd0; + syncfifo0_sink_payload_end <= 1'd0; + syncfifo2_sink_payload_req_id <= 16'd0; + syncfifo0_sink_payload_req_id <= 16'd0; + syncfifo2_sink_payload_cmp_id <= 16'd0; + syncfifo0_sink_payload_cmp_id <= 16'd0; + syncfifo2_sink_payload_err <= 1'd0; + syncfifo0_sink_payload_err <= 1'd0; + syncfifo2_sink_payload_tag <= 8'd0; + syncfifo0_sink_payload_tag <= 8'd0; + syncfifo2_sink_payload_dat <= 64'd0; + syncfifo0_sink_payload_dat <= 64'd0; + syncfifo2_sink_payload_channel <= 8'd0; + syncfifo0_sink_payload_channel <= 8'd0; + syncfifo2_sink_payload_user_id <= 8'd0; + syncfifo0_sink_payload_user_id <= 8'd0; + syncfifo3_sink_valid <= 1'd0; + syncfifo1_sink_valid <= 1'd0; + syncfifo3_sink_first <= 1'd0; + syncfifo1_sink_first <= 1'd0; + syncfifo3_sink_last <= 1'd0; + syncfifo1_sink_last <= 1'd0; + syncfifo3_sink_payload_adr <= 32'd0; + syncfifo1_sink_payload_adr <= 32'd0; + syncfifo3_sink_payload_len <= 10'd0; + syncfifo1_sink_payload_len <= 10'd0; + syncfifo3_sink_payload_end <= 1'd0; + syncfifo1_sink_payload_end <= 1'd0; + syncfifo3_sink_payload_req_id <= 16'd0; + syncfifo1_sink_payload_req_id <= 16'd0; + syncfifo3_sink_payload_cmp_id <= 16'd0; + syncfifo1_sink_payload_cmp_id <= 16'd0; + syncfifo3_sink_payload_err <= 1'd0; + syncfifo1_sink_payload_err <= 1'd0; + syncfifo3_sink_payload_tag <= 8'd0; + syncfifo1_sink_payload_tag <= 8'd0; + syncfifo3_sink_payload_dat <= 64'd0; + syncfifo1_sink_payload_dat <= 64'd0; + syncfifo3_sink_payload_channel <= 8'd0; + syncfifo1_sink_payload_channel <= 8'd0; + syncfifo3_sink_payload_user_id <= 8'd0; + syncfifo1_sink_payload_user_id <= 8'd0; + cmp_reorder_ready <= 1'd0; + case (cmp_reorder_payload_tag) + 1'd0: begin + syncfifo0_sink_valid <= cmp_reorder_valid; + cmp_reorder_ready <= syncfifo0_sink_ready; + syncfifo0_sink_first <= cmp_reorder_first; + syncfifo0_sink_last <= cmp_reorder_last; + syncfifo0_sink_payload_adr <= cmp_reorder_payload_adr; + syncfifo0_sink_payload_len <= cmp_reorder_payload_len; + syncfifo0_sink_payload_end <= cmp_reorder_payload_end; + syncfifo0_sink_payload_req_id <= cmp_reorder_payload_req_id; + syncfifo0_sink_payload_cmp_id <= cmp_reorder_payload_cmp_id; + syncfifo0_sink_payload_err <= cmp_reorder_payload_err; + syncfifo0_sink_payload_tag <= cmp_reorder_payload_tag; + syncfifo0_sink_payload_dat <= cmp_reorder_payload_dat; + syncfifo0_sink_payload_channel <= cmp_reorder_payload_channel; + syncfifo0_sink_payload_user_id <= cmp_reorder_payload_user_id; + end + 1'd1: begin + syncfifo1_sink_valid <= cmp_reorder_valid; + cmp_reorder_ready <= syncfifo1_sink_ready; + syncfifo1_sink_first <= cmp_reorder_first; + syncfifo1_sink_last <= cmp_reorder_last; + syncfifo1_sink_payload_adr <= cmp_reorder_payload_adr; + syncfifo1_sink_payload_len <= cmp_reorder_payload_len; + syncfifo1_sink_payload_end <= cmp_reorder_payload_end; + syncfifo1_sink_payload_req_id <= cmp_reorder_payload_req_id; + syncfifo1_sink_payload_cmp_id <= cmp_reorder_payload_cmp_id; + syncfifo1_sink_payload_err <= cmp_reorder_payload_err; + syncfifo1_sink_payload_tag <= cmp_reorder_payload_tag; + syncfifo1_sink_payload_dat <= cmp_reorder_payload_dat; + syncfifo1_sink_payload_channel <= cmp_reorder_payload_channel; + syncfifo1_sink_payload_user_id <= cmp_reorder_payload_user_id; + end + 2'd2: begin + syncfifo2_sink_valid <= cmp_reorder_valid; + cmp_reorder_ready <= syncfifo2_sink_ready; + syncfifo2_sink_first <= cmp_reorder_first; + syncfifo2_sink_last <= cmp_reorder_last; + syncfifo2_sink_payload_adr <= cmp_reorder_payload_adr; + syncfifo2_sink_payload_len <= cmp_reorder_payload_len; + syncfifo2_sink_payload_end <= cmp_reorder_payload_end; + syncfifo2_sink_payload_req_id <= cmp_reorder_payload_req_id; + syncfifo2_sink_payload_cmp_id <= cmp_reorder_payload_cmp_id; + syncfifo2_sink_payload_err <= cmp_reorder_payload_err; + syncfifo2_sink_payload_tag <= cmp_reorder_payload_tag; + syncfifo2_sink_payload_dat <= cmp_reorder_payload_dat; + syncfifo2_sink_payload_channel <= cmp_reorder_payload_channel; + syncfifo2_sink_payload_user_id <= cmp_reorder_payload_user_id; + end + 2'd3: begin + syncfifo3_sink_valid <= cmp_reorder_valid; + cmp_reorder_ready <= syncfifo3_sink_ready; + syncfifo3_sink_first <= cmp_reorder_first; + syncfifo3_sink_last <= cmp_reorder_last; + syncfifo3_sink_payload_adr <= cmp_reorder_payload_adr; + syncfifo3_sink_payload_len <= cmp_reorder_payload_len; + syncfifo3_sink_payload_end <= cmp_reorder_payload_end; + syncfifo3_sink_payload_req_id <= cmp_reorder_payload_req_id; + syncfifo3_sink_payload_cmp_id <= cmp_reorder_payload_cmp_id; + syncfifo3_sink_payload_err <= cmp_reorder_payload_err; + syncfifo3_sink_payload_tag <= cmp_reorder_payload_tag; + syncfifo3_sink_payload_dat <= cmp_reorder_payload_dat; + syncfifo3_sink_payload_channel <= cmp_reorder_payload_channel; + syncfifo3_sink_payload_user_id <= cmp_reorder_payload_user_id; + end + default: begin + cmp_reorder_ready <= 1'd1; + end + endcase +end +always @(*) begin + requests_queue_source_ready <= 1'd0; + if (((master_in_source_valid & master_in_source_last) & master_in_source_payload_end)) begin + requests_queue_source_ready <= master_in_source_ready; + end +end +always @(*) begin + master_in_source_valid <= 1'd0; + master_in_source_first <= 1'd0; + master_in_source_last <= 1'd0; + master_in_source_payload_adr <= 32'd0; + master_in_source_payload_len <= 10'd0; + master_in_source_payload_end <= 1'd0; + master_in_source_payload_req_id <= 16'd0; + syncfifo2_source_ready <= 1'd0; + master_in_source_payload_cmp_id <= 16'd0; + syncfifo0_source_ready <= 1'd0; + master_in_source_payload_err <= 1'd0; + syncfifo1_source_ready <= 1'd0; + master_in_source_payload_tag <= 8'd0; + syncfifo3_source_ready <= 1'd0; + master_in_source_payload_dat <= 64'd0; + master_in_source_payload_channel <= 8'd0; + master_in_source_payload_user_id <= 8'd0; + case (requests_queue_source_payload_tag) + 1'd0: begin + master_in_source_valid <= syncfifo0_source_valid; + syncfifo0_source_ready <= master_in_source_ready; + master_in_source_first <= syncfifo0_source_first; + master_in_source_last <= syncfifo0_source_last; + master_in_source_payload_adr <= syncfifo0_source_payload_adr; + master_in_source_payload_len <= syncfifo0_source_payload_len; + master_in_source_payload_end <= syncfifo0_source_payload_end; + master_in_source_payload_req_id <= syncfifo0_source_payload_req_id; + master_in_source_payload_cmp_id <= syncfifo0_source_payload_cmp_id; + master_in_source_payload_err <= syncfifo0_source_payload_err; + master_in_source_payload_tag <= syncfifo0_source_payload_tag; + master_in_source_payload_dat <= syncfifo0_source_payload_dat; + master_in_source_payload_channel <= syncfifo0_source_payload_channel; + master_in_source_payload_user_id <= syncfifo0_source_payload_user_id; + end + 1'd1: begin + master_in_source_valid <= syncfifo1_source_valid; + syncfifo1_source_ready <= master_in_source_ready; + master_in_source_first <= syncfifo1_source_first; + master_in_source_last <= syncfifo1_source_last; + master_in_source_payload_adr <= syncfifo1_source_payload_adr; + master_in_source_payload_len <= syncfifo1_source_payload_len; + master_in_source_payload_end <= syncfifo1_source_payload_end; + master_in_source_payload_req_id <= syncfifo1_source_payload_req_id; + master_in_source_payload_cmp_id <= syncfifo1_source_payload_cmp_id; + master_in_source_payload_err <= syncfifo1_source_payload_err; + master_in_source_payload_tag <= syncfifo1_source_payload_tag; + master_in_source_payload_dat <= syncfifo1_source_payload_dat; + master_in_source_payload_channel <= syncfifo1_source_payload_channel; + master_in_source_payload_user_id <= syncfifo1_source_payload_user_id; + end + 2'd2: begin + master_in_source_valid <= syncfifo2_source_valid; + syncfifo2_source_ready <= master_in_source_ready; + master_in_source_first <= syncfifo2_source_first; + master_in_source_last <= syncfifo2_source_last; + master_in_source_payload_adr <= syncfifo2_source_payload_adr; + master_in_source_payload_len <= syncfifo2_source_payload_len; + master_in_source_payload_end <= syncfifo2_source_payload_end; + master_in_source_payload_req_id <= syncfifo2_source_payload_req_id; + master_in_source_payload_cmp_id <= syncfifo2_source_payload_cmp_id; + master_in_source_payload_err <= syncfifo2_source_payload_err; + master_in_source_payload_tag <= syncfifo2_source_payload_tag; + master_in_source_payload_dat <= syncfifo2_source_payload_dat; + master_in_source_payload_channel <= syncfifo2_source_payload_channel; + master_in_source_payload_user_id <= syncfifo2_source_payload_user_id; + end + 2'd3: begin + master_in_source_valid <= syncfifo3_source_valid; + syncfifo3_source_ready <= master_in_source_ready; + master_in_source_first <= syncfifo3_source_first; + master_in_source_last <= syncfifo3_source_last; + master_in_source_payload_adr <= syncfifo3_source_payload_adr; + master_in_source_payload_len <= syncfifo3_source_payload_len; + master_in_source_payload_end <= syncfifo3_source_payload_end; + master_in_source_payload_req_id <= syncfifo3_source_payload_req_id; + master_in_source_payload_cmp_id <= syncfifo3_source_payload_cmp_id; + master_in_source_payload_err <= syncfifo3_source_payload_err; + master_in_source_payload_tag <= syncfifo3_source_payload_tag; + master_in_source_payload_dat <= syncfifo3_source_payload_dat; + master_in_source_payload_channel <= syncfifo3_source_payload_channel; + master_in_source_payload_user_id <= syncfifo3_source_payload_user_id; + end + endcase + master_in_source_payload_channel <= requests_queue_source_payload_channel; + master_in_source_payload_user_id <= requests_queue_source_payload_user_id; +end +assign cmp_reorder_first = master_out_source_first; +assign cmp_reorder_last = master_out_source_last; +assign cmp_reorder_payload_adr = master_out_source_payload_adr; +assign cmp_reorder_payload_len = master_out_source_payload_len; +assign cmp_reorder_payload_end = master_out_source_payload_end; +assign cmp_reorder_payload_req_id = master_out_source_payload_req_id; +assign cmp_reorder_payload_cmp_id = master_out_source_payload_cmp_id; +assign cmp_reorder_payload_err = master_out_source_payload_err; +assign cmp_reorder_payload_tag = master_out_source_payload_tag; +assign cmp_reorder_payload_dat = master_out_source_payload_dat; +assign cmp_reorder_payload_channel = master_out_source_payload_channel; +assign cmp_reorder_payload_user_id = master_out_source_payload_user_id; +assign tags_queue_syncfifo_din = {tags_queue_fifo_in_last, tags_queue_fifo_in_first, tags_queue_fifo_in_payload_tag}; +assign {tags_queue_fifo_out_last, tags_queue_fifo_out_first, tags_queue_fifo_out_payload_tag} = tags_queue_syncfifo_dout; +assign tags_queue_sink_ready = tags_queue_syncfifo_writable; +assign tags_queue_syncfifo_we = tags_queue_sink_valid; +assign tags_queue_fifo_in_first = tags_queue_sink_first; +assign tags_queue_fifo_in_last = tags_queue_sink_last; +assign tags_queue_fifo_in_payload_tag = tags_queue_sink_payload_tag; +assign tags_queue_source_valid = tags_queue_readable; +assign tags_queue_source_first = tags_queue_fifo_out_first; +assign tags_queue_source_last = tags_queue_fifo_out_last; +assign tags_queue_source_payload_tag = tags_queue_fifo_out_payload_tag; +assign tags_queue_re = tags_queue_source_ready; +assign tags_queue_syncfifo_re = (tags_queue_syncfifo_readable & ((~tags_queue_readable) | tags_queue_re)); +assign tags_queue_level1 = (tags_queue_level0 + tags_queue_readable); +always @(*) begin + tags_queue_wrport_adr <= 2'd0; + if (tags_queue_replace) begin + tags_queue_wrport_adr <= (tags_queue_produce - 1'd1); + end else begin + tags_queue_wrport_adr <= tags_queue_produce; + end +end +assign tags_queue_wrport_dat_w = tags_queue_syncfifo_din; +assign tags_queue_wrport_we = (tags_queue_syncfifo_we & (tags_queue_syncfifo_writable | tags_queue_replace)); +assign tags_queue_do_read = (tags_queue_syncfifo_readable & tags_queue_syncfifo_re); +assign tags_queue_rdport_adr = tags_queue_consume; +assign tags_queue_syncfifo_dout = tags_queue_rdport_dat_r; +assign tags_queue_rdport_re = tags_queue_do_read; +assign tags_queue_syncfifo_writable = (tags_queue_level0 != 3'd4); +assign tags_queue_syncfifo_readable = (tags_queue_level0 != 1'd0); +assign requests_queue_syncfifo_din = {requests_queue_fifo_in_last, requests_queue_fifo_in_first, requests_queue_fifo_in_payload_user_id, requests_queue_fifo_in_payload_channel, requests_queue_fifo_in_payload_tag}; +assign {requests_queue_fifo_out_last, requests_queue_fifo_out_first, requests_queue_fifo_out_payload_user_id, requests_queue_fifo_out_payload_channel, requests_queue_fifo_out_payload_tag} = requests_queue_syncfifo_dout; +assign requests_queue_sink_ready = requests_queue_syncfifo_writable; +assign requests_queue_syncfifo_we = requests_queue_sink_valid; +assign requests_queue_fifo_in_first = requests_queue_sink_first; +assign requests_queue_fifo_in_last = requests_queue_sink_last; +assign requests_queue_fifo_in_payload_tag = requests_queue_sink_payload_tag; +assign requests_queue_fifo_in_payload_channel = requests_queue_sink_payload_channel; +assign requests_queue_fifo_in_payload_user_id = requests_queue_sink_payload_user_id; +assign requests_queue_source_valid = requests_queue_readable; +assign requests_queue_source_first = requests_queue_fifo_out_first; +assign requests_queue_source_last = requests_queue_fifo_out_last; +assign requests_queue_source_payload_tag = requests_queue_fifo_out_payload_tag; +assign requests_queue_source_payload_channel = requests_queue_fifo_out_payload_channel; +assign requests_queue_source_payload_user_id = requests_queue_fifo_out_payload_user_id; +assign requests_queue_re = requests_queue_source_ready; +assign requests_queue_syncfifo_re = (requests_queue_syncfifo_readable & ((~requests_queue_readable) | requests_queue_re)); +assign requests_queue_level1 = (requests_queue_level0 + requests_queue_readable); +always @(*) begin + requests_queue_wrport_adr <= 2'd0; + if (requests_queue_replace) begin + requests_queue_wrport_adr <= (requests_queue_produce - 1'd1); + end else begin + requests_queue_wrport_adr <= requests_queue_produce; + end +end +assign requests_queue_wrport_dat_w = requests_queue_syncfifo_din; +assign requests_queue_wrport_we = (requests_queue_syncfifo_we & (requests_queue_syncfifo_writable | requests_queue_replace)); +assign requests_queue_do_read = (requests_queue_syncfifo_readable & requests_queue_syncfifo_re); +assign requests_queue_rdport_adr = requests_queue_consume; +assign requests_queue_syncfifo_dout = requests_queue_rdport_dat_r; +assign requests_queue_rdport_re = requests_queue_do_read; +assign requests_queue_syncfifo_writable = (requests_queue_level0 != 3'd4); +assign requests_queue_syncfifo_readable = (requests_queue_level0 != 1'd0); +always @(*) begin + master_out_sink_payload_tag <= 8'd0; + master_out_sink_valid <= 1'd0; + tags_queue_source_ready <= 1'd0; + fsm0_next_state0 <= 2'd0; + requests_queue_sink_valid <= 1'd0; + master_in_sink_ready <= 1'd0; + fsm0_next_state0 <= fsm0_state0; + case (fsm0_state0) + 1'd1: begin + master_out_sink_valid <= master_in_sink_valid; + master_in_sink_ready <= master_out_sink_ready; + master_out_sink_payload_tag <= 6'd32; + if (((master_out_sink_valid & master_out_sink_ready) & master_out_sink_last)) begin + fsm0_next_state0 <= 1'd0; + end + end + 2'd2: begin + master_out_sink_valid <= master_in_sink_valid; + master_out_sink_payload_tag <= tags_queue_source_payload_tag; + master_in_sink_ready <= master_out_sink_ready; + if (((master_out_sink_valid & master_out_sink_ready) & master_out_sink_last)) begin + tags_queue_source_ready <= 1'd1; + requests_queue_sink_valid <= 1'd1; + fsm0_next_state0 <= 1'd0; + end + end + default: begin + if ((master_in_sink_valid & master_in_sink_first)) begin + if (master_in_sink_payload_we) begin + fsm0_next_state0 <= 1'd1; + end else begin + if ((tags_queue_source_valid & requests_queue_sink_ready)) begin + fsm0_next_state0 <= 2'd2; + end + end + end + end + endcase +end +assign syncfifo0_syncfifo0_din = {syncfifo0_fifo_in_last, syncfifo0_fifo_in_first, syncfifo0_fifo_in_payload_user_id, syncfifo0_fifo_in_payload_channel, syncfifo0_fifo_in_payload_dat, syncfifo0_fifo_in_payload_tag, syncfifo0_fifo_in_payload_err, syncfifo0_fifo_in_payload_cmp_id, syncfifo0_fifo_in_payload_req_id, syncfifo0_fifo_in_payload_end, syncfifo0_fifo_in_payload_len, syncfifo0_fifo_in_payload_adr}; +assign {syncfifo0_fifo_out_last, syncfifo0_fifo_out_first, syncfifo0_fifo_out_payload_user_id, syncfifo0_fifo_out_payload_channel, syncfifo0_fifo_out_payload_dat, syncfifo0_fifo_out_payload_tag, syncfifo0_fifo_out_payload_err, syncfifo0_fifo_out_payload_cmp_id, syncfifo0_fifo_out_payload_req_id, syncfifo0_fifo_out_payload_end, syncfifo0_fifo_out_payload_len, syncfifo0_fifo_out_payload_adr} = syncfifo0_syncfifo0_dout; +assign syncfifo0_sink_ready = syncfifo0_syncfifo0_writable; +assign syncfifo0_syncfifo0_we = syncfifo0_sink_valid; +assign syncfifo0_fifo_in_first = syncfifo0_sink_first; +assign syncfifo0_fifo_in_last = syncfifo0_sink_last; +assign syncfifo0_fifo_in_payload_adr = syncfifo0_sink_payload_adr; +assign syncfifo0_fifo_in_payload_len = syncfifo0_sink_payload_len; +assign syncfifo0_fifo_in_payload_end = syncfifo0_sink_payload_end; +assign syncfifo0_fifo_in_payload_req_id = syncfifo0_sink_payload_req_id; +assign syncfifo0_fifo_in_payload_cmp_id = syncfifo0_sink_payload_cmp_id; +assign syncfifo0_fifo_in_payload_err = syncfifo0_sink_payload_err; +assign syncfifo0_fifo_in_payload_tag = syncfifo0_sink_payload_tag; +assign syncfifo0_fifo_in_payload_dat = syncfifo0_sink_payload_dat; +assign syncfifo0_fifo_in_payload_channel = syncfifo0_sink_payload_channel; +assign syncfifo0_fifo_in_payload_user_id = syncfifo0_sink_payload_user_id; +assign syncfifo0_source_valid = syncfifo0_readable; +assign syncfifo0_source_first = syncfifo0_fifo_out_first; +assign syncfifo0_source_last = syncfifo0_fifo_out_last; +assign syncfifo0_source_payload_adr = syncfifo0_fifo_out_payload_adr; +assign syncfifo0_source_payload_len = syncfifo0_fifo_out_payload_len; +assign syncfifo0_source_payload_end = syncfifo0_fifo_out_payload_end; +assign syncfifo0_source_payload_req_id = syncfifo0_fifo_out_payload_req_id; +assign syncfifo0_source_payload_cmp_id = syncfifo0_fifo_out_payload_cmp_id; +assign syncfifo0_source_payload_err = syncfifo0_fifo_out_payload_err; +assign syncfifo0_source_payload_tag = syncfifo0_fifo_out_payload_tag; +assign syncfifo0_source_payload_dat = syncfifo0_fifo_out_payload_dat; +assign syncfifo0_source_payload_channel = syncfifo0_fifo_out_payload_channel; +assign syncfifo0_source_payload_user_id = syncfifo0_fifo_out_payload_user_id; +assign syncfifo0_re = syncfifo0_source_ready; +assign syncfifo0_syncfifo0_re = (syncfifo0_syncfifo0_readable & ((~syncfifo0_readable) | syncfifo0_re)); +assign syncfifo0_level1 = (syncfifo0_level0 + syncfifo0_readable); +always @(*) begin + syncfifo0_wrport_adr <= 8'd0; + if (syncfifo0_replace) begin + syncfifo0_wrport_adr <= (syncfifo0_produce - 1'd1); + end else begin + syncfifo0_wrport_adr <= syncfifo0_produce; + end +end +assign syncfifo0_wrport_dat_w = syncfifo0_syncfifo0_din; +assign syncfifo0_wrport_we = (syncfifo0_syncfifo0_we & (syncfifo0_syncfifo0_writable | syncfifo0_replace)); +assign syncfifo0_do_read = (syncfifo0_syncfifo0_readable & syncfifo0_syncfifo0_re); +assign syncfifo0_rdport_adr = syncfifo0_consume; +assign syncfifo0_syncfifo0_dout = syncfifo0_rdport_dat_r; +assign syncfifo0_rdport_re = syncfifo0_do_read; +assign syncfifo0_syncfifo0_writable = (syncfifo0_level0 != 9'd256); +assign syncfifo0_syncfifo0_readable = (syncfifo0_level0 != 1'd0); +assign syncfifo1_syncfifo1_din = {syncfifo1_fifo_in_last, syncfifo1_fifo_in_first, syncfifo1_fifo_in_payload_user_id, syncfifo1_fifo_in_payload_channel, syncfifo1_fifo_in_payload_dat, syncfifo1_fifo_in_payload_tag, syncfifo1_fifo_in_payload_err, syncfifo1_fifo_in_payload_cmp_id, syncfifo1_fifo_in_payload_req_id, syncfifo1_fifo_in_payload_end, syncfifo1_fifo_in_payload_len, syncfifo1_fifo_in_payload_adr}; +assign {syncfifo1_fifo_out_last, syncfifo1_fifo_out_first, syncfifo1_fifo_out_payload_user_id, syncfifo1_fifo_out_payload_channel, syncfifo1_fifo_out_payload_dat, syncfifo1_fifo_out_payload_tag, syncfifo1_fifo_out_payload_err, syncfifo1_fifo_out_payload_cmp_id, syncfifo1_fifo_out_payload_req_id, syncfifo1_fifo_out_payload_end, syncfifo1_fifo_out_payload_len, syncfifo1_fifo_out_payload_adr} = syncfifo1_syncfifo1_dout; +assign syncfifo1_sink_ready = syncfifo1_syncfifo1_writable; +assign syncfifo1_syncfifo1_we = syncfifo1_sink_valid; +assign syncfifo1_fifo_in_first = syncfifo1_sink_first; +assign syncfifo1_fifo_in_last = syncfifo1_sink_last; +assign syncfifo1_fifo_in_payload_adr = syncfifo1_sink_payload_adr; +assign syncfifo1_fifo_in_payload_len = syncfifo1_sink_payload_len; +assign syncfifo1_fifo_in_payload_end = syncfifo1_sink_payload_end; +assign syncfifo1_fifo_in_payload_req_id = syncfifo1_sink_payload_req_id; +assign syncfifo1_fifo_in_payload_cmp_id = syncfifo1_sink_payload_cmp_id; +assign syncfifo1_fifo_in_payload_err = syncfifo1_sink_payload_err; +assign syncfifo1_fifo_in_payload_tag = syncfifo1_sink_payload_tag; +assign syncfifo1_fifo_in_payload_dat = syncfifo1_sink_payload_dat; +assign syncfifo1_fifo_in_payload_channel = syncfifo1_sink_payload_channel; +assign syncfifo1_fifo_in_payload_user_id = syncfifo1_sink_payload_user_id; +assign syncfifo1_source_valid = syncfifo1_readable; +assign syncfifo1_source_first = syncfifo1_fifo_out_first; +assign syncfifo1_source_last = syncfifo1_fifo_out_last; +assign syncfifo1_source_payload_adr = syncfifo1_fifo_out_payload_adr; +assign syncfifo1_source_payload_len = syncfifo1_fifo_out_payload_len; +assign syncfifo1_source_payload_end = syncfifo1_fifo_out_payload_end; +assign syncfifo1_source_payload_req_id = syncfifo1_fifo_out_payload_req_id; +assign syncfifo1_source_payload_cmp_id = syncfifo1_fifo_out_payload_cmp_id; +assign syncfifo1_source_payload_err = syncfifo1_fifo_out_payload_err; +assign syncfifo1_source_payload_tag = syncfifo1_fifo_out_payload_tag; +assign syncfifo1_source_payload_dat = syncfifo1_fifo_out_payload_dat; +assign syncfifo1_source_payload_channel = syncfifo1_fifo_out_payload_channel; +assign syncfifo1_source_payload_user_id = syncfifo1_fifo_out_payload_user_id; +assign syncfifo1_re = syncfifo1_source_ready; +assign syncfifo1_syncfifo1_re = (syncfifo1_syncfifo1_readable & ((~syncfifo1_readable) | syncfifo1_re)); +assign syncfifo1_level1 = (syncfifo1_level0 + syncfifo1_readable); +always @(*) begin + syncfifo1_wrport_adr <= 8'd0; + if (syncfifo1_replace) begin + syncfifo1_wrport_adr <= (syncfifo1_produce - 1'd1); + end else begin + syncfifo1_wrport_adr <= syncfifo1_produce; + end +end +assign syncfifo1_wrport_dat_w = syncfifo1_syncfifo1_din; +assign syncfifo1_wrport_we = (syncfifo1_syncfifo1_we & (syncfifo1_syncfifo1_writable | syncfifo1_replace)); +assign syncfifo1_do_read = (syncfifo1_syncfifo1_readable & syncfifo1_syncfifo1_re); +assign syncfifo1_rdport_adr = syncfifo1_consume; +assign syncfifo1_syncfifo1_dout = syncfifo1_rdport_dat_r; +assign syncfifo1_rdport_re = syncfifo1_do_read; +assign syncfifo1_syncfifo1_writable = (syncfifo1_level0 != 9'd256); +assign syncfifo1_syncfifo1_readable = (syncfifo1_level0 != 1'd0); +assign syncfifo2_syncfifo2_din = {syncfifo2_fifo_in_last, syncfifo2_fifo_in_first, syncfifo2_fifo_in_payload_user_id, syncfifo2_fifo_in_payload_channel, syncfifo2_fifo_in_payload_dat, syncfifo2_fifo_in_payload_tag, syncfifo2_fifo_in_payload_err, syncfifo2_fifo_in_payload_cmp_id, syncfifo2_fifo_in_payload_req_id, syncfifo2_fifo_in_payload_end, syncfifo2_fifo_in_payload_len, syncfifo2_fifo_in_payload_adr}; +assign {syncfifo2_fifo_out_last, syncfifo2_fifo_out_first, syncfifo2_fifo_out_payload_user_id, syncfifo2_fifo_out_payload_channel, syncfifo2_fifo_out_payload_dat, syncfifo2_fifo_out_payload_tag, syncfifo2_fifo_out_payload_err, syncfifo2_fifo_out_payload_cmp_id, syncfifo2_fifo_out_payload_req_id, syncfifo2_fifo_out_payload_end, syncfifo2_fifo_out_payload_len, syncfifo2_fifo_out_payload_adr} = syncfifo2_syncfifo2_dout; +assign syncfifo2_sink_ready = syncfifo2_syncfifo2_writable; +assign syncfifo2_syncfifo2_we = syncfifo2_sink_valid; +assign syncfifo2_fifo_in_first = syncfifo2_sink_first; +assign syncfifo2_fifo_in_last = syncfifo2_sink_last; +assign syncfifo2_fifo_in_payload_adr = syncfifo2_sink_payload_adr; +assign syncfifo2_fifo_in_payload_len = syncfifo2_sink_payload_len; +assign syncfifo2_fifo_in_payload_end = syncfifo2_sink_payload_end; +assign syncfifo2_fifo_in_payload_req_id = syncfifo2_sink_payload_req_id; +assign syncfifo2_fifo_in_payload_cmp_id = syncfifo2_sink_payload_cmp_id; +assign syncfifo2_fifo_in_payload_err = syncfifo2_sink_payload_err; +assign syncfifo2_fifo_in_payload_tag = syncfifo2_sink_payload_tag; +assign syncfifo2_fifo_in_payload_dat = syncfifo2_sink_payload_dat; +assign syncfifo2_fifo_in_payload_channel = syncfifo2_sink_payload_channel; +assign syncfifo2_fifo_in_payload_user_id = syncfifo2_sink_payload_user_id; +assign syncfifo2_source_valid = syncfifo2_readable; +assign syncfifo2_source_first = syncfifo2_fifo_out_first; +assign syncfifo2_source_last = syncfifo2_fifo_out_last; +assign syncfifo2_source_payload_adr = syncfifo2_fifo_out_payload_adr; +assign syncfifo2_source_payload_len = syncfifo2_fifo_out_payload_len; +assign syncfifo2_source_payload_end = syncfifo2_fifo_out_payload_end; +assign syncfifo2_source_payload_req_id = syncfifo2_fifo_out_payload_req_id; +assign syncfifo2_source_payload_cmp_id = syncfifo2_fifo_out_payload_cmp_id; +assign syncfifo2_source_payload_err = syncfifo2_fifo_out_payload_err; +assign syncfifo2_source_payload_tag = syncfifo2_fifo_out_payload_tag; +assign syncfifo2_source_payload_dat = syncfifo2_fifo_out_payload_dat; +assign syncfifo2_source_payload_channel = syncfifo2_fifo_out_payload_channel; +assign syncfifo2_source_payload_user_id = syncfifo2_fifo_out_payload_user_id; +assign syncfifo2_re = syncfifo2_source_ready; +assign syncfifo2_syncfifo2_re = (syncfifo2_syncfifo2_readable & ((~syncfifo2_readable) | syncfifo2_re)); +assign syncfifo2_level1 = (syncfifo2_level0 + syncfifo2_readable); +always @(*) begin + syncfifo2_wrport_adr <= 8'd0; + if (syncfifo2_replace) begin + syncfifo2_wrport_adr <= (syncfifo2_produce - 1'd1); + end else begin + syncfifo2_wrport_adr <= syncfifo2_produce; + end +end +assign syncfifo2_wrport_dat_w = syncfifo2_syncfifo2_din; +assign syncfifo2_wrport_we = (syncfifo2_syncfifo2_we & (syncfifo2_syncfifo2_writable | syncfifo2_replace)); +assign syncfifo2_do_read = (syncfifo2_syncfifo2_readable & syncfifo2_syncfifo2_re); +assign syncfifo2_rdport_adr = syncfifo2_consume; +assign syncfifo2_syncfifo2_dout = syncfifo2_rdport_dat_r; +assign syncfifo2_rdport_re = syncfifo2_do_read; +assign syncfifo2_syncfifo2_writable = (syncfifo2_level0 != 9'd256); +assign syncfifo2_syncfifo2_readable = (syncfifo2_level0 != 1'd0); +assign syncfifo3_syncfifo3_din = {syncfifo3_fifo_in_last, syncfifo3_fifo_in_first, syncfifo3_fifo_in_payload_user_id, syncfifo3_fifo_in_payload_channel, syncfifo3_fifo_in_payload_dat, syncfifo3_fifo_in_payload_tag, syncfifo3_fifo_in_payload_err, syncfifo3_fifo_in_payload_cmp_id, syncfifo3_fifo_in_payload_req_id, syncfifo3_fifo_in_payload_end, syncfifo3_fifo_in_payload_len, syncfifo3_fifo_in_payload_adr}; +assign {syncfifo3_fifo_out_last, syncfifo3_fifo_out_first, syncfifo3_fifo_out_payload_user_id, syncfifo3_fifo_out_payload_channel, syncfifo3_fifo_out_payload_dat, syncfifo3_fifo_out_payload_tag, syncfifo3_fifo_out_payload_err, syncfifo3_fifo_out_payload_cmp_id, syncfifo3_fifo_out_payload_req_id, syncfifo3_fifo_out_payload_end, syncfifo3_fifo_out_payload_len, syncfifo3_fifo_out_payload_adr} = syncfifo3_syncfifo3_dout; +assign syncfifo3_sink_ready = syncfifo3_syncfifo3_writable; +assign syncfifo3_syncfifo3_we = syncfifo3_sink_valid; +assign syncfifo3_fifo_in_first = syncfifo3_sink_first; +assign syncfifo3_fifo_in_last = syncfifo3_sink_last; +assign syncfifo3_fifo_in_payload_adr = syncfifo3_sink_payload_adr; +assign syncfifo3_fifo_in_payload_len = syncfifo3_sink_payload_len; +assign syncfifo3_fifo_in_payload_end = syncfifo3_sink_payload_end; +assign syncfifo3_fifo_in_payload_req_id = syncfifo3_sink_payload_req_id; +assign syncfifo3_fifo_in_payload_cmp_id = syncfifo3_sink_payload_cmp_id; +assign syncfifo3_fifo_in_payload_err = syncfifo3_sink_payload_err; +assign syncfifo3_fifo_in_payload_tag = syncfifo3_sink_payload_tag; +assign syncfifo3_fifo_in_payload_dat = syncfifo3_sink_payload_dat; +assign syncfifo3_fifo_in_payload_channel = syncfifo3_sink_payload_channel; +assign syncfifo3_fifo_in_payload_user_id = syncfifo3_sink_payload_user_id; +assign syncfifo3_source_valid = syncfifo3_readable; +assign syncfifo3_source_first = syncfifo3_fifo_out_first; +assign syncfifo3_source_last = syncfifo3_fifo_out_last; +assign syncfifo3_source_payload_adr = syncfifo3_fifo_out_payload_adr; +assign syncfifo3_source_payload_len = syncfifo3_fifo_out_payload_len; +assign syncfifo3_source_payload_end = syncfifo3_fifo_out_payload_end; +assign syncfifo3_source_payload_req_id = syncfifo3_fifo_out_payload_req_id; +assign syncfifo3_source_payload_cmp_id = syncfifo3_fifo_out_payload_cmp_id; +assign syncfifo3_source_payload_err = syncfifo3_fifo_out_payload_err; +assign syncfifo3_source_payload_tag = syncfifo3_fifo_out_payload_tag; +assign syncfifo3_source_payload_dat = syncfifo3_fifo_out_payload_dat; +assign syncfifo3_source_payload_channel = syncfifo3_fifo_out_payload_channel; +assign syncfifo3_source_payload_user_id = syncfifo3_fifo_out_payload_user_id; +assign syncfifo3_re = syncfifo3_source_ready; +assign syncfifo3_syncfifo3_re = (syncfifo3_syncfifo3_readable & ((~syncfifo3_readable) | syncfifo3_re)); +assign syncfifo3_level1 = (syncfifo3_level0 + syncfifo3_readable); +always @(*) begin + syncfifo3_wrport_adr <= 8'd0; + if (syncfifo3_replace) begin + syncfifo3_wrport_adr <= (syncfifo3_produce - 1'd1); + end else begin + syncfifo3_wrport_adr <= syncfifo3_produce; + end +end +assign syncfifo3_wrport_dat_w = syncfifo3_syncfifo3_din; +assign syncfifo3_wrport_we = (syncfifo3_syncfifo3_we & (syncfifo3_syncfifo3_writable | syncfifo3_replace)); +assign syncfifo3_do_read = (syncfifo3_syncfifo3_readable & syncfifo3_syncfifo3_re); +assign syncfifo3_rdport_adr = syncfifo3_consume; +assign syncfifo3_syncfifo3_dout = syncfifo3_rdport_dat_r; +assign syncfifo3_rdport_re = syncfifo3_do_read; +assign syncfifo3_syncfifo3_writable = (syncfifo3_level0 != 9'd256); +assign syncfifo3_syncfifo3_readable = (syncfifo3_level0 != 1'd0); +always @(*) begin + tags_queue_sink_valid <= 1'd0; + tags_queue_sink_payload_tag <= 2'd0; + fsm1_next_state0 <= 2'd0; + master_out_source_ready <= 1'd0; + fill_tag_litepciecrossbar_next_value <= 2'd0; + cmp_reorder_valid <= 1'd0; + fill_tag_litepciecrossbar_next_value_ce <= 1'd0; + fsm1_next_state0 <= fsm1_state0; + case (fsm1_state0) + 1'd1: begin + if ((master_out_source_valid & master_out_source_first)) begin + fsm1_next_state0 <= 2'd2; + end else begin + master_out_source_ready <= 1'd1; + end + end + 2'd2: begin + cmp_reorder_valid <= master_out_source_valid; + master_out_source_ready <= cmp_reorder_ready; + if (((master_out_source_valid & master_out_source_ready) & master_out_source_last)) begin + if (master_out_source_payload_end) begin + tags_queue_sink_valid <= 1'd1; + tags_queue_sink_payload_tag <= master_out_source_payload_tag; + end + fsm1_next_state0 <= 1'd1; + end + end + default: begin + tags_queue_sink_valid <= 1'd1; + tags_queue_sink_payload_tag <= fill_tag; + fill_tag_litepciecrossbar_next_value <= (fill_tag + 1'd1); + fill_tag_litepciecrossbar_next_value_ce <= 1'd1; + if ((fill_tag == 2'd3)) begin + fsm1_next_state0 <= 1'd1; + end + end + endcase +end +always @(*) begin + arbiter0_request <= 2'd0; + arbiter0_request[0] <= arbiter0_status0_ongoing0; + arbiter0_request[1] <= arbiter0_status1_ongoing0; +end +always @(*) begin + master_in_sink_first <= 1'd0; + master_in_sink_last <= 1'd0; + pcie_dma0_litepciemasterinternalport1_sink_ready <= 1'd0; + master_in_sink_payload_we <= 1'd0; + master_in_sink_payload_adr <= 32'd0; + master_in_sink_payload_len <= 10'd0; + master_in_sink_payload_req_id <= 16'd0; + master_in_sink_payload_tag <= 8'd0; + master_in_sink_payload_dat <= 64'd0; + master_in_sink_payload_channel <= 8'd0; + master_in_sink_payload_user_id <= 8'd0; + pcie_dma1_litepciemasterinternalport1_sink_ready <= 1'd0; + master_in_sink_valid <= 1'd0; + case (arbiter0_grant) + 1'd0: begin + master_in_sink_valid <= pcie_dma0_litepciemasterinternalport1_sink_valid; + pcie_dma0_litepciemasterinternalport1_sink_ready <= master_in_sink_ready; + master_in_sink_first <= pcie_dma0_litepciemasterinternalport1_sink_first; + master_in_sink_last <= pcie_dma0_litepciemasterinternalport1_sink_last; + master_in_sink_payload_we <= pcie_dma0_litepciemasterinternalport1_sink_payload_we; + master_in_sink_payload_adr <= pcie_dma0_litepciemasterinternalport1_sink_payload_adr; + master_in_sink_payload_len <= pcie_dma0_litepciemasterinternalport1_sink_payload_len; + master_in_sink_payload_req_id <= pcie_dma0_litepciemasterinternalport1_sink_payload_req_id; + master_in_sink_payload_tag <= pcie_dma0_litepciemasterinternalport1_sink_payload_tag; + master_in_sink_payload_dat <= pcie_dma0_litepciemasterinternalport1_sink_payload_dat; + master_in_sink_payload_channel <= pcie_dma0_litepciemasterinternalport1_sink_payload_channel; + master_in_sink_payload_user_id <= pcie_dma0_litepciemasterinternalport1_sink_payload_user_id; + end + 1'd1: begin + master_in_sink_valid <= pcie_dma1_litepciemasterinternalport1_sink_valid; + pcie_dma1_litepciemasterinternalport1_sink_ready <= master_in_sink_ready; + master_in_sink_first <= pcie_dma1_litepciemasterinternalport1_sink_first; + master_in_sink_last <= pcie_dma1_litepciemasterinternalport1_sink_last; + master_in_sink_payload_we <= pcie_dma1_litepciemasterinternalport1_sink_payload_we; + master_in_sink_payload_adr <= pcie_dma1_litepciemasterinternalport1_sink_payload_adr; + master_in_sink_payload_len <= pcie_dma1_litepciemasterinternalport1_sink_payload_len; + master_in_sink_payload_req_id <= pcie_dma1_litepciemasterinternalport1_sink_payload_req_id; + master_in_sink_payload_tag <= pcie_dma1_litepciemasterinternalport1_sink_payload_tag; + master_in_sink_payload_dat <= pcie_dma1_litepciemasterinternalport1_sink_payload_dat; + master_in_sink_payload_channel <= pcie_dma1_litepciemasterinternalport1_sink_payload_channel; + master_in_sink_payload_user_id <= pcie_dma1_litepciemasterinternalport1_sink_payload_user_id; + end + endcase +end +always @(*) begin + arbiter0_status0_last <= 1'd0; + if (pcie_dma0_litepciemasterinternalport1_sink_valid) begin + arbiter0_status0_last <= (pcie_dma0_litepciemasterinternalport1_sink_last & pcie_dma0_litepciemasterinternalport1_sink_ready); + end +end +assign arbiter0_status0_ongoing0 = ((pcie_dma0_litepciemasterinternalport1_sink_valid | arbiter0_status0_ongoing1) & (~arbiter0_status0_last)); +always @(*) begin + arbiter0_status1_last <= 1'd0; + if (pcie_dma1_litepciemasterinternalport1_sink_valid) begin + arbiter0_status1_last <= (pcie_dma1_litepciemasterinternalport1_sink_last & pcie_dma1_litepciemasterinternalport1_sink_ready); + end +end +assign arbiter0_status1_ongoing0 = ((pcie_dma1_litepciemasterinternalport1_sink_valid | arbiter0_status1_ongoing1) & (~arbiter0_status1_last)); +always @(*) begin + dispatcher0_sel1 <= 2'd0; + if (dispatcher0_first) begin + dispatcher0_sel1 <= dispatcher0_sel0; + end else begin + dispatcher0_sel1 <= dispatcher0_sel_ongoing; + end +end +always @(*) begin + pcie_dma1_litepciemasterinternalport1_source_payload_err <= 1'd0; + pcie_dma1_litepciemasterinternalport1_source_payload_tag <= 8'd0; + pcie_dma1_litepciemasterinternalport1_source_payload_dat <= 64'd0; + pcie_dma1_litepciemasterinternalport1_source_payload_channel <= 8'd0; + pcie_dma1_litepciemasterinternalport1_source_payload_user_id <= 8'd0; + master_in_source_ready <= 1'd0; + pcie_dma0_litepciemasterinternalport1_source_valid <= 1'd0; + pcie_dma0_litepciemasterinternalport1_source_first <= 1'd0; + pcie_dma0_litepciemasterinternalport1_source_last <= 1'd0; + pcie_dma0_litepciemasterinternalport1_source_payload_adr <= 32'd0; + pcie_dma0_litepciemasterinternalport1_source_payload_len <= 10'd0; + pcie_dma0_litepciemasterinternalport1_source_payload_end <= 1'd0; + pcie_dma0_litepciemasterinternalport1_source_payload_req_id <= 16'd0; + pcie_dma0_litepciemasterinternalport1_source_payload_cmp_id <= 16'd0; + pcie_dma0_litepciemasterinternalport1_source_payload_err <= 1'd0; + pcie_dma0_litepciemasterinternalport1_source_payload_tag <= 8'd0; + pcie_dma1_litepciemasterinternalport1_source_valid <= 1'd0; + pcie_dma0_litepciemasterinternalport1_source_payload_dat <= 64'd0; + pcie_dma0_litepciemasterinternalport1_source_payload_channel <= 8'd0; + pcie_dma1_litepciemasterinternalport1_source_first <= 1'd0; + pcie_dma0_litepciemasterinternalport1_source_payload_user_id <= 8'd0; + pcie_dma1_litepciemasterinternalport1_source_last <= 1'd0; + pcie_dma1_litepciemasterinternalport1_source_payload_adr <= 32'd0; + pcie_dma1_litepciemasterinternalport1_source_payload_len <= 10'd0; + pcie_dma1_litepciemasterinternalport1_source_payload_end <= 1'd0; + pcie_dma1_litepciemasterinternalport1_source_payload_req_id <= 16'd0; + pcie_dma1_litepciemasterinternalport1_source_payload_cmp_id <= 16'd0; + case (dispatcher0_sel1) + 1'd1: begin + pcie_dma0_litepciemasterinternalport1_source_valid <= master_in_source_valid; + master_in_source_ready <= pcie_dma0_litepciemasterinternalport1_source_ready; + pcie_dma0_litepciemasterinternalport1_source_first <= master_in_source_first; + pcie_dma0_litepciemasterinternalport1_source_last <= master_in_source_last; + pcie_dma0_litepciemasterinternalport1_source_payload_adr <= master_in_source_payload_adr; + pcie_dma0_litepciemasterinternalport1_source_payload_len <= master_in_source_payload_len; + pcie_dma0_litepciemasterinternalport1_source_payload_end <= master_in_source_payload_end; + pcie_dma0_litepciemasterinternalport1_source_payload_req_id <= master_in_source_payload_req_id; + pcie_dma0_litepciemasterinternalport1_source_payload_cmp_id <= master_in_source_payload_cmp_id; + pcie_dma0_litepciemasterinternalport1_source_payload_err <= master_in_source_payload_err; + pcie_dma0_litepciemasterinternalport1_source_payload_tag <= master_in_source_payload_tag; + pcie_dma0_litepciemasterinternalport1_source_payload_dat <= master_in_source_payload_dat; + pcie_dma0_litepciemasterinternalport1_source_payload_channel <= master_in_source_payload_channel; + pcie_dma0_litepciemasterinternalport1_source_payload_user_id <= master_in_source_payload_user_id; + end + 2'd2: begin + pcie_dma1_litepciemasterinternalport1_source_valid <= master_in_source_valid; + master_in_source_ready <= pcie_dma1_litepciemasterinternalport1_source_ready; + pcie_dma1_litepciemasterinternalport1_source_first <= master_in_source_first; + pcie_dma1_litepciemasterinternalport1_source_last <= master_in_source_last; + pcie_dma1_litepciemasterinternalport1_source_payload_adr <= master_in_source_payload_adr; + pcie_dma1_litepciemasterinternalport1_source_payload_len <= master_in_source_payload_len; + pcie_dma1_litepciemasterinternalport1_source_payload_end <= master_in_source_payload_end; + pcie_dma1_litepciemasterinternalport1_source_payload_req_id <= master_in_source_payload_req_id; + pcie_dma1_litepciemasterinternalport1_source_payload_cmp_id <= master_in_source_payload_cmp_id; + pcie_dma1_litepciemasterinternalport1_source_payload_err <= master_in_source_payload_err; + pcie_dma1_litepciemasterinternalport1_source_payload_tag <= master_in_source_payload_tag; + pcie_dma1_litepciemasterinternalport1_source_payload_dat <= master_in_source_payload_dat; + pcie_dma1_litepciemasterinternalport1_source_payload_channel <= master_in_source_payload_channel; + pcie_dma1_litepciemasterinternalport1_source_payload_user_id <= master_in_source_payload_user_id; + end + default: begin + master_in_source_ready <= 1'd1; + end + endcase +end +always @(*) begin + dispatcher0_last <= 1'd0; + if (master_in_source_valid) begin + dispatcher0_last <= (master_in_source_last & master_in_source_ready); + end +end +assign dispatcher0_ongoing0 = ((master_in_source_valid | dispatcher0_ongoing1) & (~dispatcher0_last)); +always @(*) begin + arbiter1_request <= 2'd0; + arbiter1_request[0] <= arbiter1_status2_ongoing0; + arbiter1_request[1] <= arbiter1_status3_ongoing0; +end +always @(*) begin + sink_payload_req_id <= 16'd0; + sink_payload_tag <= 8'd0; + sink_payload_dat <= 64'd0; + sink_payload_channel <= 8'd0; + sink_payload_user_id <= 8'd0; + pcie_dma1_litepciemasterinternalport0_sink_ready <= 1'd0; + sink_valid <= 1'd0; + sink_first <= 1'd0; + sink_last <= 1'd0; + pcie_dma0_litepciemasterinternalport0_sink_ready <= 1'd0; + sink_payload_we <= 1'd0; + sink_payload_adr <= 32'd0; + sink_payload_len <= 10'd0; + case (arbiter1_grant) + 1'd0: begin + sink_valid <= pcie_dma0_litepciemasterinternalport0_sink_valid; + pcie_dma0_litepciemasterinternalport0_sink_ready <= sink_ready; + sink_first <= pcie_dma0_litepciemasterinternalport0_sink_first; + sink_last <= pcie_dma0_litepciemasterinternalport0_sink_last; + sink_payload_we <= pcie_dma0_litepciemasterinternalport0_sink_payload_we; + sink_payload_adr <= pcie_dma0_litepciemasterinternalport0_sink_payload_adr; + sink_payload_len <= pcie_dma0_litepciemasterinternalport0_sink_payload_len; + sink_payload_req_id <= pcie_dma0_litepciemasterinternalport0_sink_payload_req_id; + sink_payload_tag <= pcie_dma0_litepciemasterinternalport0_sink_payload_tag; + sink_payload_dat <= pcie_dma0_litepciemasterinternalport0_sink_payload_dat; + sink_payload_channel <= pcie_dma0_litepciemasterinternalport0_sink_payload_channel; + sink_payload_user_id <= pcie_dma0_litepciemasterinternalport0_sink_payload_user_id; + end + 1'd1: begin + sink_valid <= pcie_dma1_litepciemasterinternalport0_sink_valid; + pcie_dma1_litepciemasterinternalport0_sink_ready <= sink_ready; + sink_first <= pcie_dma1_litepciemasterinternalport0_sink_first; + sink_last <= pcie_dma1_litepciemasterinternalport0_sink_last; + sink_payload_we <= pcie_dma1_litepciemasterinternalport0_sink_payload_we; + sink_payload_adr <= pcie_dma1_litepciemasterinternalport0_sink_payload_adr; + sink_payload_len <= pcie_dma1_litepciemasterinternalport0_sink_payload_len; + sink_payload_req_id <= pcie_dma1_litepciemasterinternalport0_sink_payload_req_id; + sink_payload_tag <= pcie_dma1_litepciemasterinternalport0_sink_payload_tag; + sink_payload_dat <= pcie_dma1_litepciemasterinternalport0_sink_payload_dat; + sink_payload_channel <= pcie_dma1_litepciemasterinternalport0_sink_payload_channel; + sink_payload_user_id <= pcie_dma1_litepciemasterinternalport0_sink_payload_user_id; + end + endcase +end +always @(*) begin + arbiter1_status2_last <= 1'd0; + if (pcie_dma0_litepciemasterinternalport0_sink_valid) begin + arbiter1_status2_last <= (pcie_dma0_litepciemasterinternalport0_sink_last & pcie_dma0_litepciemasterinternalport0_sink_ready); + end +end +assign arbiter1_status2_ongoing0 = ((pcie_dma0_litepciemasterinternalport0_sink_valid | arbiter1_status2_ongoing1) & (~arbiter1_status2_last)); +always @(*) begin + arbiter1_status3_last <= 1'd0; + if (pcie_dma1_litepciemasterinternalport0_sink_valid) begin + arbiter1_status3_last <= (pcie_dma1_litepciemasterinternalport0_sink_last & pcie_dma1_litepciemasterinternalport0_sink_ready); + end +end +assign arbiter1_status3_ongoing0 = ((pcie_dma1_litepciemasterinternalport0_sink_valid | arbiter1_status3_ongoing1) & (~arbiter1_status3_last)); +always @(*) begin + dispatcher1_sel1 <= 2'd0; + if (dispatcher1_first) begin + dispatcher1_sel1 <= dispatcher1_sel0; + end else begin + dispatcher1_sel1 <= dispatcher1_sel_ongoing; + end +end +always @(*) begin + pcie_dma0_litepciemasterinternalport0_source_payload_err <= 1'd0; + pcie_dma0_litepciemasterinternalport0_source_payload_tag <= 8'd0; + pcie_dma1_litepciemasterinternalport0_source_valid <= 1'd0; + pcie_dma0_litepciemasterinternalport0_source_payload_dat <= 64'd0; + pcie_dma0_litepciemasterinternalport0_source_payload_channel <= 8'd0; + pcie_dma1_litepciemasterinternalport0_source_first <= 1'd0; + pcie_dma0_litepciemasterinternalport0_source_payload_user_id <= 8'd0; + pcie_dma1_litepciemasterinternalport0_source_last <= 1'd0; + source_ready <= 1'd0; + pcie_dma1_litepciemasterinternalport0_source_payload_adr <= 32'd0; + pcie_dma1_litepciemasterinternalport0_source_payload_len <= 10'd0; + pcie_dma1_litepciemasterinternalport0_source_payload_end <= 1'd0; + pcie_dma1_litepciemasterinternalport0_source_payload_req_id <= 16'd0; + pcie_dma1_litepciemasterinternalport0_source_payload_cmp_id <= 16'd0; + pcie_dma1_litepciemasterinternalport0_source_payload_err <= 1'd0; + pcie_dma1_litepciemasterinternalport0_source_payload_tag <= 8'd0; + pcie_dma1_litepciemasterinternalport0_source_payload_dat <= 64'd0; + pcie_dma1_litepciemasterinternalport0_source_payload_channel <= 8'd0; + pcie_dma1_litepciemasterinternalport0_source_payload_user_id <= 8'd0; + pcie_dma0_litepciemasterinternalport0_source_valid <= 1'd0; + pcie_dma0_litepciemasterinternalport0_source_first <= 1'd0; + pcie_dma0_litepciemasterinternalport0_source_last <= 1'd0; + pcie_dma0_litepciemasterinternalport0_source_payload_adr <= 32'd0; + pcie_dma0_litepciemasterinternalport0_source_payload_len <= 10'd0; + pcie_dma0_litepciemasterinternalport0_source_payload_end <= 1'd0; + pcie_dma0_litepciemasterinternalport0_source_payload_req_id <= 16'd0; + pcie_dma0_litepciemasterinternalport0_source_payload_cmp_id <= 16'd0; + case (dispatcher1_sel1) + 1'd1: begin + pcie_dma0_litepciemasterinternalport0_source_valid <= source_valid; + source_ready <= pcie_dma0_litepciemasterinternalport0_source_ready; + pcie_dma0_litepciemasterinternalport0_source_first <= source_first; + pcie_dma0_litepciemasterinternalport0_source_last <= source_last; + pcie_dma0_litepciemasterinternalport0_source_payload_adr <= source_payload_adr; + pcie_dma0_litepciemasterinternalport0_source_payload_len <= source_payload_len; + pcie_dma0_litepciemasterinternalport0_source_payload_end <= source_payload_end; + pcie_dma0_litepciemasterinternalport0_source_payload_req_id <= source_payload_req_id; + pcie_dma0_litepciemasterinternalport0_source_payload_cmp_id <= source_payload_cmp_id; + pcie_dma0_litepciemasterinternalport0_source_payload_err <= source_payload_err; + pcie_dma0_litepciemasterinternalport0_source_payload_tag <= source_payload_tag; + pcie_dma0_litepciemasterinternalport0_source_payload_dat <= source_payload_dat; + pcie_dma0_litepciemasterinternalport0_source_payload_channel <= source_payload_channel; + pcie_dma0_litepciemasterinternalport0_source_payload_user_id <= source_payload_user_id; + end + 2'd2: begin + pcie_dma1_litepciemasterinternalport0_source_valid <= source_valid; + source_ready <= pcie_dma1_litepciemasterinternalport0_source_ready; + pcie_dma1_litepciemasterinternalport0_source_first <= source_first; + pcie_dma1_litepciemasterinternalport0_source_last <= source_last; + pcie_dma1_litepciemasterinternalport0_source_payload_adr <= source_payload_adr; + pcie_dma1_litepciemasterinternalport0_source_payload_len <= source_payload_len; + pcie_dma1_litepciemasterinternalport0_source_payload_end <= source_payload_end; + pcie_dma1_litepciemasterinternalport0_source_payload_req_id <= source_payload_req_id; + pcie_dma1_litepciemasterinternalport0_source_payload_cmp_id <= source_payload_cmp_id; + pcie_dma1_litepciemasterinternalport0_source_payload_err <= source_payload_err; + pcie_dma1_litepciemasterinternalport0_source_payload_tag <= source_payload_tag; + pcie_dma1_litepciemasterinternalport0_source_payload_dat <= source_payload_dat; + pcie_dma1_litepciemasterinternalport0_source_payload_channel <= source_payload_channel; + pcie_dma1_litepciemasterinternalport0_source_payload_user_id <= source_payload_user_id; + end + default: begin + source_ready <= 1'd1; + end + endcase +end +always @(*) begin + dispatcher1_last <= 1'd0; + if (source_valid) begin + dispatcher1_last <= (source_last & source_ready); + end +end +assign dispatcher1_ongoing0 = ((source_valid | dispatcher1_ongoing1) & (~dispatcher1_last)); +always @(*) begin + arbiter2_request <= 2'd0; + arbiter2_request[0] <= arbiter2_status4_ongoing0; + arbiter2_request[1] <= arbiter2_status5_ongoing0; +end +always @(*) begin + master_sink_payload_user_id <= 8'd0; + master_sink_valid <= 1'd0; + master_sink_first <= 1'd0; + master_sink_last <= 1'd0; + master_sink_payload_we <= 1'd0; + master_out_sink_ready <= 1'd0; + master_sink_payload_adr <= 32'd0; + sink_ready <= 1'd0; + master_sink_payload_len <= 10'd0; + master_sink_payload_req_id <= 16'd0; + master_sink_payload_tag <= 8'd0; + master_sink_payload_dat <= 64'd0; + master_sink_payload_channel <= 8'd0; + case (arbiter2_grant) + 1'd0: begin + master_sink_valid <= master_out_sink_valid; + master_out_sink_ready <= master_sink_ready; + master_sink_first <= master_out_sink_first; + master_sink_last <= master_out_sink_last; + master_sink_payload_we <= master_out_sink_payload_we; + master_sink_payload_adr <= master_out_sink_payload_adr; + master_sink_payload_len <= master_out_sink_payload_len; + master_sink_payload_req_id <= master_out_sink_payload_req_id; + master_sink_payload_tag <= master_out_sink_payload_tag; + master_sink_payload_dat <= master_out_sink_payload_dat; + master_sink_payload_channel <= master_out_sink_payload_channel; + master_sink_payload_user_id <= master_out_sink_payload_user_id; + end + 1'd1: begin + master_sink_valid <= sink_valid; + sink_ready <= master_sink_ready; + master_sink_first <= sink_first; + master_sink_last <= sink_last; + master_sink_payload_we <= sink_payload_we; + master_sink_payload_adr <= sink_payload_adr; + master_sink_payload_len <= sink_payload_len; + master_sink_payload_req_id <= sink_payload_req_id; + master_sink_payload_tag <= sink_payload_tag; + master_sink_payload_dat <= sink_payload_dat; + master_sink_payload_channel <= sink_payload_channel; + master_sink_payload_user_id <= sink_payload_user_id; + end + endcase +end +always @(*) begin + arbiter2_status4_last <= 1'd0; + if (master_out_sink_valid) begin + arbiter2_status4_last <= (master_out_sink_last & master_out_sink_ready); + end +end +assign arbiter2_status4_ongoing0 = ((master_out_sink_valid | arbiter2_status4_ongoing1) & (~arbiter2_status4_last)); +always @(*) begin + arbiter2_status5_last <= 1'd0; + if (sink_valid) begin + arbiter2_status5_last <= (sink_last & sink_ready); + end +end +assign arbiter2_status5_ongoing0 = ((sink_valid | arbiter2_status5_ongoing1) & (~arbiter2_status5_last)); +always @(*) begin + pcie_bridge_wishbone_we <= 1'd0; + pcie_bridge_source_ready <= 1'd0; + pcie_bridge_sink_valid <= 1'd0; + pcie_bridge_wishbone_cyc <= 1'd0; + pcie_bridge_update_dat <= 1'd0; + pcie_bridge_wishbone_stb <= 1'd0; + litepciewishbonebridge_next_state <= 2'd0; + litepciewishbonebridge_next_state <= litepciewishbonebridge_state; + case (litepciewishbonebridge_state) + 1'd1: begin + pcie_bridge_wishbone_stb <= 1'd1; + pcie_bridge_wishbone_we <= 1'd1; + pcie_bridge_wishbone_cyc <= 1'd1; + if (pcie_bridge_wishbone_ack) begin + pcie_bridge_source_ready <= 1'd1; + litepciewishbonebridge_next_state <= 1'd0; + end + end + 2'd2: begin + pcie_bridge_wishbone_stb <= 1'd1; + pcie_bridge_wishbone_we <= 1'd0; + pcie_bridge_wishbone_cyc <= 1'd1; + if (pcie_bridge_wishbone_ack) begin + pcie_bridge_update_dat <= 1'd1; + litepciewishbonebridge_next_state <= 2'd3; + end + end + 2'd3: begin + pcie_bridge_sink_valid <= 1'd1; + if (pcie_bridge_sink_ready) begin + pcie_bridge_source_ready <= 1'd1; + litepciewishbonebridge_next_state <= 1'd0; + end + end + default: begin + if ((pcie_bridge_source_valid & pcie_bridge_source_first)) begin + if (pcie_bridge_source_payload_we) begin + litepciewishbonebridge_next_state <= 1'd1; + end else begin + litepciewishbonebridge_next_state <= 2'd2; + end + end else begin + pcie_bridge_source_ready <= 1'd1; + end + end + endcase +end +assign pcie_dma0_loopback_sink_valid = pcie_dma0_reader_source_source_valid0; +assign pcie_dma0_reader_source_source_ready0 = pcie_dma0_loopback_sink_ready; +assign pcie_dma0_loopback_sink_first = pcie_dma0_reader_source_source_first0; +assign pcie_dma0_loopback_sink_last = pcie_dma0_reader_source_source_last0; +assign pcie_dma0_loopback_sink_payload_data = pcie_dma0_reader_source_source_payload_data; +assign pcie_dma0_writer_sink_valid = pcie_dma0_loopback_source_valid; +assign pcie_dma0_loopback_source_ready = pcie_dma0_writer_sink_ready; +assign pcie_dma0_writer_sink_first = pcie_dma0_loopback_source_first; +assign pcie_dma0_writer_sink_last = pcie_dma0_loopback_source_last; +assign pcie_dma0_writer_sink_payload_data = pcie_dma0_loopback_source_payload_data; +assign pcie_dma0_buffering_sink_sink_valid = pcie_dma0_loopback_next_source_valid; +assign pcie_dma0_loopback_next_source_ready = pcie_dma0_buffering_sink_sink_ready; +assign pcie_dma0_buffering_sink_sink_first = pcie_dma0_loopback_next_source_first; +assign pcie_dma0_buffering_sink_sink_last = pcie_dma0_loopback_next_source_last; +assign pcie_dma0_buffering_sink_sink_payload_data = pcie_dma0_loopback_next_source_payload_data; +assign pcie_dma0_loopback_next_sink_valid = pcie_dma0_buffering_source_source_valid; +assign pcie_dma0_buffering_source_source_ready = pcie_dma0_loopback_next_sink_ready; +assign pcie_dma0_loopback_next_sink_first = pcie_dma0_buffering_source_source_first; +assign pcie_dma0_loopback_next_sink_last = pcie_dma0_buffering_source_source_last; +assign pcie_dma0_loopback_next_sink_payload_data = pcie_dma0_buffering_source_source_payload_data; +assign pcie_dma0_writer_splitter_reset = (~pcie_dma0_writer_enable_storage); +assign pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_valid = pcie_dma0_writer_source_source_valid; +assign pcie_dma0_writer_source_source_ready = pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_ready; +assign pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_first = pcie_dma0_writer_source_source_first; +assign pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_last = pcie_dma0_writer_source_source_last; +assign pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_payload_address = pcie_dma0_writer_source_source_payload_address; +assign pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_payload_length = pcie_dma0_writer_source_source_payload_length; +assign pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_payload_control = pcie_dma0_writer_source_source_payload_control; +assign pcie_dma0_writer_fifo_syncfifo_we1 = (pcie_dma0_writer_sink_valid & pcie_dma0_writer_enable_storage); +assign pcie_dma0_writer_sink_ready = (pcie_dma0_writer_fifo_syncfifo_writable1 | (~pcie_dma0_writer_enable_storage)); +assign pcie_dma0_writer_fifo_syncfifo_din1 = {pcie_dma0_writer_sink_last, pcie_dma0_writer_sink_payload_data}; +assign pcie_dma0_writer_resetinserter_reset = (~pcie_dma0_writer_enable_storage); +assign pcie_dma0_litepciemasterinternalport0_sink_payload_channel = 1'd0; +assign pcie_dma0_litepciemasterinternalport0_sink_payload_user_id = pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_user_id; +assign pcie_dma0_litepciemasterinternalport0_sink_first = (pcie_dma0_writer_counter == 1'd0); +assign pcie_dma0_litepciemasterinternalport0_sink_last = ((~pcie_dma0_writer_enable_storage) | (pcie_dma0_writer_counter == (pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_length[23:3] - 1'd1))); +assign pcie_dma0_litepciemasterinternalport0_sink_payload_we = 1'd1; +assign pcie_dma0_litepciemasterinternalport0_sink_payload_adr = pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_address; +assign pcie_dma0_litepciemasterinternalport0_sink_payload_req_id = s7pciephy_id; +assign pcie_dma0_litepciemasterinternalport0_sink_payload_tag = 1'd0; +assign pcie_dma0_litepciemasterinternalport0_sink_payload_len = pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_length[23:2]; +assign pcie_dma0_litepciemasterinternalport0_sink_payload_dat = pcie_dma0_writer_fifo_syncfifo_dout1[63:0]; +assign pcie_dma0_writer_irq = (((pcie_dma0_writer_splitter_bufferizeendpoints_source_valid & pcie_dma0_writer_splitter_bufferizeendpoints_source_ready) & pcie_dma0_writer_splitter_bufferizeendpoints_source_last) & (~pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_control[0])); +assign pcie_dma0_writer_fifo_reset = (pcie_dma0_writer_flush_storage & pcie_dma0_writer_flush_re); +assign pcie_dma0_writer_level_status = pcie_dma0_writer_fifo_level0; +assign pcie_dma0_writer_source_source_valid = pcie_dma0_writer_fifo_source_valid; +assign pcie_dma0_writer_source_source_first = pcie_dma0_writer_fifo_source_first; +assign pcie_dma0_writer_fifo_source_ready = (pcie_dma0_writer_source_source_valid & pcie_dma0_writer_source_source_ready); +assign pcie_dma0_writer_source_source_payload_address = pcie_dma0_writer_fifo_source_payload_address; +assign pcie_dma0_writer_source_source_payload_length = pcie_dma0_writer_fifo_source_payload_length; +assign pcie_dma0_writer_source_source_payload_control = pcie_dma0_writer_fifo_source_payload_control; +assign pcie_dma0_writer_fifo_syncfifo_din0 = {pcie_dma0_writer_fifo_fifo_in_last, pcie_dma0_writer_fifo_fifo_in_first, pcie_dma0_writer_fifo_fifo_in_payload_control, pcie_dma0_writer_fifo_fifo_in_payload_length, pcie_dma0_writer_fifo_fifo_in_payload_address}; +assign {pcie_dma0_writer_fifo_fifo_out_last, pcie_dma0_writer_fifo_fifo_out_first, pcie_dma0_writer_fifo_fifo_out_payload_control, pcie_dma0_writer_fifo_fifo_out_payload_length, pcie_dma0_writer_fifo_fifo_out_payload_address} = pcie_dma0_writer_fifo_syncfifo_dout0; +assign pcie_dma0_writer_fifo_sink_ready = pcie_dma0_writer_fifo_syncfifo_writable0; +assign pcie_dma0_writer_fifo_syncfifo_we0 = pcie_dma0_writer_fifo_sink_valid; +assign pcie_dma0_writer_fifo_fifo_in_first = pcie_dma0_writer_fifo_sink_first; +assign pcie_dma0_writer_fifo_fifo_in_last = pcie_dma0_writer_fifo_sink_last; +assign pcie_dma0_writer_fifo_fifo_in_payload_address = pcie_dma0_writer_fifo_sink_payload_address; +assign pcie_dma0_writer_fifo_fifo_in_payload_length = pcie_dma0_writer_fifo_sink_payload_length; +assign pcie_dma0_writer_fifo_fifo_in_payload_control = pcie_dma0_writer_fifo_sink_payload_control; +assign pcie_dma0_writer_fifo_source_valid = pcie_dma0_writer_fifo_syncfifo_readable0; +assign pcie_dma0_writer_fifo_source_first = pcie_dma0_writer_fifo_fifo_out_first; +assign pcie_dma0_writer_fifo_source_last = pcie_dma0_writer_fifo_fifo_out_last; +assign pcie_dma0_writer_fifo_source_payload_address = pcie_dma0_writer_fifo_fifo_out_payload_address; +assign pcie_dma0_writer_fifo_source_payload_length = pcie_dma0_writer_fifo_fifo_out_payload_length; +assign pcie_dma0_writer_fifo_source_payload_control = pcie_dma0_writer_fifo_fifo_out_payload_control; +assign pcie_dma0_writer_fifo_syncfifo_re0 = pcie_dma0_writer_fifo_source_ready; +always @(*) begin + pcie_dma0_writer_fifo_wrport_adr0 <= 8'd0; + if (pcie_dma0_writer_fifo_replace0) begin + pcie_dma0_writer_fifo_wrport_adr0 <= (pcie_dma0_writer_fifo_produce0 - 1'd1); + end else begin + pcie_dma0_writer_fifo_wrport_adr0 <= pcie_dma0_writer_fifo_produce0; + end +end +assign pcie_dma0_writer_fifo_wrport_dat_w0 = pcie_dma0_writer_fifo_syncfifo_din0; +assign pcie_dma0_writer_fifo_wrport_we0 = (pcie_dma0_writer_fifo_syncfifo_we0 & (pcie_dma0_writer_fifo_syncfifo_writable0 | pcie_dma0_writer_fifo_replace0)); +assign pcie_dma0_writer_fifo_do_read0 = (pcie_dma0_writer_fifo_syncfifo_readable0 & pcie_dma0_writer_fifo_syncfifo_re0); +assign pcie_dma0_writer_fifo_rdport_adr0 = pcie_dma0_writer_fifo_consume0; +assign pcie_dma0_writer_fifo_syncfifo_dout0 = pcie_dma0_writer_fifo_rdport_dat_r0; +assign pcie_dma0_writer_fifo_syncfifo_writable0 = (pcie_dma0_writer_fifo_level0 != 9'd256); +assign pcie_dma0_writer_fifo_syncfifo_readable0 = (pcie_dma0_writer_fifo_level0 != 1'd0); +assign pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_payload_address = (pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_payload_address + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_offset); +assign pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_payload_control = pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_payload_control; +assign pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_payload_user_id = pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_user_id; +assign pcie_dma0_writer_splitter_bufferizeendpoints_sink_valid = pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_valid; +assign pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_ready = pcie_dma0_writer_splitter_bufferizeendpoints_sink_ready; +assign pcie_dma0_writer_splitter_bufferizeendpoints_sink_first = pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_first; +assign pcie_dma0_writer_splitter_bufferizeendpoints_sink_last = pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_last; +assign pcie_dma0_writer_splitter_bufferizeendpoints_sink_payload_address = pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_payload_address; +assign pcie_dma0_writer_splitter_bufferizeendpoints_sink_payload_length = pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_payload_length; +assign pcie_dma0_writer_splitter_bufferizeendpoints_sink_payload_control = pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_payload_control; +assign pcie_dma0_writer_splitter_bufferizeendpoints_sink_payload_user_id = pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_payload_user_id; +always @(*) begin + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_user_id_litepciedma0_bufferizeendpoints0_next_value1 <= 32'd0; + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_user_id_litepciedma0_bufferizeendpoints0_next_value_ce1 <= 1'd0; + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_payload_length <= 24'd0; + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_ready <= 1'd0; + bufferizeendpoints0_next_state0 <= 2'd0; + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_bufferizeendpoints0_next_value0 <= 32'd0; + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_bufferizeendpoints0_next_value_ce0 <= 1'd0; + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_valid <= 1'd0; + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_first <= 1'd0; + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_last <= 1'd0; + bufferizeendpoints0_next_state0 <= bufferizeendpoints0_state0; + case (bufferizeendpoints0_state0) + 1'd1: begin + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_valid <= 1'd1; + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_first <= (pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_offset == 1'd0); + if (((pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_payload_length - pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_offset) > s7pciephy_max_payload_size)) begin + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_last <= pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_end; + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_payload_length <= s7pciephy_max_payload_size; + if (pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_ready) begin + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_bufferizeendpoints0_next_value0 <= (pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_offset + s7pciephy_max_payload_size); + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_bufferizeendpoints0_next_value_ce0 <= 1'd1; + if (pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_end) begin + bufferizeendpoints0_next_state0 <= 2'd2; + end + end + end else begin + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_last <= 1'd1; + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_payload_length <= (pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_payload_length - pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_offset); + if (pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_source_ready) begin + bufferizeendpoints0_next_state0 <= 2'd2; + end + end + end + 2'd2: begin + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_ready <= 1'd1; + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_user_id_litepciedma0_bufferizeendpoints0_next_value1 <= (pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_user_id + 1'd1); + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_user_id_litepciedma0_bufferizeendpoints0_next_value_ce1 <= 1'd1; + bufferizeendpoints0_next_state0 <= 1'd0; + end + default: begin + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_bufferizeendpoints0_next_value0 <= 1'd0; + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_bufferizeendpoints0_next_value_ce0 <= 1'd1; + if (pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_valid) begin + bufferizeendpoints0_next_state0 <= 1'd1; + end else begin + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_sink_ready <= 1'd1; + end + end + endcase +end +assign pcie_dma0_writer_splitter_bufferizeendpoints_sink_ready = ((~pcie_dma0_writer_splitter_bufferizeendpoints_source_valid) | pcie_dma0_writer_splitter_bufferizeendpoints_source_ready); +assign pcie_dma0_writer_fifo_syncfifo_re1 = (pcie_dma0_writer_fifo_syncfifo_readable1 & ((~pcie_dma0_writer_fifo_readable) | pcie_dma0_writer_fifo_re)); +assign pcie_dma0_writer_fifo_level2 = (pcie_dma0_writer_fifo_level1 + pcie_dma0_writer_fifo_readable); +always @(*) begin + pcie_dma0_writer_fifo_wrport_adr1 <= 8'd0; + if (pcie_dma0_writer_fifo_replace1) begin + pcie_dma0_writer_fifo_wrport_adr1 <= (pcie_dma0_writer_fifo_produce1 - 1'd1); + end else begin + pcie_dma0_writer_fifo_wrport_adr1 <= pcie_dma0_writer_fifo_produce1; + end +end +assign pcie_dma0_writer_fifo_wrport_dat_w1 = pcie_dma0_writer_fifo_syncfifo_din1; +assign pcie_dma0_writer_fifo_wrport_we1 = (pcie_dma0_writer_fifo_syncfifo_we1 & (pcie_dma0_writer_fifo_syncfifo_writable1 | pcie_dma0_writer_fifo_replace1)); +assign pcie_dma0_writer_fifo_do_read1 = (pcie_dma0_writer_fifo_syncfifo_readable1 & pcie_dma0_writer_fifo_syncfifo_re1); +assign pcie_dma0_writer_fifo_rdport_adr1 = pcie_dma0_writer_fifo_consume1; +assign pcie_dma0_writer_fifo_syncfifo_dout1 = pcie_dma0_writer_fifo_rdport_dat_r1; +assign pcie_dma0_writer_fifo_rdport_re = pcie_dma0_writer_fifo_do_read1; +assign pcie_dma0_writer_fifo_syncfifo_writable1 = (pcie_dma0_writer_fifo_level1 != 9'd256); +assign pcie_dma0_writer_fifo_syncfifo_readable1 = (pcie_dma0_writer_fifo_level1 != 1'd0); +always @(*) begin + pcie_dma0_writer_counter_litepciedma0_fsm0_next_value <= 13'd0; + pcie_dma0_writer_splitter_bufferizeendpoints_source_ready <= 1'd0; + pcie_dma0_writer_counter_litepciedma0_fsm0_next_value_ce <= 1'd0; + pcie_dma0_writer_fifo_re <= 1'd0; + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_end <= 1'd0; + pcie_dma0_litepciemasterinternalport0_sink_valid <= 1'd0; + fsm0_next_state1 <= 1'd0; + fsm0_next_state1 <= fsm0_state1; + case (fsm0_state1) + 1'd1: begin + pcie_dma0_litepciemasterinternalport0_sink_valid <= 1'd1; + if (pcie_dma0_litepciemasterinternalport0_sink_ready) begin + pcie_dma0_writer_counter_litepciedma0_fsm0_next_value <= (pcie_dma0_writer_counter + 1'd1); + pcie_dma0_writer_counter_litepciedma0_fsm0_next_value_ce <= 1'd1; + pcie_dma0_writer_fifo_re <= (~(pcie_dma0_writer_fifo_syncfifo_dout1[64] & (~pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_control[1]))); + if (pcie_dma0_litepciemasterinternalport0_sink_last) begin + pcie_dma0_writer_fifo_re <= 1'd1; + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_end <= (pcie_dma0_writer_fifo_syncfifo_dout1[64] & (~pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_control[1])); + pcie_dma0_writer_splitter_bufferizeendpoints_source_ready <= 1'd1; + fsm0_next_state1 <= 1'd0; + end + end + end + default: begin + pcie_dma0_writer_counter_litepciedma0_fsm0_next_value <= 1'd0; + pcie_dma0_writer_counter_litepciedma0_fsm0_next_value_ce <= 1'd1; + if (pcie_dma0_writer_splitter_bufferizeendpoints_source_valid) begin + if ((pcie_dma0_writer_fifo_level2 >= pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_length[23:3])) begin + fsm0_next_state1 <= 1'd1; + end + end + end + endcase +end +assign pcie_dma0_reader_splitter_reset = (~pcie_dma0_reader_enable_storage); +assign pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_valid = pcie_dma0_reader_source_source_valid1; +assign pcie_dma0_reader_source_source_ready1 = pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_ready; +assign pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_first = pcie_dma0_reader_source_source_first1; +assign pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_last = pcie_dma0_reader_source_source_last1; +assign pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_payload_address = pcie_dma0_reader_source_source_payload_address; +assign pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_payload_length = pcie_dma0_reader_source_source_payload_length; +assign pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_payload_control = pcie_dma0_reader_source_source_payload_control; +assign pcie_dma0_reader_fifo_reset1 = (~pcie_dma0_reader_enable_storage); +assign pcie_dma0_reader_source_source_valid0 = pcie_dma0_reader_fifo_source_valid1; +assign pcie_dma0_reader_fifo_source_ready1 = pcie_dma0_reader_source_source_ready0; +assign pcie_dma0_reader_source_source_first0 = pcie_dma0_reader_fifo_source_first1; +assign pcie_dma0_reader_source_source_last0 = pcie_dma0_reader_fifo_source_last1; +assign pcie_dma0_reader_source_source_payload_data = pcie_dma0_reader_fifo_source_payload_data; +assign pcie_dma0_reader_fifo_sink_valid1 = pcie_dma0_litepciemasterinternalport1_source_valid; +assign pcie_dma0_reader_fifo_sink_first1 = (pcie_dma0_litepciemasterinternalport1_source_first & (pcie_dma0_litepciemasterinternalport1_source_payload_user_id != pcie_dma0_reader_last_user_id)); +assign pcie_dma0_reader_fifo_sink_payload_data = pcie_dma0_litepciemasterinternalport1_source_payload_dat; +assign pcie_dma0_litepciemasterinternalport1_source_ready = (pcie_dma0_reader_fifo_sink_ready1 | (~pcie_dma0_reader_enable_storage)); +assign pcie_dma0_litepciemasterinternalport1_sink_payload_channel = 1'd1; +assign pcie_dma0_litepciemasterinternalport1_sink_payload_user_id = pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_user_id; +assign pcie_dma0_litepciemasterinternalport1_sink_first = 1'd1; +assign pcie_dma0_litepciemasterinternalport1_sink_last = 1'd1; +assign pcie_dma0_litepciemasterinternalport1_sink_payload_we = 1'd0; +assign pcie_dma0_litepciemasterinternalport1_sink_payload_adr = pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_address; +assign pcie_dma0_litepciemasterinternalport1_sink_payload_len = pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_length[23:2]; +assign pcie_dma0_litepciemasterinternalport1_sink_payload_req_id = s7pciephy_id; +assign pcie_dma0_litepciemasterinternalport1_sink_payload_dat = 1'd0; +always @(*) begin + pcie_dma0_reader_pending_words_queue <= 11'd0; + if ((pcie_dma0_reader_splitter_bufferizeendpoints_source_valid & pcie_dma0_reader_splitter_bufferizeendpoints_source_ready)) begin + pcie_dma0_reader_pending_words_queue <= pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_length[23:3]; + end +end +always @(*) begin + pcie_dma0_reader_pending_words_dequeue <= 11'd0; + if ((pcie_dma0_reader_fifo_source_valid1 & pcie_dma0_reader_fifo_source_ready1)) begin + pcie_dma0_reader_pending_words_dequeue <= 1'd1; + end +end +assign pcie_dma0_reader_irq = (((pcie_dma0_reader_splitter_bufferizeendpoints_source_valid & pcie_dma0_reader_splitter_bufferizeendpoints_source_ready) & pcie_dma0_reader_splitter_bufferizeendpoints_source_last) & (~pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_control[0])); +assign pcie_dma0_reader_fifo_reset0 = (pcie_dma0_reader_flush_storage & pcie_dma0_reader_flush_re); +assign pcie_dma0_reader_level_status = pcie_dma0_reader_fifo_level0; +assign pcie_dma0_reader_source_source_valid1 = pcie_dma0_reader_fifo_source_valid0; +assign pcie_dma0_reader_source_source_first1 = pcie_dma0_reader_fifo_source_first0; +assign pcie_dma0_reader_fifo_source_ready0 = (pcie_dma0_reader_source_source_valid1 & pcie_dma0_reader_source_source_ready1); +assign pcie_dma0_reader_source_source_payload_address = pcie_dma0_reader_fifo_source_payload_address; +assign pcie_dma0_reader_source_source_payload_length = pcie_dma0_reader_fifo_source_payload_length; +assign pcie_dma0_reader_source_source_payload_control = pcie_dma0_reader_fifo_source_payload_control; +assign pcie_dma0_reader_fifo_syncfifo_din0 = {pcie_dma0_reader_fifo_fifo_in_last0, pcie_dma0_reader_fifo_fifo_in_first0, pcie_dma0_reader_fifo_fifo_in_payload_control, pcie_dma0_reader_fifo_fifo_in_payload_length, pcie_dma0_reader_fifo_fifo_in_payload_address}; +assign {pcie_dma0_reader_fifo_fifo_out_last0, pcie_dma0_reader_fifo_fifo_out_first0, pcie_dma0_reader_fifo_fifo_out_payload_control, pcie_dma0_reader_fifo_fifo_out_payload_length, pcie_dma0_reader_fifo_fifo_out_payload_address} = pcie_dma0_reader_fifo_syncfifo_dout0; +assign pcie_dma0_reader_fifo_sink_ready0 = pcie_dma0_reader_fifo_syncfifo_writable0; +assign pcie_dma0_reader_fifo_syncfifo_we0 = pcie_dma0_reader_fifo_sink_valid0; +assign pcie_dma0_reader_fifo_fifo_in_first0 = pcie_dma0_reader_fifo_sink_first0; +assign pcie_dma0_reader_fifo_fifo_in_last0 = pcie_dma0_reader_fifo_sink_last0; +assign pcie_dma0_reader_fifo_fifo_in_payload_address = pcie_dma0_reader_fifo_sink_payload_address; +assign pcie_dma0_reader_fifo_fifo_in_payload_length = pcie_dma0_reader_fifo_sink_payload_length; +assign pcie_dma0_reader_fifo_fifo_in_payload_control = pcie_dma0_reader_fifo_sink_payload_control; +assign pcie_dma0_reader_fifo_source_valid0 = pcie_dma0_reader_fifo_syncfifo_readable0; +assign pcie_dma0_reader_fifo_source_first0 = pcie_dma0_reader_fifo_fifo_out_first0; +assign pcie_dma0_reader_fifo_source_last0 = pcie_dma0_reader_fifo_fifo_out_last0; +assign pcie_dma0_reader_fifo_source_payload_address = pcie_dma0_reader_fifo_fifo_out_payload_address; +assign pcie_dma0_reader_fifo_source_payload_length = pcie_dma0_reader_fifo_fifo_out_payload_length; +assign pcie_dma0_reader_fifo_source_payload_control = pcie_dma0_reader_fifo_fifo_out_payload_control; +assign pcie_dma0_reader_fifo_syncfifo_re0 = pcie_dma0_reader_fifo_source_ready0; +always @(*) begin + pcie_dma0_reader_fifo_wrport_adr0 <= 8'd0; + if (pcie_dma0_reader_fifo_replace0) begin + pcie_dma0_reader_fifo_wrport_adr0 <= (pcie_dma0_reader_fifo_produce0 - 1'd1); + end else begin + pcie_dma0_reader_fifo_wrport_adr0 <= pcie_dma0_reader_fifo_produce0; + end +end +assign pcie_dma0_reader_fifo_wrport_dat_w0 = pcie_dma0_reader_fifo_syncfifo_din0; +assign pcie_dma0_reader_fifo_wrport_we0 = (pcie_dma0_reader_fifo_syncfifo_we0 & (pcie_dma0_reader_fifo_syncfifo_writable0 | pcie_dma0_reader_fifo_replace0)); +assign pcie_dma0_reader_fifo_do_read0 = (pcie_dma0_reader_fifo_syncfifo_readable0 & pcie_dma0_reader_fifo_syncfifo_re0); +assign pcie_dma0_reader_fifo_rdport_adr0 = pcie_dma0_reader_fifo_consume0; +assign pcie_dma0_reader_fifo_syncfifo_dout0 = pcie_dma0_reader_fifo_rdport_dat_r0; +assign pcie_dma0_reader_fifo_syncfifo_writable0 = (pcie_dma0_reader_fifo_level0 != 9'd256); +assign pcie_dma0_reader_fifo_syncfifo_readable0 = (pcie_dma0_reader_fifo_level0 != 1'd0); +assign pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_payload_address = (pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_payload_address + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_offset); +assign pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_payload_control = pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_payload_control; +assign pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_payload_user_id = pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_user_id; +assign pcie_dma0_reader_splitter_bufferizeendpoints_sink_valid = pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_valid; +assign pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_ready = pcie_dma0_reader_splitter_bufferizeendpoints_sink_ready; +assign pcie_dma0_reader_splitter_bufferizeendpoints_sink_first = pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_first; +assign pcie_dma0_reader_splitter_bufferizeendpoints_sink_last = pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_last; +assign pcie_dma0_reader_splitter_bufferizeendpoints_sink_payload_address = pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_payload_address; +assign pcie_dma0_reader_splitter_bufferizeendpoints_sink_payload_length = pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_payload_length; +assign pcie_dma0_reader_splitter_bufferizeendpoints_sink_payload_control = pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_payload_control; +assign pcie_dma0_reader_splitter_bufferizeendpoints_sink_payload_user_id = pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_payload_user_id; +always @(*) begin + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_valid <= 1'd0; + bufferizeendpoints0_next_state1 <= 2'd0; + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_first <= 1'd0; + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_next_value0 <= 32'd0; + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_last <= 1'd0; + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_next_value_ce0 <= 1'd0; + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_payload_length <= 24'd0; + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_user_id_litepciedma0_next_value1 <= 32'd0; + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_ready <= 1'd0; + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_user_id_litepciedma0_next_value_ce1 <= 1'd0; + bufferizeendpoints0_next_state1 <= bufferizeendpoints0_state1; + case (bufferizeendpoints0_state1) + 1'd1: begin + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_valid <= 1'd1; + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_first <= (pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_offset == 1'd0); + if (((pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_payload_length - pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_offset) > s7pciephy_max_request_size)) begin + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_last <= pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_end; + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_payload_length <= s7pciephy_max_request_size; + if (pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_ready) begin + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_next_value0 <= (pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_offset + s7pciephy_max_request_size); + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_next_value_ce0 <= 1'd1; + if (pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_end) begin + bufferizeendpoints0_next_state1 <= 2'd2; + end + end + end else begin + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_last <= 1'd1; + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_payload_length <= (pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_payload_length - pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_offset); + if (pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_source_ready) begin + bufferizeendpoints0_next_state1 <= 2'd2; + end + end + end + 2'd2: begin + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_ready <= 1'd1; + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_user_id_litepciedma0_next_value1 <= (pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_user_id + 1'd1); + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_user_id_litepciedma0_next_value_ce1 <= 1'd1; + bufferizeendpoints0_next_state1 <= 1'd0; + end + default: begin + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_next_value0 <= 1'd0; + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_next_value_ce0 <= 1'd1; + if (pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_valid) begin + bufferizeendpoints0_next_state1 <= 1'd1; + end else begin + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_sink_ready <= 1'd1; + end + end + endcase +end +assign pcie_dma0_reader_splitter_bufferizeendpoints_sink_ready = ((~pcie_dma0_reader_splitter_bufferizeendpoints_source_valid) | pcie_dma0_reader_splitter_bufferizeendpoints_source_ready); +assign pcie_dma0_reader_fifo_syncfifo_din1 = {pcie_dma0_reader_fifo_fifo_in_last1, pcie_dma0_reader_fifo_fifo_in_first1, pcie_dma0_reader_fifo_fifo_in_payload_data}; +assign {pcie_dma0_reader_fifo_fifo_out_last1, pcie_dma0_reader_fifo_fifo_out_first1, pcie_dma0_reader_fifo_fifo_out_payload_data} = pcie_dma0_reader_fifo_syncfifo_dout1; +assign pcie_dma0_reader_fifo_sink_ready1 = pcie_dma0_reader_fifo_syncfifo_writable1; +assign pcie_dma0_reader_fifo_syncfifo_we1 = pcie_dma0_reader_fifo_sink_valid1; +assign pcie_dma0_reader_fifo_fifo_in_first1 = pcie_dma0_reader_fifo_sink_first1; +assign pcie_dma0_reader_fifo_fifo_in_last1 = pcie_dma0_reader_fifo_sink_last1; +assign pcie_dma0_reader_fifo_fifo_in_payload_data = pcie_dma0_reader_fifo_sink_payload_data; +assign pcie_dma0_reader_fifo_source_valid1 = pcie_dma0_reader_fifo_readable; +assign pcie_dma0_reader_fifo_source_first1 = pcie_dma0_reader_fifo_fifo_out_first1; +assign pcie_dma0_reader_fifo_source_last1 = pcie_dma0_reader_fifo_fifo_out_last1; +assign pcie_dma0_reader_fifo_source_payload_data = pcie_dma0_reader_fifo_fifo_out_payload_data; +assign pcie_dma0_reader_fifo_re = pcie_dma0_reader_fifo_source_ready1; +assign pcie_dma0_reader_fifo_syncfifo_re1 = (pcie_dma0_reader_fifo_syncfifo_readable1 & ((~pcie_dma0_reader_fifo_readable) | pcie_dma0_reader_fifo_re)); +assign pcie_dma0_reader_fifo_level2 = (pcie_dma0_reader_fifo_level1 + pcie_dma0_reader_fifo_readable); +always @(*) begin + pcie_dma0_reader_fifo_wrport_adr1 <= 10'd0; + if (pcie_dma0_reader_fifo_replace1) begin + pcie_dma0_reader_fifo_wrport_adr1 <= (pcie_dma0_reader_fifo_produce1 - 1'd1); + end else begin + pcie_dma0_reader_fifo_wrport_adr1 <= pcie_dma0_reader_fifo_produce1; + end +end +assign pcie_dma0_reader_fifo_wrport_dat_w1 = pcie_dma0_reader_fifo_syncfifo_din1; +assign pcie_dma0_reader_fifo_wrport_we1 = (pcie_dma0_reader_fifo_syncfifo_we1 & (pcie_dma0_reader_fifo_syncfifo_writable1 | pcie_dma0_reader_fifo_replace1)); +assign pcie_dma0_reader_fifo_do_read1 = (pcie_dma0_reader_fifo_syncfifo_readable1 & pcie_dma0_reader_fifo_syncfifo_re1); +assign pcie_dma0_reader_fifo_rdport_adr1 = pcie_dma0_reader_fifo_consume1; +assign pcie_dma0_reader_fifo_syncfifo_dout1 = pcie_dma0_reader_fifo_rdport_dat_r1; +assign pcie_dma0_reader_fifo_rdport_re = pcie_dma0_reader_fifo_do_read1; +assign pcie_dma0_reader_fifo_syncfifo_writable1 = (pcie_dma0_reader_fifo_level1 != 11'd1024); +assign pcie_dma0_reader_fifo_syncfifo_readable1 = (pcie_dma0_reader_fifo_level1 != 1'd0); +always @(*) begin + fsm0_next_state2 <= 1'd0; + pcie_dma0_reader_splitter_bufferizeendpoints_source_ready <= 1'd0; + pcie_dma0_litepciemasterinternalport1_sink_valid <= 1'd0; + fsm0_next_state2 <= fsm0_state2; + case (fsm0_state2) + 1'd1: begin + pcie_dma0_litepciemasterinternalport1_sink_valid <= pcie_dma0_reader_enable_storage; + if ((pcie_dma0_litepciemasterinternalport1_sink_ready | (~pcie_dma0_reader_enable_storage))) begin + pcie_dma0_reader_splitter_bufferizeendpoints_source_ready <= 1'd1; + fsm0_next_state2 <= 1'd0; + end + end + default: begin + if (pcie_dma0_reader_splitter_bufferizeendpoints_source_valid) begin + if ((pcie_dma0_reader_pending_words < 10'd960)) begin + fsm0_next_state2 <= 1'd1; + end + end + end + endcase +end +always @(*) begin + pcie_dma0_loopback_source_last <= 1'd0; + pcie_dma0_loopback_source_payload_data <= 64'd0; + pcie_dma0_loopback_next_source_valid <= 1'd0; + pcie_dma0_loopback_next_source_first <= 1'd0; + pcie_dma0_loopback_next_source_last <= 1'd0; + pcie_dma0_loopback_next_source_payload_data <= 64'd0; + pcie_dma0_loopback_next_sink_ready <= 1'd0; + pcie_dma0_loopback_sink_ready <= 1'd0; + pcie_dma0_loopback_source_valid <= 1'd0; + pcie_dma0_loopback_source_first <= 1'd0; + if (pcie_dma0_loopback_storage) begin + pcie_dma0_loopback_source_valid <= pcie_dma0_loopback_sink_valid; + pcie_dma0_loopback_sink_ready <= pcie_dma0_loopback_source_ready; + pcie_dma0_loopback_source_first <= pcie_dma0_loopback_sink_first; + pcie_dma0_loopback_source_last <= pcie_dma0_loopback_sink_last; + pcie_dma0_loopback_source_payload_data <= pcie_dma0_loopback_sink_payload_data; + end else begin + pcie_dma0_loopback_next_source_valid <= pcie_dma0_loopback_sink_valid; + pcie_dma0_loopback_sink_ready <= pcie_dma0_loopback_next_source_ready; + pcie_dma0_loopback_next_source_first <= pcie_dma0_loopback_sink_first; + pcie_dma0_loopback_next_source_last <= pcie_dma0_loopback_sink_last; + pcie_dma0_loopback_next_source_payload_data <= pcie_dma0_loopback_sink_payload_data; + pcie_dma0_loopback_source_valid <= pcie_dma0_loopback_next_sink_valid; + pcie_dma0_loopback_next_sink_ready <= pcie_dma0_loopback_source_ready; + pcie_dma0_loopback_source_first <= pcie_dma0_loopback_next_sink_first; + pcie_dma0_loopback_source_last <= pcie_dma0_loopback_next_sink_last; + pcie_dma0_loopback_source_payload_data <= pcie_dma0_loopback_next_sink_payload_data; + end +end +assign pcie_dma0_buffering_reader_fifo_sink_first = pcie_dma0_buffering_sink_sink_first; +assign pcie_dma0_buffering_reader_fifo_sink_last = pcie_dma0_buffering_sink_sink_last; +assign pcie_dma0_buffering_reader_fifo_sink_payload_data = pcie_dma0_buffering_sink_sink_payload_data; +always @(*) begin + pcie_dma0_buffering_reader_fifo_sink_valid <= 1'd0; + pcie_dma0_buffering_sink_sink_ready <= 1'd0; + if ((pcie_dma0_buffering_reader_fifo_level1 < pcie_dma0_buffering_reader_fifo_depth_storage[10:3])) begin + pcie_dma0_buffering_reader_fifo_sink_valid <= pcie_dma0_buffering_sink_sink_valid; + pcie_dma0_buffering_sink_sink_ready <= pcie_dma0_buffering_reader_fifo_sink_ready; + end +end +assign pcie_dma0_buffering_next_source_valid = pcie_dma0_buffering_reader_fifo_source_valid; +assign pcie_dma0_buffering_reader_fifo_source_ready = pcie_dma0_buffering_next_source_ready; +assign pcie_dma0_buffering_next_source_first = pcie_dma0_buffering_reader_fifo_source_first; +assign pcie_dma0_buffering_next_source_last = pcie_dma0_buffering_reader_fifo_source_last; +assign pcie_dma0_buffering_next_source_payload_data = pcie_dma0_buffering_reader_fifo_source_payload_data; +assign pcie_dma0_buffering_writer_fifo_sink_first = pcie_dma0_buffering_next_sink_first; +assign pcie_dma0_buffering_writer_fifo_sink_last = pcie_dma0_buffering_next_sink_last; +assign pcie_dma0_buffering_writer_fifo_sink_payload_data = pcie_dma0_buffering_next_sink_payload_data; +always @(*) begin + pcie_dma0_buffering_next_sink_ready <= 1'd0; + pcie_dma0_buffering_writer_fifo_sink_valid <= 1'd0; + if ((pcie_dma0_buffering_writer_fifo_level1 < pcie_dma0_buffering_writer_fifo_depth_storage[10:3])) begin + pcie_dma0_buffering_writer_fifo_sink_valid <= pcie_dma0_buffering_next_sink_valid; + pcie_dma0_buffering_next_sink_ready <= pcie_dma0_buffering_writer_fifo_sink_ready; + end +end +assign pcie_dma0_buffering_source_source_valid = pcie_dma0_buffering_writer_fifo_source_valid; +assign pcie_dma0_buffering_writer_fifo_source_ready = pcie_dma0_buffering_source_source_ready; +assign pcie_dma0_buffering_source_source_first = pcie_dma0_buffering_writer_fifo_source_first; +assign pcie_dma0_buffering_source_source_last = pcie_dma0_buffering_writer_fifo_source_last; +assign pcie_dma0_buffering_source_source_payload_data = pcie_dma0_buffering_writer_fifo_source_payload_data; +assign pcie_dma0_buffering_reader_fifo_level_status[10:3] = pcie_dma0_buffering_reader_fifo_level1; +assign pcie_dma0_buffering_writer_fifo_level_status[10:3] = pcie_dma0_buffering_writer_fifo_level1; +assign pcie_dma0_buffering_reader_fifo_syncfifo_din = {pcie_dma0_buffering_reader_fifo_fifo_in_last, pcie_dma0_buffering_reader_fifo_fifo_in_first, pcie_dma0_buffering_reader_fifo_fifo_in_payload_data}; +assign {pcie_dma0_buffering_reader_fifo_fifo_out_last, pcie_dma0_buffering_reader_fifo_fifo_out_first, pcie_dma0_buffering_reader_fifo_fifo_out_payload_data} = pcie_dma0_buffering_reader_fifo_syncfifo_dout; +assign pcie_dma0_buffering_reader_fifo_sink_ready = pcie_dma0_buffering_reader_fifo_syncfifo_writable; +assign pcie_dma0_buffering_reader_fifo_syncfifo_we = pcie_dma0_buffering_reader_fifo_sink_valid; +assign pcie_dma0_buffering_reader_fifo_fifo_in_first = pcie_dma0_buffering_reader_fifo_sink_first; +assign pcie_dma0_buffering_reader_fifo_fifo_in_last = pcie_dma0_buffering_reader_fifo_sink_last; +assign pcie_dma0_buffering_reader_fifo_fifo_in_payload_data = pcie_dma0_buffering_reader_fifo_sink_payload_data; +assign pcie_dma0_buffering_reader_fifo_source_valid = pcie_dma0_buffering_reader_fifo_readable; +assign pcie_dma0_buffering_reader_fifo_source_first = pcie_dma0_buffering_reader_fifo_fifo_out_first; +assign pcie_dma0_buffering_reader_fifo_source_last = pcie_dma0_buffering_reader_fifo_fifo_out_last; +assign pcie_dma0_buffering_reader_fifo_source_payload_data = pcie_dma0_buffering_reader_fifo_fifo_out_payload_data; +assign pcie_dma0_buffering_reader_fifo_re = pcie_dma0_buffering_reader_fifo_source_ready; +assign pcie_dma0_buffering_reader_fifo_syncfifo_re = (pcie_dma0_buffering_reader_fifo_syncfifo_readable & ((~pcie_dma0_buffering_reader_fifo_readable) | pcie_dma0_buffering_reader_fifo_re)); +assign pcie_dma0_buffering_reader_fifo_level1 = (pcie_dma0_buffering_reader_fifo_level0 + pcie_dma0_buffering_reader_fifo_readable); +always @(*) begin + pcie_dma0_buffering_reader_fifo_wrport_adr <= 7'd0; + if (pcie_dma0_buffering_reader_fifo_replace) begin + pcie_dma0_buffering_reader_fifo_wrport_adr <= (pcie_dma0_buffering_reader_fifo_produce - 1'd1); + end else begin + pcie_dma0_buffering_reader_fifo_wrport_adr <= pcie_dma0_buffering_reader_fifo_produce; + end +end +assign pcie_dma0_buffering_reader_fifo_wrport_dat_w = pcie_dma0_buffering_reader_fifo_syncfifo_din; +assign pcie_dma0_buffering_reader_fifo_wrport_we = (pcie_dma0_buffering_reader_fifo_syncfifo_we & (pcie_dma0_buffering_reader_fifo_syncfifo_writable | pcie_dma0_buffering_reader_fifo_replace)); +assign pcie_dma0_buffering_reader_fifo_do_read = (pcie_dma0_buffering_reader_fifo_syncfifo_readable & pcie_dma0_buffering_reader_fifo_syncfifo_re); +assign pcie_dma0_buffering_reader_fifo_rdport_adr = pcie_dma0_buffering_reader_fifo_consume; +assign pcie_dma0_buffering_reader_fifo_syncfifo_dout = pcie_dma0_buffering_reader_fifo_rdport_dat_r; +assign pcie_dma0_buffering_reader_fifo_rdport_re = pcie_dma0_buffering_reader_fifo_do_read; +assign pcie_dma0_buffering_reader_fifo_syncfifo_writable = (pcie_dma0_buffering_reader_fifo_level0 != 8'd128); +assign pcie_dma0_buffering_reader_fifo_syncfifo_readable = (pcie_dma0_buffering_reader_fifo_level0 != 1'd0); +assign pcie_dma0_buffering_writer_fifo_syncfifo_din = {pcie_dma0_buffering_writer_fifo_fifo_in_last, pcie_dma0_buffering_writer_fifo_fifo_in_first, pcie_dma0_buffering_writer_fifo_fifo_in_payload_data}; +assign {pcie_dma0_buffering_writer_fifo_fifo_out_last, pcie_dma0_buffering_writer_fifo_fifo_out_first, pcie_dma0_buffering_writer_fifo_fifo_out_payload_data} = pcie_dma0_buffering_writer_fifo_syncfifo_dout; +assign pcie_dma0_buffering_writer_fifo_sink_ready = pcie_dma0_buffering_writer_fifo_syncfifo_writable; +assign pcie_dma0_buffering_writer_fifo_syncfifo_we = pcie_dma0_buffering_writer_fifo_sink_valid; +assign pcie_dma0_buffering_writer_fifo_fifo_in_first = pcie_dma0_buffering_writer_fifo_sink_first; +assign pcie_dma0_buffering_writer_fifo_fifo_in_last = pcie_dma0_buffering_writer_fifo_sink_last; +assign pcie_dma0_buffering_writer_fifo_fifo_in_payload_data = pcie_dma0_buffering_writer_fifo_sink_payload_data; +assign pcie_dma0_buffering_writer_fifo_source_valid = pcie_dma0_buffering_writer_fifo_readable; +assign pcie_dma0_buffering_writer_fifo_source_first = pcie_dma0_buffering_writer_fifo_fifo_out_first; +assign pcie_dma0_buffering_writer_fifo_source_last = pcie_dma0_buffering_writer_fifo_fifo_out_last; +assign pcie_dma0_buffering_writer_fifo_source_payload_data = pcie_dma0_buffering_writer_fifo_fifo_out_payload_data; +assign pcie_dma0_buffering_writer_fifo_re = pcie_dma0_buffering_writer_fifo_source_ready; +assign pcie_dma0_buffering_writer_fifo_syncfifo_re = (pcie_dma0_buffering_writer_fifo_syncfifo_readable & ((~pcie_dma0_buffering_writer_fifo_readable) | pcie_dma0_buffering_writer_fifo_re)); +assign pcie_dma0_buffering_writer_fifo_level1 = (pcie_dma0_buffering_writer_fifo_level0 + pcie_dma0_buffering_writer_fifo_readable); +always @(*) begin + pcie_dma0_buffering_writer_fifo_wrport_adr <= 7'd0; + if (pcie_dma0_buffering_writer_fifo_replace) begin + pcie_dma0_buffering_writer_fifo_wrport_adr <= (pcie_dma0_buffering_writer_fifo_produce - 1'd1); + end else begin + pcie_dma0_buffering_writer_fifo_wrport_adr <= pcie_dma0_buffering_writer_fifo_produce; + end +end +assign pcie_dma0_buffering_writer_fifo_wrport_dat_w = pcie_dma0_buffering_writer_fifo_syncfifo_din; +assign pcie_dma0_buffering_writer_fifo_wrport_we = (pcie_dma0_buffering_writer_fifo_syncfifo_we & (pcie_dma0_buffering_writer_fifo_syncfifo_writable | pcie_dma0_buffering_writer_fifo_replace)); +assign pcie_dma0_buffering_writer_fifo_do_read = (pcie_dma0_buffering_writer_fifo_syncfifo_readable & pcie_dma0_buffering_writer_fifo_syncfifo_re); +assign pcie_dma0_buffering_writer_fifo_rdport_adr = pcie_dma0_buffering_writer_fifo_consume; +assign pcie_dma0_buffering_writer_fifo_syncfifo_dout = pcie_dma0_buffering_writer_fifo_rdport_dat_r; +assign pcie_dma0_buffering_writer_fifo_rdport_re = pcie_dma0_buffering_writer_fifo_do_read; +assign pcie_dma0_buffering_writer_fifo_syncfifo_writable = (pcie_dma0_buffering_writer_fifo_level0 != 8'd128); +assign pcie_dma0_buffering_writer_fifo_syncfifo_readable = (pcie_dma0_buffering_writer_fifo_level0 != 1'd0); +assign pcie_dma1_loopback_sink_valid = pcie_dma1_reader_source_source_valid0; +assign pcie_dma1_reader_source_source_ready0 = pcie_dma1_loopback_sink_ready; +assign pcie_dma1_loopback_sink_first = pcie_dma1_reader_source_source_first0; +assign pcie_dma1_loopback_sink_last = pcie_dma1_reader_source_source_last0; +assign pcie_dma1_loopback_sink_payload_data = pcie_dma1_reader_source_source_payload_data; +assign pcie_dma1_writer_sink_valid = pcie_dma1_loopback_source_valid; +assign pcie_dma1_loopback_source_ready = pcie_dma1_writer_sink_ready; +assign pcie_dma1_writer_sink_first = pcie_dma1_loopback_source_first; +assign pcie_dma1_writer_sink_last = pcie_dma1_loopback_source_last; +assign pcie_dma1_writer_sink_payload_data = pcie_dma1_loopback_source_payload_data; +assign pcie_dma1_buffering_sink_sink_valid = pcie_dma1_loopback_next_source_valid; +assign pcie_dma1_loopback_next_source_ready = pcie_dma1_buffering_sink_sink_ready; +assign pcie_dma1_buffering_sink_sink_first = pcie_dma1_loopback_next_source_first; +assign pcie_dma1_buffering_sink_sink_last = pcie_dma1_loopback_next_source_last; +assign pcie_dma1_buffering_sink_sink_payload_data = pcie_dma1_loopback_next_source_payload_data; +assign pcie_dma1_loopback_next_sink_valid = pcie_dma1_buffering_source_source_valid; +assign pcie_dma1_buffering_source_source_ready = pcie_dma1_loopback_next_sink_ready; +assign pcie_dma1_loopback_next_sink_first = pcie_dma1_buffering_source_source_first; +assign pcie_dma1_loopback_next_sink_last = pcie_dma1_buffering_source_source_last; +assign pcie_dma1_loopback_next_sink_payload_data = pcie_dma1_buffering_source_source_payload_data; +assign pcie_dma1_writer_splitter_reset = (~pcie_dma1_writer_enable_storage); +assign pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_valid = pcie_dma1_writer_source_source_valid; +assign pcie_dma1_writer_source_source_ready = pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_ready; +assign pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_first = pcie_dma1_writer_source_source_first; +assign pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_last = pcie_dma1_writer_source_source_last; +assign pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_payload_address = pcie_dma1_writer_source_source_payload_address; +assign pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_payload_length = pcie_dma1_writer_source_source_payload_length; +assign pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_payload_control = pcie_dma1_writer_source_source_payload_control; +assign pcie_dma1_writer_fifo_syncfifo_we1 = (pcie_dma1_writer_sink_valid & pcie_dma1_writer_enable_storage); +assign pcie_dma1_writer_sink_ready = (pcie_dma1_writer_fifo_syncfifo_writable1 | (~pcie_dma1_writer_enable_storage)); +assign pcie_dma1_writer_fifo_syncfifo_din1 = {pcie_dma1_writer_sink_last, pcie_dma1_writer_sink_payload_data}; +assign pcie_dma1_writer_resetinserter_reset = (~pcie_dma1_writer_enable_storage); +assign pcie_dma1_litepciemasterinternalport0_sink_payload_channel = 2'd2; +assign pcie_dma1_litepciemasterinternalport0_sink_payload_user_id = pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_user_id; +assign pcie_dma1_litepciemasterinternalport0_sink_first = (pcie_dma1_writer_counter == 1'd0); +assign pcie_dma1_litepciemasterinternalport0_sink_last = ((~pcie_dma1_writer_enable_storage) | (pcie_dma1_writer_counter == (pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_length[23:3] - 1'd1))); +assign pcie_dma1_litepciemasterinternalport0_sink_payload_we = 1'd1; +assign pcie_dma1_litepciemasterinternalport0_sink_payload_adr = pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_address; +assign pcie_dma1_litepciemasterinternalport0_sink_payload_req_id = s7pciephy_id; +assign pcie_dma1_litepciemasterinternalport0_sink_payload_tag = 1'd0; +assign pcie_dma1_litepciemasterinternalport0_sink_payload_len = pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_length[23:2]; +assign pcie_dma1_litepciemasterinternalport0_sink_payload_dat = pcie_dma1_writer_fifo_syncfifo_dout1[63:0]; +assign pcie_dma1_writer_irq = (((pcie_dma1_writer_splitter_bufferizeendpoints_source_valid & pcie_dma1_writer_splitter_bufferizeendpoints_source_ready) & pcie_dma1_writer_splitter_bufferizeendpoints_source_last) & (~pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_control[0])); +assign pcie_dma1_writer_fifo_reset = (pcie_dma1_writer_flush_storage & pcie_dma1_writer_flush_re); +assign pcie_dma1_writer_level_status = pcie_dma1_writer_fifo_level0; +assign pcie_dma1_writer_source_source_valid = pcie_dma1_writer_fifo_source_valid; +assign pcie_dma1_writer_source_source_first = pcie_dma1_writer_fifo_source_first; +assign pcie_dma1_writer_fifo_source_ready = (pcie_dma1_writer_source_source_valid & pcie_dma1_writer_source_source_ready); +assign pcie_dma1_writer_source_source_payload_address = pcie_dma1_writer_fifo_source_payload_address; +assign pcie_dma1_writer_source_source_payload_length = pcie_dma1_writer_fifo_source_payload_length; +assign pcie_dma1_writer_source_source_payload_control = pcie_dma1_writer_fifo_source_payload_control; +assign pcie_dma1_writer_fifo_syncfifo_din0 = {pcie_dma1_writer_fifo_fifo_in_last, pcie_dma1_writer_fifo_fifo_in_first, pcie_dma1_writer_fifo_fifo_in_payload_control, pcie_dma1_writer_fifo_fifo_in_payload_length, pcie_dma1_writer_fifo_fifo_in_payload_address}; +assign {pcie_dma1_writer_fifo_fifo_out_last, pcie_dma1_writer_fifo_fifo_out_first, pcie_dma1_writer_fifo_fifo_out_payload_control, pcie_dma1_writer_fifo_fifo_out_payload_length, pcie_dma1_writer_fifo_fifo_out_payload_address} = pcie_dma1_writer_fifo_syncfifo_dout0; +assign pcie_dma1_writer_fifo_sink_ready = pcie_dma1_writer_fifo_syncfifo_writable0; +assign pcie_dma1_writer_fifo_syncfifo_we0 = pcie_dma1_writer_fifo_sink_valid; +assign pcie_dma1_writer_fifo_fifo_in_first = pcie_dma1_writer_fifo_sink_first; +assign pcie_dma1_writer_fifo_fifo_in_last = pcie_dma1_writer_fifo_sink_last; +assign pcie_dma1_writer_fifo_fifo_in_payload_address = pcie_dma1_writer_fifo_sink_payload_address; +assign pcie_dma1_writer_fifo_fifo_in_payload_length = pcie_dma1_writer_fifo_sink_payload_length; +assign pcie_dma1_writer_fifo_fifo_in_payload_control = pcie_dma1_writer_fifo_sink_payload_control; +assign pcie_dma1_writer_fifo_source_valid = pcie_dma1_writer_fifo_syncfifo_readable0; +assign pcie_dma1_writer_fifo_source_first = pcie_dma1_writer_fifo_fifo_out_first; +assign pcie_dma1_writer_fifo_source_last = pcie_dma1_writer_fifo_fifo_out_last; +assign pcie_dma1_writer_fifo_source_payload_address = pcie_dma1_writer_fifo_fifo_out_payload_address; +assign pcie_dma1_writer_fifo_source_payload_length = pcie_dma1_writer_fifo_fifo_out_payload_length; +assign pcie_dma1_writer_fifo_source_payload_control = pcie_dma1_writer_fifo_fifo_out_payload_control; +assign pcie_dma1_writer_fifo_syncfifo_re0 = pcie_dma1_writer_fifo_source_ready; +always @(*) begin + pcie_dma1_writer_fifo_wrport_adr0 <= 8'd0; + if (pcie_dma1_writer_fifo_replace0) begin + pcie_dma1_writer_fifo_wrport_adr0 <= (pcie_dma1_writer_fifo_produce0 - 1'd1); + end else begin + pcie_dma1_writer_fifo_wrport_adr0 <= pcie_dma1_writer_fifo_produce0; + end +end +assign pcie_dma1_writer_fifo_wrport_dat_w0 = pcie_dma1_writer_fifo_syncfifo_din0; +assign pcie_dma1_writer_fifo_wrport_we0 = (pcie_dma1_writer_fifo_syncfifo_we0 & (pcie_dma1_writer_fifo_syncfifo_writable0 | pcie_dma1_writer_fifo_replace0)); +assign pcie_dma1_writer_fifo_do_read0 = (pcie_dma1_writer_fifo_syncfifo_readable0 & pcie_dma1_writer_fifo_syncfifo_re0); +assign pcie_dma1_writer_fifo_rdport_adr0 = pcie_dma1_writer_fifo_consume0; +assign pcie_dma1_writer_fifo_syncfifo_dout0 = pcie_dma1_writer_fifo_rdport_dat_r0; +assign pcie_dma1_writer_fifo_syncfifo_writable0 = (pcie_dma1_writer_fifo_level0 != 9'd256); +assign pcie_dma1_writer_fifo_syncfifo_readable0 = (pcie_dma1_writer_fifo_level0 != 1'd0); +assign pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_payload_address = (pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_payload_address + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_offset); +assign pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_payload_control = pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_payload_control; +assign pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_payload_user_id = pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_user_id; +assign pcie_dma1_writer_splitter_bufferizeendpoints_sink_valid = pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_valid; +assign pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_ready = pcie_dma1_writer_splitter_bufferizeendpoints_sink_ready; +assign pcie_dma1_writer_splitter_bufferizeendpoints_sink_first = pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_first; +assign pcie_dma1_writer_splitter_bufferizeendpoints_sink_last = pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_last; +assign pcie_dma1_writer_splitter_bufferizeendpoints_sink_payload_address = pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_payload_address; +assign pcie_dma1_writer_splitter_bufferizeendpoints_sink_payload_length = pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_payload_length; +assign pcie_dma1_writer_splitter_bufferizeendpoints_sink_payload_control = pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_payload_control; +assign pcie_dma1_writer_splitter_bufferizeendpoints_sink_payload_user_id = pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_payload_user_id; +always @(*) begin + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_ready <= 1'd0; + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_user_id_litepciedma1_bufferizeendpoints1_next_value1 <= 32'd0; + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_user_id_litepciedma1_bufferizeendpoints1_next_value_ce1 <= 1'd0; + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_valid <= 1'd0; + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_first <= 1'd0; + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_last <= 1'd0; + bufferizeendpoints1_next_state0 <= 2'd0; + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_payload_length <= 24'd0; + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_bufferizeendpoints1_next_value0 <= 32'd0; + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_bufferizeendpoints1_next_value_ce0 <= 1'd0; + bufferizeendpoints1_next_state0 <= bufferizeendpoints1_state0; + case (bufferizeendpoints1_state0) + 1'd1: begin + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_valid <= 1'd1; + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_first <= (pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_offset == 1'd0); + if (((pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_payload_length - pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_offset) > s7pciephy_max_payload_size)) begin + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_last <= pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_end; + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_payload_length <= s7pciephy_max_payload_size; + if (pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_ready) begin + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_bufferizeendpoints1_next_value0 <= (pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_offset + s7pciephy_max_payload_size); + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_bufferizeendpoints1_next_value_ce0 <= 1'd1; + if (pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_end) begin + bufferizeendpoints1_next_state0 <= 2'd2; + end + end + end else begin + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_last <= 1'd1; + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_payload_length <= (pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_payload_length - pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_offset); + if (pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_source_ready) begin + bufferizeendpoints1_next_state0 <= 2'd2; + end + end + end + 2'd2: begin + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_ready <= 1'd1; + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_user_id_litepciedma1_bufferizeendpoints1_next_value1 <= (pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_user_id + 1'd1); + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_user_id_litepciedma1_bufferizeendpoints1_next_value_ce1 <= 1'd1; + bufferizeendpoints1_next_state0 <= 1'd0; + end + default: begin + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_bufferizeendpoints1_next_value0 <= 1'd0; + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_bufferizeendpoints1_next_value_ce0 <= 1'd1; + if (pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_valid) begin + bufferizeendpoints1_next_state0 <= 1'd1; + end else begin + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_sink_ready <= 1'd1; + end + end + endcase +end +assign pcie_dma1_writer_splitter_bufferizeendpoints_sink_ready = ((~pcie_dma1_writer_splitter_bufferizeendpoints_source_valid) | pcie_dma1_writer_splitter_bufferizeendpoints_source_ready); +assign pcie_dma1_writer_fifo_syncfifo_re1 = (pcie_dma1_writer_fifo_syncfifo_readable1 & ((~pcie_dma1_writer_fifo_readable) | pcie_dma1_writer_fifo_re)); +assign pcie_dma1_writer_fifo_level2 = (pcie_dma1_writer_fifo_level1 + pcie_dma1_writer_fifo_readable); +always @(*) begin + pcie_dma1_writer_fifo_wrport_adr1 <= 8'd0; + if (pcie_dma1_writer_fifo_replace1) begin + pcie_dma1_writer_fifo_wrport_adr1 <= (pcie_dma1_writer_fifo_produce1 - 1'd1); + end else begin + pcie_dma1_writer_fifo_wrport_adr1 <= pcie_dma1_writer_fifo_produce1; + end +end +assign pcie_dma1_writer_fifo_wrport_dat_w1 = pcie_dma1_writer_fifo_syncfifo_din1; +assign pcie_dma1_writer_fifo_wrport_we1 = (pcie_dma1_writer_fifo_syncfifo_we1 & (pcie_dma1_writer_fifo_syncfifo_writable1 | pcie_dma1_writer_fifo_replace1)); +assign pcie_dma1_writer_fifo_do_read1 = (pcie_dma1_writer_fifo_syncfifo_readable1 & pcie_dma1_writer_fifo_syncfifo_re1); +assign pcie_dma1_writer_fifo_rdport_adr1 = pcie_dma1_writer_fifo_consume1; +assign pcie_dma1_writer_fifo_syncfifo_dout1 = pcie_dma1_writer_fifo_rdport_dat_r1; +assign pcie_dma1_writer_fifo_rdport_re = pcie_dma1_writer_fifo_do_read1; +assign pcie_dma1_writer_fifo_syncfifo_writable1 = (pcie_dma1_writer_fifo_level1 != 9'd256); +assign pcie_dma1_writer_fifo_syncfifo_readable1 = (pcie_dma1_writer_fifo_level1 != 1'd0); +always @(*) begin + pcie_dma1_writer_splitter_bufferizeendpoints_source_ready <= 1'd0; + fsm1_next_state1 <= 1'd0; + pcie_dma1_writer_counter_litepciedma1_fsm1_next_value <= 13'd0; + pcie_dma1_writer_counter_litepciedma1_fsm1_next_value_ce <= 1'd0; + pcie_dma1_writer_fifo_re <= 1'd0; + pcie_dma1_litepciemasterinternalport0_sink_valid <= 1'd0; + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_end <= 1'd0; + fsm1_next_state1 <= fsm1_state1; + case (fsm1_state1) + 1'd1: begin + pcie_dma1_litepciemasterinternalport0_sink_valid <= 1'd1; + if (pcie_dma1_litepciemasterinternalport0_sink_ready) begin + pcie_dma1_writer_counter_litepciedma1_fsm1_next_value <= (pcie_dma1_writer_counter + 1'd1); + pcie_dma1_writer_counter_litepciedma1_fsm1_next_value_ce <= 1'd1; + pcie_dma1_writer_fifo_re <= (~(pcie_dma1_writer_fifo_syncfifo_dout1[64] & (~pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_control[1]))); + if (pcie_dma1_litepciemasterinternalport0_sink_last) begin + pcie_dma1_writer_fifo_re <= 1'd1; + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_end <= (pcie_dma1_writer_fifo_syncfifo_dout1[64] & (~pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_control[1])); + pcie_dma1_writer_splitter_bufferizeendpoints_source_ready <= 1'd1; + fsm1_next_state1 <= 1'd0; + end + end + end + default: begin + pcie_dma1_writer_counter_litepciedma1_fsm1_next_value <= 1'd0; + pcie_dma1_writer_counter_litepciedma1_fsm1_next_value_ce <= 1'd1; + if (pcie_dma1_writer_splitter_bufferizeendpoints_source_valid) begin + if ((pcie_dma1_writer_fifo_level2 >= pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_length[23:3])) begin + fsm1_next_state1 <= 1'd1; + end + end + end + endcase +end +assign pcie_dma1_reader_splitter_reset = (~pcie_dma1_reader_enable_storage); +assign pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_valid = pcie_dma1_reader_source_source_valid1; +assign pcie_dma1_reader_source_source_ready1 = pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_ready; +assign pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_first = pcie_dma1_reader_source_source_first1; +assign pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_last = pcie_dma1_reader_source_source_last1; +assign pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_payload_address = pcie_dma1_reader_source_source_payload_address; +assign pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_payload_length = pcie_dma1_reader_source_source_payload_length; +assign pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_payload_control = pcie_dma1_reader_source_source_payload_control; +assign pcie_dma1_reader_fifo_reset1 = (~pcie_dma1_reader_enable_storage); +assign pcie_dma1_reader_source_source_valid0 = pcie_dma1_reader_fifo_source_valid1; +assign pcie_dma1_reader_fifo_source_ready1 = pcie_dma1_reader_source_source_ready0; +assign pcie_dma1_reader_source_source_first0 = pcie_dma1_reader_fifo_source_first1; +assign pcie_dma1_reader_source_source_last0 = pcie_dma1_reader_fifo_source_last1; +assign pcie_dma1_reader_source_source_payload_data = pcie_dma1_reader_fifo_source_payload_data; +assign pcie_dma1_reader_fifo_sink_valid1 = pcie_dma1_litepciemasterinternalport1_source_valid; +assign pcie_dma1_reader_fifo_sink_first1 = (pcie_dma1_litepciemasterinternalport1_source_first & (pcie_dma1_litepciemasterinternalport1_source_payload_user_id != pcie_dma1_reader_last_user_id)); +assign pcie_dma1_reader_fifo_sink_payload_data = pcie_dma1_litepciemasterinternalport1_source_payload_dat; +assign pcie_dma1_litepciemasterinternalport1_source_ready = (pcie_dma1_reader_fifo_sink_ready1 | (~pcie_dma1_reader_enable_storage)); +assign pcie_dma1_litepciemasterinternalport1_sink_payload_channel = 2'd3; +assign pcie_dma1_litepciemasterinternalport1_sink_payload_user_id = pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_user_id; +assign pcie_dma1_litepciemasterinternalport1_sink_first = 1'd1; +assign pcie_dma1_litepciemasterinternalport1_sink_last = 1'd1; +assign pcie_dma1_litepciemasterinternalport1_sink_payload_we = 1'd0; +assign pcie_dma1_litepciemasterinternalport1_sink_payload_adr = pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_address; +assign pcie_dma1_litepciemasterinternalport1_sink_payload_len = pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_length[23:2]; +assign pcie_dma1_litepciemasterinternalport1_sink_payload_req_id = s7pciephy_id; +assign pcie_dma1_litepciemasterinternalport1_sink_payload_dat = 1'd0; +always @(*) begin + pcie_dma1_reader_pending_words_queue <= 11'd0; + if ((pcie_dma1_reader_splitter_bufferizeendpoints_source_valid & pcie_dma1_reader_splitter_bufferizeendpoints_source_ready)) begin + pcie_dma1_reader_pending_words_queue <= pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_length[23:3]; + end +end +always @(*) begin + pcie_dma1_reader_pending_words_dequeue <= 11'd0; + if ((pcie_dma1_reader_fifo_source_valid1 & pcie_dma1_reader_fifo_source_ready1)) begin + pcie_dma1_reader_pending_words_dequeue <= 1'd1; + end +end +assign pcie_dma1_reader_irq = (((pcie_dma1_reader_splitter_bufferizeendpoints_source_valid & pcie_dma1_reader_splitter_bufferizeendpoints_source_ready) & pcie_dma1_reader_splitter_bufferizeendpoints_source_last) & (~pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_control[0])); +assign pcie_dma1_reader_fifo_reset0 = (pcie_dma1_reader_flush_storage & pcie_dma1_reader_flush_re); +assign pcie_dma1_reader_level_status = pcie_dma1_reader_fifo_level0; +assign pcie_dma1_reader_source_source_valid1 = pcie_dma1_reader_fifo_source_valid0; +assign pcie_dma1_reader_source_source_first1 = pcie_dma1_reader_fifo_source_first0; +assign pcie_dma1_reader_fifo_source_ready0 = (pcie_dma1_reader_source_source_valid1 & pcie_dma1_reader_source_source_ready1); +assign pcie_dma1_reader_source_source_payload_address = pcie_dma1_reader_fifo_source_payload_address; +assign pcie_dma1_reader_source_source_payload_length = pcie_dma1_reader_fifo_source_payload_length; +assign pcie_dma1_reader_source_source_payload_control = pcie_dma1_reader_fifo_source_payload_control; +assign pcie_dma1_reader_fifo_syncfifo_din0 = {pcie_dma1_reader_fifo_fifo_in_last0, pcie_dma1_reader_fifo_fifo_in_first0, pcie_dma1_reader_fifo_fifo_in_payload_control, pcie_dma1_reader_fifo_fifo_in_payload_length, pcie_dma1_reader_fifo_fifo_in_payload_address}; +assign {pcie_dma1_reader_fifo_fifo_out_last0, pcie_dma1_reader_fifo_fifo_out_first0, pcie_dma1_reader_fifo_fifo_out_payload_control, pcie_dma1_reader_fifo_fifo_out_payload_length, pcie_dma1_reader_fifo_fifo_out_payload_address} = pcie_dma1_reader_fifo_syncfifo_dout0; +assign pcie_dma1_reader_fifo_sink_ready0 = pcie_dma1_reader_fifo_syncfifo_writable0; +assign pcie_dma1_reader_fifo_syncfifo_we0 = pcie_dma1_reader_fifo_sink_valid0; +assign pcie_dma1_reader_fifo_fifo_in_first0 = pcie_dma1_reader_fifo_sink_first0; +assign pcie_dma1_reader_fifo_fifo_in_last0 = pcie_dma1_reader_fifo_sink_last0; +assign pcie_dma1_reader_fifo_fifo_in_payload_address = pcie_dma1_reader_fifo_sink_payload_address; +assign pcie_dma1_reader_fifo_fifo_in_payload_length = pcie_dma1_reader_fifo_sink_payload_length; +assign pcie_dma1_reader_fifo_fifo_in_payload_control = pcie_dma1_reader_fifo_sink_payload_control; +assign pcie_dma1_reader_fifo_source_valid0 = pcie_dma1_reader_fifo_syncfifo_readable0; +assign pcie_dma1_reader_fifo_source_first0 = pcie_dma1_reader_fifo_fifo_out_first0; +assign pcie_dma1_reader_fifo_source_last0 = pcie_dma1_reader_fifo_fifo_out_last0; +assign pcie_dma1_reader_fifo_source_payload_address = pcie_dma1_reader_fifo_fifo_out_payload_address; +assign pcie_dma1_reader_fifo_source_payload_length = pcie_dma1_reader_fifo_fifo_out_payload_length; +assign pcie_dma1_reader_fifo_source_payload_control = pcie_dma1_reader_fifo_fifo_out_payload_control; +assign pcie_dma1_reader_fifo_syncfifo_re0 = pcie_dma1_reader_fifo_source_ready0; +always @(*) begin + pcie_dma1_reader_fifo_wrport_adr0 <= 8'd0; + if (pcie_dma1_reader_fifo_replace0) begin + pcie_dma1_reader_fifo_wrport_adr0 <= (pcie_dma1_reader_fifo_produce0 - 1'd1); + end else begin + pcie_dma1_reader_fifo_wrport_adr0 <= pcie_dma1_reader_fifo_produce0; + end +end +assign pcie_dma1_reader_fifo_wrport_dat_w0 = pcie_dma1_reader_fifo_syncfifo_din0; +assign pcie_dma1_reader_fifo_wrport_we0 = (pcie_dma1_reader_fifo_syncfifo_we0 & (pcie_dma1_reader_fifo_syncfifo_writable0 | pcie_dma1_reader_fifo_replace0)); +assign pcie_dma1_reader_fifo_do_read0 = (pcie_dma1_reader_fifo_syncfifo_readable0 & pcie_dma1_reader_fifo_syncfifo_re0); +assign pcie_dma1_reader_fifo_rdport_adr0 = pcie_dma1_reader_fifo_consume0; +assign pcie_dma1_reader_fifo_syncfifo_dout0 = pcie_dma1_reader_fifo_rdport_dat_r0; +assign pcie_dma1_reader_fifo_syncfifo_writable0 = (pcie_dma1_reader_fifo_level0 != 9'd256); +assign pcie_dma1_reader_fifo_syncfifo_readable0 = (pcie_dma1_reader_fifo_level0 != 1'd0); +assign pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_payload_address = (pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_payload_address + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_offset); +assign pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_payload_control = pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_payload_control; +assign pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_payload_user_id = pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_user_id; +assign pcie_dma1_reader_splitter_bufferizeendpoints_sink_valid = pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_valid; +assign pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_ready = pcie_dma1_reader_splitter_bufferizeendpoints_sink_ready; +assign pcie_dma1_reader_splitter_bufferizeendpoints_sink_first = pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_first; +assign pcie_dma1_reader_splitter_bufferizeendpoints_sink_last = pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_last; +assign pcie_dma1_reader_splitter_bufferizeendpoints_sink_payload_address = pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_payload_address; +assign pcie_dma1_reader_splitter_bufferizeendpoints_sink_payload_length = pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_payload_length; +assign pcie_dma1_reader_splitter_bufferizeendpoints_sink_payload_control = pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_payload_control; +assign pcie_dma1_reader_splitter_bufferizeendpoints_sink_payload_user_id = pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_payload_user_id; +always @(*) begin + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_first <= 1'd0; + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_last <= 1'd0; + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_user_id_litepciedma1_next_value1 <= 32'd0; + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_user_id_litepciedma1_next_value_ce1 <= 1'd0; + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_payload_length <= 24'd0; + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_ready <= 1'd0; + bufferizeendpoints1_next_state1 <= 2'd0; + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_next_value0 <= 32'd0; + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_next_value_ce0 <= 1'd0; + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_valid <= 1'd0; + bufferizeendpoints1_next_state1 <= bufferizeendpoints1_state1; + case (bufferizeendpoints1_state1) + 1'd1: begin + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_valid <= 1'd1; + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_first <= (pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_offset == 1'd0); + if (((pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_payload_length - pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_offset) > s7pciephy_max_request_size)) begin + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_last <= pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_end; + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_payload_length <= s7pciephy_max_request_size; + if (pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_ready) begin + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_next_value0 <= (pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_offset + s7pciephy_max_request_size); + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_next_value_ce0 <= 1'd1; + if (pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_end) begin + bufferizeendpoints1_next_state1 <= 2'd2; + end + end + end else begin + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_last <= 1'd1; + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_payload_length <= (pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_payload_length - pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_offset); + if (pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_source_ready) begin + bufferizeendpoints1_next_state1 <= 2'd2; + end + end + end + 2'd2: begin + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_ready <= 1'd1; + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_user_id_litepciedma1_next_value1 <= (pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_user_id + 1'd1); + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_user_id_litepciedma1_next_value_ce1 <= 1'd1; + bufferizeendpoints1_next_state1 <= 1'd0; + end + default: begin + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_next_value0 <= 1'd0; + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_next_value_ce0 <= 1'd1; + if (pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_valid) begin + bufferizeendpoints1_next_state1 <= 1'd1; + end else begin + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_sink_ready <= 1'd1; + end + end + endcase +end +assign pcie_dma1_reader_splitter_bufferizeendpoints_sink_ready = ((~pcie_dma1_reader_splitter_bufferizeendpoints_source_valid) | pcie_dma1_reader_splitter_bufferizeendpoints_source_ready); +assign pcie_dma1_reader_fifo_syncfifo_din1 = {pcie_dma1_reader_fifo_fifo_in_last1, pcie_dma1_reader_fifo_fifo_in_first1, pcie_dma1_reader_fifo_fifo_in_payload_data}; +assign {pcie_dma1_reader_fifo_fifo_out_last1, pcie_dma1_reader_fifo_fifo_out_first1, pcie_dma1_reader_fifo_fifo_out_payload_data} = pcie_dma1_reader_fifo_syncfifo_dout1; +assign pcie_dma1_reader_fifo_sink_ready1 = pcie_dma1_reader_fifo_syncfifo_writable1; +assign pcie_dma1_reader_fifo_syncfifo_we1 = pcie_dma1_reader_fifo_sink_valid1; +assign pcie_dma1_reader_fifo_fifo_in_first1 = pcie_dma1_reader_fifo_sink_first1; +assign pcie_dma1_reader_fifo_fifo_in_last1 = pcie_dma1_reader_fifo_sink_last1; +assign pcie_dma1_reader_fifo_fifo_in_payload_data = pcie_dma1_reader_fifo_sink_payload_data; +assign pcie_dma1_reader_fifo_source_valid1 = pcie_dma1_reader_fifo_readable; +assign pcie_dma1_reader_fifo_source_first1 = pcie_dma1_reader_fifo_fifo_out_first1; +assign pcie_dma1_reader_fifo_source_last1 = pcie_dma1_reader_fifo_fifo_out_last1; +assign pcie_dma1_reader_fifo_source_payload_data = pcie_dma1_reader_fifo_fifo_out_payload_data; +assign pcie_dma1_reader_fifo_re = pcie_dma1_reader_fifo_source_ready1; +assign pcie_dma1_reader_fifo_syncfifo_re1 = (pcie_dma1_reader_fifo_syncfifo_readable1 & ((~pcie_dma1_reader_fifo_readable) | pcie_dma1_reader_fifo_re)); +assign pcie_dma1_reader_fifo_level2 = (pcie_dma1_reader_fifo_level1 + pcie_dma1_reader_fifo_readable); +always @(*) begin + pcie_dma1_reader_fifo_wrport_adr1 <= 10'd0; + if (pcie_dma1_reader_fifo_replace1) begin + pcie_dma1_reader_fifo_wrport_adr1 <= (pcie_dma1_reader_fifo_produce1 - 1'd1); + end else begin + pcie_dma1_reader_fifo_wrport_adr1 <= pcie_dma1_reader_fifo_produce1; + end +end +assign pcie_dma1_reader_fifo_wrport_dat_w1 = pcie_dma1_reader_fifo_syncfifo_din1; +assign pcie_dma1_reader_fifo_wrport_we1 = (pcie_dma1_reader_fifo_syncfifo_we1 & (pcie_dma1_reader_fifo_syncfifo_writable1 | pcie_dma1_reader_fifo_replace1)); +assign pcie_dma1_reader_fifo_do_read1 = (pcie_dma1_reader_fifo_syncfifo_readable1 & pcie_dma1_reader_fifo_syncfifo_re1); +assign pcie_dma1_reader_fifo_rdport_adr1 = pcie_dma1_reader_fifo_consume1; +assign pcie_dma1_reader_fifo_syncfifo_dout1 = pcie_dma1_reader_fifo_rdport_dat_r1; +assign pcie_dma1_reader_fifo_rdport_re = pcie_dma1_reader_fifo_do_read1; +assign pcie_dma1_reader_fifo_syncfifo_writable1 = (pcie_dma1_reader_fifo_level1 != 11'd1024); +assign pcie_dma1_reader_fifo_syncfifo_readable1 = (pcie_dma1_reader_fifo_level1 != 1'd0); +always @(*) begin + fsm1_next_state2 <= 1'd0; + pcie_dma1_reader_splitter_bufferizeendpoints_source_ready <= 1'd0; + pcie_dma1_litepciemasterinternalport1_sink_valid <= 1'd0; + fsm1_next_state2 <= fsm1_state2; + case (fsm1_state2) + 1'd1: begin + pcie_dma1_litepciemasterinternalport1_sink_valid <= pcie_dma1_reader_enable_storage; + if ((pcie_dma1_litepciemasterinternalport1_sink_ready | (~pcie_dma1_reader_enable_storage))) begin + pcie_dma1_reader_splitter_bufferizeendpoints_source_ready <= 1'd1; + fsm1_next_state2 <= 1'd0; + end + end + default: begin + if (pcie_dma1_reader_splitter_bufferizeendpoints_source_valid) begin + if ((pcie_dma1_reader_pending_words < 10'd960)) begin + fsm1_next_state2 <= 1'd1; + end + end + end + endcase +end +always @(*) begin + pcie_dma1_loopback_next_source_payload_data <= 64'd0; + pcie_dma1_loopback_next_sink_ready <= 1'd0; + pcie_dma1_loopback_sink_ready <= 1'd0; + pcie_dma1_loopback_source_valid <= 1'd0; + pcie_dma1_loopback_source_first <= 1'd0; + pcie_dma1_loopback_source_last <= 1'd0; + pcie_dma1_loopback_source_payload_data <= 64'd0; + pcie_dma1_loopback_next_source_valid <= 1'd0; + pcie_dma1_loopback_next_source_first <= 1'd0; + pcie_dma1_loopback_next_source_last <= 1'd0; + if (pcie_dma1_loopback_storage) begin + pcie_dma1_loopback_source_valid <= pcie_dma1_loopback_sink_valid; + pcie_dma1_loopback_sink_ready <= pcie_dma1_loopback_source_ready; + pcie_dma1_loopback_source_first <= pcie_dma1_loopback_sink_first; + pcie_dma1_loopback_source_last <= pcie_dma1_loopback_sink_last; + pcie_dma1_loopback_source_payload_data <= pcie_dma1_loopback_sink_payload_data; + end else begin + pcie_dma1_loopback_next_source_valid <= pcie_dma1_loopback_sink_valid; + pcie_dma1_loopback_sink_ready <= pcie_dma1_loopback_next_source_ready; + pcie_dma1_loopback_next_source_first <= pcie_dma1_loopback_sink_first; + pcie_dma1_loopback_next_source_last <= pcie_dma1_loopback_sink_last; + pcie_dma1_loopback_next_source_payload_data <= pcie_dma1_loopback_sink_payload_data; + pcie_dma1_loopback_source_valid <= pcie_dma1_loopback_next_sink_valid; + pcie_dma1_loopback_next_sink_ready <= pcie_dma1_loopback_source_ready; + pcie_dma1_loopback_source_first <= pcie_dma1_loopback_next_sink_first; + pcie_dma1_loopback_source_last <= pcie_dma1_loopback_next_sink_last; + pcie_dma1_loopback_source_payload_data <= pcie_dma1_loopback_next_sink_payload_data; + end +end +assign pcie_dma1_buffering_reader_fifo_sink_first = pcie_dma1_buffering_sink_sink_first; +assign pcie_dma1_buffering_reader_fifo_sink_last = pcie_dma1_buffering_sink_sink_last; +assign pcie_dma1_buffering_reader_fifo_sink_payload_data = pcie_dma1_buffering_sink_sink_payload_data; +always @(*) begin + pcie_dma1_buffering_reader_fifo_sink_valid <= 1'd0; + pcie_dma1_buffering_sink_sink_ready <= 1'd0; + if ((pcie_dma1_buffering_reader_fifo_level1 < pcie_dma1_buffering_reader_fifo_depth_storage[10:3])) begin + pcie_dma1_buffering_reader_fifo_sink_valid <= pcie_dma1_buffering_sink_sink_valid; + pcie_dma1_buffering_sink_sink_ready <= pcie_dma1_buffering_reader_fifo_sink_ready; + end +end +assign pcie_dma1_buffering_next_source_valid = pcie_dma1_buffering_reader_fifo_source_valid; +assign pcie_dma1_buffering_reader_fifo_source_ready = pcie_dma1_buffering_next_source_ready; +assign pcie_dma1_buffering_next_source_first = pcie_dma1_buffering_reader_fifo_source_first; +assign pcie_dma1_buffering_next_source_last = pcie_dma1_buffering_reader_fifo_source_last; +assign pcie_dma1_buffering_next_source_payload_data = pcie_dma1_buffering_reader_fifo_source_payload_data; +assign pcie_dma1_buffering_writer_fifo_sink_first = pcie_dma1_buffering_next_sink_first; +assign pcie_dma1_buffering_writer_fifo_sink_last = pcie_dma1_buffering_next_sink_last; +assign pcie_dma1_buffering_writer_fifo_sink_payload_data = pcie_dma1_buffering_next_sink_payload_data; +always @(*) begin + pcie_dma1_buffering_writer_fifo_sink_valid <= 1'd0; + pcie_dma1_buffering_next_sink_ready <= 1'd0; + if ((pcie_dma1_buffering_writer_fifo_level1 < pcie_dma1_buffering_writer_fifo_depth_storage[10:3])) begin + pcie_dma1_buffering_writer_fifo_sink_valid <= pcie_dma1_buffering_next_sink_valid; + pcie_dma1_buffering_next_sink_ready <= pcie_dma1_buffering_writer_fifo_sink_ready; + end +end +assign pcie_dma1_buffering_source_source_valid = pcie_dma1_buffering_writer_fifo_source_valid; +assign pcie_dma1_buffering_writer_fifo_source_ready = pcie_dma1_buffering_source_source_ready; +assign pcie_dma1_buffering_source_source_first = pcie_dma1_buffering_writer_fifo_source_first; +assign pcie_dma1_buffering_source_source_last = pcie_dma1_buffering_writer_fifo_source_last; +assign pcie_dma1_buffering_source_source_payload_data = pcie_dma1_buffering_writer_fifo_source_payload_data; +assign pcie_dma1_buffering_reader_fifo_level_status[10:3] = pcie_dma1_buffering_reader_fifo_level1; +assign pcie_dma1_buffering_writer_fifo_level_status[10:3] = pcie_dma1_buffering_writer_fifo_level1; +assign pcie_dma1_buffering_reader_fifo_syncfifo_din = {pcie_dma1_buffering_reader_fifo_fifo_in_last, pcie_dma1_buffering_reader_fifo_fifo_in_first, pcie_dma1_buffering_reader_fifo_fifo_in_payload_data}; +assign {pcie_dma1_buffering_reader_fifo_fifo_out_last, pcie_dma1_buffering_reader_fifo_fifo_out_first, pcie_dma1_buffering_reader_fifo_fifo_out_payload_data} = pcie_dma1_buffering_reader_fifo_syncfifo_dout; +assign pcie_dma1_buffering_reader_fifo_sink_ready = pcie_dma1_buffering_reader_fifo_syncfifo_writable; +assign pcie_dma1_buffering_reader_fifo_syncfifo_we = pcie_dma1_buffering_reader_fifo_sink_valid; +assign pcie_dma1_buffering_reader_fifo_fifo_in_first = pcie_dma1_buffering_reader_fifo_sink_first; +assign pcie_dma1_buffering_reader_fifo_fifo_in_last = pcie_dma1_buffering_reader_fifo_sink_last; +assign pcie_dma1_buffering_reader_fifo_fifo_in_payload_data = pcie_dma1_buffering_reader_fifo_sink_payload_data; +assign pcie_dma1_buffering_reader_fifo_source_valid = pcie_dma1_buffering_reader_fifo_readable; +assign pcie_dma1_buffering_reader_fifo_source_first = pcie_dma1_buffering_reader_fifo_fifo_out_first; +assign pcie_dma1_buffering_reader_fifo_source_last = pcie_dma1_buffering_reader_fifo_fifo_out_last; +assign pcie_dma1_buffering_reader_fifo_source_payload_data = pcie_dma1_buffering_reader_fifo_fifo_out_payload_data; +assign pcie_dma1_buffering_reader_fifo_re = pcie_dma1_buffering_reader_fifo_source_ready; +assign pcie_dma1_buffering_reader_fifo_syncfifo_re = (pcie_dma1_buffering_reader_fifo_syncfifo_readable & ((~pcie_dma1_buffering_reader_fifo_readable) | pcie_dma1_buffering_reader_fifo_re)); +assign pcie_dma1_buffering_reader_fifo_level1 = (pcie_dma1_buffering_reader_fifo_level0 + pcie_dma1_buffering_reader_fifo_readable); +always @(*) begin + pcie_dma1_buffering_reader_fifo_wrport_adr <= 7'd0; + if (pcie_dma1_buffering_reader_fifo_replace) begin + pcie_dma1_buffering_reader_fifo_wrport_adr <= (pcie_dma1_buffering_reader_fifo_produce - 1'd1); + end else begin + pcie_dma1_buffering_reader_fifo_wrport_adr <= pcie_dma1_buffering_reader_fifo_produce; + end +end +assign pcie_dma1_buffering_reader_fifo_wrport_dat_w = pcie_dma1_buffering_reader_fifo_syncfifo_din; +assign pcie_dma1_buffering_reader_fifo_wrport_we = (pcie_dma1_buffering_reader_fifo_syncfifo_we & (pcie_dma1_buffering_reader_fifo_syncfifo_writable | pcie_dma1_buffering_reader_fifo_replace)); +assign pcie_dma1_buffering_reader_fifo_do_read = (pcie_dma1_buffering_reader_fifo_syncfifo_readable & pcie_dma1_buffering_reader_fifo_syncfifo_re); +assign pcie_dma1_buffering_reader_fifo_rdport_adr = pcie_dma1_buffering_reader_fifo_consume; +assign pcie_dma1_buffering_reader_fifo_syncfifo_dout = pcie_dma1_buffering_reader_fifo_rdport_dat_r; +assign pcie_dma1_buffering_reader_fifo_rdport_re = pcie_dma1_buffering_reader_fifo_do_read; +assign pcie_dma1_buffering_reader_fifo_syncfifo_writable = (pcie_dma1_buffering_reader_fifo_level0 != 8'd128); +assign pcie_dma1_buffering_reader_fifo_syncfifo_readable = (pcie_dma1_buffering_reader_fifo_level0 != 1'd0); +assign pcie_dma1_buffering_writer_fifo_syncfifo_din = {pcie_dma1_buffering_writer_fifo_fifo_in_last, pcie_dma1_buffering_writer_fifo_fifo_in_first, pcie_dma1_buffering_writer_fifo_fifo_in_payload_data}; +assign {pcie_dma1_buffering_writer_fifo_fifo_out_last, pcie_dma1_buffering_writer_fifo_fifo_out_first, pcie_dma1_buffering_writer_fifo_fifo_out_payload_data} = pcie_dma1_buffering_writer_fifo_syncfifo_dout; +assign pcie_dma1_buffering_writer_fifo_sink_ready = pcie_dma1_buffering_writer_fifo_syncfifo_writable; +assign pcie_dma1_buffering_writer_fifo_syncfifo_we = pcie_dma1_buffering_writer_fifo_sink_valid; +assign pcie_dma1_buffering_writer_fifo_fifo_in_first = pcie_dma1_buffering_writer_fifo_sink_first; +assign pcie_dma1_buffering_writer_fifo_fifo_in_last = pcie_dma1_buffering_writer_fifo_sink_last; +assign pcie_dma1_buffering_writer_fifo_fifo_in_payload_data = pcie_dma1_buffering_writer_fifo_sink_payload_data; +assign pcie_dma1_buffering_writer_fifo_source_valid = pcie_dma1_buffering_writer_fifo_readable; +assign pcie_dma1_buffering_writer_fifo_source_first = pcie_dma1_buffering_writer_fifo_fifo_out_first; +assign pcie_dma1_buffering_writer_fifo_source_last = pcie_dma1_buffering_writer_fifo_fifo_out_last; +assign pcie_dma1_buffering_writer_fifo_source_payload_data = pcie_dma1_buffering_writer_fifo_fifo_out_payload_data; +assign pcie_dma1_buffering_writer_fifo_re = pcie_dma1_buffering_writer_fifo_source_ready; +assign pcie_dma1_buffering_writer_fifo_syncfifo_re = (pcie_dma1_buffering_writer_fifo_syncfifo_readable & ((~pcie_dma1_buffering_writer_fifo_readable) | pcie_dma1_buffering_writer_fifo_re)); +assign pcie_dma1_buffering_writer_fifo_level1 = (pcie_dma1_buffering_writer_fifo_level0 + pcie_dma1_buffering_writer_fifo_readable); +always @(*) begin + pcie_dma1_buffering_writer_fifo_wrport_adr <= 7'd0; + if (pcie_dma1_buffering_writer_fifo_replace) begin + pcie_dma1_buffering_writer_fifo_wrport_adr <= (pcie_dma1_buffering_writer_fifo_produce - 1'd1); + end else begin + pcie_dma1_buffering_writer_fifo_wrport_adr <= pcie_dma1_buffering_writer_fifo_produce; + end +end +assign pcie_dma1_buffering_writer_fifo_wrport_dat_w = pcie_dma1_buffering_writer_fifo_syncfifo_din; +assign pcie_dma1_buffering_writer_fifo_wrport_we = (pcie_dma1_buffering_writer_fifo_syncfifo_we & (pcie_dma1_buffering_writer_fifo_syncfifo_writable | pcie_dma1_buffering_writer_fifo_replace)); +assign pcie_dma1_buffering_writer_fifo_do_read = (pcie_dma1_buffering_writer_fifo_syncfifo_readable & pcie_dma1_buffering_writer_fifo_syncfifo_re); +assign pcie_dma1_buffering_writer_fifo_rdport_adr = pcie_dma1_buffering_writer_fifo_consume; +assign pcie_dma1_buffering_writer_fifo_syncfifo_dout = pcie_dma1_buffering_writer_fifo_rdport_dat_r; +assign pcie_dma1_buffering_writer_fifo_rdport_re = pcie_dma1_buffering_writer_fifo_do_read; +assign pcie_dma1_buffering_writer_fifo_syncfifo_writable = (pcie_dma1_buffering_writer_fifo_level0 != 8'd128); +assign pcie_dma1_buffering_writer_fifo_syncfifo_readable = (pcie_dma1_buffering_writer_fifo_level0 != 1'd0); +always @(*) begin + pcie_msi_clear <= 32'd0; + if (pcie_msi_clear_re) begin + pcie_msi_clear <= pcie_msi_clear_storage; + end +end +assign pcie_msi_enable = pcie_msi_enable_storage; +assign pcie_msi_vector_status = pcie_msi_vector; +assign pcie_msi_source_valid = (pcie_msi_msi != 1'd0); +assign fmeter_clk = freqmeter; +assign freqmeter_period_done = (freqmeter_period_counter == 27'd100000000); +assign freqmeter_ce = 1'd1; +assign freqmeter_sampler_latch = freqmeter_period_done; +assign freqmeter_sampler_i = freqmeter_gray_decoder_o; +assign freqmeter_status = freqmeter_sampler_o; +always @(*) begin + freqmeter_q_next_binary <= 6'd0; + if (freqmeter_ce) begin + freqmeter_q_next_binary <= (freqmeter_q_binary + 1'd1); + end else begin + freqmeter_q_next_binary <= freqmeter_q_binary; + end +end +assign freqmeter_q_next = (freqmeter_q_next_binary ^ freqmeter_q_next_binary[5:1]); +always @(*) begin + freqmeter_gray_decoder_o_comb <= 6'd0; + freqmeter_gray_decoder_o_comb[5] <= freqmeter_gray_decoder_i[5]; + freqmeter_gray_decoder_o_comb[4] <= (freqmeter_gray_decoder_o_comb[5] ^ freqmeter_gray_decoder_i[4]); + freqmeter_gray_decoder_o_comb[3] <= (freqmeter_gray_decoder_o_comb[4] ^ freqmeter_gray_decoder_i[3]); + freqmeter_gray_decoder_o_comb[2] <= (freqmeter_gray_decoder_o_comb[3] ^ freqmeter_gray_decoder_i[2]); + freqmeter_gray_decoder_o_comb[1] <= (freqmeter_gray_decoder_o_comb[2] ^ freqmeter_gray_decoder_i[1]); + freqmeter_gray_decoder_o_comb[0] <= (freqmeter_gray_decoder_o_comb[1] ^ freqmeter_gray_decoder_i[0]); +end +assign freqmeter_sampler_inc = (freqmeter_sampler_i - freqmeter_sampler_i_d); +assign hdmi_in0_charsync0_raw_data = hdmi_in0_s7datacapture0_d; +assign hdmi_in0_wer0_data = hdmi_in0_charsync0_data; +assign hdmi_in0_decoding0_valid_i = hdmi_in0_charsync0_synced; +assign hdmi_in0_decoding0_input = hdmi_in0_charsync0_data; +assign hdmi_in0_charsync1_raw_data = hdmi_in0_s7datacapture1_d; +assign hdmi_in0_wer1_data = hdmi_in0_charsync1_data; +assign hdmi_in0_decoding1_valid_i = hdmi_in0_charsync1_synced; +assign hdmi_in0_decoding1_input = hdmi_in0_charsync1_data; +assign hdmi_in0_charsync2_raw_data = hdmi_in0_s7datacapture2_d; +assign hdmi_in0_wer2_data = hdmi_in0_charsync2_data; +assign hdmi_in0_decoding2_valid_i = hdmi_in0_charsync2_synced; +assign hdmi_in0_decoding2_input = hdmi_in0_charsync2_data; +assign hdmi_in0_chansync_valid_i = ((hdmi_in0_decoding0_valid_o & hdmi_in0_decoding1_valid_o) & hdmi_in0_decoding2_valid_o); +assign hdmi_in0_chansync_data_in0_raw = hdmi_in0_decoding0_output_raw; +assign hdmi_in0_chansync_data_in0_d = hdmi_in0_decoding0_output_d; +assign hdmi_in0_chansync_data_in0_c = hdmi_in0_decoding0_output_c; +assign hdmi_in0_chansync_data_in0_de = hdmi_in0_decoding0_output_de; +assign hdmi_in0_chansync_data_in1_raw = hdmi_in0_decoding1_output_raw; +assign hdmi_in0_chansync_data_in1_d = hdmi_in0_decoding1_output_d; +assign hdmi_in0_chansync_data_in1_c = hdmi_in0_decoding1_output_c; +assign hdmi_in0_chansync_data_in1_de = hdmi_in0_decoding1_output_de; +assign hdmi_in0_chansync_data_in2_raw = hdmi_in0_decoding2_output_raw; +assign hdmi_in0_chansync_data_in2_d = hdmi_in0_decoding2_output_d; +assign hdmi_in0_chansync_data_in2_c = hdmi_in0_decoding2_output_c; +assign hdmi_in0_chansync_data_in2_de = hdmi_in0_decoding2_output_de; +assign hdmi_in0_syncpol_valid_i = hdmi_in0_chansync_chan_synced; +assign hdmi_in0_syncpol_data_in0_raw = hdmi_in0_chansync_data_out0_raw; +assign hdmi_in0_syncpol_data_in0_d = hdmi_in0_chansync_data_out0_d; +assign hdmi_in0_syncpol_data_in0_c = hdmi_in0_chansync_data_out0_c; +assign hdmi_in0_syncpol_data_in0_de = hdmi_in0_chansync_data_out0_de; +assign hdmi_in0_syncpol_data_in1_raw = hdmi_in0_chansync_data_out1_raw; +assign hdmi_in0_syncpol_data_in1_d = hdmi_in0_chansync_data_out1_d; +assign hdmi_in0_syncpol_data_in1_c = hdmi_in0_chansync_data_out1_c; +assign hdmi_in0_syncpol_data_in1_de = hdmi_in0_chansync_data_out1_de; +assign hdmi_in0_syncpol_data_in2_raw = hdmi_in0_chansync_data_out2_raw; +assign hdmi_in0_syncpol_data_in2_d = hdmi_in0_chansync_data_out2_d; +assign hdmi_in0_syncpol_data_in2_c = hdmi_in0_chansync_data_out2_c; +assign hdmi_in0_syncpol_data_in2_de = hdmi_in0_chansync_data_out2_de; +assign hdmi_in0_resdetection_valid_i = hdmi_in0_syncpol_valid_o; +assign hdmi_in0_resdetection_de = hdmi_in0_syncpol_de; +assign hdmi_in0_resdetection_vsync = hdmi_in0_syncpol_vsync; +assign hdmi_in0_frame_valid_i = hdmi_in0_syncpol_valid_o; +assign hdmi_in0_frame_de = hdmi_in0_syncpol_de; +assign hdmi_in0_frame_vsync = hdmi_in0_syncpol_vsync; +assign hdmi_in0_frame_r = hdmi_in0_syncpol_r; +assign hdmi_in0_frame_g = hdmi_in0_syncpol_g; +assign hdmi_in0_frame_b = hdmi_in0_syncpol_b; +assign hdmi_in0_dma_frame_valid = hdmi_in0_frame_frame_valid; +assign hdmi_in0_frame_frame_ready = hdmi_in0_dma_frame_ready; +assign hdmi_in0_dma_frame_first = hdmi_in0_frame_frame_first; +assign hdmi_in0_dma_frame_last = hdmi_in0_frame_frame_last; +assign hdmi_in0_dma_frame_payload_sof = hdmi_in0_frame_frame_payload_sof; +assign hdmi_in0_dma_frame_payload_pixels = hdmi_in0_frame_frame_payload_pixels; +assign hdmi_in0_hpd_notif_status = 1'd1; +assign hdmi_in0_sda_pu = 1'd0; +assign hdmi_in0_sda_pd = hdmi_in0_sda_drv_reg; +assign hdmi_in0_sda_o = (~hdmi_in0_sda_drv_reg); +assign hdmi_in0_scl_rising = (hdmi_in0_scl_i & (~hdmi_in0_scl_r)); +assign hdmi_in0_sda_rising = (hdmi_in0_sda_i & (~hdmi_in0_sda_r)); +assign hdmi_in0_sda_falling = ((~hdmi_in0_sda_i) & hdmi_in0_sda_r); +assign hdmi_in0_start = (hdmi_in0_scl_i & hdmi_in0_sda_falling); +assign hdmi_in0_adr = hdmi_in0_offset_counter; +always @(*) begin + hdmi_in0_sda_drv <= 1'd0; + if (hdmi_in0_zero_drv) begin + hdmi_in0_sda_drv <= 1'd1; + end else begin + if (hdmi_in0_data_drv) begin + hdmi_in0_sda_drv <= (~hdmi_in0_data_bit); + end + end +end +always @(*) begin + hdmi_in0_data_drv_stop <= 1'd0; + hdmi_in0_update_is_read <= 1'd0; + hdmi_in0_zero_drv <= 1'd0; + hdmi_in0_oc_load <= 1'd0; + hdmi_in0_oc_inc <= 1'd0; + edid_next_state <= 4'd0; + hdmi_in0_data_drv_en <= 1'd0; + edid_next_state <= edid_state; + case (edid_state) + 1'd1: begin + if ((hdmi_in0_counter == 4'd8)) begin + if ((hdmi_in0_din[7:1] == 7'd80)) begin + hdmi_in0_update_is_read <= 1'd1; + edid_next_state <= 2'd2; + end else begin + edid_next_state <= 1'd0; + end + end + if (hdmi_in0_start) begin + edid_next_state <= 1'd1; + end + end + 2'd2: begin + if ((~hdmi_in0_scl_i)) begin + edid_next_state <= 2'd3; + end + if (hdmi_in0_start) begin + edid_next_state <= 1'd1; + end + end + 2'd3: begin + hdmi_in0_zero_drv <= 1'd1; + if (hdmi_in0_scl_i) begin + edid_next_state <= 3'd4; + end + if (hdmi_in0_start) begin + edid_next_state <= 1'd1; + end + end + 3'd4: begin + hdmi_in0_zero_drv <= 1'd1; + if ((~hdmi_in0_scl_i)) begin + if (hdmi_in0_is_read) begin + edid_next_state <= 4'd9; + end else begin + edid_next_state <= 3'd5; + end + end + if (hdmi_in0_start) begin + edid_next_state <= 1'd1; + end + end + 3'd5: begin + if ((hdmi_in0_counter == 4'd8)) begin + hdmi_in0_oc_load <= 1'd1; + edid_next_state <= 3'd6; + end + if (hdmi_in0_start) begin + edid_next_state <= 1'd1; + end + end + 3'd6: begin + if ((~hdmi_in0_scl_i)) begin + edid_next_state <= 3'd7; + end + if (hdmi_in0_start) begin + edid_next_state <= 1'd1; + end + end + 3'd7: begin + hdmi_in0_zero_drv <= 1'd1; + if (hdmi_in0_scl_i) begin + edid_next_state <= 4'd8; + end + if (hdmi_in0_start) begin + edid_next_state <= 1'd1; + end + end + 4'd8: begin + hdmi_in0_zero_drv <= 1'd1; + if ((~hdmi_in0_scl_i)) begin + edid_next_state <= 1'd1; + end + if (hdmi_in0_start) begin + edid_next_state <= 1'd1; + end + end + 4'd9: begin + if ((~hdmi_in0_scl_i)) begin + if ((hdmi_in0_counter == 4'd8)) begin + hdmi_in0_data_drv_stop <= 1'd1; + edid_next_state <= 4'd10; + end else begin + hdmi_in0_data_drv_en <= 1'd1; + end + end + if (hdmi_in0_start) begin + edid_next_state <= 1'd1; + end + end + 4'd10: begin + if (hdmi_in0_scl_rising) begin + hdmi_in0_oc_inc <= 1'd1; + if (hdmi_in0_sda_i) begin + edid_next_state <= 1'd0; + end else begin + edid_next_state <= 4'd9; + end + end + if (hdmi_in0_start) begin + edid_next_state <= 1'd1; + end + end + default: begin + if (hdmi_in0_start) begin + edid_next_state <= 1'd1; + end + end + endcase +end +assign hdmi_in0_locked_status = hdmi_in0_locked; +assign hdmi_in0_s7datacapture0_sync_mcntvalue_i = hdmi_in0_s7datacapture0_serdes_m_cntvalue; +assign hdmi_in0_s7datacapture0_cntvalueout_m_status = hdmi_in0_s7datacapture0_sync_mcntvalue_o; +assign hdmi_in0_s7datacapture0_sync_scntvalue_i = hdmi_in0_s7datacapture0_serdes_s_cntvalue; +assign hdmi_in0_s7datacapture0_cntvalueout_s_status = hdmi_in0_s7datacapture0_sync_scntvalue_o; +assign hdmi_in0_s7datacapture0_serdes_m_d = (~hdmi_in0_s7datacapture0_serdes_m_q); +assign hdmi_in0_s7datacapture0_serdes_s_d = hdmi_in0_s7datacapture0_serdes_s_q; +assign hdmi_in0_s7datacapture0_gearbox_i = hdmi_in0_s7datacapture0_serdes_m_d; +assign hdmi_in0_s7datacapture0_d = hdmi_in0_s7datacapture0_gearbox_o; +assign hdmi_in0_s7datacapture0_mdata = hdmi_in0_s7datacapture0_serdes_m_d; +assign hdmi_in0_s7datacapture0_sdata = hdmi_in0_s7datacapture0_serdes_s_d; +assign hdmi_in0_s7datacapture0_too_late = (hdmi_in0_s7datacapture0_lateness == 8'd255); +assign hdmi_in0_s7datacapture0_too_early = (hdmi_in0_s7datacapture0_lateness == 1'd0); +assign hdmi_in0_s7datacapture0_delay_rst = hdmi_in0_s7datacapture0_do_delay_rst_o; +assign hdmi_in0_s7datacapture0_delay_master_inc = hdmi_in0_s7datacapture0_do_delay_master_inc_o; +assign hdmi_in0_s7datacapture0_delay_master_ce = (hdmi_in0_s7datacapture0_do_delay_master_inc_o | hdmi_in0_s7datacapture0_do_delay_master_dec_o); +assign hdmi_in0_s7datacapture0_delay_slave_inc = hdmi_in0_s7datacapture0_do_delay_slave_inc_o; +assign hdmi_in0_s7datacapture0_delay_slave_ce = (hdmi_in0_s7datacapture0_do_delay_slave_inc_o | hdmi_in0_s7datacapture0_do_delay_slave_dec_o); +assign hdmi_in0_s7datacapture0_do_delay_rst_i = (hdmi_in0_s7datacapture0_dly_ctl_re & hdmi_in0_s7datacapture0_dly_ctl_r[0]); +assign hdmi_in0_s7datacapture0_do_delay_master_inc_i = (hdmi_in0_s7datacapture0_dly_ctl_re & hdmi_in0_s7datacapture0_dly_ctl_r[1]); +assign hdmi_in0_s7datacapture0_do_delay_master_dec_i = (hdmi_in0_s7datacapture0_dly_ctl_re & hdmi_in0_s7datacapture0_dly_ctl_r[2]); +assign hdmi_in0_s7datacapture0_do_delay_slave_inc_i = (hdmi_in0_s7datacapture0_dly_ctl_re & hdmi_in0_s7datacapture0_dly_ctl_r[3]); +assign hdmi_in0_s7datacapture0_do_delay_slave_dec_i = (hdmi_in0_s7datacapture0_dly_ctl_re & hdmi_in0_s7datacapture0_dly_ctl_r[4]); +assign hdmi_in0_s7datacapture0_reset_lateness = hdmi_in0_s7datacapture0_do_reset_lateness_o; +assign hdmi_in0_s7datacapture0_do_reset_lateness_i = hdmi_in0_s7datacapture0_phase_reset_re; +assign hdmi_in0_s7datacapture0_sync_mcntvalue_wait = (~hdmi_in0_s7datacapture0_sync_mcntvalue_ping_i); +assign hdmi_in0_s7datacapture0_sync_mcntvalue_ping_i = ((hdmi_in0_s7datacapture0_sync_mcntvalue_starter | hdmi_in0_s7datacapture0_sync_mcntvalue_pong_o) | hdmi_in0_s7datacapture0_sync_mcntvalue_done); +assign hdmi_in0_s7datacapture0_sync_mcntvalue_pong_i = hdmi_in0_s7datacapture0_sync_mcntvalue_ping_o1; +assign hdmi_in0_s7datacapture0_sync_mcntvalue_ping_o0 = (hdmi_in0_s7datacapture0_sync_mcntvalue_ping_toggle_o ^ hdmi_in0_s7datacapture0_sync_mcntvalue_ping_toggle_o_r); +assign hdmi_in0_s7datacapture0_sync_mcntvalue_pong_o = (hdmi_in0_s7datacapture0_sync_mcntvalue_pong_toggle_o ^ hdmi_in0_s7datacapture0_sync_mcntvalue_pong_toggle_o_r); +assign hdmi_in0_s7datacapture0_sync_mcntvalue_done = (hdmi_in0_s7datacapture0_sync_mcntvalue_count == 1'd0); +assign hdmi_in0_s7datacapture0_sync_scntvalue_wait = (~hdmi_in0_s7datacapture0_sync_scntvalue_ping_i); +assign hdmi_in0_s7datacapture0_sync_scntvalue_ping_i = ((hdmi_in0_s7datacapture0_sync_scntvalue_starter | hdmi_in0_s7datacapture0_sync_scntvalue_pong_o) | hdmi_in0_s7datacapture0_sync_scntvalue_done); +assign hdmi_in0_s7datacapture0_sync_scntvalue_pong_i = hdmi_in0_s7datacapture0_sync_scntvalue_ping_o1; +assign hdmi_in0_s7datacapture0_sync_scntvalue_ping_o0 = (hdmi_in0_s7datacapture0_sync_scntvalue_ping_toggle_o ^ hdmi_in0_s7datacapture0_sync_scntvalue_ping_toggle_o_r); +assign hdmi_in0_s7datacapture0_sync_scntvalue_pong_o = (hdmi_in0_s7datacapture0_sync_scntvalue_pong_toggle_o ^ hdmi_in0_s7datacapture0_sync_scntvalue_pong_toggle_o_r); +assign hdmi_in0_s7datacapture0_sync_scntvalue_done = (hdmi_in0_s7datacapture0_sync_scntvalue_count == 1'd0); +assign hdmi_in0_s7datacapture0_gearbox_rst = (pix1p25x_rst | hdmi_in0_pix_rst); +assign data0_cap_write_clk = pix1p25x_clk; +assign data0_cap_read_clk = hdmi_in0_pix_clk; +assign data0_cap_write_rst = hdmi_in0_s7datacapture0_gearbox_rst; +assign data0_cap_read_rst = hdmi_in0_s7datacapture0_gearbox_rst; +assign hdmi_in0_s7datacapture0_transition = (hdmi_in0_s7datacapture0_mdata_d != hdmi_in0_s7datacapture0_mdata); +assign hdmi_in0_s7datacapture0_inc = (hdmi_in0_s7datacapture0_transition & (hdmi_in0_s7datacapture0_mdata == hdmi_in0_s7datacapture0_sdata)); +assign hdmi_in0_s7datacapture0_dec = (hdmi_in0_s7datacapture0_transition & (hdmi_in0_s7datacapture0_mdata != hdmi_in0_s7datacapture0_sdata)); +assign hdmi_in0_s7datacapture0_do_delay_rst_o = (hdmi_in0_s7datacapture0_do_delay_rst_toggle_o ^ hdmi_in0_s7datacapture0_do_delay_rst_toggle_o_r); +assign hdmi_in0_s7datacapture0_do_delay_master_inc_o = (hdmi_in0_s7datacapture0_do_delay_master_inc_toggle_o ^ hdmi_in0_s7datacapture0_do_delay_master_inc_toggle_o_r); +assign hdmi_in0_s7datacapture0_do_delay_master_dec_o = (hdmi_in0_s7datacapture0_do_delay_master_dec_toggle_o ^ hdmi_in0_s7datacapture0_do_delay_master_dec_toggle_o_r); +assign hdmi_in0_s7datacapture0_do_delay_slave_inc_o = (hdmi_in0_s7datacapture0_do_delay_slave_inc_toggle_o ^ hdmi_in0_s7datacapture0_do_delay_slave_inc_toggle_o_r); +assign hdmi_in0_s7datacapture0_do_delay_slave_dec_o = (hdmi_in0_s7datacapture0_do_delay_slave_dec_toggle_o ^ hdmi_in0_s7datacapture0_do_delay_slave_dec_toggle_o_r); +assign hdmi_in0_s7datacapture0_do_reset_lateness_o = (hdmi_in0_s7datacapture0_do_reset_lateness_toggle_o ^ hdmi_in0_s7datacapture0_do_reset_lateness_toggle_o_r); +assign hdmi_in0_charsync0_raw = {hdmi_in0_charsync0_raw_data, hdmi_in0_charsync0_raw_data1}; +always @(*) begin + hdmi_in0_wer0_transitions <= 8'd0; + hdmi_in0_wer0_transitions[0] <= (hdmi_in0_wer0_data_r[0] ^ hdmi_in0_wer0_data_r[1]); + hdmi_in0_wer0_transitions[1] <= (hdmi_in0_wer0_data_r[1] ^ hdmi_in0_wer0_data_r[2]); + hdmi_in0_wer0_transitions[2] <= (hdmi_in0_wer0_data_r[2] ^ hdmi_in0_wer0_data_r[3]); + hdmi_in0_wer0_transitions[3] <= (hdmi_in0_wer0_data_r[3] ^ hdmi_in0_wer0_data_r[4]); + hdmi_in0_wer0_transitions[4] <= (hdmi_in0_wer0_data_r[4] ^ hdmi_in0_wer0_data_r[5]); + hdmi_in0_wer0_transitions[5] <= (hdmi_in0_wer0_data_r[5] ^ hdmi_in0_wer0_data_r[6]); + hdmi_in0_wer0_transitions[6] <= (hdmi_in0_wer0_data_r[6] ^ hdmi_in0_wer0_data_r[7]); + hdmi_in0_wer0_transitions[7] <= (hdmi_in0_wer0_data_r[7] ^ hdmi_in0_wer0_data_r[8]); +end +assign hdmi_in0_wer0_i = hdmi_in0_wer0_wer_counter_r_updated; +assign hdmi_in0_wer0_o = (hdmi_in0_wer0_toggle_o ^ hdmi_in0_wer0_toggle_o_r); +assign hdmi_in0_s7datacapture1_sync_mcntvalue_i = hdmi_in0_s7datacapture1_serdes_m_cntvalue; +assign hdmi_in0_s7datacapture1_cntvalueout_m_status = hdmi_in0_s7datacapture1_sync_mcntvalue_o; +assign hdmi_in0_s7datacapture1_sync_scntvalue_i = hdmi_in0_s7datacapture1_serdes_s_cntvalue; +assign hdmi_in0_s7datacapture1_cntvalueout_s_status = hdmi_in0_s7datacapture1_sync_scntvalue_o; +assign hdmi_in0_s7datacapture1_serdes_m_d = (~hdmi_in0_s7datacapture1_serdes_m_q); +assign hdmi_in0_s7datacapture1_serdes_s_d = hdmi_in0_s7datacapture1_serdes_s_q; +assign hdmi_in0_s7datacapture1_gearbox_i = hdmi_in0_s7datacapture1_serdes_m_d; +assign hdmi_in0_s7datacapture1_d = hdmi_in0_s7datacapture1_gearbox_o; +assign hdmi_in0_s7datacapture1_mdata = hdmi_in0_s7datacapture1_serdes_m_d; +assign hdmi_in0_s7datacapture1_sdata = hdmi_in0_s7datacapture1_serdes_s_d; +assign hdmi_in0_s7datacapture1_too_late = (hdmi_in0_s7datacapture1_lateness == 8'd255); +assign hdmi_in0_s7datacapture1_too_early = (hdmi_in0_s7datacapture1_lateness == 1'd0); +assign hdmi_in0_s7datacapture1_delay_rst = hdmi_in0_s7datacapture1_do_delay_rst_o; +assign hdmi_in0_s7datacapture1_delay_master_inc = hdmi_in0_s7datacapture1_do_delay_master_inc_o; +assign hdmi_in0_s7datacapture1_delay_master_ce = (hdmi_in0_s7datacapture1_do_delay_master_inc_o | hdmi_in0_s7datacapture1_do_delay_master_dec_o); +assign hdmi_in0_s7datacapture1_delay_slave_inc = hdmi_in0_s7datacapture1_do_delay_slave_inc_o; +assign hdmi_in0_s7datacapture1_delay_slave_ce = (hdmi_in0_s7datacapture1_do_delay_slave_inc_o | hdmi_in0_s7datacapture1_do_delay_slave_dec_o); +assign hdmi_in0_s7datacapture1_do_delay_rst_i = (hdmi_in0_s7datacapture1_dly_ctl_re & hdmi_in0_s7datacapture1_dly_ctl_r[0]); +assign hdmi_in0_s7datacapture1_do_delay_master_inc_i = (hdmi_in0_s7datacapture1_dly_ctl_re & hdmi_in0_s7datacapture1_dly_ctl_r[1]); +assign hdmi_in0_s7datacapture1_do_delay_master_dec_i = (hdmi_in0_s7datacapture1_dly_ctl_re & hdmi_in0_s7datacapture1_dly_ctl_r[2]); +assign hdmi_in0_s7datacapture1_do_delay_slave_inc_i = (hdmi_in0_s7datacapture1_dly_ctl_re & hdmi_in0_s7datacapture1_dly_ctl_r[3]); +assign hdmi_in0_s7datacapture1_do_delay_slave_dec_i = (hdmi_in0_s7datacapture1_dly_ctl_re & hdmi_in0_s7datacapture1_dly_ctl_r[4]); +assign hdmi_in0_s7datacapture1_reset_lateness = hdmi_in0_s7datacapture1_do_reset_lateness_o; +assign hdmi_in0_s7datacapture1_do_reset_lateness_i = hdmi_in0_s7datacapture1_phase_reset_re; +assign hdmi_in0_s7datacapture1_sync_mcntvalue_wait = (~hdmi_in0_s7datacapture1_sync_mcntvalue_ping_i); +assign hdmi_in0_s7datacapture1_sync_mcntvalue_ping_i = ((hdmi_in0_s7datacapture1_sync_mcntvalue_starter | hdmi_in0_s7datacapture1_sync_mcntvalue_pong_o) | hdmi_in0_s7datacapture1_sync_mcntvalue_done); +assign hdmi_in0_s7datacapture1_sync_mcntvalue_pong_i = hdmi_in0_s7datacapture1_sync_mcntvalue_ping_o1; +assign hdmi_in0_s7datacapture1_sync_mcntvalue_ping_o0 = (hdmi_in0_s7datacapture1_sync_mcntvalue_ping_toggle_o ^ hdmi_in0_s7datacapture1_sync_mcntvalue_ping_toggle_o_r); +assign hdmi_in0_s7datacapture1_sync_mcntvalue_pong_o = (hdmi_in0_s7datacapture1_sync_mcntvalue_pong_toggle_o ^ hdmi_in0_s7datacapture1_sync_mcntvalue_pong_toggle_o_r); +assign hdmi_in0_s7datacapture1_sync_mcntvalue_done = (hdmi_in0_s7datacapture1_sync_mcntvalue_count == 1'd0); +assign hdmi_in0_s7datacapture1_sync_scntvalue_wait = (~hdmi_in0_s7datacapture1_sync_scntvalue_ping_i); +assign hdmi_in0_s7datacapture1_sync_scntvalue_ping_i = ((hdmi_in0_s7datacapture1_sync_scntvalue_starter | hdmi_in0_s7datacapture1_sync_scntvalue_pong_o) | hdmi_in0_s7datacapture1_sync_scntvalue_done); +assign hdmi_in0_s7datacapture1_sync_scntvalue_pong_i = hdmi_in0_s7datacapture1_sync_scntvalue_ping_o1; +assign hdmi_in0_s7datacapture1_sync_scntvalue_ping_o0 = (hdmi_in0_s7datacapture1_sync_scntvalue_ping_toggle_o ^ hdmi_in0_s7datacapture1_sync_scntvalue_ping_toggle_o_r); +assign hdmi_in0_s7datacapture1_sync_scntvalue_pong_o = (hdmi_in0_s7datacapture1_sync_scntvalue_pong_toggle_o ^ hdmi_in0_s7datacapture1_sync_scntvalue_pong_toggle_o_r); +assign hdmi_in0_s7datacapture1_sync_scntvalue_done = (hdmi_in0_s7datacapture1_sync_scntvalue_count == 1'd0); +assign hdmi_in0_s7datacapture1_gearbox_rst = (pix1p25x_rst | hdmi_in0_pix_rst); +assign data1_cap_write_clk = pix1p25x_clk; +assign data1_cap_read_clk = hdmi_in0_pix_clk; +assign data1_cap_write_rst = hdmi_in0_s7datacapture1_gearbox_rst; +assign data1_cap_read_rst = hdmi_in0_s7datacapture1_gearbox_rst; +assign hdmi_in0_s7datacapture1_transition = (hdmi_in0_s7datacapture1_mdata_d != hdmi_in0_s7datacapture1_mdata); +assign hdmi_in0_s7datacapture1_inc = (hdmi_in0_s7datacapture1_transition & (hdmi_in0_s7datacapture1_mdata == hdmi_in0_s7datacapture1_sdata)); +assign hdmi_in0_s7datacapture1_dec = (hdmi_in0_s7datacapture1_transition & (hdmi_in0_s7datacapture1_mdata != hdmi_in0_s7datacapture1_sdata)); +assign hdmi_in0_s7datacapture1_do_delay_rst_o = (hdmi_in0_s7datacapture1_do_delay_rst_toggle_o ^ hdmi_in0_s7datacapture1_do_delay_rst_toggle_o_r); +assign hdmi_in0_s7datacapture1_do_delay_master_inc_o = (hdmi_in0_s7datacapture1_do_delay_master_inc_toggle_o ^ hdmi_in0_s7datacapture1_do_delay_master_inc_toggle_o_r); +assign hdmi_in0_s7datacapture1_do_delay_master_dec_o = (hdmi_in0_s7datacapture1_do_delay_master_dec_toggle_o ^ hdmi_in0_s7datacapture1_do_delay_master_dec_toggle_o_r); +assign hdmi_in0_s7datacapture1_do_delay_slave_inc_o = (hdmi_in0_s7datacapture1_do_delay_slave_inc_toggle_o ^ hdmi_in0_s7datacapture1_do_delay_slave_inc_toggle_o_r); +assign hdmi_in0_s7datacapture1_do_delay_slave_dec_o = (hdmi_in0_s7datacapture1_do_delay_slave_dec_toggle_o ^ hdmi_in0_s7datacapture1_do_delay_slave_dec_toggle_o_r); +assign hdmi_in0_s7datacapture1_do_reset_lateness_o = (hdmi_in0_s7datacapture1_do_reset_lateness_toggle_o ^ hdmi_in0_s7datacapture1_do_reset_lateness_toggle_o_r); +assign hdmi_in0_charsync1_raw = {hdmi_in0_charsync1_raw_data, hdmi_in0_charsync1_raw_data1}; +always @(*) begin + hdmi_in0_wer1_transitions <= 8'd0; + hdmi_in0_wer1_transitions[0] <= (hdmi_in0_wer1_data_r[0] ^ hdmi_in0_wer1_data_r[1]); + hdmi_in0_wer1_transitions[1] <= (hdmi_in0_wer1_data_r[1] ^ hdmi_in0_wer1_data_r[2]); + hdmi_in0_wer1_transitions[2] <= (hdmi_in0_wer1_data_r[2] ^ hdmi_in0_wer1_data_r[3]); + hdmi_in0_wer1_transitions[3] <= (hdmi_in0_wer1_data_r[3] ^ hdmi_in0_wer1_data_r[4]); + hdmi_in0_wer1_transitions[4] <= (hdmi_in0_wer1_data_r[4] ^ hdmi_in0_wer1_data_r[5]); + hdmi_in0_wer1_transitions[5] <= (hdmi_in0_wer1_data_r[5] ^ hdmi_in0_wer1_data_r[6]); + hdmi_in0_wer1_transitions[6] <= (hdmi_in0_wer1_data_r[6] ^ hdmi_in0_wer1_data_r[7]); + hdmi_in0_wer1_transitions[7] <= (hdmi_in0_wer1_data_r[7] ^ hdmi_in0_wer1_data_r[8]); +end +assign hdmi_in0_wer1_i = hdmi_in0_wer1_wer_counter_r_updated; +assign hdmi_in0_wer1_o = (hdmi_in0_wer1_toggle_o ^ hdmi_in0_wer1_toggle_o_r); +assign hdmi_in0_s7datacapture2_sync_mcntvalue_i = hdmi_in0_s7datacapture2_serdes_m_cntvalue; +assign hdmi_in0_s7datacapture2_cntvalueout_m_status = hdmi_in0_s7datacapture2_sync_mcntvalue_o; +assign hdmi_in0_s7datacapture2_sync_scntvalue_i = hdmi_in0_s7datacapture2_serdes_s_cntvalue; +assign hdmi_in0_s7datacapture2_cntvalueout_s_status = hdmi_in0_s7datacapture2_sync_scntvalue_o; +assign hdmi_in0_s7datacapture2_serdes_m_d = (~hdmi_in0_s7datacapture2_serdes_m_q); +assign hdmi_in0_s7datacapture2_serdes_s_d = hdmi_in0_s7datacapture2_serdes_s_q; +assign hdmi_in0_s7datacapture2_gearbox_i = hdmi_in0_s7datacapture2_serdes_m_d; +assign hdmi_in0_s7datacapture2_d = hdmi_in0_s7datacapture2_gearbox_o; +assign hdmi_in0_s7datacapture2_mdata = hdmi_in0_s7datacapture2_serdes_m_d; +assign hdmi_in0_s7datacapture2_sdata = hdmi_in0_s7datacapture2_serdes_s_d; +assign hdmi_in0_s7datacapture2_too_late = (hdmi_in0_s7datacapture2_lateness == 8'd255); +assign hdmi_in0_s7datacapture2_too_early = (hdmi_in0_s7datacapture2_lateness == 1'd0); +assign hdmi_in0_s7datacapture2_delay_rst = hdmi_in0_s7datacapture2_do_delay_rst_o; +assign hdmi_in0_s7datacapture2_delay_master_inc = hdmi_in0_s7datacapture2_do_delay_master_inc_o; +assign hdmi_in0_s7datacapture2_delay_master_ce = (hdmi_in0_s7datacapture2_do_delay_master_inc_o | hdmi_in0_s7datacapture2_do_delay_master_dec_o); +assign hdmi_in0_s7datacapture2_delay_slave_inc = hdmi_in0_s7datacapture2_do_delay_slave_inc_o; +assign hdmi_in0_s7datacapture2_delay_slave_ce = (hdmi_in0_s7datacapture2_do_delay_slave_inc_o | hdmi_in0_s7datacapture2_do_delay_slave_dec_o); +assign hdmi_in0_s7datacapture2_do_delay_rst_i = (hdmi_in0_s7datacapture2_dly_ctl_re & hdmi_in0_s7datacapture2_dly_ctl_r[0]); +assign hdmi_in0_s7datacapture2_do_delay_master_inc_i = (hdmi_in0_s7datacapture2_dly_ctl_re & hdmi_in0_s7datacapture2_dly_ctl_r[1]); +assign hdmi_in0_s7datacapture2_do_delay_master_dec_i = (hdmi_in0_s7datacapture2_dly_ctl_re & hdmi_in0_s7datacapture2_dly_ctl_r[2]); +assign hdmi_in0_s7datacapture2_do_delay_slave_inc_i = (hdmi_in0_s7datacapture2_dly_ctl_re & hdmi_in0_s7datacapture2_dly_ctl_r[3]); +assign hdmi_in0_s7datacapture2_do_delay_slave_dec_i = (hdmi_in0_s7datacapture2_dly_ctl_re & hdmi_in0_s7datacapture2_dly_ctl_r[4]); +assign hdmi_in0_s7datacapture2_reset_lateness = hdmi_in0_s7datacapture2_do_reset_lateness_o; +assign hdmi_in0_s7datacapture2_do_reset_lateness_i = hdmi_in0_s7datacapture2_phase_reset_re; +assign hdmi_in0_s7datacapture2_sync_mcntvalue_wait = (~hdmi_in0_s7datacapture2_sync_mcntvalue_ping_i); +assign hdmi_in0_s7datacapture2_sync_mcntvalue_ping_i = ((hdmi_in0_s7datacapture2_sync_mcntvalue_starter | hdmi_in0_s7datacapture2_sync_mcntvalue_pong_o) | hdmi_in0_s7datacapture2_sync_mcntvalue_done); +assign hdmi_in0_s7datacapture2_sync_mcntvalue_pong_i = hdmi_in0_s7datacapture2_sync_mcntvalue_ping_o1; +assign hdmi_in0_s7datacapture2_sync_mcntvalue_ping_o0 = (hdmi_in0_s7datacapture2_sync_mcntvalue_ping_toggle_o ^ hdmi_in0_s7datacapture2_sync_mcntvalue_ping_toggle_o_r); +assign hdmi_in0_s7datacapture2_sync_mcntvalue_pong_o = (hdmi_in0_s7datacapture2_sync_mcntvalue_pong_toggle_o ^ hdmi_in0_s7datacapture2_sync_mcntvalue_pong_toggle_o_r); +assign hdmi_in0_s7datacapture2_sync_mcntvalue_done = (hdmi_in0_s7datacapture2_sync_mcntvalue_count == 1'd0); +assign hdmi_in0_s7datacapture2_sync_scntvalue_wait = (~hdmi_in0_s7datacapture2_sync_scntvalue_ping_i); +assign hdmi_in0_s7datacapture2_sync_scntvalue_ping_i = ((hdmi_in0_s7datacapture2_sync_scntvalue_starter | hdmi_in0_s7datacapture2_sync_scntvalue_pong_o) | hdmi_in0_s7datacapture2_sync_scntvalue_done); +assign hdmi_in0_s7datacapture2_sync_scntvalue_pong_i = hdmi_in0_s7datacapture2_sync_scntvalue_ping_o1; +assign hdmi_in0_s7datacapture2_sync_scntvalue_ping_o0 = (hdmi_in0_s7datacapture2_sync_scntvalue_ping_toggle_o ^ hdmi_in0_s7datacapture2_sync_scntvalue_ping_toggle_o_r); +assign hdmi_in0_s7datacapture2_sync_scntvalue_pong_o = (hdmi_in0_s7datacapture2_sync_scntvalue_pong_toggle_o ^ hdmi_in0_s7datacapture2_sync_scntvalue_pong_toggle_o_r); +assign hdmi_in0_s7datacapture2_sync_scntvalue_done = (hdmi_in0_s7datacapture2_sync_scntvalue_count == 1'd0); +assign hdmi_in0_s7datacapture2_gearbox_rst = (pix1p25x_rst | hdmi_in0_pix_rst); +assign data2_cap_write_clk = pix1p25x_clk; +assign data2_cap_read_clk = hdmi_in0_pix_clk; +assign data2_cap_write_rst = hdmi_in0_s7datacapture2_gearbox_rst; +assign data2_cap_read_rst = hdmi_in0_s7datacapture2_gearbox_rst; +assign hdmi_in0_s7datacapture2_transition = (hdmi_in0_s7datacapture2_mdata_d != hdmi_in0_s7datacapture2_mdata); +assign hdmi_in0_s7datacapture2_inc = (hdmi_in0_s7datacapture2_transition & (hdmi_in0_s7datacapture2_mdata == hdmi_in0_s7datacapture2_sdata)); +assign hdmi_in0_s7datacapture2_dec = (hdmi_in0_s7datacapture2_transition & (hdmi_in0_s7datacapture2_mdata != hdmi_in0_s7datacapture2_sdata)); +assign hdmi_in0_s7datacapture2_do_delay_rst_o = (hdmi_in0_s7datacapture2_do_delay_rst_toggle_o ^ hdmi_in0_s7datacapture2_do_delay_rst_toggle_o_r); +assign hdmi_in0_s7datacapture2_do_delay_master_inc_o = (hdmi_in0_s7datacapture2_do_delay_master_inc_toggle_o ^ hdmi_in0_s7datacapture2_do_delay_master_inc_toggle_o_r); +assign hdmi_in0_s7datacapture2_do_delay_master_dec_o = (hdmi_in0_s7datacapture2_do_delay_master_dec_toggle_o ^ hdmi_in0_s7datacapture2_do_delay_master_dec_toggle_o_r); +assign hdmi_in0_s7datacapture2_do_delay_slave_inc_o = (hdmi_in0_s7datacapture2_do_delay_slave_inc_toggle_o ^ hdmi_in0_s7datacapture2_do_delay_slave_inc_toggle_o_r); +assign hdmi_in0_s7datacapture2_do_delay_slave_dec_o = (hdmi_in0_s7datacapture2_do_delay_slave_dec_toggle_o ^ hdmi_in0_s7datacapture2_do_delay_slave_dec_toggle_o_r); +assign hdmi_in0_s7datacapture2_do_reset_lateness_o = (hdmi_in0_s7datacapture2_do_reset_lateness_toggle_o ^ hdmi_in0_s7datacapture2_do_reset_lateness_toggle_o_r); +assign hdmi_in0_charsync2_raw = {hdmi_in0_charsync2_raw_data, hdmi_in0_charsync2_raw_data1}; +always @(*) begin + hdmi_in0_wer2_transitions <= 8'd0; + hdmi_in0_wer2_transitions[0] <= (hdmi_in0_wer2_data_r[0] ^ hdmi_in0_wer2_data_r[1]); + hdmi_in0_wer2_transitions[1] <= (hdmi_in0_wer2_data_r[1] ^ hdmi_in0_wer2_data_r[2]); + hdmi_in0_wer2_transitions[2] <= (hdmi_in0_wer2_data_r[2] ^ hdmi_in0_wer2_data_r[3]); + hdmi_in0_wer2_transitions[3] <= (hdmi_in0_wer2_data_r[3] ^ hdmi_in0_wer2_data_r[4]); + hdmi_in0_wer2_transitions[4] <= (hdmi_in0_wer2_data_r[4] ^ hdmi_in0_wer2_data_r[5]); + hdmi_in0_wer2_transitions[5] <= (hdmi_in0_wer2_data_r[5] ^ hdmi_in0_wer2_data_r[6]); + hdmi_in0_wer2_transitions[6] <= (hdmi_in0_wer2_data_r[6] ^ hdmi_in0_wer2_data_r[7]); + hdmi_in0_wer2_transitions[7] <= (hdmi_in0_wer2_data_r[7] ^ hdmi_in0_wer2_data_r[8]); +end +assign hdmi_in0_wer2_i = hdmi_in0_wer2_wer_counter_r_updated; +assign hdmi_in0_wer2_o = (hdmi_in0_wer2_toggle_o ^ hdmi_in0_wer2_toggle_o_r); +assign hdmi_in0_chansync_syncbuffer0_din = {hdmi_in0_chansync_data_in0_de, hdmi_in0_chansync_data_in0_c, hdmi_in0_chansync_data_in0_d, hdmi_in0_chansync_data_in0_raw}; +assign {hdmi_in0_chansync_data_out0_de, hdmi_in0_chansync_data_out0_c, hdmi_in0_chansync_data_out0_d, hdmi_in0_chansync_data_out0_raw} = hdmi_in0_chansync_syncbuffer0_dout; +assign hdmi_in0_chansync_is_control0 = (~hdmi_in0_chansync_data_out0_de); +assign hdmi_in0_chansync_syncbuffer0_re = ((~hdmi_in0_chansync_is_control0) | hdmi_in0_chansync_all_control); +assign hdmi_in0_chansync_syncbuffer1_din = {hdmi_in0_chansync_data_in1_de, hdmi_in0_chansync_data_in1_c, hdmi_in0_chansync_data_in1_d, hdmi_in0_chansync_data_in1_raw}; +assign {hdmi_in0_chansync_data_out1_de, hdmi_in0_chansync_data_out1_c, hdmi_in0_chansync_data_out1_d, hdmi_in0_chansync_data_out1_raw} = hdmi_in0_chansync_syncbuffer1_dout; +assign hdmi_in0_chansync_is_control1 = (~hdmi_in0_chansync_data_out1_de); +assign hdmi_in0_chansync_syncbuffer1_re = ((~hdmi_in0_chansync_is_control1) | hdmi_in0_chansync_all_control); +assign hdmi_in0_chansync_syncbuffer2_din = {hdmi_in0_chansync_data_in2_de, hdmi_in0_chansync_data_in2_c, hdmi_in0_chansync_data_in2_d, hdmi_in0_chansync_data_in2_raw}; +assign {hdmi_in0_chansync_data_out2_de, hdmi_in0_chansync_data_out2_c, hdmi_in0_chansync_data_out2_d, hdmi_in0_chansync_data_out2_raw} = hdmi_in0_chansync_syncbuffer2_dout; +assign hdmi_in0_chansync_is_control2 = (~hdmi_in0_chansync_data_out2_de); +assign hdmi_in0_chansync_syncbuffer2_re = ((~hdmi_in0_chansync_is_control2) | hdmi_in0_chansync_all_control); +assign hdmi_in0_chansync_all_control = ((hdmi_in0_chansync_is_control0 & hdmi_in0_chansync_is_control1) & hdmi_in0_chansync_is_control2); +assign hdmi_in0_chansync_some_control = ((hdmi_in0_chansync_is_control0 | hdmi_in0_chansync_is_control1) | hdmi_in0_chansync_is_control2); +assign hdmi_in0_chansync_syncbuffer0_wrport_adr = hdmi_in0_chansync_syncbuffer0_produce; +assign hdmi_in0_chansync_syncbuffer0_wrport_dat_w = hdmi_in0_chansync_syncbuffer0_din; +assign hdmi_in0_chansync_syncbuffer0_wrport_we = 1'd1; +assign hdmi_in0_chansync_syncbuffer0_rdport_adr = hdmi_in0_chansync_syncbuffer0_consume; +assign hdmi_in0_chansync_syncbuffer0_dout = hdmi_in0_chansync_syncbuffer0_rdport_dat_r; +assign hdmi_in0_chansync_syncbuffer1_wrport_adr = hdmi_in0_chansync_syncbuffer1_produce; +assign hdmi_in0_chansync_syncbuffer1_wrport_dat_w = hdmi_in0_chansync_syncbuffer1_din; +assign hdmi_in0_chansync_syncbuffer1_wrport_we = 1'd1; +assign hdmi_in0_chansync_syncbuffer1_rdport_adr = hdmi_in0_chansync_syncbuffer1_consume; +assign hdmi_in0_chansync_syncbuffer1_dout = hdmi_in0_chansync_syncbuffer1_rdport_dat_r; +assign hdmi_in0_chansync_syncbuffer2_wrport_adr = hdmi_in0_chansync_syncbuffer2_produce; +assign hdmi_in0_chansync_syncbuffer2_wrport_dat_w = hdmi_in0_chansync_syncbuffer2_din; +assign hdmi_in0_chansync_syncbuffer2_wrport_we = 1'd1; +assign hdmi_in0_chansync_syncbuffer2_rdport_adr = hdmi_in0_chansync_syncbuffer2_consume; +assign hdmi_in0_chansync_syncbuffer2_dout = hdmi_in0_chansync_syncbuffer2_rdport_dat_r; +assign hdmi_in0_syncpol_de = hdmi_in0_syncpol_de_r; +assign hdmi_in0_syncpol_hsync = hdmi_in0_syncpol_c_out[0]; +assign hdmi_in0_syncpol_vsync = hdmi_in0_syncpol_c_out[1]; +assign hdmi_in0_syncpol_de_rising = (hdmi_in0_syncpol_de_r & (~hdmi_in0_syncpol_data_in0_de)); +assign hdmi_in0_resdetection_pn_de = ((~hdmi_in0_resdetection_de) & hdmi_in0_resdetection_de_r); +assign hdmi_in0_resdetection_p_vsync = (hdmi_in0_resdetection_vsync & (~hdmi_in0_resdetection_vsync_r)); +assign hdmi_in0_frame_new_frame = (hdmi_in0_frame_vsync & (~hdmi_in0_frame_vsync_r)); +assign hdmi_in0_frame_rgb2ycbcr_sink_valid = hdmi_in0_frame_valid_i; +assign hdmi_in0_frame_rgb2ycbcr_sink_payload_r = hdmi_in0_frame_r; +assign hdmi_in0_frame_rgb2ycbcr_sink_payload_g = hdmi_in0_frame_g; +assign hdmi_in0_frame_rgb2ycbcr_sink_payload_b = hdmi_in0_frame_b; +assign hdmi_in0_frame_chroma_downsampler_sink_valid = hdmi_in0_frame_rgb2ycbcr_source_valid; +assign hdmi_in0_frame_rgb2ycbcr_source_ready = hdmi_in0_frame_chroma_downsampler_sink_ready; +assign hdmi_in0_frame_chroma_downsampler_sink_first = hdmi_in0_frame_rgb2ycbcr_source_first; +assign hdmi_in0_frame_chroma_downsampler_sink_last = hdmi_in0_frame_rgb2ycbcr_source_last; +assign hdmi_in0_frame_chroma_downsampler_sink_payload_y = hdmi_in0_frame_rgb2ycbcr_source_payload_y; +assign hdmi_in0_frame_chroma_downsampler_sink_payload_cb = hdmi_in0_frame_rgb2ycbcr_source_payload_cb; +assign hdmi_in0_frame_chroma_downsampler_sink_payload_cr = hdmi_in0_frame_rgb2ycbcr_source_payload_cr; +assign hdmi_in0_frame_chroma_downsampler_source_ready = 1'd1; +assign hdmi_in0_frame_chroma_downsampler_first = (hdmi_in0_frame_de & (~hdmi_in0_frame_de_r)); +assign hdmi_in0_frame_encoded_pixel = {hdmi_in0_frame_chroma_downsampler_source_payload_cb_cr, hdmi_in0_frame_chroma_downsampler_source_payload_y}; +assign hdmi_in0_frame_fifo_sink_payload_pixels = hdmi_in0_frame_cur_word; +assign hdmi_in0_frame_fifo_sink_valid = hdmi_in0_frame_cur_word_valid; +assign hdmi_in0_frame_frame_valid = hdmi_in0_frame_fifo_source_valid; +assign hdmi_in0_frame_fifo_source_ready = hdmi_in0_frame_frame_ready; +assign hdmi_in0_frame_frame_first = hdmi_in0_frame_fifo_source_first; +assign hdmi_in0_frame_frame_last = hdmi_in0_frame_fifo_source_last; +assign hdmi_in0_frame_frame_payload_sof = hdmi_in0_frame_fifo_source_payload_sof; +assign hdmi_in0_frame_frame_payload_pixels = hdmi_in0_frame_fifo_source_payload_pixels; +assign hdmi_in0_frame_busy = 1'd0; +assign hdmi_in0_frame_pix_overflow_reset = hdmi_in0_frame_overflow_reset_o; +assign hdmi_in0_frame_overflow_reset_ack_i = hdmi_in0_frame_pix_overflow_reset; +assign hdmi_in0_frame_overflow_w = (hdmi_in0_frame_sys_overflow & (~hdmi_in0_frame_overflow_mask)); +assign hdmi_in0_frame_overflow_reset_i = hdmi_in0_frame_overflow_re; +assign hdmi_in0_frame_rgb2ycbcr_pipe_ce = (hdmi_in0_frame_rgb2ycbcr_source_ready | (~hdmi_in0_frame_rgb2ycbcr_valid_n7)); +assign hdmi_in0_frame_rgb2ycbcr_sink_ready = hdmi_in0_frame_rgb2ycbcr_pipe_ce; +assign hdmi_in0_frame_rgb2ycbcr_source_valid = hdmi_in0_frame_rgb2ycbcr_valid_n7; +assign hdmi_in0_frame_rgb2ycbcr_busy = ((((((((1'd0 | hdmi_in0_frame_rgb2ycbcr_valid_n0) | hdmi_in0_frame_rgb2ycbcr_valid_n1) | hdmi_in0_frame_rgb2ycbcr_valid_n2) | hdmi_in0_frame_rgb2ycbcr_valid_n3) | hdmi_in0_frame_rgb2ycbcr_valid_n4) | hdmi_in0_frame_rgb2ycbcr_valid_n5) | hdmi_in0_frame_rgb2ycbcr_valid_n6) | hdmi_in0_frame_rgb2ycbcr_valid_n7); +assign hdmi_in0_frame_rgb2ycbcr_source_first = hdmi_in0_frame_rgb2ycbcr_first_n7; +assign hdmi_in0_frame_rgb2ycbcr_source_last = hdmi_in0_frame_rgb2ycbcr_last_n7; +assign hdmi_in0_frame_rgb2ycbcr_ce = hdmi_in0_frame_rgb2ycbcr_pipe_ce; +assign hdmi_in0_frame_rgb2ycbcr_sink_r = hdmi_in0_frame_rgb2ycbcr_sink_payload_r; +assign hdmi_in0_frame_rgb2ycbcr_sink_g = hdmi_in0_frame_rgb2ycbcr_sink_payload_g; +assign hdmi_in0_frame_rgb2ycbcr_sink_b = hdmi_in0_frame_rgb2ycbcr_sink_payload_b; +assign hdmi_in0_frame_rgb2ycbcr_source_payload_y = hdmi_in0_frame_rgb2ycbcr_source_y; +assign hdmi_in0_frame_rgb2ycbcr_source_payload_cb = hdmi_in0_frame_rgb2ycbcr_source_cb; +assign hdmi_in0_frame_rgb2ycbcr_source_payload_cr = hdmi_in0_frame_rgb2ycbcr_source_cr; +assign hdmi_in0_frame_chroma_downsampler_pipe_ce = (hdmi_in0_frame_chroma_downsampler_source_ready | (~hdmi_in0_frame_chroma_downsampler_valid_n2)); +assign hdmi_in0_frame_chroma_downsampler_sink_ready = hdmi_in0_frame_chroma_downsampler_pipe_ce; +assign hdmi_in0_frame_chroma_downsampler_source_valid = hdmi_in0_frame_chroma_downsampler_valid_n2; +assign hdmi_in0_frame_chroma_downsampler_busy = (((1'd0 | hdmi_in0_frame_chroma_downsampler_valid_n0) | hdmi_in0_frame_chroma_downsampler_valid_n1) | hdmi_in0_frame_chroma_downsampler_valid_n2); +assign hdmi_in0_frame_chroma_downsampler_source_first = hdmi_in0_frame_chroma_downsampler_first_n2; +assign hdmi_in0_frame_chroma_downsampler_source_last = hdmi_in0_frame_chroma_downsampler_last_n2; +assign hdmi_in0_frame_chroma_downsampler_ce = hdmi_in0_frame_chroma_downsampler_pipe_ce; +assign hdmi_in0_frame_chroma_downsampler_sink_y = hdmi_in0_frame_chroma_downsampler_sink_payload_y; +assign hdmi_in0_frame_chroma_downsampler_sink_cb = hdmi_in0_frame_chroma_downsampler_sink_payload_cb; +assign hdmi_in0_frame_chroma_downsampler_sink_cr = hdmi_in0_frame_chroma_downsampler_sink_payload_cr; +assign hdmi_in0_frame_chroma_downsampler_source_payload_y = hdmi_in0_frame_chroma_downsampler_source_y; +assign hdmi_in0_frame_chroma_downsampler_source_payload_cb_cr = hdmi_in0_frame_chroma_downsampler_source_cb_cr; +assign hdmi_in0_frame_chroma_downsampler_cb_mean = hdmi_in0_frame_chroma_downsampler_cb_sum[8:1]; +assign hdmi_in0_frame_chroma_downsampler_cr_mean = hdmi_in0_frame_chroma_downsampler_cr_sum[8:1]; +assign hdmi_in0_frame_fifo_asyncfifo_din = {hdmi_in0_frame_fifo_fifo_in_last, hdmi_in0_frame_fifo_fifo_in_first, hdmi_in0_frame_fifo_fifo_in_payload_pixels, hdmi_in0_frame_fifo_fifo_in_payload_sof}; +assign {hdmi_in0_frame_fifo_fifo_out_last, hdmi_in0_frame_fifo_fifo_out_first, hdmi_in0_frame_fifo_fifo_out_payload_pixels, hdmi_in0_frame_fifo_fifo_out_payload_sof} = hdmi_in0_frame_fifo_asyncfifo_dout; +assign hdmi_in0_frame_fifo_sink_ready = hdmi_in0_frame_fifo_asyncfifo_writable; +assign hdmi_in0_frame_fifo_asyncfifo_we = hdmi_in0_frame_fifo_sink_valid; +assign hdmi_in0_frame_fifo_fifo_in_first = hdmi_in0_frame_fifo_sink_first; +assign hdmi_in0_frame_fifo_fifo_in_last = hdmi_in0_frame_fifo_sink_last; +assign hdmi_in0_frame_fifo_fifo_in_payload_sof = hdmi_in0_frame_fifo_sink_payload_sof; +assign hdmi_in0_frame_fifo_fifo_in_payload_pixels = hdmi_in0_frame_fifo_sink_payload_pixels; +assign hdmi_in0_frame_fifo_source_valid = hdmi_in0_frame_fifo_asyncfifo_readable; +assign hdmi_in0_frame_fifo_source_first = hdmi_in0_frame_fifo_fifo_out_first; +assign hdmi_in0_frame_fifo_source_last = hdmi_in0_frame_fifo_fifo_out_last; +assign hdmi_in0_frame_fifo_source_payload_sof = hdmi_in0_frame_fifo_fifo_out_payload_sof; +assign hdmi_in0_frame_fifo_source_payload_pixels = hdmi_in0_frame_fifo_fifo_out_payload_pixels; +assign hdmi_in0_frame_fifo_asyncfifo_re = hdmi_in0_frame_fifo_source_ready; +assign hdmi_in0_frame_fifo_graycounter0_ce = (hdmi_in0_frame_fifo_asyncfifo_writable & hdmi_in0_frame_fifo_asyncfifo_we); +assign hdmi_in0_frame_fifo_graycounter1_ce = (hdmi_in0_frame_fifo_asyncfifo_readable & hdmi_in0_frame_fifo_asyncfifo_re); +assign hdmi_in0_frame_fifo_asyncfifo_writable = (((hdmi_in0_frame_fifo_graycounter0_q[9] == hdmi_in0_frame_fifo_consume_wdomain[9]) | (hdmi_in0_frame_fifo_graycounter0_q[8] == hdmi_in0_frame_fifo_consume_wdomain[8])) | (hdmi_in0_frame_fifo_graycounter0_q[7:0] != hdmi_in0_frame_fifo_consume_wdomain[7:0])); +assign hdmi_in0_frame_fifo_asyncfifo_readable = (hdmi_in0_frame_fifo_graycounter1_q != hdmi_in0_frame_fifo_produce_rdomain); +assign hdmi_in0_frame_fifo_wrport_adr = hdmi_in0_frame_fifo_graycounter0_q_binary[8:0]; +assign hdmi_in0_frame_fifo_wrport_dat_w = hdmi_in0_frame_fifo_asyncfifo_din; +assign hdmi_in0_frame_fifo_wrport_we = hdmi_in0_frame_fifo_graycounter0_ce; +assign hdmi_in0_frame_fifo_rdport_adr = hdmi_in0_frame_fifo_graycounter1_q_next_binary[8:0]; +assign hdmi_in0_frame_fifo_asyncfifo_dout = hdmi_in0_frame_fifo_rdport_dat_r; +always @(*) begin + hdmi_in0_frame_fifo_graycounter0_q_next_binary <= 10'd0; + if (hdmi_in0_frame_fifo_graycounter0_ce) begin + hdmi_in0_frame_fifo_graycounter0_q_next_binary <= (hdmi_in0_frame_fifo_graycounter0_q_binary + 1'd1); + end else begin + hdmi_in0_frame_fifo_graycounter0_q_next_binary <= hdmi_in0_frame_fifo_graycounter0_q_binary; + end +end +assign hdmi_in0_frame_fifo_graycounter0_q_next = (hdmi_in0_frame_fifo_graycounter0_q_next_binary ^ hdmi_in0_frame_fifo_graycounter0_q_next_binary[9:1]); +always @(*) begin + hdmi_in0_frame_fifo_graycounter1_q_next_binary <= 10'd0; + if (hdmi_in0_frame_fifo_graycounter1_ce) begin + hdmi_in0_frame_fifo_graycounter1_q_next_binary <= (hdmi_in0_frame_fifo_graycounter1_q_binary + 1'd1); + end else begin + hdmi_in0_frame_fifo_graycounter1_q_next_binary <= hdmi_in0_frame_fifo_graycounter1_q_binary; + end +end +assign hdmi_in0_frame_fifo_graycounter1_q_next = (hdmi_in0_frame_fifo_graycounter1_q_next_binary ^ hdmi_in0_frame_fifo_graycounter1_q_next_binary[9:1]); +assign hdmi_in0_frame_overflow_reset_o = (hdmi_in0_frame_overflow_reset_toggle_o ^ hdmi_in0_frame_overflow_reset_toggle_o_r); +assign hdmi_in0_frame_overflow_reset_ack_o = (hdmi_in0_frame_overflow_reset_ack_toggle_o ^ hdmi_in0_frame_overflow_reset_ack_toggle_o_r); +assign hdmi_in0_dma_slot_array_address_reached = hdmi_in0_dma_current_address; +assign hdmi_in0_dma_last_word = (hdmi_in0_dma_mwords_remaining == 1'd1); +assign hdmi_in0_dma_memory_word = {hdmi_in0_dma_frame_payload_pixels, hdmi_in0_dma_frame_payload_pixels, hdmi_in0_dma_frame_payload_pixels, hdmi_in0_dma_frame_payload_pixels, hdmi_in0_dma_frame_payload_pixels, hdmi_in0_dma_frame_payload_pixels, hdmi_in0_dma_frame_payload_pixels, hdmi_in0_dma_frame_payload_pixels, hdmi_in0_dma_frame_payload_pixels, hdmi_in0_dma_frame_payload_pixels, hdmi_in0_dma_frame_payload_pixels, hdmi_in0_dma_frame_payload_pixels, hdmi_in0_dma_frame_payload_pixels, hdmi_in0_dma_frame_payload_pixels, hdmi_in0_dma_frame_payload_pixels, hdmi_in0_dma_frame_payload_pixels}; +assign hdmi_in0_dma_sink_sink_payload_address = hdmi_in0_dma_current_address; +assign hdmi_in0_dma_sink_sink_payload_data = hdmi_in0_dma_memory_word; +assign hdmi_in0_dma_slot_array_change_slot = ((~hdmi_in0_dma_slot_array_address_valid) | hdmi_in0_dma_slot_array_address_done); +assign hdmi_in0_dma_slot_array_address = comb_rhs_array_muxed36; +assign hdmi_in0_dma_slot_array_address_valid = comb_rhs_array_muxed37; +assign hdmi_in0_dma_slot_array_slot0_address_reached = hdmi_in0_dma_slot_array_address_reached; +assign hdmi_in0_dma_slot_array_slot1_address_reached = hdmi_in0_dma_slot_array_address_reached; +assign hdmi_in0_dma_slot_array_slot0_address_done = (hdmi_in0_dma_slot_array_address_done & (hdmi_in0_dma_slot_array_current_slot == 1'd0)); +assign hdmi_in0_dma_slot_array_slot1_address_done = (hdmi_in0_dma_slot_array_address_done & (hdmi_in0_dma_slot_array_current_slot == 1'd1)); +always @(*) begin + hdmi_in0_dma_slot_array_slot0_clear <= 1'd0; + if ((hdmi_in0_dma_slot_array_pending_re & hdmi_in0_dma_slot_array_pending_r[0])) begin + hdmi_in0_dma_slot_array_slot0_clear <= 1'd1; + end +end +always @(*) begin + hdmi_in0_dma_slot_array_status_w <= 2'd0; + hdmi_in0_dma_slot_array_status_w[0] <= hdmi_in0_dma_slot_array_slot0_status; + hdmi_in0_dma_slot_array_status_w[1] <= hdmi_in0_dma_slot_array_slot1_status; +end +always @(*) begin + hdmi_in0_dma_slot_array_slot1_clear <= 1'd0; + if ((hdmi_in0_dma_slot_array_pending_re & hdmi_in0_dma_slot_array_pending_r[1])) begin + hdmi_in0_dma_slot_array_slot1_clear <= 1'd1; + end +end +always @(*) begin + hdmi_in0_dma_slot_array_pending_w <= 2'd0; + hdmi_in0_dma_slot_array_pending_w[0] <= hdmi_in0_dma_slot_array_slot0_pending; + hdmi_in0_dma_slot_array_pending_w[1] <= hdmi_in0_dma_slot_array_slot1_pending; +end +assign hdmi_in0_dma_slot_array_irq = ((hdmi_in0_dma_slot_array_pending_w[0] & hdmi_in0_dma_slot_array_storage[0]) | (hdmi_in0_dma_slot_array_pending_w[1] & hdmi_in0_dma_slot_array_storage[1])); +assign hdmi_in0_dma_slot_array_slot0_status = hdmi_in0_dma_slot_array_slot0_trigger; +assign hdmi_in0_dma_slot_array_slot0_pending = hdmi_in0_dma_slot_array_slot0_trigger; +assign hdmi_in0_dma_slot_array_slot1_status = hdmi_in0_dma_slot_array_slot1_trigger; +assign hdmi_in0_dma_slot_array_slot1_pending = hdmi_in0_dma_slot_array_slot1_trigger; +assign hdmi_in0_dma_slot_array_slot0_address = hdmi_in0_dma_slot_array_slot0_address_storage[28:5]; +assign hdmi_in0_dma_slot_array_slot0_address_valid = hdmi_in0_dma_slot_array_slot0_status_storage[0]; +assign hdmi_in0_dma_slot_array_slot0_status_dat_w = 2'd2; +assign hdmi_in0_dma_slot_array_slot0_status_we = hdmi_in0_dma_slot_array_slot0_address_done; +assign hdmi_in0_dma_slot_array_slot0_address_dat_w[28:5] = hdmi_in0_dma_slot_array_slot0_address_reached; +assign hdmi_in0_dma_slot_array_slot0_address_we = hdmi_in0_dma_slot_array_slot0_address_done; +assign hdmi_in0_dma_slot_array_slot0_trigger = hdmi_in0_dma_slot_array_slot0_status_storage[1]; +assign hdmi_in0_dma_slot_array_slot1_address = hdmi_in0_dma_slot_array_slot1_address_storage[28:5]; +assign hdmi_in0_dma_slot_array_slot1_address_valid = hdmi_in0_dma_slot_array_slot1_status_storage[0]; +assign hdmi_in0_dma_slot_array_slot1_status_dat_w = 2'd2; +assign hdmi_in0_dma_slot_array_slot1_status_we = hdmi_in0_dma_slot_array_slot1_address_done; +assign hdmi_in0_dma_slot_array_slot1_address_dat_w[28:5] = hdmi_in0_dma_slot_array_slot1_address_reached; +assign hdmi_in0_dma_slot_array_slot1_address_we = hdmi_in0_dma_slot_array_slot1_address_done; +assign hdmi_in0_dma_slot_array_slot1_trigger = hdmi_in0_dma_slot_array_slot1_status_storage[1]; +assign litedramcrossbar_litedramnativeport0_cmd_payload_we0 = 1'd1; +assign litedramcrossbar_litedramnativeport0_cmd_payload_addr0 = hdmi_in0_dma_sink_sink_payload_address; +assign litedramcrossbar_litedramnativeport0_cmd_valid0 = (hdmi_in0_dma_fifo_sink_ready & hdmi_in0_dma_sink_sink_valid); +assign hdmi_in0_dma_sink_sink_ready = (hdmi_in0_dma_fifo_sink_ready & litedramcrossbar_litedramnativeport0_cmd_ready0); +assign hdmi_in0_dma_fifo_sink_valid = (hdmi_in0_dma_sink_sink_valid & litedramcrossbar_litedramnativeport0_cmd_ready0); +assign hdmi_in0_dma_fifo_sink_payload_data = hdmi_in0_dma_sink_sink_payload_data; +assign litedramcrossbar_litedramnativeport0_wdata_payload_we = 32'd4294967295; +assign litedramcrossbar_litedramnativeport0_wdata_valid = hdmi_in0_dma_fifo_source_valid; +assign hdmi_in0_dma_fifo_source_ready = litedramcrossbar_litedramnativeport0_wdata_ready; +assign litedramcrossbar_litedramnativeport0_wdata_payload_data = hdmi_in0_dma_fifo_source_payload_data; +assign hdmi_in0_dma_fifo_syncfifo_din = {hdmi_in0_dma_fifo_fifo_in_last, hdmi_in0_dma_fifo_fifo_in_first, hdmi_in0_dma_fifo_fifo_in_payload_data}; +assign {hdmi_in0_dma_fifo_fifo_out_last, hdmi_in0_dma_fifo_fifo_out_first, hdmi_in0_dma_fifo_fifo_out_payload_data} = hdmi_in0_dma_fifo_syncfifo_dout; +assign hdmi_in0_dma_fifo_sink_ready = hdmi_in0_dma_fifo_syncfifo_writable; +assign hdmi_in0_dma_fifo_syncfifo_we = hdmi_in0_dma_fifo_sink_valid; +assign hdmi_in0_dma_fifo_fifo_in_first = hdmi_in0_dma_fifo_sink_first; +assign hdmi_in0_dma_fifo_fifo_in_last = hdmi_in0_dma_fifo_sink_last; +assign hdmi_in0_dma_fifo_fifo_in_payload_data = hdmi_in0_dma_fifo_sink_payload_data; +assign hdmi_in0_dma_fifo_source_valid = hdmi_in0_dma_fifo_syncfifo_readable; +assign hdmi_in0_dma_fifo_source_first = hdmi_in0_dma_fifo_fifo_out_first; +assign hdmi_in0_dma_fifo_source_last = hdmi_in0_dma_fifo_fifo_out_last; +assign hdmi_in0_dma_fifo_source_payload_data = hdmi_in0_dma_fifo_fifo_out_payload_data; +assign hdmi_in0_dma_fifo_syncfifo_re = hdmi_in0_dma_fifo_source_ready; +always @(*) begin + hdmi_in0_dma_fifo_wrport_adr <= 4'd0; + if (hdmi_in0_dma_fifo_replace) begin + hdmi_in0_dma_fifo_wrport_adr <= (hdmi_in0_dma_fifo_produce - 1'd1); + end else begin + hdmi_in0_dma_fifo_wrport_adr <= hdmi_in0_dma_fifo_produce; + end +end +assign hdmi_in0_dma_fifo_wrport_dat_w = hdmi_in0_dma_fifo_syncfifo_din; +assign hdmi_in0_dma_fifo_wrport_we = (hdmi_in0_dma_fifo_syncfifo_we & (hdmi_in0_dma_fifo_syncfifo_writable | hdmi_in0_dma_fifo_replace)); +assign hdmi_in0_dma_fifo_do_read = (hdmi_in0_dma_fifo_syncfifo_readable & hdmi_in0_dma_fifo_syncfifo_re); +assign hdmi_in0_dma_fifo_rdport_adr = hdmi_in0_dma_fifo_consume; +assign hdmi_in0_dma_fifo_syncfifo_dout = hdmi_in0_dma_fifo_rdport_dat_r; +assign hdmi_in0_dma_fifo_syncfifo_writable = (hdmi_in0_dma_fifo_level != 5'd16); +assign hdmi_in0_dma_fifo_syncfifo_readable = (hdmi_in0_dma_fifo_level != 1'd0); +always @(*) begin + hdmi_in0_dma_frame_ready <= 1'd0; + hdmi_in0_dma_reset_words <= 1'd0; + dma_next_state <= 2'd0; + hdmi_in0_dma_count_word <= 1'd0; + hdmi_in0_dma_sink_sink_valid <= 1'd0; + hdmi_in0_dma_slot_array_address_done <= 1'd0; + dma_next_state <= dma_state; + case (dma_state) + 1'd1: begin + hdmi_in0_dma_frame_ready <= hdmi_in0_dma_sink_sink_ready; + if (hdmi_in0_dma_frame_valid) begin + hdmi_in0_dma_sink_sink_valid <= 1'd1; + if (hdmi_in0_dma_sink_sink_ready) begin + hdmi_in0_dma_count_word <= 1'd1; + if (hdmi_in0_dma_last_word) begin + dma_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + if ((~litedramcrossbar_litedramnativeport0_wdata_valid)) begin + hdmi_in0_dma_slot_array_address_done <= 1'd1; + dma_next_state <= 1'd0; + end + end + default: begin + hdmi_in0_dma_reset_words <= 1'd1; + hdmi_in0_dma_frame_ready <= ((~hdmi_in0_dma_slot_array_address_valid) | (~hdmi_in0_dma_frame_payload_sof)); + if (((hdmi_in0_dma_slot_array_address_valid & hdmi_in0_dma_frame_payload_sof) & hdmi_in0_dma_frame_valid)) begin + dma_next_state <= 1'd1; + end + end + endcase +end +assign hdmi_out0_core_source_source_ready = 1'd1; +assign hdmi_out0_resetinserter_reset = (hdmi_out0_core_source_source_param_de & (~hdmi_out0_de_r)); +assign hdmi_out0_resetinserter_sink_sink_valid = hdmi_out0_core_source_valid_d; +assign hdmi_out0_resetinserter_sink_sink_payload_y = hdmi_out0_core_source_data_d[7:0]; +assign hdmi_out0_resetinserter_sink_sink_payload_cb_cr = hdmi_out0_core_source_data_d[15:8]; +assign hdmi_out0_sink_valid = hdmi_out0_resetinserter_source_source_valid; +assign hdmi_out0_resetinserter_source_source_ready = hdmi_out0_sink_ready; +assign hdmi_out0_sink_first = hdmi_out0_resetinserter_source_source_first; +assign hdmi_out0_sink_last = hdmi_out0_resetinserter_source_source_last; +assign hdmi_out0_sink_payload_y = hdmi_out0_resetinserter_source_source_payload_y; +assign hdmi_out0_sink_payload_cb = hdmi_out0_resetinserter_source_source_payload_cb; +assign hdmi_out0_sink_payload_cr = hdmi_out0_resetinserter_source_source_payload_cr; +assign hdmi_out0_driver_sink_sink_valid = hdmi_out0_source_valid; +assign hdmi_out0_source_ready = hdmi_out0_driver_sink_sink_ready; +assign hdmi_out0_driver_sink_sink_first = hdmi_out0_source_first; +assign hdmi_out0_driver_sink_sink_last = hdmi_out0_source_last; +assign hdmi_out0_driver_sink_sink_payload_r = hdmi_out0_source_payload_r; +assign hdmi_out0_driver_sink_sink_payload_g = hdmi_out0_source_payload_g; +assign hdmi_out0_driver_sink_sink_payload_b = hdmi_out0_source_payload_b; +assign hdmi_out0_sink_payload_de = hdmi_out0_core_source_source_param_de; +assign hdmi_out0_sink_payload_vsync = hdmi_out0_core_source_source_param_vsync; +assign hdmi_out0_sink_payload_hsync = hdmi_out0_core_source_source_param_hsync; +assign hdmi_out0_driver_sink_sink_param_de = hdmi_out0_source_payload_de; +assign hdmi_out0_driver_sink_sink_param_vsync = hdmi_out0_source_payload_vsync; +assign hdmi_out0_driver_sink_sink_param_hsync = hdmi_out0_source_payload_hsync; +assign hdmi_out0_core_timinggenerator_sink_valid = hdmi_out0_core_initiator_source_source_valid; +assign hdmi_out0_core_dmareader_sink_valid = hdmi_out0_core_initiator_source_source_valid; +assign hdmi_out0_core_initiator_source_source_ready = hdmi_out0_core_timinggenerator_sink_ready; +assign hdmi_out0_core_source_source_valid = (hdmi_out0_core_timinggenerator_source_valid & ((~hdmi_out0_core_timinggenerator_source_payload_de) | hdmi_out0_core_dmareader_source_valid)); +always @(*) begin + hdmi_out0_core_timinggenerator_source_ready <= 1'd0; + hdmi_out0_core_dmareader_source_ready <= 1'd0; + if ((~hdmi_out0_core_initiator_source_source_valid)) begin + hdmi_out0_core_timinggenerator_source_ready <= 1'd1; + hdmi_out0_core_dmareader_source_ready <= 1'd1; + end else begin + if ((hdmi_out0_core_source_source_valid & hdmi_out0_core_source_source_ready)) begin + hdmi_out0_core_timinggenerator_source_ready <= 1'd1; + hdmi_out0_core_dmareader_source_ready <= (hdmi_out0_core_timinggenerator_source_payload_de | 1'd0); + end + end +end +assign hdmi_out0_core_timinggenerator_sink_payload_hres = hdmi_out0_core_initiator_source_source_payload_hres; +assign hdmi_out0_core_timinggenerator_sink_payload_hsync_start = hdmi_out0_core_initiator_source_source_payload_hsync_start; +assign hdmi_out0_core_timinggenerator_sink_payload_hsync_end = hdmi_out0_core_initiator_source_source_payload_hsync_end; +assign hdmi_out0_core_timinggenerator_sink_payload_hscan = hdmi_out0_core_initiator_source_source_payload_hscan; +assign hdmi_out0_core_timinggenerator_sink_payload_vres = hdmi_out0_core_initiator_source_source_payload_vres; +assign hdmi_out0_core_timinggenerator_sink_payload_vsync_start = hdmi_out0_core_initiator_source_source_payload_vsync_start; +assign hdmi_out0_core_timinggenerator_sink_payload_vsync_end = hdmi_out0_core_initiator_source_source_payload_vsync_end; +assign hdmi_out0_core_timinggenerator_sink_payload_vscan = hdmi_out0_core_initiator_source_source_payload_vscan; +assign hdmi_out0_core_dmareader_sink_payload_base = hdmi_out0_core_initiator_source_source_payload_base; +assign hdmi_out0_core_dmareader_sink_payload_length = hdmi_out0_core_initiator_source_source_payload_length; +assign hdmi_out0_core_source_source_param_de = hdmi_out0_core_timinggenerator_source_payload_de; +assign hdmi_out0_core_source_source_param_hsync = hdmi_out0_core_timinggenerator_source_payload_hsync; +assign hdmi_out0_core_source_source_param_vsync = hdmi_out0_core_timinggenerator_source_payload_vsync; +assign hdmi_out0_core_source_source_payload_data = hdmi_out0_core_dmareader_source_payload_data; +assign hdmi_out0_core_i = hdmi_out0_core_underflow_update_underflow_update_re; +assign hdmi_out0_core_underflow_update = hdmi_out0_core_o; +assign hdmi_out0_core_initiator_cdc_sink_payload_hres = hdmi_out0_core_initiator_csrstorage0_storage; +assign hdmi_out0_core_initiator_cdc_sink_payload_hsync_start = hdmi_out0_core_initiator_csrstorage1_storage; +assign hdmi_out0_core_initiator_cdc_sink_payload_hsync_end = hdmi_out0_core_initiator_csrstorage2_storage; +assign hdmi_out0_core_initiator_cdc_sink_payload_hscan = hdmi_out0_core_initiator_csrstorage3_storage; +assign hdmi_out0_core_initiator_cdc_sink_payload_vres = hdmi_out0_core_initiator_csrstorage4_storage; +assign hdmi_out0_core_initiator_cdc_sink_payload_vsync_start = hdmi_out0_core_initiator_csrstorage5_storage; +assign hdmi_out0_core_initiator_cdc_sink_payload_vsync_end = hdmi_out0_core_initiator_csrstorage6_storage; +assign hdmi_out0_core_initiator_cdc_sink_payload_vscan = hdmi_out0_core_initiator_csrstorage7_storage; +assign hdmi_out0_core_initiator_cdc_sink_payload_base = hdmi_out0_core_initiator_csrstorage8_storage; +assign hdmi_out0_core_initiator_cdc_sink_payload_length = hdmi_out0_core_initiator_csrstorage9_storage; +assign hdmi_out0_core_initiator_cdc_sink_valid = hdmi_out0_core_initiator_enable_storage; +assign hdmi_out0_core_initiator_source_source_valid = hdmi_out0_core_initiator_cdc_source_valid; +assign hdmi_out0_core_initiator_cdc_source_ready = hdmi_out0_core_initiator_source_source_ready; +assign hdmi_out0_core_initiator_source_source_first = hdmi_out0_core_initiator_cdc_source_first; +assign hdmi_out0_core_initiator_source_source_last = hdmi_out0_core_initiator_cdc_source_last; +assign hdmi_out0_core_initiator_source_source_payload_hres = hdmi_out0_core_initiator_cdc_source_payload_hres; +assign hdmi_out0_core_initiator_source_source_payload_hsync_start = hdmi_out0_core_initiator_cdc_source_payload_hsync_start; +assign hdmi_out0_core_initiator_source_source_payload_hsync_end = hdmi_out0_core_initiator_cdc_source_payload_hsync_end; +assign hdmi_out0_core_initiator_source_source_payload_hscan = hdmi_out0_core_initiator_cdc_source_payload_hscan; +assign hdmi_out0_core_initiator_source_source_payload_vres = hdmi_out0_core_initiator_cdc_source_payload_vres; +assign hdmi_out0_core_initiator_source_source_payload_vsync_start = hdmi_out0_core_initiator_cdc_source_payload_vsync_start; +assign hdmi_out0_core_initiator_source_source_payload_vsync_end = hdmi_out0_core_initiator_cdc_source_payload_vsync_end; +assign hdmi_out0_core_initiator_source_source_payload_vscan = hdmi_out0_core_initiator_cdc_source_payload_vscan; +assign hdmi_out0_core_initiator_source_source_payload_base = hdmi_out0_core_initiator_cdc_source_payload_base; +assign hdmi_out0_core_initiator_source_source_payload_length = hdmi_out0_core_initiator_cdc_source_payload_length; +assign hdmi_out0_core_initiator_cdc_asyncfifo_din = {hdmi_out0_core_initiator_cdc_fifo_in_last, hdmi_out0_core_initiator_cdc_fifo_in_first, hdmi_out0_core_initiator_cdc_fifo_in_payload_length, hdmi_out0_core_initiator_cdc_fifo_in_payload_base, hdmi_out0_core_initiator_cdc_fifo_in_payload_vscan, hdmi_out0_core_initiator_cdc_fifo_in_payload_vsync_end, hdmi_out0_core_initiator_cdc_fifo_in_payload_vsync_start, hdmi_out0_core_initiator_cdc_fifo_in_payload_vres, hdmi_out0_core_initiator_cdc_fifo_in_payload_hscan, hdmi_out0_core_initiator_cdc_fifo_in_payload_hsync_end, hdmi_out0_core_initiator_cdc_fifo_in_payload_hsync_start, hdmi_out0_core_initiator_cdc_fifo_in_payload_hres}; +assign {hdmi_out0_core_initiator_cdc_fifo_out_last, hdmi_out0_core_initiator_cdc_fifo_out_first, hdmi_out0_core_initiator_cdc_fifo_out_payload_length, hdmi_out0_core_initiator_cdc_fifo_out_payload_base, hdmi_out0_core_initiator_cdc_fifo_out_payload_vscan, hdmi_out0_core_initiator_cdc_fifo_out_payload_vsync_end, hdmi_out0_core_initiator_cdc_fifo_out_payload_vsync_start, hdmi_out0_core_initiator_cdc_fifo_out_payload_vres, hdmi_out0_core_initiator_cdc_fifo_out_payload_hscan, hdmi_out0_core_initiator_cdc_fifo_out_payload_hsync_end, hdmi_out0_core_initiator_cdc_fifo_out_payload_hsync_start, hdmi_out0_core_initiator_cdc_fifo_out_payload_hres} = hdmi_out0_core_initiator_cdc_asyncfifo_dout; +assign hdmi_out0_core_initiator_cdc_sink_ready = hdmi_out0_core_initiator_cdc_asyncfifo_writable; +assign hdmi_out0_core_initiator_cdc_asyncfifo_we = hdmi_out0_core_initiator_cdc_sink_valid; +assign hdmi_out0_core_initiator_cdc_fifo_in_first = hdmi_out0_core_initiator_cdc_sink_first; +assign hdmi_out0_core_initiator_cdc_fifo_in_last = hdmi_out0_core_initiator_cdc_sink_last; +assign hdmi_out0_core_initiator_cdc_fifo_in_payload_hres = hdmi_out0_core_initiator_cdc_sink_payload_hres; +assign hdmi_out0_core_initiator_cdc_fifo_in_payload_hsync_start = hdmi_out0_core_initiator_cdc_sink_payload_hsync_start; +assign hdmi_out0_core_initiator_cdc_fifo_in_payload_hsync_end = hdmi_out0_core_initiator_cdc_sink_payload_hsync_end; +assign hdmi_out0_core_initiator_cdc_fifo_in_payload_hscan = hdmi_out0_core_initiator_cdc_sink_payload_hscan; +assign hdmi_out0_core_initiator_cdc_fifo_in_payload_vres = hdmi_out0_core_initiator_cdc_sink_payload_vres; +assign hdmi_out0_core_initiator_cdc_fifo_in_payload_vsync_start = hdmi_out0_core_initiator_cdc_sink_payload_vsync_start; +assign hdmi_out0_core_initiator_cdc_fifo_in_payload_vsync_end = hdmi_out0_core_initiator_cdc_sink_payload_vsync_end; +assign hdmi_out0_core_initiator_cdc_fifo_in_payload_vscan = hdmi_out0_core_initiator_cdc_sink_payload_vscan; +assign hdmi_out0_core_initiator_cdc_fifo_in_payload_base = hdmi_out0_core_initiator_cdc_sink_payload_base; +assign hdmi_out0_core_initiator_cdc_fifo_in_payload_length = hdmi_out0_core_initiator_cdc_sink_payload_length; +assign hdmi_out0_core_initiator_cdc_source_valid = hdmi_out0_core_initiator_cdc_asyncfifo_readable; +assign hdmi_out0_core_initiator_cdc_source_first = hdmi_out0_core_initiator_cdc_fifo_out_first; +assign hdmi_out0_core_initiator_cdc_source_last = hdmi_out0_core_initiator_cdc_fifo_out_last; +assign hdmi_out0_core_initiator_cdc_source_payload_hres = hdmi_out0_core_initiator_cdc_fifo_out_payload_hres; +assign hdmi_out0_core_initiator_cdc_source_payload_hsync_start = hdmi_out0_core_initiator_cdc_fifo_out_payload_hsync_start; +assign hdmi_out0_core_initiator_cdc_source_payload_hsync_end = hdmi_out0_core_initiator_cdc_fifo_out_payload_hsync_end; +assign hdmi_out0_core_initiator_cdc_source_payload_hscan = hdmi_out0_core_initiator_cdc_fifo_out_payload_hscan; +assign hdmi_out0_core_initiator_cdc_source_payload_vres = hdmi_out0_core_initiator_cdc_fifo_out_payload_vres; +assign hdmi_out0_core_initiator_cdc_source_payload_vsync_start = hdmi_out0_core_initiator_cdc_fifo_out_payload_vsync_start; +assign hdmi_out0_core_initiator_cdc_source_payload_vsync_end = hdmi_out0_core_initiator_cdc_fifo_out_payload_vsync_end; +assign hdmi_out0_core_initiator_cdc_source_payload_vscan = hdmi_out0_core_initiator_cdc_fifo_out_payload_vscan; +assign hdmi_out0_core_initiator_cdc_source_payload_base = hdmi_out0_core_initiator_cdc_fifo_out_payload_base; +assign hdmi_out0_core_initiator_cdc_source_payload_length = hdmi_out0_core_initiator_cdc_fifo_out_payload_length; +assign hdmi_out0_core_initiator_cdc_asyncfifo_re = hdmi_out0_core_initiator_cdc_source_ready; +assign hdmi_out0_core_initiator_cdc_graycounter0_ce = (hdmi_out0_core_initiator_cdc_asyncfifo_writable & hdmi_out0_core_initiator_cdc_asyncfifo_we); +assign hdmi_out0_core_initiator_cdc_graycounter1_ce = (hdmi_out0_core_initiator_cdc_asyncfifo_readable & hdmi_out0_core_initiator_cdc_asyncfifo_re); +assign hdmi_out0_core_initiator_cdc_asyncfifo_writable = (((hdmi_out0_core_initiator_cdc_graycounter0_q[2] == hdmi_out0_core_initiator_cdc_consume_wdomain[2]) | (hdmi_out0_core_initiator_cdc_graycounter0_q[1] == hdmi_out0_core_initiator_cdc_consume_wdomain[1])) | (hdmi_out0_core_initiator_cdc_graycounter0_q[0] != hdmi_out0_core_initiator_cdc_consume_wdomain[0])); +assign hdmi_out0_core_initiator_cdc_asyncfifo_readable = (hdmi_out0_core_initiator_cdc_graycounter1_q != hdmi_out0_core_initiator_cdc_produce_rdomain); +assign hdmi_out0_core_initiator_cdc_wrport_adr = hdmi_out0_core_initiator_cdc_graycounter0_q_binary[1:0]; +assign hdmi_out0_core_initiator_cdc_wrport_dat_w = hdmi_out0_core_initiator_cdc_asyncfifo_din; +assign hdmi_out0_core_initiator_cdc_wrport_we = hdmi_out0_core_initiator_cdc_graycounter0_ce; +assign hdmi_out0_core_initiator_cdc_rdport_adr = hdmi_out0_core_initiator_cdc_graycounter1_q_next_binary[1:0]; +assign hdmi_out0_core_initiator_cdc_asyncfifo_dout = hdmi_out0_core_initiator_cdc_rdport_dat_r; +always @(*) begin + hdmi_out0_core_initiator_cdc_graycounter0_q_next_binary <= 3'd0; + if (hdmi_out0_core_initiator_cdc_graycounter0_ce) begin + hdmi_out0_core_initiator_cdc_graycounter0_q_next_binary <= (hdmi_out0_core_initiator_cdc_graycounter0_q_binary + 1'd1); + end else begin + hdmi_out0_core_initiator_cdc_graycounter0_q_next_binary <= hdmi_out0_core_initiator_cdc_graycounter0_q_binary; + end +end +assign hdmi_out0_core_initiator_cdc_graycounter0_q_next = (hdmi_out0_core_initiator_cdc_graycounter0_q_next_binary ^ hdmi_out0_core_initiator_cdc_graycounter0_q_next_binary[2:1]); +always @(*) begin + hdmi_out0_core_initiator_cdc_graycounter1_q_next_binary <= 3'd0; + if (hdmi_out0_core_initiator_cdc_graycounter1_ce) begin + hdmi_out0_core_initiator_cdc_graycounter1_q_next_binary <= (hdmi_out0_core_initiator_cdc_graycounter1_q_binary + 1'd1); + end else begin + hdmi_out0_core_initiator_cdc_graycounter1_q_next_binary <= hdmi_out0_core_initiator_cdc_graycounter1_q_binary; + end +end +assign hdmi_out0_core_initiator_cdc_graycounter1_q_next = (hdmi_out0_core_initiator_cdc_graycounter1_q_next_binary ^ hdmi_out0_core_initiator_cdc_graycounter1_q_next_binary[2:1]); +always @(*) begin + hdmi_out0_core_timinggenerator_source_valid <= 1'd0; + hdmi_out0_core_timinggenerator_active <= 1'd0; + hdmi_out0_core_timinggenerator_source_payload_de <= 1'd0; + if (hdmi_out0_core_timinggenerator_sink_valid) begin + hdmi_out0_core_timinggenerator_active <= (hdmi_out0_core_timinggenerator_hactive & hdmi_out0_core_timinggenerator_vactive); + hdmi_out0_core_timinggenerator_source_valid <= 1'd1; + if (hdmi_out0_core_timinggenerator_active) begin + hdmi_out0_core_timinggenerator_source_payload_de <= 1'd1; + end + end +end +assign hdmi_out0_core_timinggenerator_sink_ready = (hdmi_out0_core_timinggenerator_source_ready & hdmi_out0_core_timinggenerator_source_last); +assign hdmi_out0_core_dmareader_base = hdmi_out0_core_dmareader_sink_payload_base[31:1]; +assign hdmi_out0_core_dmareader_length = hdmi_out0_core_dmareader_sink_payload_length[31:1]; +assign hdmi_out0_core_dmareader_sink_sink_payload_address = (hdmi_out0_core_dmareader_base + hdmi_out0_core_dmareader_offset); +assign hdmi_out0_core_dmareader_source_valid = hdmi_out0_core_dmareader_source_source_valid; +assign hdmi_out0_core_dmareader_source_source_ready = hdmi_out0_core_dmareader_source_ready; +assign hdmi_out0_core_dmareader_source_first = hdmi_out0_core_dmareader_source_source_first; +assign hdmi_out0_core_dmareader_source_last = hdmi_out0_core_dmareader_source_source_last; +assign hdmi_out0_core_dmareader_source_payload_data = hdmi_out0_core_dmareader_source_source_payload_data; +assign litedramcrossbar_litedramnativeport1_cmd_payload_we1 = 1'd0; +assign litedramcrossbar_litedramnativeport1_cmd_payload_addr1 = hdmi_out0_core_dmareader_sink_sink_payload_address; +assign litedramcrossbar_litedramnativeport1_cmd_valid1 = (hdmi_out0_core_dmareader_sink_sink_valid & hdmi_out0_core_dmareader_request_enable); +assign hdmi_out0_core_dmareader_sink_sink_ready = (litedramcrossbar_litedramnativeport1_cmd_ready1 & hdmi_out0_core_dmareader_request_enable); +assign hdmi_out0_core_dmareader_request_issued = (litedramcrossbar_litedramnativeport1_cmd_valid1 & litedramcrossbar_litedramnativeport1_cmd_ready1); +assign hdmi_out0_core_dmareader_request_enable = (hdmi_out0_core_dmareader_rsv_level != 10'd512); +assign hdmi_out0_core_dmareader_fifo_sink_valid = litedramcrossbar_litedramnativeport1_rdata_valid1; +assign litedramcrossbar_litedramnativeport1_rdata_ready1 = hdmi_out0_core_dmareader_fifo_sink_ready; +assign hdmi_out0_core_dmareader_fifo_sink_first = litedramcrossbar_litedramnativeport1_rdata_first1; +assign hdmi_out0_core_dmareader_fifo_sink_last = litedramcrossbar_litedramnativeport1_rdata_last1; +assign hdmi_out0_core_dmareader_fifo_sink_payload_data = litedramcrossbar_litedramnativeport1_rdata_payload_data1; +assign hdmi_out0_core_dmareader_source_source_valid = hdmi_out0_core_dmareader_fifo_source_valid; +assign hdmi_out0_core_dmareader_fifo_source_ready = hdmi_out0_core_dmareader_source_source_ready; +assign hdmi_out0_core_dmareader_source_source_first = hdmi_out0_core_dmareader_fifo_source_first; +assign hdmi_out0_core_dmareader_source_source_last = hdmi_out0_core_dmareader_fifo_source_last; +assign hdmi_out0_core_dmareader_source_source_payload_data = hdmi_out0_core_dmareader_fifo_source_payload_data; +assign hdmi_out0_core_dmareader_data_dequeued = (hdmi_out0_core_dmareader_source_source_valid & hdmi_out0_core_dmareader_source_source_ready); +assign hdmi_out0_core_dmareader_fifo_syncfifo_din = {hdmi_out0_core_dmareader_fifo_fifo_in_last, hdmi_out0_core_dmareader_fifo_fifo_in_first, hdmi_out0_core_dmareader_fifo_fifo_in_payload_data}; +assign {hdmi_out0_core_dmareader_fifo_fifo_out_last, hdmi_out0_core_dmareader_fifo_fifo_out_first, hdmi_out0_core_dmareader_fifo_fifo_out_payload_data} = hdmi_out0_core_dmareader_fifo_syncfifo_dout; +assign hdmi_out0_core_dmareader_fifo_sink_ready = hdmi_out0_core_dmareader_fifo_syncfifo_writable; +assign hdmi_out0_core_dmareader_fifo_syncfifo_we = hdmi_out0_core_dmareader_fifo_sink_valid; +assign hdmi_out0_core_dmareader_fifo_fifo_in_first = hdmi_out0_core_dmareader_fifo_sink_first; +assign hdmi_out0_core_dmareader_fifo_fifo_in_last = hdmi_out0_core_dmareader_fifo_sink_last; +assign hdmi_out0_core_dmareader_fifo_fifo_in_payload_data = hdmi_out0_core_dmareader_fifo_sink_payload_data; +assign hdmi_out0_core_dmareader_fifo_source_valid = hdmi_out0_core_dmareader_fifo_readable; +assign hdmi_out0_core_dmareader_fifo_source_first = hdmi_out0_core_dmareader_fifo_fifo_out_first; +assign hdmi_out0_core_dmareader_fifo_source_last = hdmi_out0_core_dmareader_fifo_fifo_out_last; +assign hdmi_out0_core_dmareader_fifo_source_payload_data = hdmi_out0_core_dmareader_fifo_fifo_out_payload_data; +assign hdmi_out0_core_dmareader_fifo_re = hdmi_out0_core_dmareader_fifo_source_ready; +assign hdmi_out0_core_dmareader_fifo_syncfifo_re = (hdmi_out0_core_dmareader_fifo_syncfifo_readable & ((~hdmi_out0_core_dmareader_fifo_readable) | hdmi_out0_core_dmareader_fifo_re)); +assign hdmi_out0_core_dmareader_fifo_level1 = (hdmi_out0_core_dmareader_fifo_level0 + hdmi_out0_core_dmareader_fifo_readable); +always @(*) begin + hdmi_out0_core_dmareader_fifo_wrport_adr <= 9'd0; + if (hdmi_out0_core_dmareader_fifo_replace) begin + hdmi_out0_core_dmareader_fifo_wrport_adr <= (hdmi_out0_core_dmareader_fifo_produce - 1'd1); + end else begin + hdmi_out0_core_dmareader_fifo_wrport_adr <= hdmi_out0_core_dmareader_fifo_produce; + end +end +assign hdmi_out0_core_dmareader_fifo_wrport_dat_w = hdmi_out0_core_dmareader_fifo_syncfifo_din; +assign hdmi_out0_core_dmareader_fifo_wrport_we = (hdmi_out0_core_dmareader_fifo_syncfifo_we & (hdmi_out0_core_dmareader_fifo_syncfifo_writable | hdmi_out0_core_dmareader_fifo_replace)); +assign hdmi_out0_core_dmareader_fifo_do_read = (hdmi_out0_core_dmareader_fifo_syncfifo_readable & hdmi_out0_core_dmareader_fifo_syncfifo_re); +assign hdmi_out0_core_dmareader_fifo_rdport_adr = hdmi_out0_core_dmareader_fifo_consume; +assign hdmi_out0_core_dmareader_fifo_syncfifo_dout = hdmi_out0_core_dmareader_fifo_rdport_dat_r; +assign hdmi_out0_core_dmareader_fifo_rdport_re = hdmi_out0_core_dmareader_fifo_do_read; +assign hdmi_out0_core_dmareader_fifo_syncfifo_writable = (hdmi_out0_core_dmareader_fifo_level0 != 10'd512); +assign hdmi_out0_core_dmareader_fifo_syncfifo_readable = (hdmi_out0_core_dmareader_fifo_level0 != 1'd0); +always @(*) begin + litedramcrossbar_litedramnativeport1_flush <= 1'd0; + videoout_next_state <= 1'd0; + hdmi_out0_core_dmareader_offset_videoout_next_value <= 28'd0; + hdmi_out0_core_dmareader_sink_ready <= 1'd0; + hdmi_out0_core_dmareader_offset_videoout_next_value_ce <= 1'd0; + hdmi_out0_core_dmareader_sink_sink_valid <= 1'd0; + videoout_next_state <= videoout_state; + case (videoout_state) + 1'd1: begin + hdmi_out0_core_dmareader_sink_sink_valid <= 1'd1; + if (hdmi_out0_core_dmareader_sink_sink_ready) begin + hdmi_out0_core_dmareader_offset_videoout_next_value <= (hdmi_out0_core_dmareader_offset + 1'd1); + hdmi_out0_core_dmareader_offset_videoout_next_value_ce <= 1'd1; + if ((hdmi_out0_core_dmareader_offset == (hdmi_out0_core_dmareader_length - 1'd1))) begin + hdmi_out0_core_dmareader_sink_ready <= 1'd1; + videoout_next_state <= 1'd0; + end + end + end + default: begin + hdmi_out0_core_dmareader_offset_videoout_next_value <= 1'd0; + hdmi_out0_core_dmareader_offset_videoout_next_value_ce <= 1'd1; + if (hdmi_out0_core_dmareader_sink_valid) begin + videoout_next_state <= 1'd1; + end else begin + litedramcrossbar_litedramnativeport1_flush <= 1'd1; + end + end + endcase +end +assign hdmi_out0_core_o = (hdmi_out0_core_toggle_o ^ hdmi_out0_core_toggle_o_r); +assign hdmi_out0_driver_hdmi_phy_sink_valid = hdmi_out0_driver_sink_sink_valid; +assign hdmi_out0_driver_sink_sink_ready = hdmi_out0_driver_hdmi_phy_sink_ready; +assign hdmi_out0_driver_hdmi_phy_sink_first = hdmi_out0_driver_sink_sink_first; +assign hdmi_out0_driver_hdmi_phy_sink_last = hdmi_out0_driver_sink_sink_last; +assign hdmi_out0_driver_hdmi_phy_sink_payload_r = hdmi_out0_driver_sink_sink_payload_r; +assign hdmi_out0_driver_hdmi_phy_sink_payload_g = hdmi_out0_driver_sink_sink_payload_g; +assign hdmi_out0_driver_hdmi_phy_sink_payload_b = hdmi_out0_driver_sink_sink_payload_b; +assign hdmi_out0_driver_hdmi_phy_sink_param_hsync = hdmi_out0_driver_sink_sink_param_hsync; +assign hdmi_out0_driver_hdmi_phy_sink_param_vsync = hdmi_out0_driver_sink_sink_param_vsync; +assign hdmi_out0_driver_hdmi_phy_sink_param_de = hdmi_out0_driver_sink_sink_param_de; +assign hdmi_out0_pix_rst = (~hdmi_out0_driver_s7hdmioutclocking_mmcm_locked); +assign hdmi_out0_driver_s7hdmioutclocking_data0 = hdmi_out0_driver_s7hdmioutclocking; +assign hdmi_out0_driver_s7hdmioutclocking_data1 = (~hdmi_out0_driver_s7hdmioutclocking_data0); +assign hdmi_out0_driver_hdmi_phy_sink_ready = 1'd1; +assign hdmi_out0_driver_hdmi_phy_es0_d0 = hdmi_out0_driver_hdmi_phy_sink_payload_b; +assign hdmi_out0_driver_hdmi_phy_es1_d0 = hdmi_out0_driver_hdmi_phy_sink_payload_g; +assign hdmi_out0_driver_hdmi_phy_es2_d0 = hdmi_out0_driver_hdmi_phy_sink_payload_r; +assign hdmi_out0_driver_hdmi_phy_es0_c = {hdmi_out0_driver_hdmi_phy_sink_param_vsync, hdmi_out0_driver_hdmi_phy_sink_param_hsync}; +assign hdmi_out0_driver_hdmi_phy_es1_c = 1'd0; +assign hdmi_out0_driver_hdmi_phy_es2_c = 1'd0; +assign hdmi_out0_driver_hdmi_phy_es0_de = hdmi_out0_driver_hdmi_phy_sink_param_de; +assign hdmi_out0_driver_hdmi_phy_es1_de = hdmi_out0_driver_hdmi_phy_sink_param_de; +assign hdmi_out0_driver_hdmi_phy_es2_de = hdmi_out0_driver_hdmi_phy_sink_param_de; +assign hdmi_out0_driver_hdmi_phy_es0_data = hdmi_out0_driver_hdmi_phy_es0_out; +assign hdmi_out0_driver_hdmi_phy_es0_q_m8_n = ((hdmi_out0_driver_hdmi_phy_es0_n1d > 3'd4) | ((hdmi_out0_driver_hdmi_phy_es0_n1d == 3'd4) & (~hdmi_out0_driver_hdmi_phy_es0_d1[0]))); +assign hdmi_out0_driver_hdmi_phy_es1_data = hdmi_out0_driver_hdmi_phy_es1_out; +assign hdmi_out0_driver_hdmi_phy_es1_q_m8_n = ((hdmi_out0_driver_hdmi_phy_es1_n1d > 3'd4) | ((hdmi_out0_driver_hdmi_phy_es1_n1d == 3'd4) & (~hdmi_out0_driver_hdmi_phy_es1_d1[0]))); +assign hdmi_out0_driver_hdmi_phy_es2_data = hdmi_out0_driver_hdmi_phy_es2_out; +assign hdmi_out0_driver_hdmi_phy_es2_q_m8_n = ((hdmi_out0_driver_hdmi_phy_es2_n1d > 3'd4) | ((hdmi_out0_driver_hdmi_phy_es2_n1d == 3'd4) & (~hdmi_out0_driver_hdmi_phy_es2_d1[0]))); +always @(*) begin + hdmi_out0_resetinserter_y_fifo_sink_payload_data <= 8'd0; + hdmi_out0_resetinserter_sink_sink_ready <= 1'd0; + hdmi_out0_resetinserter_cb_fifo_sink_payload_data <= 8'd0; + hdmi_out0_resetinserter_cr_fifo_sink_payload_data <= 8'd0; + hdmi_out0_resetinserter_y_fifo_sink_valid <= 1'd0; + hdmi_out0_resetinserter_cb_fifo_sink_valid <= 1'd0; + hdmi_out0_resetinserter_cr_fifo_sink_valid <= 1'd0; + if ((~hdmi_out0_resetinserter_parity_in)) begin + hdmi_out0_resetinserter_y_fifo_sink_valid <= (hdmi_out0_resetinserter_sink_sink_valid & hdmi_out0_resetinserter_sink_sink_ready); + hdmi_out0_resetinserter_y_fifo_sink_payload_data <= hdmi_out0_resetinserter_sink_sink_payload_y; + hdmi_out0_resetinserter_cb_fifo_sink_valid <= (hdmi_out0_resetinserter_sink_sink_valid & hdmi_out0_resetinserter_sink_sink_ready); + hdmi_out0_resetinserter_cb_fifo_sink_payload_data <= hdmi_out0_resetinserter_sink_sink_payload_cb_cr; + hdmi_out0_resetinserter_sink_sink_ready <= (hdmi_out0_resetinserter_y_fifo_sink_ready & hdmi_out0_resetinserter_cb_fifo_sink_ready); + end else begin + hdmi_out0_resetinserter_y_fifo_sink_valid <= (hdmi_out0_resetinserter_sink_sink_valid & hdmi_out0_resetinserter_sink_sink_ready); + hdmi_out0_resetinserter_y_fifo_sink_payload_data <= hdmi_out0_resetinserter_sink_sink_payload_y; + hdmi_out0_resetinserter_cr_fifo_sink_valid <= (hdmi_out0_resetinserter_sink_sink_valid & hdmi_out0_resetinserter_sink_sink_ready); + hdmi_out0_resetinserter_cr_fifo_sink_payload_data <= hdmi_out0_resetinserter_sink_sink_payload_cb_cr; + hdmi_out0_resetinserter_sink_sink_ready <= (hdmi_out0_resetinserter_y_fifo_sink_ready & hdmi_out0_resetinserter_cr_fifo_sink_ready); + end +end +assign hdmi_out0_resetinserter_source_source_valid = ((hdmi_out0_resetinserter_y_fifo_source_valid & hdmi_out0_resetinserter_cb_fifo_source_valid) & hdmi_out0_resetinserter_cr_fifo_source_valid); +assign hdmi_out0_resetinserter_source_source_payload_y = hdmi_out0_resetinserter_y_fifo_source_payload_data; +assign hdmi_out0_resetinserter_source_source_payload_cb = hdmi_out0_resetinserter_cb_fifo_source_payload_data; +assign hdmi_out0_resetinserter_source_source_payload_cr = hdmi_out0_resetinserter_cr_fifo_source_payload_data; +assign hdmi_out0_resetinserter_y_fifo_source_ready = (hdmi_out0_resetinserter_source_source_valid & hdmi_out0_resetinserter_source_source_ready); +assign hdmi_out0_resetinserter_cb_fifo_source_ready = ((hdmi_out0_resetinserter_source_source_valid & hdmi_out0_resetinserter_source_source_ready) & hdmi_out0_resetinserter_parity_out); +assign hdmi_out0_resetinserter_cr_fifo_source_ready = ((hdmi_out0_resetinserter_source_source_valid & hdmi_out0_resetinserter_source_source_ready) & hdmi_out0_resetinserter_parity_out); +assign hdmi_out0_resetinserter_y_fifo_syncfifo_din = {hdmi_out0_resetinserter_y_fifo_fifo_in_last, hdmi_out0_resetinserter_y_fifo_fifo_in_first, hdmi_out0_resetinserter_y_fifo_fifo_in_payload_data}; +assign {hdmi_out0_resetinserter_y_fifo_fifo_out_last, hdmi_out0_resetinserter_y_fifo_fifo_out_first, hdmi_out0_resetinserter_y_fifo_fifo_out_payload_data} = hdmi_out0_resetinserter_y_fifo_syncfifo_dout; +assign hdmi_out0_resetinserter_y_fifo_sink_ready = hdmi_out0_resetinserter_y_fifo_syncfifo_writable; +assign hdmi_out0_resetinserter_y_fifo_syncfifo_we = hdmi_out0_resetinserter_y_fifo_sink_valid; +assign hdmi_out0_resetinserter_y_fifo_fifo_in_first = hdmi_out0_resetinserter_y_fifo_sink_first; +assign hdmi_out0_resetinserter_y_fifo_fifo_in_last = hdmi_out0_resetinserter_y_fifo_sink_last; +assign hdmi_out0_resetinserter_y_fifo_fifo_in_payload_data = hdmi_out0_resetinserter_y_fifo_sink_payload_data; +assign hdmi_out0_resetinserter_y_fifo_source_valid = hdmi_out0_resetinserter_y_fifo_syncfifo_readable; +assign hdmi_out0_resetinserter_y_fifo_source_first = hdmi_out0_resetinserter_y_fifo_fifo_out_first; +assign hdmi_out0_resetinserter_y_fifo_source_last = hdmi_out0_resetinserter_y_fifo_fifo_out_last; +assign hdmi_out0_resetinserter_y_fifo_source_payload_data = hdmi_out0_resetinserter_y_fifo_fifo_out_payload_data; +assign hdmi_out0_resetinserter_y_fifo_syncfifo_re = hdmi_out0_resetinserter_y_fifo_source_ready; +always @(*) begin + hdmi_out0_resetinserter_y_fifo_wrport_adr <= 2'd0; + if (hdmi_out0_resetinserter_y_fifo_replace) begin + hdmi_out0_resetinserter_y_fifo_wrport_adr <= (hdmi_out0_resetinserter_y_fifo_produce - 1'd1); + end else begin + hdmi_out0_resetinserter_y_fifo_wrport_adr <= hdmi_out0_resetinserter_y_fifo_produce; + end +end +assign hdmi_out0_resetinserter_y_fifo_wrport_dat_w = hdmi_out0_resetinserter_y_fifo_syncfifo_din; +assign hdmi_out0_resetinserter_y_fifo_wrport_we = (hdmi_out0_resetinserter_y_fifo_syncfifo_we & (hdmi_out0_resetinserter_y_fifo_syncfifo_writable | hdmi_out0_resetinserter_y_fifo_replace)); +assign hdmi_out0_resetinserter_y_fifo_do_read = (hdmi_out0_resetinserter_y_fifo_syncfifo_readable & hdmi_out0_resetinserter_y_fifo_syncfifo_re); +assign hdmi_out0_resetinserter_y_fifo_rdport_adr = hdmi_out0_resetinserter_y_fifo_consume; +assign hdmi_out0_resetinserter_y_fifo_syncfifo_dout = hdmi_out0_resetinserter_y_fifo_rdport_dat_r; +assign hdmi_out0_resetinserter_y_fifo_syncfifo_writable = (hdmi_out0_resetinserter_y_fifo_level != 3'd4); +assign hdmi_out0_resetinserter_y_fifo_syncfifo_readable = (hdmi_out0_resetinserter_y_fifo_level != 1'd0); +assign hdmi_out0_resetinserter_cb_fifo_syncfifo_din = {hdmi_out0_resetinserter_cb_fifo_fifo_in_last, hdmi_out0_resetinserter_cb_fifo_fifo_in_first, hdmi_out0_resetinserter_cb_fifo_fifo_in_payload_data}; +assign {hdmi_out0_resetinserter_cb_fifo_fifo_out_last, hdmi_out0_resetinserter_cb_fifo_fifo_out_first, hdmi_out0_resetinserter_cb_fifo_fifo_out_payload_data} = hdmi_out0_resetinserter_cb_fifo_syncfifo_dout; +assign hdmi_out0_resetinserter_cb_fifo_sink_ready = hdmi_out0_resetinserter_cb_fifo_syncfifo_writable; +assign hdmi_out0_resetinserter_cb_fifo_syncfifo_we = hdmi_out0_resetinserter_cb_fifo_sink_valid; +assign hdmi_out0_resetinserter_cb_fifo_fifo_in_first = hdmi_out0_resetinserter_cb_fifo_sink_first; +assign hdmi_out0_resetinserter_cb_fifo_fifo_in_last = hdmi_out0_resetinserter_cb_fifo_sink_last; +assign hdmi_out0_resetinserter_cb_fifo_fifo_in_payload_data = hdmi_out0_resetinserter_cb_fifo_sink_payload_data; +assign hdmi_out0_resetinserter_cb_fifo_source_valid = hdmi_out0_resetinserter_cb_fifo_syncfifo_readable; +assign hdmi_out0_resetinserter_cb_fifo_source_first = hdmi_out0_resetinserter_cb_fifo_fifo_out_first; +assign hdmi_out0_resetinserter_cb_fifo_source_last = hdmi_out0_resetinserter_cb_fifo_fifo_out_last; +assign hdmi_out0_resetinserter_cb_fifo_source_payload_data = hdmi_out0_resetinserter_cb_fifo_fifo_out_payload_data; +assign hdmi_out0_resetinserter_cb_fifo_syncfifo_re = hdmi_out0_resetinserter_cb_fifo_source_ready; +always @(*) begin + hdmi_out0_resetinserter_cb_fifo_wrport_adr <= 2'd0; + if (hdmi_out0_resetinserter_cb_fifo_replace) begin + hdmi_out0_resetinserter_cb_fifo_wrport_adr <= (hdmi_out0_resetinserter_cb_fifo_produce - 1'd1); + end else begin + hdmi_out0_resetinserter_cb_fifo_wrport_adr <= hdmi_out0_resetinserter_cb_fifo_produce; + end +end +assign hdmi_out0_resetinserter_cb_fifo_wrport_dat_w = hdmi_out0_resetinserter_cb_fifo_syncfifo_din; +assign hdmi_out0_resetinserter_cb_fifo_wrport_we = (hdmi_out0_resetinserter_cb_fifo_syncfifo_we & (hdmi_out0_resetinserter_cb_fifo_syncfifo_writable | hdmi_out0_resetinserter_cb_fifo_replace)); +assign hdmi_out0_resetinserter_cb_fifo_do_read = (hdmi_out0_resetinserter_cb_fifo_syncfifo_readable & hdmi_out0_resetinserter_cb_fifo_syncfifo_re); +assign hdmi_out0_resetinserter_cb_fifo_rdport_adr = hdmi_out0_resetinserter_cb_fifo_consume; +assign hdmi_out0_resetinserter_cb_fifo_syncfifo_dout = hdmi_out0_resetinserter_cb_fifo_rdport_dat_r; +assign hdmi_out0_resetinserter_cb_fifo_syncfifo_writable = (hdmi_out0_resetinserter_cb_fifo_level != 3'd4); +assign hdmi_out0_resetinserter_cb_fifo_syncfifo_readable = (hdmi_out0_resetinserter_cb_fifo_level != 1'd0); +assign hdmi_out0_resetinserter_cr_fifo_syncfifo_din = {hdmi_out0_resetinserter_cr_fifo_fifo_in_last, hdmi_out0_resetinserter_cr_fifo_fifo_in_first, hdmi_out0_resetinserter_cr_fifo_fifo_in_payload_data}; +assign {hdmi_out0_resetinserter_cr_fifo_fifo_out_last, hdmi_out0_resetinserter_cr_fifo_fifo_out_first, hdmi_out0_resetinserter_cr_fifo_fifo_out_payload_data} = hdmi_out0_resetinserter_cr_fifo_syncfifo_dout; +assign hdmi_out0_resetinserter_cr_fifo_sink_ready = hdmi_out0_resetinserter_cr_fifo_syncfifo_writable; +assign hdmi_out0_resetinserter_cr_fifo_syncfifo_we = hdmi_out0_resetinserter_cr_fifo_sink_valid; +assign hdmi_out0_resetinserter_cr_fifo_fifo_in_first = hdmi_out0_resetinserter_cr_fifo_sink_first; +assign hdmi_out0_resetinserter_cr_fifo_fifo_in_last = hdmi_out0_resetinserter_cr_fifo_sink_last; +assign hdmi_out0_resetinserter_cr_fifo_fifo_in_payload_data = hdmi_out0_resetinserter_cr_fifo_sink_payload_data; +assign hdmi_out0_resetinserter_cr_fifo_source_valid = hdmi_out0_resetinserter_cr_fifo_syncfifo_readable; +assign hdmi_out0_resetinserter_cr_fifo_source_first = hdmi_out0_resetinserter_cr_fifo_fifo_out_first; +assign hdmi_out0_resetinserter_cr_fifo_source_last = hdmi_out0_resetinserter_cr_fifo_fifo_out_last; +assign hdmi_out0_resetinserter_cr_fifo_source_payload_data = hdmi_out0_resetinserter_cr_fifo_fifo_out_payload_data; +assign hdmi_out0_resetinserter_cr_fifo_syncfifo_re = hdmi_out0_resetinserter_cr_fifo_source_ready; +always @(*) begin + hdmi_out0_resetinserter_cr_fifo_wrport_adr <= 2'd0; + if (hdmi_out0_resetinserter_cr_fifo_replace) begin + hdmi_out0_resetinserter_cr_fifo_wrport_adr <= (hdmi_out0_resetinserter_cr_fifo_produce - 1'd1); + end else begin + hdmi_out0_resetinserter_cr_fifo_wrport_adr <= hdmi_out0_resetinserter_cr_fifo_produce; + end +end +assign hdmi_out0_resetinserter_cr_fifo_wrport_dat_w = hdmi_out0_resetinserter_cr_fifo_syncfifo_din; +assign hdmi_out0_resetinserter_cr_fifo_wrport_we = (hdmi_out0_resetinserter_cr_fifo_syncfifo_we & (hdmi_out0_resetinserter_cr_fifo_syncfifo_writable | hdmi_out0_resetinserter_cr_fifo_replace)); +assign hdmi_out0_resetinserter_cr_fifo_do_read = (hdmi_out0_resetinserter_cr_fifo_syncfifo_readable & hdmi_out0_resetinserter_cr_fifo_syncfifo_re); +assign hdmi_out0_resetinserter_cr_fifo_rdport_adr = hdmi_out0_resetinserter_cr_fifo_consume; +assign hdmi_out0_resetinserter_cr_fifo_syncfifo_dout = hdmi_out0_resetinserter_cr_fifo_rdport_dat_r; +assign hdmi_out0_resetinserter_cr_fifo_syncfifo_writable = (hdmi_out0_resetinserter_cr_fifo_level != 3'd4); +assign hdmi_out0_resetinserter_cr_fifo_syncfifo_readable = (hdmi_out0_resetinserter_cr_fifo_level != 1'd0); +assign hdmi_out0_pipe_ce = (hdmi_out0_source_ready | (~hdmi_out0_valid_n3)); +assign hdmi_out0_sink_ready = hdmi_out0_pipe_ce; +assign hdmi_out0_source_valid = hdmi_out0_valid_n3; +assign hdmi_out0_busy = ((((1'd0 | hdmi_out0_valid_n0) | hdmi_out0_valid_n1) | hdmi_out0_valid_n2) | hdmi_out0_valid_n3); +assign hdmi_out0_source_first = hdmi_out0_first_n3; +assign hdmi_out0_source_last = hdmi_out0_last_n3; +assign hdmi_out0_ce = hdmi_out0_pipe_ce; +assign hdmi_out0_sink_y = hdmi_out0_sink_payload_y; +assign hdmi_out0_sink_cb = hdmi_out0_sink_payload_cb; +assign hdmi_out0_sink_cr = hdmi_out0_sink_payload_cr; +assign hdmi_out0_source_payload_r = hdmi_out0_source_r; +assign hdmi_out0_source_payload_g = hdmi_out0_source_g; +assign hdmi_out0_source_payload_b = hdmi_out0_source_b; +assign hdmi_out0_source_payload_hsync = hdmi_out0_next_s5; +assign hdmi_out0_source_payload_vsync = hdmi_out0_next_s11; +assign hdmi_out0_source_payload_de = hdmi_out0_next_s17; +always @(*) begin + netv2_dat_w_next_value_ce0 <= 1'd0; + netv2_wishbone_dat_r <= 32'd0; + netv2_adr_next_value1 <= 14'd0; + netv2_adr_next_value_ce1 <= 1'd0; + netv2_we_next_value2 <= 1'd0; + netv2_wishbone_ack <= 1'd0; + netv2_we_next_value_ce2 <= 1'd0; + next_state <= 2'd0; + netv2_dat_w_next_value0 <= 32'd0; + next_state <= state; + case (state) + 1'd1: begin + netv2_adr_next_value1 <= 1'd0; + netv2_adr_next_value_ce1 <= 1'd1; + netv2_we_next_value2 <= 1'd0; + netv2_we_next_value_ce2 <= 1'd1; + next_state <= 2'd2; + end + 2'd2: begin + netv2_wishbone_ack <= 1'd1; + netv2_wishbone_dat_r <= netv2_dat_r; + next_state <= 1'd0; + end + default: begin + netv2_dat_w_next_value0 <= netv2_wishbone_dat_w; + netv2_dat_w_next_value_ce0 <= 1'd1; + if ((netv2_wishbone_cyc & netv2_wishbone_stb)) begin + netv2_adr_next_value1 <= netv2_wishbone_adr; + netv2_adr_next_value_ce1 <= 1'd1; + netv2_we_next_value2 <= (netv2_wishbone_we & (netv2_wishbone_sel != 1'd0)); + netv2_we_next_value_ce2 <= 1'd1; + next_state <= 1'd1; + end + end + endcase +end +assign shared_adr = comb_rhs_array_muxed38; +assign shared_dat_w = comb_rhs_array_muxed39; +assign shared_sel = comb_rhs_array_muxed40; +assign shared_cyc = comb_rhs_array_muxed41; +assign shared_stb = comb_rhs_array_muxed42; +assign shared_we = comb_rhs_array_muxed43; +assign shared_cti = comb_rhs_array_muxed44; +assign shared_bte = comb_rhs_array_muxed45; +assign netv2_cpu_ibus_dat_r = shared_dat_r; +assign netv2_cpu_dbus_dat_r = shared_dat_r; +assign etherbone_liteethetherbonewishbonemaster_bus_dat_r = shared_dat_r; +assign pcie_bridge_wishbone_dat_r = shared_dat_r; +assign netv2_cpu_ibus_ack = (shared_ack & (grant == 1'd0)); +assign netv2_cpu_dbus_ack = (shared_ack & (grant == 1'd1)); +assign etherbone_liteethetherbonewishbonemaster_bus_ack = (shared_ack & (grant == 2'd2)); +assign pcie_bridge_wishbone_ack = (shared_ack & (grant == 2'd3)); +assign netv2_cpu_ibus_err = (shared_err & (grant == 1'd0)); +assign netv2_cpu_dbus_err = (shared_err & (grant == 1'd1)); +assign etherbone_liteethetherbonewishbonemaster_bus_err = (shared_err & (grant == 2'd2)); +assign pcie_bridge_wishbone_err = (shared_err & (grant == 2'd3)); +assign request = {pcie_bridge_wishbone_cyc, etherbone_liteethetherbonewishbonemaster_bus_cyc, netv2_cpu_dbus_cyc, netv2_cpu_ibus_cyc}; +always @(*) begin + slave_sel <= 4'd0; + slave_sel[0] <= (shared_adr[29:13] == 1'd0); + slave_sel[1] <= (shared_adr[29:11] == 12'd2048); + slave_sel[2] <= (shared_adr[29:27] == 2'd2); + slave_sel[3] <= (shared_adr[29:14] == 16'd33280); +end +assign netv2_netv2_ram_bus_adr = shared_adr; +assign netv2_netv2_ram_bus_dat_w = shared_dat_w; +assign netv2_netv2_ram_bus_sel = shared_sel; +assign netv2_netv2_ram_bus_stb = shared_stb; +assign netv2_netv2_ram_bus_we = shared_we; +assign netv2_netv2_ram_bus_cti = shared_cti; +assign netv2_netv2_ram_bus_bte = shared_bte; +assign netv2_ram_bus_ram_bus_adr = shared_adr; +assign netv2_ram_bus_ram_bus_dat_w = shared_dat_w; +assign netv2_ram_bus_ram_bus_sel = shared_sel; +assign netv2_ram_bus_ram_bus_stb = shared_stb; +assign netv2_ram_bus_ram_bus_we = shared_we; +assign netv2_ram_bus_ram_bus_cti = shared_cti; +assign netv2_ram_bus_ram_bus_bte = shared_bte; +assign netv2_wb_sdram_adr = shared_adr; +assign netv2_wb_sdram_dat_w = shared_dat_w; +assign netv2_wb_sdram_sel = shared_sel; +assign netv2_wb_sdram_stb = shared_stb; +assign netv2_wb_sdram_we = shared_we; +assign netv2_wb_sdram_cti = shared_cti; +assign netv2_wb_sdram_bte = shared_bte; +assign netv2_wishbone_adr = shared_adr; +assign netv2_wishbone_dat_w = shared_dat_w; +assign netv2_wishbone_sel = shared_sel; +assign netv2_wishbone_stb = shared_stb; +assign netv2_wishbone_we = shared_we; +assign netv2_wishbone_cti = shared_cti; +assign netv2_wishbone_bte = shared_bte; +assign netv2_netv2_ram_bus_cyc = (shared_cyc & slave_sel[0]); +assign netv2_ram_bus_ram_bus_cyc = (shared_cyc & slave_sel[1]); +assign netv2_wb_sdram_cyc = (shared_cyc & slave_sel[2]); +assign netv2_wishbone_cyc = (shared_cyc & slave_sel[3]); +assign shared_err = (((netv2_netv2_ram_bus_err | netv2_ram_bus_ram_bus_err) | netv2_wb_sdram_err) | netv2_wishbone_err); +assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack)); +always @(*) begin + shared_ack <= 1'd0; + error <= 1'd0; + shared_dat_r <= 32'd0; + shared_ack <= (((netv2_netv2_ram_bus_ack | netv2_ram_bus_ram_bus_ack) | netv2_wb_sdram_ack) | netv2_wishbone_ack); + shared_dat_r <= (((({32{slave_sel_r[0]}} & netv2_netv2_ram_bus_dat_r) | ({32{slave_sel_r[1]}} & netv2_ram_bus_ram_bus_dat_r)) | ({32{slave_sel_r[2]}} & netv2_wb_sdram_dat_r)) | ({32{slave_sel_r[3]}} & netv2_wishbone_dat_r)); + if (done) begin + shared_dat_r <= 32'd4294967295; + shared_ack <= 1'd1; + error <= 1'd1; + end +end +assign done = (count == 1'd0); +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 3'd6); +assign crg_reset_r = interface0_bank_bus_dat_w[0]; +assign crg_reset_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd0)); +assign crg_reset_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd0)); +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd0); +assign csrbank1_reset0_r = interface1_bank_bus_dat_w[0]; +assign csrbank1_reset0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[1:0] == 1'd0)); +assign csrbank1_reset0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[1:0] == 1'd0)); +assign csrbank1_scratch0_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_scratch0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[1:0] == 1'd1)); +assign csrbank1_scratch0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[1:0] == 1'd1)); +assign csrbank1_bus_errors_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_bus_errors_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[1:0] == 2'd2)); +assign csrbank1_bus_errors_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[1:0] == 2'd2)); +assign csrbank1_reset0_w = netv2_soccontroller_reset_storage; +assign csrbank1_scratch0_w = netv2_soccontroller_scratch_storage[31:0]; +assign csrbank1_bus_errors_w = netv2_soccontroller_bus_errors_status[31:0]; +assign netv2_soccontroller_bus_errors_we = csrbank1_bus_errors_we; +assign netv2_soccontroller_bus_errors_re = csrbank1_bus_errors_re; +assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 4'd11); +assign csrbank2_rst0_r = interface2_bank_bus_dat_w[0]; +assign csrbank2_rst0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[3:0] == 1'd0)); +assign csrbank2_rst0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[3:0] == 1'd0)); +assign csrbank2_half_sys8x_taps0_r = interface2_bank_bus_dat_w[4:0]; +assign csrbank2_half_sys8x_taps0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[3:0] == 1'd1)); +assign csrbank2_half_sys8x_taps0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[3:0] == 1'd1)); +assign csrbank2_wlevel_en0_r = interface2_bank_bus_dat_w[0]; +assign csrbank2_wlevel_en0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[3:0] == 2'd2)); +assign csrbank2_wlevel_en0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[3:0] == 2'd2)); +assign a7ddrphy_wlevel_strobe_r = interface2_bank_bus_dat_w[0]; +assign a7ddrphy_wlevel_strobe_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[3:0] == 2'd3)); +assign a7ddrphy_wlevel_strobe_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[3:0] == 2'd3)); +assign csrbank2_dly_sel0_r = interface2_bank_bus_dat_w[3:0]; +assign csrbank2_dly_sel0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[3:0] == 3'd4)); +assign csrbank2_dly_sel0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[3:0] == 3'd4)); +assign a7ddrphy_rdly_dq_rst_r = interface2_bank_bus_dat_w[0]; +assign a7ddrphy_rdly_dq_rst_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[3:0] == 3'd5)); +assign a7ddrphy_rdly_dq_rst_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[3:0] == 3'd5)); +assign a7ddrphy_rdly_dq_inc_r = interface2_bank_bus_dat_w[0]; +assign a7ddrphy_rdly_dq_inc_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[3:0] == 3'd6)); +assign a7ddrphy_rdly_dq_inc_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[3:0] == 3'd6)); +assign a7ddrphy_rdly_dq_bitslip_rst_r = interface2_bank_bus_dat_w[0]; +assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[3:0] == 3'd7)); +assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[3:0] == 3'd7)); +assign a7ddrphy_rdly_dq_bitslip_r = interface2_bank_bus_dat_w[0]; +assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[3:0] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[3:0] == 4'd8)); +assign a7ddrphy_wdly_dq_bitslip_rst_r = interface2_bank_bus_dat_w[0]; +assign a7ddrphy_wdly_dq_bitslip_rst_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[3:0] == 4'd9)); +assign a7ddrphy_wdly_dq_bitslip_rst_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[3:0] == 4'd9)); +assign a7ddrphy_wdly_dq_bitslip_r = interface2_bank_bus_dat_w[0]; +assign a7ddrphy_wdly_dq_bitslip_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[3:0] == 4'd10)); +assign a7ddrphy_wdly_dq_bitslip_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[3:0] == 4'd10)); +assign csrbank2_rdphase0_r = interface2_bank_bus_dat_w[1:0]; +assign csrbank2_rdphase0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[3:0] == 4'd11)); +assign csrbank2_rdphase0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[3:0] == 4'd11)); +assign csrbank2_wrphase0_r = interface2_bank_bus_dat_w[1:0]; +assign csrbank2_wrphase0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[3:0] == 4'd12)); +assign csrbank2_wrphase0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[3:0] == 4'd12)); +assign csrbank2_rst0_w = a7ddrphy_rst_storage; +assign csrbank2_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; +assign csrbank2_wlevel_en0_w = a7ddrphy_wlevel_en_storage; +assign csrbank2_dly_sel0_w = a7ddrphy_dly_sel_storage[3:0]; +assign csrbank2_rdphase0_w = a7ddrphy_rdphase_storage[1:0]; +assign csrbank2_wrphase0_w = a7ddrphy_wrphase_storage[1:0]; +assign csrbank3_sel = (interface3_bank_bus_adr[13:9] == 3'd7); +assign csrbank3_id1_r = interface3_bank_bus_dat_w[24:0]; +assign csrbank3_id1_re = ((csrbank3_sel & interface3_bank_bus_we) & (interface3_bank_bus_adr[0] == 1'd0)); +assign csrbank3_id1_we = ((csrbank3_sel & (~interface3_bank_bus_we)) & (interface3_bank_bus_adr[0] == 1'd0)); +assign csrbank3_id0_r = interface3_bank_bus_dat_w[31:0]; +assign csrbank3_id0_re = ((csrbank3_sel & interface3_bank_bus_we) & (interface3_bank_bus_adr[0] == 1'd1)); +assign csrbank3_id0_we = ((csrbank3_sel & (~interface3_bank_bus_we)) & (interface3_bank_bus_adr[0] == 1'd1)); +assign csrbank3_id1_w = dna_status[56:32]; +assign csrbank3_id0_w = dna_status[31:0]; +assign dna_we = csrbank3_id0_we; +assign dna_re = csrbank3_id0_re; +assign csrbank4_sel = (interface4_bank_bus_adr[13:9] == 4'd13); +assign csrbank4_crg_reset0_r = interface4_bank_bus_dat_w[0]; +assign csrbank4_crg_reset0_re = ((csrbank4_sel & interface4_bank_bus_we) & (interface4_bank_bus_adr[1:0] == 1'd0)); +assign csrbank4_crg_reset0_we = ((csrbank4_sel & (~interface4_bank_bus_we)) & (interface4_bank_bus_adr[1:0] == 1'd0)); +assign csrbank4_mdio_w0_r = interface4_bank_bus_dat_w[2:0]; +assign csrbank4_mdio_w0_re = ((csrbank4_sel & interface4_bank_bus_we) & (interface4_bank_bus_adr[1:0] == 1'd1)); +assign csrbank4_mdio_w0_we = ((csrbank4_sel & (~interface4_bank_bus_we)) & (interface4_bank_bus_adr[1:0] == 1'd1)); +assign csrbank4_mdio_r_r = interface4_bank_bus_dat_w[0]; +assign csrbank4_mdio_r_re = ((csrbank4_sel & interface4_bank_bus_we) & (interface4_bank_bus_adr[1:0] == 2'd2)); +assign csrbank4_mdio_r_we = ((csrbank4_sel & (~interface4_bank_bus_we)) & (interface4_bank_bus_adr[1:0] == 2'd2)); +assign csrbank4_crg_reset0_w = ethphy_reset_storage; +assign ethphy_mdc = ethphy__w_storage[0]; +assign ethphy_oe = ethphy__w_storage[1]; +assign ethphy_w = ethphy__w_storage[2]; +assign csrbank4_mdio_w0_w = ethphy__w_storage[2:0]; +assign csrbank4_mdio_r_w = ethphy__r_status; +assign ethphy__r_we = csrbank4_mdio_r_we; +assign ethphy__r_re = csrbank4_mdio_r_re; +assign csrbank5_sel = (interface5_bank_bus_adr[13:9] == 4'd10); +assign csrbank5_spi_control0_r = interface5_bank_bus_dat_w[15:0]; +assign csrbank5_spi_control0_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[2:0] == 1'd0)); +assign csrbank5_spi_control0_we = ((csrbank5_sel & (~interface5_bank_bus_we)) & (interface5_bank_bus_adr[2:0] == 1'd0)); +assign csrbank5_spi_status_r = interface5_bank_bus_dat_w[0]; +assign csrbank5_spi_status_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[2:0] == 1'd1)); +assign csrbank5_spi_status_we = ((csrbank5_sel & (~interface5_bank_bus_we)) & (interface5_bank_bus_adr[2:0] == 1'd1)); +assign csrbank5_spi_mosi1_r = interface5_bank_bus_dat_w[7:0]; +assign csrbank5_spi_mosi1_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[2:0] == 2'd2)); +assign csrbank5_spi_mosi1_we = ((csrbank5_sel & (~interface5_bank_bus_we)) & (interface5_bank_bus_adr[2:0] == 2'd2)); +assign csrbank5_spi_mosi0_r = interface5_bank_bus_dat_w[31:0]; +assign csrbank5_spi_mosi0_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[2:0] == 2'd3)); +assign csrbank5_spi_mosi0_we = ((csrbank5_sel & (~interface5_bank_bus_we)) & (interface5_bank_bus_adr[2:0] == 2'd3)); +assign csrbank5_spi_miso1_r = interface5_bank_bus_dat_w[7:0]; +assign csrbank5_spi_miso1_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[2:0] == 3'd4)); +assign csrbank5_spi_miso1_we = ((csrbank5_sel & (~interface5_bank_bus_we)) & (interface5_bank_bus_adr[2:0] == 3'd4)); +assign csrbank5_spi_miso0_r = interface5_bank_bus_dat_w[31:0]; +assign csrbank5_spi_miso0_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[2:0] == 3'd5)); +assign csrbank5_spi_miso0_we = ((csrbank5_sel & (~interface5_bank_bus_we)) & (interface5_bank_bus_adr[2:0] == 3'd5)); +assign csrbank5_spi_cs0_r = interface5_bank_bus_dat_w[0]; +assign csrbank5_spi_cs0_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[2:0] == 3'd6)); +assign csrbank5_spi_cs0_we = ((csrbank5_sel & (~interface5_bank_bus_we)) & (interface5_bank_bus_adr[2:0] == 3'd6)); +assign csrbank5_spi_loopback0_r = interface5_bank_bus_dat_w[0]; +assign csrbank5_spi_loopback0_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[2:0] == 3'd7)); +assign csrbank5_spi_loopback0_we = ((csrbank5_sel & (~interface5_bank_bus_we)) & (interface5_bank_bus_adr[2:0] == 3'd7)); +always @(*) begin + flash_start1 <= 1'd0; + if (flash_control_re) begin + flash_start1 <= flash_control_storage[0]; + end +end +assign flash_length1 = flash_control_storage[15:8]; +assign csrbank5_spi_control0_w = flash_control_storage[15:0]; +assign flash_status_status = flash_done1; +assign csrbank5_spi_status_w = flash_status_status; +assign flash_status_we = csrbank5_spi_status_we; +assign flash_status_re = csrbank5_spi_status_re; +assign csrbank5_spi_mosi1_w = flash_mosi_storage[39:32]; +assign csrbank5_spi_mosi0_w = flash_mosi_storage[31:0]; +assign csrbank5_spi_miso1_w = flash_miso_status[39:32]; +assign csrbank5_spi_miso0_w = flash_miso_status[31:0]; +assign flash_miso_we = csrbank5_spi_miso0_we; +assign flash_miso_re = csrbank5_spi_miso0_re; +assign flash_sel = flash_cs_storage; +assign csrbank5_spi_cs0_w = flash_cs_storage; +assign csrbank5_spi_loopback0_w = flash_loopback_storage; +assign sram0_sel = (interface0_sram_bus_adr[13:9] == 5'd20); +always @(*) begin + interface0_sram_bus_dat_r <= 32'd0; + if (sram0_sel_r) begin + interface0_sram_bus_dat_r <= sram0_dat_r; + end +end +assign sram0_we = (sram0_sel & interface0_sram_bus_we); +assign sram0_dat_w = interface0_sram_bus_dat_w; +assign sram0_adr = interface0_sram_bus_adr[7:0]; +assign csrbank6_sel = (interface6_bank_bus_adr[13:9] == 5'd19); +assign csrbank6_edid_hpd_notif_r = interface6_bank_bus_dat_w[0]; +assign csrbank6_edid_hpd_notif_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 1'd0)); +assign csrbank6_edid_hpd_notif_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 1'd0)); +assign csrbank6_edid_hpd_en0_r = interface6_bank_bus_dat_w[0]; +assign csrbank6_edid_hpd_en0_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 1'd1)); +assign csrbank6_edid_hpd_en0_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 1'd1)); +assign csrbank6_clocking_mmcm_reset0_r = interface6_bank_bus_dat_w[0]; +assign csrbank6_clocking_mmcm_reset0_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 2'd2)); +assign csrbank6_clocking_mmcm_reset0_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 2'd2)); +assign csrbank6_clocking_locked_r = interface6_bank_bus_dat_w[0]; +assign csrbank6_clocking_locked_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 2'd3)); +assign csrbank6_clocking_locked_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 2'd3)); +assign hdmi_in0_mmcm_read_r = interface6_bank_bus_dat_w[0]; +assign hdmi_in0_mmcm_read_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 3'd4)); +assign hdmi_in0_mmcm_read_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 3'd4)); +assign hdmi_in0_mmcm_write_r = interface6_bank_bus_dat_w[0]; +assign hdmi_in0_mmcm_write_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 3'd5)); +assign hdmi_in0_mmcm_write_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 3'd5)); +assign csrbank6_clocking_mmcm_drdy_r = interface6_bank_bus_dat_w[0]; +assign csrbank6_clocking_mmcm_drdy_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 3'd6)); +assign csrbank6_clocking_mmcm_drdy_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 3'd6)); +assign csrbank6_clocking_mmcm_adr0_r = interface6_bank_bus_dat_w[6:0]; +assign csrbank6_clocking_mmcm_adr0_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 3'd7)); +assign csrbank6_clocking_mmcm_adr0_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 3'd7)); +assign csrbank6_clocking_mmcm_dat_w0_r = interface6_bank_bus_dat_w[15:0]; +assign csrbank6_clocking_mmcm_dat_w0_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 4'd8)); +assign csrbank6_clocking_mmcm_dat_w0_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 4'd8)); +assign csrbank6_clocking_mmcm_dat_r_r = interface6_bank_bus_dat_w[15:0]; +assign csrbank6_clocking_mmcm_dat_r_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 4'd9)); +assign csrbank6_clocking_mmcm_dat_r_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 4'd9)); +assign hdmi_in0_mmcm_write_o_r = interface6_bank_bus_dat_w[0]; +assign hdmi_in0_mmcm_write_o_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 4'd10)); +assign hdmi_in0_mmcm_write_o_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 4'd10)); +assign hdmi_in0_mmcm_read_o_r = interface6_bank_bus_dat_w[0]; +assign hdmi_in0_mmcm_read_o_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 4'd11)); +assign hdmi_in0_mmcm_read_o_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 4'd11)); +assign csrbank6_clocking_mmcm_dat_o_r_r = interface6_bank_bus_dat_w[15:0]; +assign csrbank6_clocking_mmcm_dat_o_r_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 4'd12)); +assign csrbank6_clocking_mmcm_dat_o_r_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 4'd12)); +assign csrbank6_clocking_mmcm_drdy_o_r = interface6_bank_bus_dat_w[0]; +assign csrbank6_clocking_mmcm_drdy_o_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 4'd13)); +assign csrbank6_clocking_mmcm_drdy_o_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 4'd13)); +assign hdmi_in0_s7datacapture0_dly_ctl_r = interface6_bank_bus_dat_w[4:0]; +assign hdmi_in0_s7datacapture0_dly_ctl_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 4'd14)); +assign hdmi_in0_s7datacapture0_dly_ctl_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 4'd14)); +assign csrbank6_data0_cap_phase_r = interface6_bank_bus_dat_w[1:0]; +assign csrbank6_data0_cap_phase_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 4'd15)); +assign csrbank6_data0_cap_phase_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 4'd15)); +assign hdmi_in0_s7datacapture0_phase_reset_r = interface6_bank_bus_dat_w[0]; +assign hdmi_in0_s7datacapture0_phase_reset_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 5'd16)); +assign hdmi_in0_s7datacapture0_phase_reset_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 5'd16)); +assign csrbank6_data0_cap_cntvalueout_m_r = interface6_bank_bus_dat_w[4:0]; +assign csrbank6_data0_cap_cntvalueout_m_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 5'd17)); +assign csrbank6_data0_cap_cntvalueout_m_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 5'd17)); +assign csrbank6_data0_cap_cntvalueout_s_r = interface6_bank_bus_dat_w[4:0]; +assign csrbank6_data0_cap_cntvalueout_s_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 5'd18)); +assign csrbank6_data0_cap_cntvalueout_s_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 5'd18)); +assign csrbank6_data0_charsync_char_synced_r = interface6_bank_bus_dat_w[0]; +assign csrbank6_data0_charsync_char_synced_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 5'd19)); +assign csrbank6_data0_charsync_char_synced_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 5'd19)); +assign csrbank6_data0_charsync_ctl_pos_r = interface6_bank_bus_dat_w[3:0]; +assign csrbank6_data0_charsync_ctl_pos_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 5'd20)); +assign csrbank6_data0_charsync_ctl_pos_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 5'd20)); +assign hdmi_in0_wer0_update_r = interface6_bank_bus_dat_w[0]; +assign hdmi_in0_wer0_update_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 5'd21)); +assign hdmi_in0_wer0_update_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 5'd21)); +assign csrbank6_data0_wer_value_r = interface6_bank_bus_dat_w[23:0]; +assign csrbank6_data0_wer_value_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 5'd22)); +assign csrbank6_data0_wer_value_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 5'd22)); +assign hdmi_in0_s7datacapture1_dly_ctl_r = interface6_bank_bus_dat_w[4:0]; +assign hdmi_in0_s7datacapture1_dly_ctl_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 5'd23)); +assign hdmi_in0_s7datacapture1_dly_ctl_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 5'd23)); +assign csrbank6_data1_cap_phase_r = interface6_bank_bus_dat_w[1:0]; +assign csrbank6_data1_cap_phase_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 5'd24)); +assign csrbank6_data1_cap_phase_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 5'd24)); +assign hdmi_in0_s7datacapture1_phase_reset_r = interface6_bank_bus_dat_w[0]; +assign hdmi_in0_s7datacapture1_phase_reset_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 5'd25)); +assign hdmi_in0_s7datacapture1_phase_reset_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 5'd25)); +assign csrbank6_data1_cap_cntvalueout_m_r = interface6_bank_bus_dat_w[4:0]; +assign csrbank6_data1_cap_cntvalueout_m_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 5'd26)); +assign csrbank6_data1_cap_cntvalueout_m_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 5'd26)); +assign csrbank6_data1_cap_cntvalueout_s_r = interface6_bank_bus_dat_w[4:0]; +assign csrbank6_data1_cap_cntvalueout_s_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 5'd27)); +assign csrbank6_data1_cap_cntvalueout_s_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 5'd27)); +assign csrbank6_data1_charsync_char_synced_r = interface6_bank_bus_dat_w[0]; +assign csrbank6_data1_charsync_char_synced_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 5'd28)); +assign csrbank6_data1_charsync_char_synced_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 5'd28)); +assign csrbank6_data1_charsync_ctl_pos_r = interface6_bank_bus_dat_w[3:0]; +assign csrbank6_data1_charsync_ctl_pos_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 5'd29)); +assign csrbank6_data1_charsync_ctl_pos_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 5'd29)); +assign hdmi_in0_wer1_update_r = interface6_bank_bus_dat_w[0]; +assign hdmi_in0_wer1_update_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 5'd30)); +assign hdmi_in0_wer1_update_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 5'd30)); +assign csrbank6_data1_wer_value_r = interface6_bank_bus_dat_w[23:0]; +assign csrbank6_data1_wer_value_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 5'd31)); +assign csrbank6_data1_wer_value_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 5'd31)); +assign hdmi_in0_s7datacapture2_dly_ctl_r = interface6_bank_bus_dat_w[4:0]; +assign hdmi_in0_s7datacapture2_dly_ctl_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd32)); +assign hdmi_in0_s7datacapture2_dly_ctl_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd32)); +assign csrbank6_data2_cap_phase_r = interface6_bank_bus_dat_w[1:0]; +assign csrbank6_data2_cap_phase_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd33)); +assign csrbank6_data2_cap_phase_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd33)); +assign hdmi_in0_s7datacapture2_phase_reset_r = interface6_bank_bus_dat_w[0]; +assign hdmi_in0_s7datacapture2_phase_reset_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd34)); +assign hdmi_in0_s7datacapture2_phase_reset_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd34)); +assign csrbank6_data2_cap_cntvalueout_m_r = interface6_bank_bus_dat_w[4:0]; +assign csrbank6_data2_cap_cntvalueout_m_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd35)); +assign csrbank6_data2_cap_cntvalueout_m_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd35)); +assign csrbank6_data2_cap_cntvalueout_s_r = interface6_bank_bus_dat_w[4:0]; +assign csrbank6_data2_cap_cntvalueout_s_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd36)); +assign csrbank6_data2_cap_cntvalueout_s_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd36)); +assign csrbank6_data2_charsync_char_synced_r = interface6_bank_bus_dat_w[0]; +assign csrbank6_data2_charsync_char_synced_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd37)); +assign csrbank6_data2_charsync_char_synced_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd37)); +assign csrbank6_data2_charsync_ctl_pos_r = interface6_bank_bus_dat_w[3:0]; +assign csrbank6_data2_charsync_ctl_pos_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd38)); +assign csrbank6_data2_charsync_ctl_pos_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd38)); +assign hdmi_in0_wer2_update_r = interface6_bank_bus_dat_w[0]; +assign hdmi_in0_wer2_update_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd39)); +assign hdmi_in0_wer2_update_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd39)); +assign csrbank6_data2_wer_value_r = interface6_bank_bus_dat_w[23:0]; +assign csrbank6_data2_wer_value_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd40)); +assign csrbank6_data2_wer_value_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd40)); +assign csrbank6_chansync_channels_synced_r = interface6_bank_bus_dat_w[0]; +assign csrbank6_chansync_channels_synced_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd41)); +assign csrbank6_chansync_channels_synced_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd41)); +assign csrbank6_resdetection_hres_r = interface6_bank_bus_dat_w[10:0]; +assign csrbank6_resdetection_hres_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd42)); +assign csrbank6_resdetection_hres_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd42)); +assign csrbank6_resdetection_vres_r = interface6_bank_bus_dat_w[10:0]; +assign csrbank6_resdetection_vres_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd43)); +assign csrbank6_resdetection_vres_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd43)); +assign hdmi_in0_frame_overflow_r = interface6_bank_bus_dat_w[0]; +assign hdmi_in0_frame_overflow_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd44)); +assign hdmi_in0_frame_overflow_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd44)); +assign csrbank6_dma_frame_size0_r = interface6_bank_bus_dat_w[28:0]; +assign csrbank6_dma_frame_size0_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd45)); +assign csrbank6_dma_frame_size0_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd45)); +assign csrbank6_dma_slot0_status0_r = interface6_bank_bus_dat_w[1:0]; +assign csrbank6_dma_slot0_status0_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd46)); +assign csrbank6_dma_slot0_status0_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd46)); +assign csrbank6_dma_slot0_address0_r = interface6_bank_bus_dat_w[28:0]; +assign csrbank6_dma_slot0_address0_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd47)); +assign csrbank6_dma_slot0_address0_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd47)); +assign csrbank6_dma_slot1_status0_r = interface6_bank_bus_dat_w[1:0]; +assign csrbank6_dma_slot1_status0_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd48)); +assign csrbank6_dma_slot1_status0_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd48)); +assign csrbank6_dma_slot1_address0_r = interface6_bank_bus_dat_w[28:0]; +assign csrbank6_dma_slot1_address0_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd49)); +assign csrbank6_dma_slot1_address0_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd49)); +assign hdmi_in0_dma_slot_array_status_r = interface6_bank_bus_dat_w[1:0]; +assign hdmi_in0_dma_slot_array_status_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd50)); +assign hdmi_in0_dma_slot_array_status_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd50)); +assign hdmi_in0_dma_slot_array_pending_r = interface6_bank_bus_dat_w[1:0]; +assign hdmi_in0_dma_slot_array_pending_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd51)); +assign hdmi_in0_dma_slot_array_pending_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd51)); +assign csrbank6_dma_ev_enable0_r = interface6_bank_bus_dat_w[1:0]; +assign csrbank6_dma_ev_enable0_re = ((csrbank6_sel & interface6_bank_bus_we) & (interface6_bank_bus_adr[5:0] == 6'd52)); +assign csrbank6_dma_ev_enable0_we = ((csrbank6_sel & (~interface6_bank_bus_we)) & (interface6_bank_bus_adr[5:0] == 6'd52)); +assign csrbank6_edid_hpd_notif_w = hdmi_in0_hpd_notif_status; +assign hdmi_in0_hpd_notif_we = csrbank6_edid_hpd_notif_we; +assign hdmi_in0_hpd_notif_re = csrbank6_edid_hpd_notif_re; +assign csrbank6_edid_hpd_en0_w = hdmi_in0_hpd_en_storage; +assign csrbank6_clocking_mmcm_reset0_w = hdmi_in0_mmcm_reset_storage; +assign csrbank6_clocking_locked_w = hdmi_in0_locked_status; +assign hdmi_in0_locked_we = csrbank6_clocking_locked_we; +assign hdmi_in0_locked_re = csrbank6_clocking_locked_re; +assign csrbank6_clocking_mmcm_drdy_w = hdmi_in0_mmcm_drdy_status; +assign hdmi_in0_mmcm_drdy_we = csrbank6_clocking_mmcm_drdy_we; +assign hdmi_in0_mmcm_drdy_re = csrbank6_clocking_mmcm_drdy_re; +assign csrbank6_clocking_mmcm_adr0_w = hdmi_in0_mmcm_adr_storage[6:0]; +assign csrbank6_clocking_mmcm_dat_w0_w = hdmi_in0_mmcm_dat_w_storage[15:0]; +assign csrbank6_clocking_mmcm_dat_r_w = hdmi_in0_mmcm_dat_r_status[15:0]; +assign hdmi_in0_mmcm_dat_r_we = csrbank6_clocking_mmcm_dat_r_we; +assign hdmi_in0_mmcm_dat_r_re = csrbank6_clocking_mmcm_dat_r_re; +assign csrbank6_clocking_mmcm_dat_o_r_w = hdmi_in0_mmcm_dat_o_r_status[15:0]; +assign hdmi_in0_mmcm_dat_o_r_we = csrbank6_clocking_mmcm_dat_o_r_we; +assign hdmi_in0_mmcm_dat_o_r_re = csrbank6_clocking_mmcm_dat_o_r_re; +assign csrbank6_clocking_mmcm_drdy_o_w = hdmi_in0_mmcm_drdy_o_status; +assign hdmi_in0_mmcm_drdy_o_we = csrbank6_clocking_mmcm_drdy_o_we; +assign hdmi_in0_mmcm_drdy_o_re = csrbank6_clocking_mmcm_drdy_o_re; +assign csrbank6_data0_cap_phase_w = hdmi_in0_s7datacapture0_phase_status[1:0]; +assign hdmi_in0_s7datacapture0_phase_we = csrbank6_data0_cap_phase_we; +assign hdmi_in0_s7datacapture0_phase_re = csrbank6_data0_cap_phase_re; +assign csrbank6_data0_cap_cntvalueout_m_w = hdmi_in0_s7datacapture0_cntvalueout_m_status[4:0]; +assign hdmi_in0_s7datacapture0_cntvalueout_m_we = csrbank6_data0_cap_cntvalueout_m_we; +assign hdmi_in0_s7datacapture0_cntvalueout_m_re = csrbank6_data0_cap_cntvalueout_m_re; +assign csrbank6_data0_cap_cntvalueout_s_w = hdmi_in0_s7datacapture0_cntvalueout_s_status[4:0]; +assign hdmi_in0_s7datacapture0_cntvalueout_s_we = csrbank6_data0_cap_cntvalueout_s_we; +assign hdmi_in0_s7datacapture0_cntvalueout_s_re = csrbank6_data0_cap_cntvalueout_s_re; +assign csrbank6_data0_charsync_char_synced_w = hdmi_in0_charsync0_char_synced_status; +assign hdmi_in0_charsync0_char_synced_we = csrbank6_data0_charsync_char_synced_we; +assign hdmi_in0_charsync0_char_synced_re = csrbank6_data0_charsync_char_synced_re; +assign csrbank6_data0_charsync_ctl_pos_w = hdmi_in0_charsync0_ctl_pos_status[3:0]; +assign hdmi_in0_charsync0_ctl_pos_we = csrbank6_data0_charsync_ctl_pos_we; +assign hdmi_in0_charsync0_ctl_pos_re = csrbank6_data0_charsync_ctl_pos_re; +assign csrbank6_data0_wer_value_w = hdmi_in0_wer0_status[23:0]; +assign hdmi_in0_wer0_we = csrbank6_data0_wer_value_we; +assign hdmi_in0_wer0_re = csrbank6_data0_wer_value_re; +assign csrbank6_data1_cap_phase_w = hdmi_in0_s7datacapture1_phase_status[1:0]; +assign hdmi_in0_s7datacapture1_phase_we = csrbank6_data1_cap_phase_we; +assign hdmi_in0_s7datacapture1_phase_re = csrbank6_data1_cap_phase_re; +assign csrbank6_data1_cap_cntvalueout_m_w = hdmi_in0_s7datacapture1_cntvalueout_m_status[4:0]; +assign hdmi_in0_s7datacapture1_cntvalueout_m_we = csrbank6_data1_cap_cntvalueout_m_we; +assign hdmi_in0_s7datacapture1_cntvalueout_m_re = csrbank6_data1_cap_cntvalueout_m_re; +assign csrbank6_data1_cap_cntvalueout_s_w = hdmi_in0_s7datacapture1_cntvalueout_s_status[4:0]; +assign hdmi_in0_s7datacapture1_cntvalueout_s_we = csrbank6_data1_cap_cntvalueout_s_we; +assign hdmi_in0_s7datacapture1_cntvalueout_s_re = csrbank6_data1_cap_cntvalueout_s_re; +assign csrbank6_data1_charsync_char_synced_w = hdmi_in0_charsync1_char_synced_status; +assign hdmi_in0_charsync1_char_synced_we = csrbank6_data1_charsync_char_synced_we; +assign hdmi_in0_charsync1_char_synced_re = csrbank6_data1_charsync_char_synced_re; +assign csrbank6_data1_charsync_ctl_pos_w = hdmi_in0_charsync1_ctl_pos_status[3:0]; +assign hdmi_in0_charsync1_ctl_pos_we = csrbank6_data1_charsync_ctl_pos_we; +assign hdmi_in0_charsync1_ctl_pos_re = csrbank6_data1_charsync_ctl_pos_re; +assign csrbank6_data1_wer_value_w = hdmi_in0_wer1_status[23:0]; +assign hdmi_in0_wer1_we = csrbank6_data1_wer_value_we; +assign hdmi_in0_wer1_re = csrbank6_data1_wer_value_re; +assign csrbank6_data2_cap_phase_w = hdmi_in0_s7datacapture2_phase_status[1:0]; +assign hdmi_in0_s7datacapture2_phase_we = csrbank6_data2_cap_phase_we; +assign hdmi_in0_s7datacapture2_phase_re = csrbank6_data2_cap_phase_re; +assign csrbank6_data2_cap_cntvalueout_m_w = hdmi_in0_s7datacapture2_cntvalueout_m_status[4:0]; +assign hdmi_in0_s7datacapture2_cntvalueout_m_we = csrbank6_data2_cap_cntvalueout_m_we; +assign hdmi_in0_s7datacapture2_cntvalueout_m_re = csrbank6_data2_cap_cntvalueout_m_re; +assign csrbank6_data2_cap_cntvalueout_s_w = hdmi_in0_s7datacapture2_cntvalueout_s_status[4:0]; +assign hdmi_in0_s7datacapture2_cntvalueout_s_we = csrbank6_data2_cap_cntvalueout_s_we; +assign hdmi_in0_s7datacapture2_cntvalueout_s_re = csrbank6_data2_cap_cntvalueout_s_re; +assign csrbank6_data2_charsync_char_synced_w = hdmi_in0_charsync2_char_synced_status; +assign hdmi_in0_charsync2_char_synced_we = csrbank6_data2_charsync_char_synced_we; +assign hdmi_in0_charsync2_char_synced_re = csrbank6_data2_charsync_char_synced_re; +assign csrbank6_data2_charsync_ctl_pos_w = hdmi_in0_charsync2_ctl_pos_status[3:0]; +assign hdmi_in0_charsync2_ctl_pos_we = csrbank6_data2_charsync_ctl_pos_we; +assign hdmi_in0_charsync2_ctl_pos_re = csrbank6_data2_charsync_ctl_pos_re; +assign csrbank6_data2_wer_value_w = hdmi_in0_wer2_status[23:0]; +assign hdmi_in0_wer2_we = csrbank6_data2_wer_value_we; +assign hdmi_in0_wer2_re = csrbank6_data2_wer_value_re; +assign csrbank6_chansync_channels_synced_w = hdmi_in0_chansync_status; +assign hdmi_in0_chansync_we = csrbank6_chansync_channels_synced_we; +assign hdmi_in0_chansync_re = csrbank6_chansync_channels_synced_re; +assign csrbank6_resdetection_hres_w = hdmi_in0_resdetection_hres_status[10:0]; +assign hdmi_in0_resdetection_hres_we = csrbank6_resdetection_hres_we; +assign hdmi_in0_resdetection_hres_re = csrbank6_resdetection_hres_re; +assign csrbank6_resdetection_vres_w = hdmi_in0_resdetection_vres_status[10:0]; +assign hdmi_in0_resdetection_vres_we = csrbank6_resdetection_vres_we; +assign hdmi_in0_resdetection_vres_re = csrbank6_resdetection_vres_re; +assign csrbank6_dma_frame_size0_w = hdmi_in0_dma_frame_size_storage[28:0]; +assign csrbank6_dma_slot0_status0_w = hdmi_in0_dma_slot_array_slot0_status_storage[1:0]; +assign csrbank6_dma_slot0_address0_w = hdmi_in0_dma_slot_array_slot0_address_storage[28:0]; +assign csrbank6_dma_slot1_status0_w = hdmi_in0_dma_slot_array_slot1_status_storage[1:0]; +assign csrbank6_dma_slot1_address0_w = hdmi_in0_dma_slot_array_slot1_address_storage[28:0]; +assign csrbank6_dma_ev_enable0_w = hdmi_in0_dma_slot_array_storage[1:0]; +assign csrbank7_sel = (interface7_bank_bus_adr[13:9] == 5'd18); +assign csrbank7_value_r = interface7_bank_bus_dat_w[31:0]; +assign csrbank7_value_re = ((csrbank7_sel & interface7_bank_bus_we) & (interface7_bank_bus_adr[0] == 1'd0)); +assign csrbank7_value_we = ((csrbank7_sel & (~interface7_bank_bus_we)) & (interface7_bank_bus_adr[0] == 1'd0)); +assign csrbank7_value_w = freqmeter_status[31:0]; +assign freqmeter_we = csrbank7_value_we; +assign freqmeter_re = csrbank7_value_re; +assign csrbank8_sel = (interface8_bank_bus_adr[13:9] == 5'd21); +assign csrbank8_core_underflow_enable0_r = interface8_bank_bus_dat_w[0]; +assign csrbank8_core_underflow_enable0_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 1'd0)); +assign csrbank8_core_underflow_enable0_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 1'd0)); +assign hdmi_out0_core_underflow_update_underflow_update_r = interface8_bank_bus_dat_w[0]; +assign hdmi_out0_core_underflow_update_underflow_update_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 1'd1)); +assign hdmi_out0_core_underflow_update_underflow_update_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 1'd1)); +assign csrbank8_core_underflow_counter_r = interface8_bank_bus_dat_w[31:0]; +assign csrbank8_core_underflow_counter_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 2'd2)); +assign csrbank8_core_underflow_counter_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 2'd2)); +assign csrbank8_core_initiator_enable0_r = interface8_bank_bus_dat_w[0]; +assign csrbank8_core_initiator_enable0_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 2'd3)); +assign csrbank8_core_initiator_enable0_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 2'd3)); +assign csrbank8_core_initiator_hres0_r = interface8_bank_bus_dat_w[11:0]; +assign csrbank8_core_initiator_hres0_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 3'd4)); +assign csrbank8_core_initiator_hres0_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 3'd4)); +assign csrbank8_core_initiator_hsync_start0_r = interface8_bank_bus_dat_w[11:0]; +assign csrbank8_core_initiator_hsync_start0_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 3'd5)); +assign csrbank8_core_initiator_hsync_start0_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 3'd5)); +assign csrbank8_core_initiator_hsync_end0_r = interface8_bank_bus_dat_w[11:0]; +assign csrbank8_core_initiator_hsync_end0_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 3'd6)); +assign csrbank8_core_initiator_hsync_end0_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 3'd6)); +assign csrbank8_core_initiator_hscan0_r = interface8_bank_bus_dat_w[11:0]; +assign csrbank8_core_initiator_hscan0_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 3'd7)); +assign csrbank8_core_initiator_hscan0_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 3'd7)); +assign csrbank8_core_initiator_vres0_r = interface8_bank_bus_dat_w[11:0]; +assign csrbank8_core_initiator_vres0_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 4'd8)); +assign csrbank8_core_initiator_vres0_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 4'd8)); +assign csrbank8_core_initiator_vsync_start0_r = interface8_bank_bus_dat_w[11:0]; +assign csrbank8_core_initiator_vsync_start0_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 4'd9)); +assign csrbank8_core_initiator_vsync_start0_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 4'd9)); +assign csrbank8_core_initiator_vsync_end0_r = interface8_bank_bus_dat_w[11:0]; +assign csrbank8_core_initiator_vsync_end0_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 4'd10)); +assign csrbank8_core_initiator_vsync_end0_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 4'd10)); +assign csrbank8_core_initiator_vscan0_r = interface8_bank_bus_dat_w[11:0]; +assign csrbank8_core_initiator_vscan0_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 4'd11)); +assign csrbank8_core_initiator_vscan0_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 4'd11)); +assign csrbank8_core_initiator_base0_r = interface8_bank_bus_dat_w[31:0]; +assign csrbank8_core_initiator_base0_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 4'd12)); +assign csrbank8_core_initiator_base0_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 4'd12)); +assign csrbank8_core_initiator_length0_r = interface8_bank_bus_dat_w[31:0]; +assign csrbank8_core_initiator_length0_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 4'd13)); +assign csrbank8_core_initiator_length0_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 4'd13)); +assign csrbank8_core_dma_delay_base0_r = interface8_bank_bus_dat_w[31:0]; +assign csrbank8_core_dma_delay_base0_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 4'd14)); +assign csrbank8_core_dma_delay_base0_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 4'd14)); +assign csrbank8_driver_clocking_mmcm_reset0_r = interface8_bank_bus_dat_w[0]; +assign csrbank8_driver_clocking_mmcm_reset0_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 4'd15)); +assign csrbank8_driver_clocking_mmcm_reset0_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 4'd15)); +assign hdmi_out0_driver_s7hdmioutclocking_mmcm_read_r = interface8_bank_bus_dat_w[0]; +assign hdmi_out0_driver_s7hdmioutclocking_mmcm_read_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 5'd16)); +assign hdmi_out0_driver_s7hdmioutclocking_mmcm_read_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 5'd16)); +assign hdmi_out0_driver_s7hdmioutclocking_mmcm_write_r = interface8_bank_bus_dat_w[0]; +assign hdmi_out0_driver_s7hdmioutclocking_mmcm_write_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 5'd17)); +assign hdmi_out0_driver_s7hdmioutclocking_mmcm_write_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 5'd17)); +assign csrbank8_driver_clocking_mmcm_drdy_r = interface8_bank_bus_dat_w[0]; +assign csrbank8_driver_clocking_mmcm_drdy_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 5'd18)); +assign csrbank8_driver_clocking_mmcm_drdy_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 5'd18)); +assign csrbank8_driver_clocking_mmcm_adr0_r = interface8_bank_bus_dat_w[6:0]; +assign csrbank8_driver_clocking_mmcm_adr0_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 5'd19)); +assign csrbank8_driver_clocking_mmcm_adr0_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 5'd19)); +assign csrbank8_driver_clocking_mmcm_dat_w0_r = interface8_bank_bus_dat_w[15:0]; +assign csrbank8_driver_clocking_mmcm_dat_w0_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 5'd20)); +assign csrbank8_driver_clocking_mmcm_dat_w0_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 5'd20)); +assign csrbank8_driver_clocking_mmcm_dat_r_r = interface8_bank_bus_dat_w[15:0]; +assign csrbank8_driver_clocking_mmcm_dat_r_re = ((csrbank8_sel & interface8_bank_bus_we) & (interface8_bank_bus_adr[4:0] == 5'd21)); +assign csrbank8_driver_clocking_mmcm_dat_r_we = ((csrbank8_sel & (~interface8_bank_bus_we)) & (interface8_bank_bus_adr[4:0] == 5'd21)); +assign csrbank8_core_underflow_enable0_w = hdmi_out0_core_underflow_enable_storage; +assign csrbank8_core_underflow_counter_w = hdmi_out0_core_underflow_counter_status[31:0]; +assign hdmi_out0_core_underflow_counter_we = csrbank8_core_underflow_counter_we; +assign hdmi_out0_core_underflow_counter_re = csrbank8_core_underflow_counter_re; +assign csrbank8_core_initiator_enable0_w = hdmi_out0_core_initiator_enable_storage; +assign csrbank8_core_initiator_hres0_w = hdmi_out0_core_initiator_csrstorage0_storage[11:0]; +assign csrbank8_core_initiator_hsync_start0_w = hdmi_out0_core_initiator_csrstorage1_storage[11:0]; +assign csrbank8_core_initiator_hsync_end0_w = hdmi_out0_core_initiator_csrstorage2_storage[11:0]; +assign csrbank8_core_initiator_hscan0_w = hdmi_out0_core_initiator_csrstorage3_storage[11:0]; +assign csrbank8_core_initiator_vres0_w = hdmi_out0_core_initiator_csrstorage4_storage[11:0]; +assign csrbank8_core_initiator_vsync_start0_w = hdmi_out0_core_initiator_csrstorage5_storage[11:0]; +assign csrbank8_core_initiator_vsync_end0_w = hdmi_out0_core_initiator_csrstorage6_storage[11:0]; +assign csrbank8_core_initiator_vscan0_w = hdmi_out0_core_initiator_csrstorage7_storage[11:0]; +assign csrbank8_core_initiator_base0_w = hdmi_out0_core_initiator_csrstorage8_storage[31:0]; +assign csrbank8_core_initiator_length0_w = hdmi_out0_core_initiator_csrstorage9_storage[31:0]; +assign csrbank8_core_dma_delay_base0_w = hdmi_out0_core_dmareader_storage[31:0]; +assign csrbank8_driver_clocking_mmcm_reset0_w = hdmi_out0_driver_s7hdmioutclocking_mmcm_reset_storage; +assign csrbank8_driver_clocking_mmcm_drdy_w = hdmi_out0_driver_s7hdmioutclocking_mmcm_drdy_status; +assign hdmi_out0_driver_s7hdmioutclocking_mmcm_drdy_we = csrbank8_driver_clocking_mmcm_drdy_we; +assign hdmi_out0_driver_s7hdmioutclocking_mmcm_drdy_re = csrbank8_driver_clocking_mmcm_drdy_re; +assign csrbank8_driver_clocking_mmcm_adr0_w = hdmi_out0_driver_s7hdmioutclocking_mmcm_adr_storage[6:0]; +assign csrbank8_driver_clocking_mmcm_dat_w0_w = hdmi_out0_driver_s7hdmioutclocking_mmcm_dat_w_storage[15:0]; +assign csrbank8_driver_clocking_mmcm_dat_r_w = hdmi_out0_driver_s7hdmioutclocking_mmcm_dat_r_status[15:0]; +assign hdmi_out0_driver_s7hdmioutclocking_mmcm_dat_r_we = csrbank8_driver_clocking_mmcm_dat_r_we; +assign hdmi_out0_driver_s7hdmioutclocking_mmcm_dat_r_re = csrbank8_driver_clocking_mmcm_dat_r_re; +assign csrbank9_sel = (interface9_bank_bus_adr[13:9] == 4'd9); +assign csrbank9_addr0_r = interface9_bank_bus_dat_w[4:0]; +assign csrbank9_addr0_re = ((csrbank9_sel & interface9_bank_bus_we) & (interface9_bank_bus_adr[1:0] == 1'd0)); +assign csrbank9_addr0_we = ((csrbank9_sel & (~interface9_bank_bus_we)) & (interface9_bank_bus_adr[1:0] == 1'd0)); +assign csrbank9_data0_r = interface9_bank_bus_dat_w[31:0]; +assign csrbank9_data0_re = ((csrbank9_sel & interface9_bank_bus_we) & (interface9_bank_bus_adr[1:0] == 1'd1)); +assign csrbank9_data0_we = ((csrbank9_sel & (~interface9_bank_bus_we)) & (interface9_bank_bus_adr[1:0] == 1'd1)); +assign csrbank9_send0_r = interface9_bank_bus_dat_w[0]; +assign csrbank9_send0_re = ((csrbank9_sel & interface9_bank_bus_we) & (interface9_bank_bus_adr[1:0] == 2'd2)); +assign csrbank9_send0_we = ((csrbank9_sel & (~interface9_bank_bus_we)) & (interface9_bank_bus_adr[1:0] == 2'd2)); +assign csrbank9_done_r = interface9_bank_bus_dat_w[0]; +assign csrbank9_done_re = ((csrbank9_sel & interface9_bank_bus_we) & (interface9_bank_bus_adr[1:0] == 2'd3)); +assign csrbank9_done_we = ((csrbank9_sel & (~interface9_bank_bus_we)) & (interface9_bank_bus_adr[1:0] == 2'd3)); +assign csrbank9_addr0_w = icap_addr_storage[4:0]; +assign csrbank9_data0_w = icap_data_storage[31:0]; +assign csrbank9_send0_w = icap_send_storage; +assign csrbank9_done_w = icap_done_status; +assign icap_done_we = csrbank9_done_we; +assign icap_done_re = csrbank9_done_re; +assign sram1_sel = (interface1_sram_bus_adr[13:9] == 2'd2); +always @(*) begin + interface1_sram_bus_dat_r <= 32'd0; + if (sram1_sel_r) begin + interface1_sram_bus_dat_r <= sram1_dat_r; + end +end +assign sram1_adr = interface1_sram_bus_adr[5:0]; +assign csrbank10_sel = (interface10_bank_bus_adr[13:9] == 4'd15); +assign csrbank10_writer_enable0_r = interface10_bank_bus_dat_w[0]; +assign csrbank10_writer_enable0_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 1'd0)); +assign csrbank10_writer_enable0_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 1'd0)); +assign csrbank10_writer_table_value1_r = interface10_bank_bus_dat_w[25:0]; +assign csrbank10_writer_table_value1_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 1'd1)); +assign csrbank10_writer_table_value1_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 1'd1)); +assign csrbank10_writer_table_value0_r = interface10_bank_bus_dat_w[31:0]; +assign csrbank10_writer_table_value0_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 2'd2)); +assign csrbank10_writer_table_value0_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 2'd2)); +assign csrbank10_writer_table_we0_r = interface10_bank_bus_dat_w[0]; +assign csrbank10_writer_table_we0_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 2'd3)); +assign csrbank10_writer_table_we0_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 2'd3)); +assign csrbank10_writer_table_loop_prog_n0_r = interface10_bank_bus_dat_w[0]; +assign csrbank10_writer_table_loop_prog_n0_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 3'd4)); +assign csrbank10_writer_table_loop_prog_n0_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 3'd4)); +assign csrbank10_writer_table_loop_status_r = interface10_bank_bus_dat_w[31:0]; +assign csrbank10_writer_table_loop_status_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 3'd5)); +assign csrbank10_writer_table_loop_status_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 3'd5)); +assign csrbank10_writer_table_level_r = interface10_bank_bus_dat_w[8:0]; +assign csrbank10_writer_table_level_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 3'd6)); +assign csrbank10_writer_table_level_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 3'd6)); +assign csrbank10_writer_table_flush0_r = interface10_bank_bus_dat_w[0]; +assign csrbank10_writer_table_flush0_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 3'd7)); +assign csrbank10_writer_table_flush0_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 3'd7)); +assign csrbank10_reader_enable0_r = interface10_bank_bus_dat_w[0]; +assign csrbank10_reader_enable0_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 4'd8)); +assign csrbank10_reader_enable0_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 4'd8)); +assign csrbank10_reader_table_value1_r = interface10_bank_bus_dat_w[25:0]; +assign csrbank10_reader_table_value1_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 4'd9)); +assign csrbank10_reader_table_value1_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 4'd9)); +assign csrbank10_reader_table_value0_r = interface10_bank_bus_dat_w[31:0]; +assign csrbank10_reader_table_value0_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 4'd10)); +assign csrbank10_reader_table_value0_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 4'd10)); +assign csrbank10_reader_table_we0_r = interface10_bank_bus_dat_w[0]; +assign csrbank10_reader_table_we0_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 4'd11)); +assign csrbank10_reader_table_we0_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 4'd11)); +assign csrbank10_reader_table_loop_prog_n0_r = interface10_bank_bus_dat_w[0]; +assign csrbank10_reader_table_loop_prog_n0_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 4'd12)); +assign csrbank10_reader_table_loop_prog_n0_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 4'd12)); +assign csrbank10_reader_table_loop_status_r = interface10_bank_bus_dat_w[31:0]; +assign csrbank10_reader_table_loop_status_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 4'd13)); +assign csrbank10_reader_table_loop_status_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 4'd13)); +assign csrbank10_reader_table_level_r = interface10_bank_bus_dat_w[8:0]; +assign csrbank10_reader_table_level_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 4'd14)); +assign csrbank10_reader_table_level_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 4'd14)); +assign csrbank10_reader_table_flush0_r = interface10_bank_bus_dat_w[0]; +assign csrbank10_reader_table_flush0_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 4'd15)); +assign csrbank10_reader_table_flush0_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 4'd15)); +assign csrbank10_loopback_enable0_r = interface10_bank_bus_dat_w[0]; +assign csrbank10_loopback_enable0_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 5'd16)); +assign csrbank10_loopback_enable0_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 5'd16)); +assign csrbank10_buffering_reader_fifo_depth0_r = interface10_bank_bus_dat_w[10:0]; +assign csrbank10_buffering_reader_fifo_depth0_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 5'd17)); +assign csrbank10_buffering_reader_fifo_depth0_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 5'd17)); +assign csrbank10_buffering_reader_fifo_level_r = interface10_bank_bus_dat_w[10:0]; +assign csrbank10_buffering_reader_fifo_level_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 5'd18)); +assign csrbank10_buffering_reader_fifo_level_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 5'd18)); +assign csrbank10_buffering_writer_fifo_depth0_r = interface10_bank_bus_dat_w[10:0]; +assign csrbank10_buffering_writer_fifo_depth0_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 5'd19)); +assign csrbank10_buffering_writer_fifo_depth0_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 5'd19)); +assign csrbank10_buffering_writer_fifo_level_r = interface10_bank_bus_dat_w[10:0]; +assign csrbank10_buffering_writer_fifo_level_re = ((csrbank10_sel & interface10_bank_bus_we) & (interface10_bank_bus_adr[4:0] == 5'd20)); +assign csrbank10_buffering_writer_fifo_level_we = ((csrbank10_sel & (~interface10_bank_bus_we)) & (interface10_bank_bus_adr[4:0] == 5'd20)); +assign csrbank10_writer_enable0_w = pcie_dma0_writer_enable_storage; +assign pcie_dma0_writer_address = pcie_dma0_writer_value_storage[31:0]; +assign pcie_dma0_writer_length = pcie_dma0_writer_value_storage[55:32]; +assign pcie_dma0_writer_irq_disable = pcie_dma0_writer_value_storage[56]; +assign pcie_dma0_writer_last_disable = pcie_dma0_writer_value_storage[57]; +assign csrbank10_writer_table_value1_w = pcie_dma0_writer_value_storage[57:32]; +assign csrbank10_writer_table_value0_w = pcie_dma0_writer_value_storage[31:0]; +assign csrbank10_writer_table_we0_w = pcie_dma0_writer_we_storage; +assign csrbank10_writer_table_loop_prog_n0_w = pcie_dma0_writer_loop_prog_n_storage; +always @(*) begin + pcie_dma0_writer_loop_status_status <= 32'd0; + pcie_dma0_writer_loop_status_status[15:0] <= pcie_dma0_writer_index; + pcie_dma0_writer_loop_status_status[31:16] <= pcie_dma0_writer_count; +end +assign csrbank10_writer_table_loop_status_w = pcie_dma0_writer_loop_status_status[31:0]; +assign pcie_dma0_writer_loop_status_we = csrbank10_writer_table_loop_status_we; +assign pcie_dma0_writer_loop_status_re = csrbank10_writer_table_loop_status_re; +assign csrbank10_writer_table_level_w = pcie_dma0_writer_level_status[8:0]; +assign pcie_dma0_writer_level_we = csrbank10_writer_table_level_we; +assign pcie_dma0_writer_level_re = csrbank10_writer_table_level_re; +assign csrbank10_writer_table_flush0_w = pcie_dma0_writer_flush_storage; +assign csrbank10_reader_enable0_w = pcie_dma0_reader_enable_storage; +assign pcie_dma0_reader_address = pcie_dma0_reader_value_storage[31:0]; +assign pcie_dma0_reader_length = pcie_dma0_reader_value_storage[55:32]; +assign pcie_dma0_reader_irq_disable = pcie_dma0_reader_value_storage[56]; +assign pcie_dma0_reader_last_disable = pcie_dma0_reader_value_storage[57]; +assign csrbank10_reader_table_value1_w = pcie_dma0_reader_value_storage[57:32]; +assign csrbank10_reader_table_value0_w = pcie_dma0_reader_value_storage[31:0]; +assign csrbank10_reader_table_we0_w = pcie_dma0_reader_we_storage; +assign csrbank10_reader_table_loop_prog_n0_w = pcie_dma0_reader_loop_prog_n_storage; +always @(*) begin + pcie_dma0_reader_loop_status_status <= 32'd0; + pcie_dma0_reader_loop_status_status[15:0] <= pcie_dma0_reader_index; + pcie_dma0_reader_loop_status_status[31:16] <= pcie_dma0_reader_count; +end +assign csrbank10_reader_table_loop_status_w = pcie_dma0_reader_loop_status_status[31:0]; +assign pcie_dma0_reader_loop_status_we = csrbank10_reader_table_loop_status_we; +assign pcie_dma0_reader_loop_status_re = csrbank10_reader_table_loop_status_re; +assign csrbank10_reader_table_level_w = pcie_dma0_reader_level_status[8:0]; +assign pcie_dma0_reader_level_we = csrbank10_reader_table_level_we; +assign pcie_dma0_reader_level_re = csrbank10_reader_table_level_re; +assign csrbank10_reader_table_flush0_w = pcie_dma0_reader_flush_storage; +assign csrbank10_loopback_enable0_w = pcie_dma0_loopback_storage; +assign csrbank10_buffering_reader_fifo_depth0_w = pcie_dma0_buffering_reader_fifo_depth_storage[10:0]; +assign csrbank10_buffering_reader_fifo_level_w = pcie_dma0_buffering_reader_fifo_level_status[10:0]; +assign pcie_dma0_buffering_reader_fifo_level_we = csrbank10_buffering_reader_fifo_level_we; +assign pcie_dma0_buffering_reader_fifo_level_re = csrbank10_buffering_reader_fifo_level_re; +assign csrbank10_buffering_writer_fifo_depth0_w = pcie_dma0_buffering_writer_fifo_depth_storage[10:0]; +assign csrbank10_buffering_writer_fifo_level_w = pcie_dma0_buffering_writer_fifo_level_status[10:0]; +assign pcie_dma0_buffering_writer_fifo_level_we = csrbank10_buffering_writer_fifo_level_we; +assign pcie_dma0_buffering_writer_fifo_level_re = csrbank10_buffering_writer_fifo_level_re; +assign csrbank11_sel = (interface11_bank_bus_adr[13:9] == 5'd16); +assign csrbank11_writer_enable0_r = interface11_bank_bus_dat_w[0]; +assign csrbank11_writer_enable0_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 1'd0)); +assign csrbank11_writer_enable0_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 1'd0)); +assign csrbank11_writer_table_value1_r = interface11_bank_bus_dat_w[25:0]; +assign csrbank11_writer_table_value1_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 1'd1)); +assign csrbank11_writer_table_value1_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 1'd1)); +assign csrbank11_writer_table_value0_r = interface11_bank_bus_dat_w[31:0]; +assign csrbank11_writer_table_value0_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 2'd2)); +assign csrbank11_writer_table_value0_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 2'd2)); +assign csrbank11_writer_table_we0_r = interface11_bank_bus_dat_w[0]; +assign csrbank11_writer_table_we0_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 2'd3)); +assign csrbank11_writer_table_we0_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 2'd3)); +assign csrbank11_writer_table_loop_prog_n0_r = interface11_bank_bus_dat_w[0]; +assign csrbank11_writer_table_loop_prog_n0_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 3'd4)); +assign csrbank11_writer_table_loop_prog_n0_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 3'd4)); +assign csrbank11_writer_table_loop_status_r = interface11_bank_bus_dat_w[31:0]; +assign csrbank11_writer_table_loop_status_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 3'd5)); +assign csrbank11_writer_table_loop_status_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 3'd5)); +assign csrbank11_writer_table_level_r = interface11_bank_bus_dat_w[8:0]; +assign csrbank11_writer_table_level_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 3'd6)); +assign csrbank11_writer_table_level_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 3'd6)); +assign csrbank11_writer_table_flush0_r = interface11_bank_bus_dat_w[0]; +assign csrbank11_writer_table_flush0_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 3'd7)); +assign csrbank11_writer_table_flush0_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 3'd7)); +assign csrbank11_reader_enable0_r = interface11_bank_bus_dat_w[0]; +assign csrbank11_reader_enable0_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 4'd8)); +assign csrbank11_reader_enable0_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 4'd8)); +assign csrbank11_reader_table_value1_r = interface11_bank_bus_dat_w[25:0]; +assign csrbank11_reader_table_value1_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 4'd9)); +assign csrbank11_reader_table_value1_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 4'd9)); +assign csrbank11_reader_table_value0_r = interface11_bank_bus_dat_w[31:0]; +assign csrbank11_reader_table_value0_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 4'd10)); +assign csrbank11_reader_table_value0_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 4'd10)); +assign csrbank11_reader_table_we0_r = interface11_bank_bus_dat_w[0]; +assign csrbank11_reader_table_we0_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 4'd11)); +assign csrbank11_reader_table_we0_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 4'd11)); +assign csrbank11_reader_table_loop_prog_n0_r = interface11_bank_bus_dat_w[0]; +assign csrbank11_reader_table_loop_prog_n0_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 4'd12)); +assign csrbank11_reader_table_loop_prog_n0_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 4'd12)); +assign csrbank11_reader_table_loop_status_r = interface11_bank_bus_dat_w[31:0]; +assign csrbank11_reader_table_loop_status_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 4'd13)); +assign csrbank11_reader_table_loop_status_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 4'd13)); +assign csrbank11_reader_table_level_r = interface11_bank_bus_dat_w[8:0]; +assign csrbank11_reader_table_level_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 4'd14)); +assign csrbank11_reader_table_level_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 4'd14)); +assign csrbank11_reader_table_flush0_r = interface11_bank_bus_dat_w[0]; +assign csrbank11_reader_table_flush0_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 4'd15)); +assign csrbank11_reader_table_flush0_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 4'd15)); +assign csrbank11_loopback_enable0_r = interface11_bank_bus_dat_w[0]; +assign csrbank11_loopback_enable0_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 5'd16)); +assign csrbank11_loopback_enable0_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 5'd16)); +assign csrbank11_buffering_reader_fifo_depth0_r = interface11_bank_bus_dat_w[10:0]; +assign csrbank11_buffering_reader_fifo_depth0_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 5'd17)); +assign csrbank11_buffering_reader_fifo_depth0_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 5'd17)); +assign csrbank11_buffering_reader_fifo_level_r = interface11_bank_bus_dat_w[10:0]; +assign csrbank11_buffering_reader_fifo_level_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 5'd18)); +assign csrbank11_buffering_reader_fifo_level_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 5'd18)); +assign csrbank11_buffering_writer_fifo_depth0_r = interface11_bank_bus_dat_w[10:0]; +assign csrbank11_buffering_writer_fifo_depth0_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 5'd19)); +assign csrbank11_buffering_writer_fifo_depth0_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 5'd19)); +assign csrbank11_buffering_writer_fifo_level_r = interface11_bank_bus_dat_w[10:0]; +assign csrbank11_buffering_writer_fifo_level_re = ((csrbank11_sel & interface11_bank_bus_we) & (interface11_bank_bus_adr[4:0] == 5'd20)); +assign csrbank11_buffering_writer_fifo_level_we = ((csrbank11_sel & (~interface11_bank_bus_we)) & (interface11_bank_bus_adr[4:0] == 5'd20)); +assign csrbank11_writer_enable0_w = pcie_dma1_writer_enable_storage; +assign pcie_dma1_writer_address = pcie_dma1_writer_value_storage[31:0]; +assign pcie_dma1_writer_length = pcie_dma1_writer_value_storage[55:32]; +assign pcie_dma1_writer_irq_disable = pcie_dma1_writer_value_storage[56]; +assign pcie_dma1_writer_last_disable = pcie_dma1_writer_value_storage[57]; +assign csrbank11_writer_table_value1_w = pcie_dma1_writer_value_storage[57:32]; +assign csrbank11_writer_table_value0_w = pcie_dma1_writer_value_storage[31:0]; +assign csrbank11_writer_table_we0_w = pcie_dma1_writer_we_storage; +assign csrbank11_writer_table_loop_prog_n0_w = pcie_dma1_writer_loop_prog_n_storage; +always @(*) begin + pcie_dma1_writer_loop_status_status <= 32'd0; + pcie_dma1_writer_loop_status_status[15:0] <= pcie_dma1_writer_index; + pcie_dma1_writer_loop_status_status[31:16] <= pcie_dma1_writer_count; +end +assign csrbank11_writer_table_loop_status_w = pcie_dma1_writer_loop_status_status[31:0]; +assign pcie_dma1_writer_loop_status_we = csrbank11_writer_table_loop_status_we; +assign pcie_dma1_writer_loop_status_re = csrbank11_writer_table_loop_status_re; +assign csrbank11_writer_table_level_w = pcie_dma1_writer_level_status[8:0]; +assign pcie_dma1_writer_level_we = csrbank11_writer_table_level_we; +assign pcie_dma1_writer_level_re = csrbank11_writer_table_level_re; +assign csrbank11_writer_table_flush0_w = pcie_dma1_writer_flush_storage; +assign csrbank11_reader_enable0_w = pcie_dma1_reader_enable_storage; +assign pcie_dma1_reader_address = pcie_dma1_reader_value_storage[31:0]; +assign pcie_dma1_reader_length = pcie_dma1_reader_value_storage[55:32]; +assign pcie_dma1_reader_irq_disable = pcie_dma1_reader_value_storage[56]; +assign pcie_dma1_reader_last_disable = pcie_dma1_reader_value_storage[57]; +assign csrbank11_reader_table_value1_w = pcie_dma1_reader_value_storage[57:32]; +assign csrbank11_reader_table_value0_w = pcie_dma1_reader_value_storage[31:0]; +assign csrbank11_reader_table_we0_w = pcie_dma1_reader_we_storage; +assign csrbank11_reader_table_loop_prog_n0_w = pcie_dma1_reader_loop_prog_n_storage; +always @(*) begin + pcie_dma1_reader_loop_status_status <= 32'd0; + pcie_dma1_reader_loop_status_status[15:0] <= pcie_dma1_reader_index; + pcie_dma1_reader_loop_status_status[31:16] <= pcie_dma1_reader_count; +end +assign csrbank11_reader_table_loop_status_w = pcie_dma1_reader_loop_status_status[31:0]; +assign pcie_dma1_reader_loop_status_we = csrbank11_reader_table_loop_status_we; +assign pcie_dma1_reader_loop_status_re = csrbank11_reader_table_loop_status_re; +assign csrbank11_reader_table_level_w = pcie_dma1_reader_level_status[8:0]; +assign pcie_dma1_reader_level_we = csrbank11_reader_table_level_we; +assign pcie_dma1_reader_level_re = csrbank11_reader_table_level_re; +assign csrbank11_reader_table_flush0_w = pcie_dma1_reader_flush_storage; +assign csrbank11_loopback_enable0_w = pcie_dma1_loopback_storage; +assign csrbank11_buffering_reader_fifo_depth0_w = pcie_dma1_buffering_reader_fifo_depth_storage[10:0]; +assign csrbank11_buffering_reader_fifo_level_w = pcie_dma1_buffering_reader_fifo_level_status[10:0]; +assign pcie_dma1_buffering_reader_fifo_level_we = csrbank11_buffering_reader_fifo_level_we; +assign pcie_dma1_buffering_reader_fifo_level_re = csrbank11_buffering_reader_fifo_level_re; +assign csrbank11_buffering_writer_fifo_depth0_w = pcie_dma1_buffering_writer_fifo_depth_storage[10:0]; +assign csrbank11_buffering_writer_fifo_level_w = pcie_dma1_buffering_writer_fifo_level_status[10:0]; +assign pcie_dma1_buffering_writer_fifo_level_we = csrbank11_buffering_writer_fifo_level_we; +assign pcie_dma1_buffering_writer_fifo_level_re = csrbank11_buffering_writer_fifo_level_re; +assign csrbank12_sel = (interface12_bank_bus_adr[13:9] == 5'd17); +assign csrbank12_enable0_r = interface12_bank_bus_dat_w[31:0]; +assign csrbank12_enable0_re = ((csrbank12_sel & interface12_bank_bus_we) & (interface12_bank_bus_adr[1:0] == 1'd0)); +assign csrbank12_enable0_we = ((csrbank12_sel & (~interface12_bank_bus_we)) & (interface12_bank_bus_adr[1:0] == 1'd0)); +assign csrbank12_clear0_r = interface12_bank_bus_dat_w[31:0]; +assign csrbank12_clear0_re = ((csrbank12_sel & interface12_bank_bus_we) & (interface12_bank_bus_adr[1:0] == 1'd1)); +assign csrbank12_clear0_we = ((csrbank12_sel & (~interface12_bank_bus_we)) & (interface12_bank_bus_adr[1:0] == 1'd1)); +assign csrbank12_vector_r = interface12_bank_bus_dat_w[31:0]; +assign csrbank12_vector_re = ((csrbank12_sel & interface12_bank_bus_we) & (interface12_bank_bus_adr[1:0] == 2'd2)); +assign csrbank12_vector_we = ((csrbank12_sel & (~interface12_bank_bus_we)) & (interface12_bank_bus_adr[1:0] == 2'd2)); +assign csrbank12_enable0_w = pcie_msi_enable_storage[31:0]; +assign csrbank12_clear0_w = pcie_msi_clear_storage[31:0]; +assign csrbank12_vector_w = pcie_msi_vector_status[31:0]; +assign pcie_msi_vector_we = csrbank12_vector_we; +assign pcie_msi_vector_re = csrbank12_vector_re; +assign csrbank13_sel = (interface13_bank_bus_adr[13:9] == 4'd14); +assign csrbank13_link_status_r = interface13_bank_bus_dat_w[9:0]; +assign csrbank13_link_status_re = ((csrbank13_sel & interface13_bank_bus_we) & (interface13_bank_bus_adr[2:0] == 1'd0)); +assign csrbank13_link_status_we = ((csrbank13_sel & (~interface13_bank_bus_we)) & (interface13_bank_bus_adr[2:0] == 1'd0)); +assign csrbank13_msi_enable_r = interface13_bank_bus_dat_w[0]; +assign csrbank13_msi_enable_re = ((csrbank13_sel & interface13_bank_bus_we) & (interface13_bank_bus_adr[2:0] == 1'd1)); +assign csrbank13_msi_enable_we = ((csrbank13_sel & (~interface13_bank_bus_we)) & (interface13_bank_bus_adr[2:0] == 1'd1)); +assign csrbank13_msix_enable_r = interface13_bank_bus_dat_w[0]; +assign csrbank13_msix_enable_re = ((csrbank13_sel & interface13_bank_bus_we) & (interface13_bank_bus_adr[2:0] == 2'd2)); +assign csrbank13_msix_enable_we = ((csrbank13_sel & (~interface13_bank_bus_we)) & (interface13_bank_bus_adr[2:0] == 2'd2)); +assign csrbank13_bus_master_enable_r = interface13_bank_bus_dat_w[0]; +assign csrbank13_bus_master_enable_re = ((csrbank13_sel & interface13_bank_bus_we) & (interface13_bank_bus_adr[2:0] == 2'd3)); +assign csrbank13_bus_master_enable_we = ((csrbank13_sel & (~interface13_bank_bus_we)) & (interface13_bank_bus_adr[2:0] == 2'd3)); +assign csrbank13_max_request_size_r = interface13_bank_bus_dat_w[15:0]; +assign csrbank13_max_request_size_re = ((csrbank13_sel & interface13_bank_bus_we) & (interface13_bank_bus_adr[2:0] == 3'd4)); +assign csrbank13_max_request_size_we = ((csrbank13_sel & (~interface13_bank_bus_we)) & (interface13_bank_bus_adr[2:0] == 3'd4)); +assign csrbank13_max_payload_size_r = interface13_bank_bus_dat_w[15:0]; +assign csrbank13_max_payload_size_re = ((csrbank13_sel & interface13_bank_bus_we) & (interface13_bank_bus_adr[2:0] == 3'd5)); +assign csrbank13_max_payload_size_we = ((csrbank13_sel & (~interface13_bank_bus_we)) & (interface13_bank_bus_adr[2:0] == 3'd5)); +always @(*) begin + s7pciephy_link_status_status <= 10'd0; + s7pciephy_link_status_status[0] <= s7pciephy_csrfield_status; + s7pciephy_link_status_status[1] <= s7pciephy_csrfield_rate; + s7pciephy_link_status_status[3:2] <= s7pciephy_csrfield_width; + s7pciephy_link_status_status[9:4] <= s7pciephy_csrfield_ltssm; +end +assign csrbank13_link_status_w = s7pciephy_link_status_status[9:0]; +assign s7pciephy_link_status_we = csrbank13_link_status_we; +assign s7pciephy_link_status_re = csrbank13_link_status_re; +assign csrbank13_msi_enable_w = s7pciephy_msi_enable_status; +assign s7pciephy_msi_enable_we = csrbank13_msi_enable_we; +assign s7pciephy_msi_enable_re = csrbank13_msi_enable_re; +assign csrbank13_msix_enable_w = s7pciephy_msix_enable_status; +assign s7pciephy_msix_enable_we = csrbank13_msix_enable_we; +assign s7pciephy_msix_enable_re = csrbank13_msix_enable_re; +assign csrbank13_bus_master_enable_w = s7pciephy_bus_master_enable_status; +assign s7pciephy_bus_master_enable_we = csrbank13_bus_master_enable_we; +assign s7pciephy_bus_master_enable_re = csrbank13_bus_master_enable_re; +assign csrbank13_max_request_size_w = s7pciephy_max_request_size_status[15:0]; +assign s7pciephy_max_request_size_we = csrbank13_max_request_size_we; +assign s7pciephy_max_request_size_re = csrbank13_max_request_size_re; +assign csrbank13_max_payload_size_w = s7pciephy_max_payload_size_status[15:0]; +assign s7pciephy_max_payload_size_we = csrbank13_max_payload_size_we; +assign s7pciephy_max_payload_size_re = csrbank13_max_payload_size_re; +assign csrbank14_sel = (interface14_bank_bus_adr[13:9] == 4'd12); +assign csrbank14_dfii_control0_r = interface14_bank_bus_dat_w[3:0]; +assign csrbank14_dfii_control0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 1'd0)); +assign csrbank14_dfii_control0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 1'd0)); +assign csrbank14_dfii_pi0_command0_r = interface14_bank_bus_dat_w[5:0]; +assign csrbank14_dfii_pi0_command0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 1'd1)); +assign csrbank14_dfii_pi0_command0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 1'd1)); +assign netv2_sdram_phaseinjector0_command_issue_r = interface14_bank_bus_dat_w[0]; +assign netv2_sdram_phaseinjector0_command_issue_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 2'd2)); +assign netv2_sdram_phaseinjector0_command_issue_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 2'd2)); +assign csrbank14_dfii_pi0_address0_r = interface14_bank_bus_dat_w[13:0]; +assign csrbank14_dfii_pi0_address0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 2'd3)); +assign csrbank14_dfii_pi0_address0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 2'd3)); +assign csrbank14_dfii_pi0_baddress0_r = interface14_bank_bus_dat_w[2:0]; +assign csrbank14_dfii_pi0_baddress0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 3'd4)); +assign csrbank14_dfii_pi0_baddress0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 3'd4)); +assign csrbank14_dfii_pi0_wrdata1_r = interface14_bank_bus_dat_w[31:0]; +assign csrbank14_dfii_pi0_wrdata1_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 3'd5)); +assign csrbank14_dfii_pi0_wrdata1_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 3'd5)); +assign csrbank14_dfii_pi0_wrdata0_r = interface14_bank_bus_dat_w[31:0]; +assign csrbank14_dfii_pi0_wrdata0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 3'd6)); +assign csrbank14_dfii_pi0_wrdata0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 3'd6)); +assign csrbank14_dfii_pi0_rddata1_r = interface14_bank_bus_dat_w[31:0]; +assign csrbank14_dfii_pi0_rddata1_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 3'd7)); +assign csrbank14_dfii_pi0_rddata1_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 3'd7)); +assign csrbank14_dfii_pi0_rddata0_r = interface14_bank_bus_dat_w[31:0]; +assign csrbank14_dfii_pi0_rddata0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 4'd8)); +assign csrbank14_dfii_pi0_rddata0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 4'd8)); +assign csrbank14_dfii_pi1_command0_r = interface14_bank_bus_dat_w[5:0]; +assign csrbank14_dfii_pi1_command0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 4'd9)); +assign csrbank14_dfii_pi1_command0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 4'd9)); +assign netv2_sdram_phaseinjector1_command_issue_r = interface14_bank_bus_dat_w[0]; +assign netv2_sdram_phaseinjector1_command_issue_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 4'd10)); +assign netv2_sdram_phaseinjector1_command_issue_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 4'd10)); +assign csrbank14_dfii_pi1_address0_r = interface14_bank_bus_dat_w[13:0]; +assign csrbank14_dfii_pi1_address0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 4'd11)); +assign csrbank14_dfii_pi1_address0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 4'd11)); +assign csrbank14_dfii_pi1_baddress0_r = interface14_bank_bus_dat_w[2:0]; +assign csrbank14_dfii_pi1_baddress0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 4'd12)); +assign csrbank14_dfii_pi1_baddress0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 4'd12)); +assign csrbank14_dfii_pi1_wrdata1_r = interface14_bank_bus_dat_w[31:0]; +assign csrbank14_dfii_pi1_wrdata1_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 4'd13)); +assign csrbank14_dfii_pi1_wrdata1_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 4'd13)); +assign csrbank14_dfii_pi1_wrdata0_r = interface14_bank_bus_dat_w[31:0]; +assign csrbank14_dfii_pi1_wrdata0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 4'd14)); +assign csrbank14_dfii_pi1_wrdata0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 4'd14)); +assign csrbank14_dfii_pi1_rddata1_r = interface14_bank_bus_dat_w[31:0]; +assign csrbank14_dfii_pi1_rddata1_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 4'd15)); +assign csrbank14_dfii_pi1_rddata1_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 4'd15)); +assign csrbank14_dfii_pi1_rddata0_r = interface14_bank_bus_dat_w[31:0]; +assign csrbank14_dfii_pi1_rddata0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 5'd16)); +assign csrbank14_dfii_pi1_rddata0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 5'd16)); +assign csrbank14_dfii_pi2_command0_r = interface14_bank_bus_dat_w[5:0]; +assign csrbank14_dfii_pi2_command0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 5'd17)); +assign csrbank14_dfii_pi2_command0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 5'd17)); +assign netv2_sdram_phaseinjector2_command_issue_r = interface14_bank_bus_dat_w[0]; +assign netv2_sdram_phaseinjector2_command_issue_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 5'd18)); +assign netv2_sdram_phaseinjector2_command_issue_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 5'd18)); +assign csrbank14_dfii_pi2_address0_r = interface14_bank_bus_dat_w[13:0]; +assign csrbank14_dfii_pi2_address0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 5'd19)); +assign csrbank14_dfii_pi2_address0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 5'd19)); +assign csrbank14_dfii_pi2_baddress0_r = interface14_bank_bus_dat_w[2:0]; +assign csrbank14_dfii_pi2_baddress0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 5'd20)); +assign csrbank14_dfii_pi2_baddress0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 5'd20)); +assign csrbank14_dfii_pi2_wrdata1_r = interface14_bank_bus_dat_w[31:0]; +assign csrbank14_dfii_pi2_wrdata1_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 5'd21)); +assign csrbank14_dfii_pi2_wrdata1_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 5'd21)); +assign csrbank14_dfii_pi2_wrdata0_r = interface14_bank_bus_dat_w[31:0]; +assign csrbank14_dfii_pi2_wrdata0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 5'd22)); +assign csrbank14_dfii_pi2_wrdata0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 5'd22)); +assign csrbank14_dfii_pi2_rddata1_r = interface14_bank_bus_dat_w[31:0]; +assign csrbank14_dfii_pi2_rddata1_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 5'd23)); +assign csrbank14_dfii_pi2_rddata1_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 5'd23)); +assign csrbank14_dfii_pi2_rddata0_r = interface14_bank_bus_dat_w[31:0]; +assign csrbank14_dfii_pi2_rddata0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 5'd24)); +assign csrbank14_dfii_pi2_rddata0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 5'd24)); +assign csrbank14_dfii_pi3_command0_r = interface14_bank_bus_dat_w[5:0]; +assign csrbank14_dfii_pi3_command0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 5'd25)); +assign csrbank14_dfii_pi3_command0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 5'd25)); +assign netv2_sdram_phaseinjector3_command_issue_r = interface14_bank_bus_dat_w[0]; +assign netv2_sdram_phaseinjector3_command_issue_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 5'd26)); +assign netv2_sdram_phaseinjector3_command_issue_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 5'd26)); +assign csrbank14_dfii_pi3_address0_r = interface14_bank_bus_dat_w[13:0]; +assign csrbank14_dfii_pi3_address0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 5'd27)); +assign csrbank14_dfii_pi3_address0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 5'd27)); +assign csrbank14_dfii_pi3_baddress0_r = interface14_bank_bus_dat_w[2:0]; +assign csrbank14_dfii_pi3_baddress0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 5'd28)); +assign csrbank14_dfii_pi3_baddress0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 5'd28)); +assign csrbank14_dfii_pi3_wrdata1_r = interface14_bank_bus_dat_w[31:0]; +assign csrbank14_dfii_pi3_wrdata1_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 5'd29)); +assign csrbank14_dfii_pi3_wrdata1_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 5'd29)); +assign csrbank14_dfii_pi3_wrdata0_r = interface14_bank_bus_dat_w[31:0]; +assign csrbank14_dfii_pi3_wrdata0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 5'd30)); +assign csrbank14_dfii_pi3_wrdata0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 5'd30)); +assign csrbank14_dfii_pi3_rddata1_r = interface14_bank_bus_dat_w[31:0]; +assign csrbank14_dfii_pi3_rddata1_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 5'd31)); +assign csrbank14_dfii_pi3_rddata1_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 5'd31)); +assign csrbank14_dfii_pi3_rddata0_r = interface14_bank_bus_dat_w[31:0]; +assign csrbank14_dfii_pi3_rddata0_re = ((csrbank14_sel & interface14_bank_bus_we) & (interface14_bank_bus_adr[5:0] == 6'd32)); +assign csrbank14_dfii_pi3_rddata0_we = ((csrbank14_sel & (~interface14_bank_bus_we)) & (interface14_bank_bus_adr[5:0] == 6'd32)); +assign netv2_sdram_sel = netv2_sdram_storage[0]; +assign netv2_sdram_cke = netv2_sdram_storage[1]; +assign netv2_sdram_odt = netv2_sdram_storage[2]; +assign netv2_sdram_reset_n = netv2_sdram_storage[3]; +assign csrbank14_dfii_control0_w = netv2_sdram_storage[3:0]; +assign csrbank14_dfii_pi0_command0_w = netv2_sdram_phaseinjector0_command_storage[5:0]; +assign csrbank14_dfii_pi0_address0_w = netv2_sdram_phaseinjector0_address_storage[13:0]; +assign csrbank14_dfii_pi0_baddress0_w = netv2_sdram_phaseinjector0_baddress_storage[2:0]; +assign csrbank14_dfii_pi0_wrdata1_w = netv2_sdram_phaseinjector0_wrdata_storage[63:32]; +assign csrbank14_dfii_pi0_wrdata0_w = netv2_sdram_phaseinjector0_wrdata_storage[31:0]; +assign csrbank14_dfii_pi0_rddata1_w = netv2_sdram_phaseinjector0_rddata_status[63:32]; +assign csrbank14_dfii_pi0_rddata0_w = netv2_sdram_phaseinjector0_rddata_status[31:0]; +assign netv2_sdram_phaseinjector0_rddata_we = csrbank14_dfii_pi0_rddata0_we; +assign netv2_sdram_phaseinjector0_rddata_re = csrbank14_dfii_pi0_rddata0_re; +assign csrbank14_dfii_pi1_command0_w = netv2_sdram_phaseinjector1_command_storage[5:0]; +assign csrbank14_dfii_pi1_address0_w = netv2_sdram_phaseinjector1_address_storage[13:0]; +assign csrbank14_dfii_pi1_baddress0_w = netv2_sdram_phaseinjector1_baddress_storage[2:0]; +assign csrbank14_dfii_pi1_wrdata1_w = netv2_sdram_phaseinjector1_wrdata_storage[63:32]; +assign csrbank14_dfii_pi1_wrdata0_w = netv2_sdram_phaseinjector1_wrdata_storage[31:0]; +assign csrbank14_dfii_pi1_rddata1_w = netv2_sdram_phaseinjector1_rddata_status[63:32]; +assign csrbank14_dfii_pi1_rddata0_w = netv2_sdram_phaseinjector1_rddata_status[31:0]; +assign netv2_sdram_phaseinjector1_rddata_we = csrbank14_dfii_pi1_rddata0_we; +assign netv2_sdram_phaseinjector1_rddata_re = csrbank14_dfii_pi1_rddata0_re; +assign csrbank14_dfii_pi2_command0_w = netv2_sdram_phaseinjector2_command_storage[5:0]; +assign csrbank14_dfii_pi2_address0_w = netv2_sdram_phaseinjector2_address_storage[13:0]; +assign csrbank14_dfii_pi2_baddress0_w = netv2_sdram_phaseinjector2_baddress_storage[2:0]; +assign csrbank14_dfii_pi2_wrdata1_w = netv2_sdram_phaseinjector2_wrdata_storage[63:32]; +assign csrbank14_dfii_pi2_wrdata0_w = netv2_sdram_phaseinjector2_wrdata_storage[31:0]; +assign csrbank14_dfii_pi2_rddata1_w = netv2_sdram_phaseinjector2_rddata_status[63:32]; +assign csrbank14_dfii_pi2_rddata0_w = netv2_sdram_phaseinjector2_rddata_status[31:0]; +assign netv2_sdram_phaseinjector2_rddata_we = csrbank14_dfii_pi2_rddata0_we; +assign netv2_sdram_phaseinjector2_rddata_re = csrbank14_dfii_pi2_rddata0_re; +assign csrbank14_dfii_pi3_command0_w = netv2_sdram_phaseinjector3_command_storage[5:0]; +assign csrbank14_dfii_pi3_address0_w = netv2_sdram_phaseinjector3_address_storage[13:0]; +assign csrbank14_dfii_pi3_baddress0_w = netv2_sdram_phaseinjector3_baddress_storage[2:0]; +assign csrbank14_dfii_pi3_wrdata1_w = netv2_sdram_phaseinjector3_wrdata_storage[63:32]; +assign csrbank14_dfii_pi3_wrdata0_w = netv2_sdram_phaseinjector3_wrdata_storage[31:0]; +assign csrbank14_dfii_pi3_rddata1_w = netv2_sdram_phaseinjector3_rddata_status[63:32]; +assign csrbank14_dfii_pi3_rddata0_w = netv2_sdram_phaseinjector3_rddata_status[31:0]; +assign netv2_sdram_phaseinjector3_rddata_we = csrbank14_dfii_pi3_rddata0_we; +assign netv2_sdram_phaseinjector3_rddata_re = csrbank14_dfii_pi3_rddata0_re; +assign csrbank15_sel = (interface15_bank_bus_adr[13:9] == 3'd5); +assign csrbank15_load0_r = interface15_bank_bus_dat_w[31:0]; +assign csrbank15_load0_re = ((csrbank15_sel & interface15_bank_bus_we) & (interface15_bank_bus_adr[2:0] == 1'd0)); +assign csrbank15_load0_we = ((csrbank15_sel & (~interface15_bank_bus_we)) & (interface15_bank_bus_adr[2:0] == 1'd0)); +assign csrbank15_reload0_r = interface15_bank_bus_dat_w[31:0]; +assign csrbank15_reload0_re = ((csrbank15_sel & interface15_bank_bus_we) & (interface15_bank_bus_adr[2:0] == 1'd1)); +assign csrbank15_reload0_we = ((csrbank15_sel & (~interface15_bank_bus_we)) & (interface15_bank_bus_adr[2:0] == 1'd1)); +assign csrbank15_en0_r = interface15_bank_bus_dat_w[0]; +assign csrbank15_en0_re = ((csrbank15_sel & interface15_bank_bus_we) & (interface15_bank_bus_adr[2:0] == 2'd2)); +assign csrbank15_en0_we = ((csrbank15_sel & (~interface15_bank_bus_we)) & (interface15_bank_bus_adr[2:0] == 2'd2)); +assign csrbank15_update_value0_r = interface15_bank_bus_dat_w[0]; +assign csrbank15_update_value0_re = ((csrbank15_sel & interface15_bank_bus_we) & (interface15_bank_bus_adr[2:0] == 2'd3)); +assign csrbank15_update_value0_we = ((csrbank15_sel & (~interface15_bank_bus_we)) & (interface15_bank_bus_adr[2:0] == 2'd3)); +assign csrbank15_value_r = interface15_bank_bus_dat_w[31:0]; +assign csrbank15_value_re = ((csrbank15_sel & interface15_bank_bus_we) & (interface15_bank_bus_adr[2:0] == 3'd4)); +assign csrbank15_value_we = ((csrbank15_sel & (~interface15_bank_bus_we)) & (interface15_bank_bus_adr[2:0] == 3'd4)); +assign netv2_eventmanager_status_r = interface15_bank_bus_dat_w[0]; +assign netv2_eventmanager_status_re = ((csrbank15_sel & interface15_bank_bus_we) & (interface15_bank_bus_adr[2:0] == 3'd5)); +assign netv2_eventmanager_status_we = ((csrbank15_sel & (~interface15_bank_bus_we)) & (interface15_bank_bus_adr[2:0] == 3'd5)); +assign netv2_eventmanager_pending_r = interface15_bank_bus_dat_w[0]; +assign netv2_eventmanager_pending_re = ((csrbank15_sel & interface15_bank_bus_we) & (interface15_bank_bus_adr[2:0] == 3'd6)); +assign netv2_eventmanager_pending_we = ((csrbank15_sel & (~interface15_bank_bus_we)) & (interface15_bank_bus_adr[2:0] == 3'd6)); +assign csrbank15_ev_enable0_r = interface15_bank_bus_dat_w[0]; +assign csrbank15_ev_enable0_re = ((csrbank15_sel & interface15_bank_bus_we) & (interface15_bank_bus_adr[2:0] == 3'd7)); +assign csrbank15_ev_enable0_we = ((csrbank15_sel & (~interface15_bank_bus_we)) & (interface15_bank_bus_adr[2:0] == 3'd7)); +assign csrbank15_load0_w = netv2_load_storage[31:0]; +assign csrbank15_reload0_w = netv2_reload_storage[31:0]; +assign csrbank15_en0_w = netv2_en_storage; +assign csrbank15_update_value0_w = netv2_update_value_storage; +assign csrbank15_value_w = netv2_value_status[31:0]; +assign netv2_value_we = csrbank15_value_we; +assign netv2_value_re = csrbank15_value_re; +assign csrbank15_ev_enable0_w = netv2_eventmanager_storage; +assign csrbank16_sel = (interface16_bank_bus_adr[13:9] == 3'd4); +assign netv2_uartcrossover_rxtx_r = interface16_bank_bus_dat_w[7:0]; +assign netv2_uartcrossover_rxtx_re = ((csrbank16_sel & interface16_bank_bus_we) & (interface16_bank_bus_adr[3:0] == 1'd0)); +assign netv2_uartcrossover_rxtx_we = ((csrbank16_sel & (~interface16_bank_bus_we)) & (interface16_bank_bus_adr[3:0] == 1'd0)); +assign csrbank16_txfull_r = interface16_bank_bus_dat_w[0]; +assign csrbank16_txfull_re = ((csrbank16_sel & interface16_bank_bus_we) & (interface16_bank_bus_adr[3:0] == 1'd1)); +assign csrbank16_txfull_we = ((csrbank16_sel & (~interface16_bank_bus_we)) & (interface16_bank_bus_adr[3:0] == 1'd1)); +assign csrbank16_rxempty_r = interface16_bank_bus_dat_w[0]; +assign csrbank16_rxempty_re = ((csrbank16_sel & interface16_bank_bus_we) & (interface16_bank_bus_adr[3:0] == 2'd2)); +assign csrbank16_rxempty_we = ((csrbank16_sel & (~interface16_bank_bus_we)) & (interface16_bank_bus_adr[3:0] == 2'd2)); +assign netv2_uartcrossover_eventmanager_status_r = interface16_bank_bus_dat_w[1:0]; +assign netv2_uartcrossover_eventmanager_status_re = ((csrbank16_sel & interface16_bank_bus_we) & (interface16_bank_bus_adr[3:0] == 2'd3)); +assign netv2_uartcrossover_eventmanager_status_we = ((csrbank16_sel & (~interface16_bank_bus_we)) & (interface16_bank_bus_adr[3:0] == 2'd3)); +assign netv2_uartcrossover_eventmanager_pending_r = interface16_bank_bus_dat_w[1:0]; +assign netv2_uartcrossover_eventmanager_pending_re = ((csrbank16_sel & interface16_bank_bus_we) & (interface16_bank_bus_adr[3:0] == 3'd4)); +assign netv2_uartcrossover_eventmanager_pending_we = ((csrbank16_sel & (~interface16_bank_bus_we)) & (interface16_bank_bus_adr[3:0] == 3'd4)); +assign csrbank16_ev_enable0_r = interface16_bank_bus_dat_w[1:0]; +assign csrbank16_ev_enable0_re = ((csrbank16_sel & interface16_bank_bus_we) & (interface16_bank_bus_adr[3:0] == 3'd5)); +assign csrbank16_ev_enable0_we = ((csrbank16_sel & (~interface16_bank_bus_we)) & (interface16_bank_bus_adr[3:0] == 3'd5)); +assign csrbank16_txempty_r = interface16_bank_bus_dat_w[0]; +assign csrbank16_txempty_re = ((csrbank16_sel & interface16_bank_bus_we) & (interface16_bank_bus_adr[3:0] == 3'd6)); +assign csrbank16_txempty_we = ((csrbank16_sel & (~interface16_bank_bus_we)) & (interface16_bank_bus_adr[3:0] == 3'd6)); +assign csrbank16_rxfull_r = interface16_bank_bus_dat_w[0]; +assign csrbank16_rxfull_re = ((csrbank16_sel & interface16_bank_bus_we) & (interface16_bank_bus_adr[3:0] == 3'd7)); +assign csrbank16_rxfull_we = ((csrbank16_sel & (~interface16_bank_bus_we)) & (interface16_bank_bus_adr[3:0] == 3'd7)); +assign netv2_xover_rxtx_r = interface16_bank_bus_dat_w[7:0]; +assign netv2_xover_rxtx_re = ((csrbank16_sel & interface16_bank_bus_we) & (interface16_bank_bus_adr[3:0] == 4'd8)); +assign netv2_xover_rxtx_we = ((csrbank16_sel & (~interface16_bank_bus_we)) & (interface16_bank_bus_adr[3:0] == 4'd8)); +assign csrbank16_xover_txfull_r = interface16_bank_bus_dat_w[0]; +assign csrbank16_xover_txfull_re = ((csrbank16_sel & interface16_bank_bus_we) & (interface16_bank_bus_adr[3:0] == 4'd9)); +assign csrbank16_xover_txfull_we = ((csrbank16_sel & (~interface16_bank_bus_we)) & (interface16_bank_bus_adr[3:0] == 4'd9)); +assign csrbank16_xover_rxempty_r = interface16_bank_bus_dat_w[0]; +assign csrbank16_xover_rxempty_re = ((csrbank16_sel & interface16_bank_bus_we) & (interface16_bank_bus_adr[3:0] == 4'd10)); +assign csrbank16_xover_rxempty_we = ((csrbank16_sel & (~interface16_bank_bus_we)) & (interface16_bank_bus_adr[3:0] == 4'd10)); +assign netv2_xover_eventmanager_status_r = interface16_bank_bus_dat_w[1:0]; +assign netv2_xover_eventmanager_status_re = ((csrbank16_sel & interface16_bank_bus_we) & (interface16_bank_bus_adr[3:0] == 4'd11)); +assign netv2_xover_eventmanager_status_we = ((csrbank16_sel & (~interface16_bank_bus_we)) & (interface16_bank_bus_adr[3:0] == 4'd11)); +assign netv2_xover_eventmanager_pending_r = interface16_bank_bus_dat_w[1:0]; +assign netv2_xover_eventmanager_pending_re = ((csrbank16_sel & interface16_bank_bus_we) & (interface16_bank_bus_adr[3:0] == 4'd12)); +assign netv2_xover_eventmanager_pending_we = ((csrbank16_sel & (~interface16_bank_bus_we)) & (interface16_bank_bus_adr[3:0] == 4'd12)); +assign csrbank16_xover_ev_enable0_r = interface16_bank_bus_dat_w[1:0]; +assign csrbank16_xover_ev_enable0_re = ((csrbank16_sel & interface16_bank_bus_we) & (interface16_bank_bus_adr[3:0] == 4'd13)); +assign csrbank16_xover_ev_enable0_we = ((csrbank16_sel & (~interface16_bank_bus_we)) & (interface16_bank_bus_adr[3:0] == 4'd13)); +assign csrbank16_xover_txempty_r = interface16_bank_bus_dat_w[0]; +assign csrbank16_xover_txempty_re = ((csrbank16_sel & interface16_bank_bus_we) & (interface16_bank_bus_adr[3:0] == 4'd14)); +assign csrbank16_xover_txempty_we = ((csrbank16_sel & (~interface16_bank_bus_we)) & (interface16_bank_bus_adr[3:0] == 4'd14)); +assign csrbank16_xover_rxfull_r = interface16_bank_bus_dat_w[0]; +assign csrbank16_xover_rxfull_re = ((csrbank16_sel & interface16_bank_bus_we) & (interface16_bank_bus_adr[3:0] == 4'd15)); +assign csrbank16_xover_rxfull_we = ((csrbank16_sel & (~interface16_bank_bus_we)) & (interface16_bank_bus_adr[3:0] == 4'd15)); +assign csrbank16_txfull_w = netv2_uartcrossover_txfull_status; +assign netv2_uartcrossover_txfull_we = csrbank16_txfull_we; +assign netv2_uartcrossover_txfull_re = csrbank16_txfull_re; +assign csrbank16_rxempty_w = netv2_uartcrossover_rxempty_status; +assign netv2_uartcrossover_rxempty_we = csrbank16_rxempty_we; +assign netv2_uartcrossover_rxempty_re = csrbank16_rxempty_re; +assign csrbank16_ev_enable0_w = netv2_uartcrossover_eventmanager_storage[1:0]; +assign csrbank16_txempty_w = netv2_uartcrossover_txempty_status; +assign netv2_uartcrossover_txempty_we = csrbank16_txempty_we; +assign netv2_uartcrossover_txempty_re = csrbank16_txempty_re; +assign csrbank16_rxfull_w = netv2_uartcrossover_rxfull_status; +assign netv2_uartcrossover_rxfull_we = csrbank16_rxfull_we; +assign netv2_uartcrossover_rxfull_re = csrbank16_rxfull_re; +assign csrbank16_xover_txfull_w = netv2_xover_txfull_status; +assign netv2_xover_txfull_we = csrbank16_xover_txfull_we; +assign netv2_xover_txfull_re = csrbank16_xover_txfull_re; +assign csrbank16_xover_rxempty_w = netv2_xover_rxempty_status; +assign netv2_xover_rxempty_we = csrbank16_xover_rxempty_we; +assign netv2_xover_rxempty_re = csrbank16_xover_rxempty_re; +assign csrbank16_xover_ev_enable0_w = netv2_xover_eventmanager_storage[1:0]; +assign csrbank16_xover_txempty_w = netv2_xover_txempty_status; +assign netv2_xover_txempty_we = csrbank16_xover_txempty_we; +assign netv2_xover_txempty_re = csrbank16_xover_txempty_re; +assign csrbank16_xover_rxfull_w = netv2_xover_rxfull_status; +assign netv2_xover_rxfull_we = csrbank16_xover_rxfull_we; +assign netv2_xover_rxfull_re = csrbank16_xover_rxfull_re; +assign csrbank17_sel = (interface17_bank_bus_adr[13:9] == 4'd8); +assign csrbank17_temperature_r = interface17_bank_bus_dat_w[11:0]; +assign csrbank17_temperature_re = ((csrbank17_sel & interface17_bank_bus_we) & (interface17_bank_bus_adr[2:0] == 1'd0)); +assign csrbank17_temperature_we = ((csrbank17_sel & (~interface17_bank_bus_we)) & (interface17_bank_bus_adr[2:0] == 1'd0)); +assign csrbank17_vccint_r = interface17_bank_bus_dat_w[11:0]; +assign csrbank17_vccint_re = ((csrbank17_sel & interface17_bank_bus_we) & (interface17_bank_bus_adr[2:0] == 1'd1)); +assign csrbank17_vccint_we = ((csrbank17_sel & (~interface17_bank_bus_we)) & (interface17_bank_bus_adr[2:0] == 1'd1)); +assign csrbank17_vccaux_r = interface17_bank_bus_dat_w[11:0]; +assign csrbank17_vccaux_re = ((csrbank17_sel & interface17_bank_bus_we) & (interface17_bank_bus_adr[2:0] == 2'd2)); +assign csrbank17_vccaux_we = ((csrbank17_sel & (~interface17_bank_bus_we)) & (interface17_bank_bus_adr[2:0] == 2'd2)); +assign csrbank17_vccbram_r = interface17_bank_bus_dat_w[11:0]; +assign csrbank17_vccbram_re = ((csrbank17_sel & interface17_bank_bus_we) & (interface17_bank_bus_adr[2:0] == 2'd3)); +assign csrbank17_vccbram_we = ((csrbank17_sel & (~interface17_bank_bus_we)) & (interface17_bank_bus_adr[2:0] == 2'd3)); +assign csrbank17_eoc_r = interface17_bank_bus_dat_w[0]; +assign csrbank17_eoc_re = ((csrbank17_sel & interface17_bank_bus_we) & (interface17_bank_bus_adr[2:0] == 3'd4)); +assign csrbank17_eoc_we = ((csrbank17_sel & (~interface17_bank_bus_we)) & (interface17_bank_bus_adr[2:0] == 3'd4)); +assign csrbank17_eos_r = interface17_bank_bus_dat_w[0]; +assign csrbank17_eos_re = ((csrbank17_sel & interface17_bank_bus_we) & (interface17_bank_bus_adr[2:0] == 3'd5)); +assign csrbank17_eos_we = ((csrbank17_sel & (~interface17_bank_bus_we)) & (interface17_bank_bus_adr[2:0] == 3'd5)); +assign csrbank17_temperature_w = xadc_temperature_status[11:0]; +assign xadc_temperature_we = csrbank17_temperature_we; +assign xadc_temperature_re = csrbank17_temperature_re; +assign csrbank17_vccint_w = xadc_vccint_status[11:0]; +assign xadc_vccint_we = csrbank17_vccint_we; +assign xadc_vccint_re = csrbank17_vccint_re; +assign csrbank17_vccaux_w = xadc_vccaux_status[11:0]; +assign xadc_vccaux_we = csrbank17_vccaux_we; +assign xadc_vccaux_re = csrbank17_vccaux_re; +assign csrbank17_vccbram_w = xadc_vccbram_status[11:0]; +assign xadc_vccbram_we = csrbank17_vccbram_we; +assign xadc_vccbram_re = csrbank17_vccbram_re; +assign csrbank17_eoc_w = xadc_eoc_status; +assign xadc_eoc_we = csrbank17_eoc_we; +assign xadc_eoc_re = csrbank17_eoc_re; +assign csrbank17_eos_w = xadc_eos_status; +assign xadc_eos_we = csrbank17_eos_we; +assign xadc_eos_re = csrbank17_eos_re; +assign csr_interconnect_adr = netv2_adr; +assign csr_interconnect_we = netv2_we; +assign csr_interconnect_dat_w = netv2_dat_w; +assign netv2_dat_r = csr_interconnect_dat_r; +assign interface0_bank_bus_adr = csr_interconnect_adr; +assign interface1_bank_bus_adr = csr_interconnect_adr; +assign interface2_bank_bus_adr = csr_interconnect_adr; +assign interface3_bank_bus_adr = csr_interconnect_adr; +assign interface4_bank_bus_adr = csr_interconnect_adr; +assign interface5_bank_bus_adr = csr_interconnect_adr; +assign interface6_bank_bus_adr = csr_interconnect_adr; +assign interface7_bank_bus_adr = csr_interconnect_adr; +assign interface8_bank_bus_adr = csr_interconnect_adr; +assign interface9_bank_bus_adr = csr_interconnect_adr; +assign interface10_bank_bus_adr = csr_interconnect_adr; +assign interface11_bank_bus_adr = csr_interconnect_adr; +assign interface12_bank_bus_adr = csr_interconnect_adr; +assign interface13_bank_bus_adr = csr_interconnect_adr; +assign interface14_bank_bus_adr = csr_interconnect_adr; +assign interface15_bank_bus_adr = csr_interconnect_adr; +assign interface16_bank_bus_adr = csr_interconnect_adr; +assign interface17_bank_bus_adr = csr_interconnect_adr; +assign interface0_sram_bus_adr = csr_interconnect_adr; +assign interface1_sram_bus_adr = csr_interconnect_adr; +assign interface0_bank_bus_we = csr_interconnect_we; +assign interface1_bank_bus_we = csr_interconnect_we; +assign interface2_bank_bus_we = csr_interconnect_we; +assign interface3_bank_bus_we = csr_interconnect_we; +assign interface4_bank_bus_we = csr_interconnect_we; +assign interface5_bank_bus_we = csr_interconnect_we; +assign interface6_bank_bus_we = csr_interconnect_we; +assign interface7_bank_bus_we = csr_interconnect_we; +assign interface8_bank_bus_we = csr_interconnect_we; +assign interface9_bank_bus_we = csr_interconnect_we; +assign interface10_bank_bus_we = csr_interconnect_we; +assign interface11_bank_bus_we = csr_interconnect_we; +assign interface12_bank_bus_we = csr_interconnect_we; +assign interface13_bank_bus_we = csr_interconnect_we; +assign interface14_bank_bus_we = csr_interconnect_we; +assign interface15_bank_bus_we = csr_interconnect_we; +assign interface16_bank_bus_we = csr_interconnect_we; +assign interface17_bank_bus_we = csr_interconnect_we; +assign interface0_sram_bus_we = csr_interconnect_we; +assign interface1_sram_bus_we = csr_interconnect_we; +assign interface0_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface1_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface2_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface3_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface4_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface5_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface6_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface7_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface8_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface9_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface10_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface11_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface12_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface13_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface14_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface15_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface16_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface17_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface0_sram_bus_dat_w = csr_interconnect_dat_w; +assign interface1_sram_bus_dat_w = csr_interconnect_dat_w; +assign csr_interconnect_dat_r = (((((((((((((((((((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r) | interface3_bank_bus_dat_r) | interface4_bank_bus_dat_r) | interface5_bank_bus_dat_r) | interface6_bank_bus_dat_r) | interface7_bank_bus_dat_r) | interface8_bank_bus_dat_r) | interface9_bank_bus_dat_r) | interface10_bank_bus_dat_r) | interface11_bank_bus_dat_r) | interface12_bank_bus_dat_r) | interface13_bank_bus_dat_r) | interface14_bank_bus_dat_r) | interface15_bank_bus_dat_r) | interface16_bank_bus_dat_r) | interface17_bank_bus_dat_r) | interface0_sram_bus_dat_r) | interface1_sram_bus_dat_r); +assign rhs_slice_proxy0 = ethcore_mac_depacketizer_header[111:96]; +assign rhs_slice_proxy1 = ethcore_mac_depacketizer_header[111:96]; +assign rhs_slice_proxy2 = ethcore_mac_depacketizer_header[95:48]; +assign rhs_slice_proxy3 = ethcore_mac_depacketizer_header[95:48]; +assign rhs_slice_proxy4 = ethcore_mac_depacketizer_header[95:48]; +assign rhs_slice_proxy5 = ethcore_mac_depacketizer_header[95:48]; +assign rhs_slice_proxy6 = ethcore_mac_depacketizer_header[95:48]; +assign rhs_slice_proxy7 = ethcore_mac_depacketizer_header[95:48]; +assign rhs_slice_proxy8 = ethcore_mac_depacketizer_header[47:0]; +assign rhs_slice_proxy9 = ethcore_mac_depacketizer_header[47:0]; +assign rhs_slice_proxy10 = ethcore_mac_depacketizer_header[47:0]; +assign rhs_slice_proxy11 = ethcore_mac_depacketizer_header[47:0]; +assign rhs_slice_proxy12 = ethcore_mac_depacketizer_header[47:0]; +assign rhs_slice_proxy13 = ethcore_mac_depacketizer_header[47:0]; +assign rhs_slice_proxy14 = ethcore_arp_rx_depacketizer_header[39:32]; +assign rhs_slice_proxy15 = ethcore_arp_rx_depacketizer_header[15:0]; +assign rhs_slice_proxy16 = ethcore_arp_rx_depacketizer_header[15:0]; +assign rhs_slice_proxy17 = ethcore_arp_rx_depacketizer_header[63:48]; +assign rhs_slice_proxy18 = ethcore_arp_rx_depacketizer_header[63:48]; +assign rhs_slice_proxy19 = ethcore_arp_rx_depacketizer_header[31:16]; +assign rhs_slice_proxy20 = ethcore_arp_rx_depacketizer_header[31:16]; +assign rhs_slice_proxy21 = ethcore_arp_rx_depacketizer_header[47:40]; +assign rhs_slice_proxy22 = ethcore_arp_rx_depacketizer_header[143:112]; +assign rhs_slice_proxy23 = ethcore_arp_rx_depacketizer_header[143:112]; +assign rhs_slice_proxy24 = ethcore_arp_rx_depacketizer_header[143:112]; +assign rhs_slice_proxy25 = ethcore_arp_rx_depacketizer_header[143:112]; +assign rhs_slice_proxy26 = ethcore_arp_rx_depacketizer_header[111:64]; +assign rhs_slice_proxy27 = ethcore_arp_rx_depacketizer_header[111:64]; +assign rhs_slice_proxy28 = ethcore_arp_rx_depacketizer_header[111:64]; +assign rhs_slice_proxy29 = ethcore_arp_rx_depacketizer_header[111:64]; +assign rhs_slice_proxy30 = ethcore_arp_rx_depacketizer_header[111:64]; +assign rhs_slice_proxy31 = ethcore_arp_rx_depacketizer_header[111:64]; +assign rhs_slice_proxy32 = ethcore_arp_rx_depacketizer_header[223:192]; +assign rhs_slice_proxy33 = ethcore_arp_rx_depacketizer_header[223:192]; +assign rhs_slice_proxy34 = ethcore_arp_rx_depacketizer_header[223:192]; +assign rhs_slice_proxy35 = ethcore_arp_rx_depacketizer_header[223:192]; +assign rhs_slice_proxy36 = ethcore_arp_rx_depacketizer_header[191:144]; +assign rhs_slice_proxy37 = ethcore_arp_rx_depacketizer_header[191:144]; +assign rhs_slice_proxy38 = ethcore_arp_rx_depacketizer_header[191:144]; +assign rhs_slice_proxy39 = ethcore_arp_rx_depacketizer_header[191:144]; +assign rhs_slice_proxy40 = ethcore_arp_rx_depacketizer_header[191:144]; +assign rhs_slice_proxy41 = ethcore_arp_rx_depacketizer_header[191:144]; +assign rhs_slice_proxy42 = ethcore_ip_rx_depacketizer_header[95:80]; +assign rhs_slice_proxy43 = ethcore_ip_rx_depacketizer_header[95:80]; +assign rhs_slice_proxy44 = ethcore_ip_rx_depacketizer_header[47:32]; +assign rhs_slice_proxy45 = ethcore_ip_rx_depacketizer_header[47:32]; +assign rhs_slice_proxy46 = ethcore_ip_rx_depacketizer_header[3:0]; +assign rhs_slice_proxy47 = ethcore_ip_rx_depacketizer_header[79:72]; +assign rhs_slice_proxy48 = ethcore_ip_rx_depacketizer_header[127:96]; +assign rhs_slice_proxy49 = ethcore_ip_rx_depacketizer_header[127:96]; +assign rhs_slice_proxy50 = ethcore_ip_rx_depacketizer_header[127:96]; +assign rhs_slice_proxy51 = ethcore_ip_rx_depacketizer_header[127:96]; +assign rhs_slice_proxy52 = ethcore_ip_rx_depacketizer_header[159:128]; +assign rhs_slice_proxy53 = ethcore_ip_rx_depacketizer_header[159:128]; +assign rhs_slice_proxy54 = ethcore_ip_rx_depacketizer_header[159:128]; +assign rhs_slice_proxy55 = ethcore_ip_rx_depacketizer_header[159:128]; +assign rhs_slice_proxy56 = ethcore_ip_rx_depacketizer_header[31:16]; +assign rhs_slice_proxy57 = ethcore_ip_rx_depacketizer_header[31:16]; +assign rhs_slice_proxy58 = ethcore_ip_rx_depacketizer_header[71:64]; +assign rhs_slice_proxy59 = ethcore_ip_rx_depacketizer_header[7:4]; +assign rhs_slice_proxy60 = ethcore_icmp_rx_depacketizer_header[31:16]; +assign rhs_slice_proxy61 = ethcore_icmp_rx_depacketizer_header[31:16]; +assign rhs_slice_proxy62 = ethcore_icmp_rx_depacketizer_header[15:8]; +assign rhs_slice_proxy63 = ethcore_icmp_rx_depacketizer_header[7:0]; +assign rhs_slice_proxy64 = ethcore_icmp_rx_depacketizer_header[63:32]; +assign rhs_slice_proxy65 = ethcore_icmp_rx_depacketizer_header[63:32]; +assign rhs_slice_proxy66 = ethcore_icmp_rx_depacketizer_header[63:32]; +assign rhs_slice_proxy67 = ethcore_icmp_rx_depacketizer_header[63:32]; +assign rhs_slice_proxy68 = ethcore_rx_depacketizer_header[63:48]; +assign rhs_slice_proxy69 = ethcore_rx_depacketizer_header[63:48]; +assign rhs_slice_proxy70 = ethcore_rx_depacketizer_header[31:16]; +assign rhs_slice_proxy71 = ethcore_rx_depacketizer_header[31:16]; +assign rhs_slice_proxy72 = ethcore_rx_depacketizer_header[47:32]; +assign rhs_slice_proxy73 = ethcore_rx_depacketizer_header[47:32]; +assign rhs_slice_proxy74 = ethcore_rx_depacketizer_header[15:0]; +assign rhs_slice_proxy75 = ethcore_rx_depacketizer_header[15:0]; +assign rhs_slice_proxy76 = etherbone_rx_depacketizer_header[31:28]; +assign rhs_slice_proxy77 = etherbone_rx_depacketizer_header[15:0]; +assign rhs_slice_proxy78 = etherbone_rx_depacketizer_header[15:0]; +assign rhs_slice_proxy79 = etherbone_rx_depacketizer_header[18]; +assign rhs_slice_proxy80 = etherbone_rx_depacketizer_header[16]; +assign rhs_slice_proxy81 = etherbone_rx_depacketizer_header[27:24]; +assign rhs_slice_proxy82 = etherbone_rx_depacketizer_header[17]; +assign rhs_slice_proxy83 = etherbone_rx_depacketizer_header[23:20]; +assign rhs_slice_proxy84 = etherbone_record_depacketizer_header[0]; +assign rhs_slice_proxy85 = etherbone_record_depacketizer_header[15:8]; +assign rhs_slice_proxy86 = etherbone_record_depacketizer_header[4]; +assign rhs_slice_proxy87 = etherbone_record_depacketizer_header[1]; +assign rhs_slice_proxy88 = etherbone_record_depacketizer_header[31:24]; +assign rhs_slice_proxy89 = etherbone_record_depacketizer_header[2]; +assign rhs_slice_proxy90 = etherbone_record_depacketizer_header[5]; +assign rhs_slice_proxy91 = etherbone_record_depacketizer_header[23:16]; +assign rhs_slice_proxy92 = etherbone_record_depacketizer_header[6]; +assign rhs_slice_proxy93 = depacketizer_header_extracter_dat[63:32]; +assign rhs_slice_proxy94 = depacketizer_header_extracter_dat[63:32]; +assign rhs_slice_proxy95 = depacketizer_header_extracter_dat[63:32]; +assign rhs_slice_proxy96 = depacketizer_header_extracter_dat[63:32]; +assign rhs_slice_proxy97 = depacketizer_header_extracter_sink_payload_dat[31:0]; +assign rhs_slice_proxy98 = depacketizer_header_extracter_sink_payload_dat[31:0]; +assign rhs_slice_proxy99 = depacketizer_header_extracter_sink_payload_dat[31:0]; +assign rhs_slice_proxy100 = depacketizer_header_extracter_sink_payload_dat[31:0]; +assign rhs_slice_proxy101 = depacketizer_header_extracter_be[7:4]; +assign rhs_slice_proxy102 = depacketizer_header_extracter_be[7:4]; +assign rhs_slice_proxy103 = depacketizer_header_extracter_be[7:4]; +assign rhs_slice_proxy104 = depacketizer_header_extracter_be[7:4]; +assign rhs_slice_proxy105 = depacketizer_header_extracter_sink_payload_be[3:0]; +assign rhs_slice_proxy106 = depacketizer_header_extracter_sink_payload_be[3:0]; +assign rhs_slice_proxy107 = depacketizer_header_extracter_sink_payload_be[3:0]; +assign rhs_slice_proxy108 = depacketizer_header_extracter_sink_payload_be[3:0]; +assign cases_slice_proxy0 = packetizer_header_inserter_sink_payload_dat[31:0]; +assign cases_slice_proxy1 = packetizer_header_inserter_sink_payload_dat[31:0]; +assign cases_slice_proxy2 = packetizer_header_inserter_sink_payload_dat[31:0]; +assign cases_slice_proxy3 = packetizer_header_inserter_sink_payload_dat[31:0]; +assign cases_slice_proxy4 = packetizer_header_inserter_sink_payload_be[3:0]; +assign cases_slice_proxy5 = packetizer_header_inserter_sink_payload_be[3:0]; +assign cases_slice_proxy6 = packetizer_header_inserter_sink_payload_be[3:0]; +assign cases_slice_proxy7 = packetizer_header_inserter_sink_payload_be[3:0]; +assign cases_slice_proxy8 = packetizer_header_inserter_dat[63:32]; +assign cases_slice_proxy9 = packetizer_header_inserter_dat[63:32]; +assign cases_slice_proxy10 = packetizer_header_inserter_dat[63:32]; +assign cases_slice_proxy11 = packetizer_header_inserter_dat[63:32]; +assign cases_slice_proxy12 = packetizer_header_inserter_sink_payload_dat[31:0]; +assign cases_slice_proxy13 = packetizer_header_inserter_sink_payload_dat[31:0]; +assign cases_slice_proxy14 = packetizer_header_inserter_sink_payload_dat[31:0]; +assign cases_slice_proxy15 = packetizer_header_inserter_sink_payload_dat[31:0]; +assign slice_proxy0 = icap__i[7:0]; +assign slice_proxy1 = icap__i[7:0]; +assign slice_proxy2 = icap__i[7:0]; +assign slice_proxy3 = icap__i[7:0]; +assign slice_proxy4 = icap__i[7:0]; +assign slice_proxy5 = icap__i[7:0]; +assign slice_proxy6 = icap__i[7:0]; +assign slice_proxy7 = icap__i[7:0]; +assign slice_proxy8 = icap__i[15:8]; +assign slice_proxy9 = icap__i[15:8]; +assign slice_proxy10 = icap__i[15:8]; +assign slice_proxy11 = icap__i[15:8]; +assign slice_proxy12 = icap__i[15:8]; +assign slice_proxy13 = icap__i[15:8]; +assign slice_proxy14 = icap__i[15:8]; +assign slice_proxy15 = icap__i[15:8]; +assign slice_proxy16 = icap__i[23:16]; +assign slice_proxy17 = icap__i[23:16]; +assign slice_proxy18 = icap__i[23:16]; +assign slice_proxy19 = icap__i[23:16]; +assign slice_proxy20 = icap__i[23:16]; +assign slice_proxy21 = icap__i[23:16]; +assign slice_proxy22 = icap__i[23:16]; +assign slice_proxy23 = icap__i[23:16]; +assign slice_proxy24 = icap__i[31:24]; +assign slice_proxy25 = icap__i[31:24]; +assign slice_proxy26 = icap__i[31:24]; +assign slice_proxy27 = icap__i[31:24]; +assign slice_proxy28 = icap__i[31:24]; +assign slice_proxy29 = icap__i[31:24]; +assign slice_proxy30 = icap__i[31:24]; +assign slice_proxy31 = icap__i[31:24]; +always @(*) begin + comb_rhs_array_muxed0 <= 1'd0; + case (netv2_sdram_choose_cmd_grant) + 1'd0: begin + comb_rhs_array_muxed0 <= netv2_sdram_choose_cmd_valids[0]; + end + 1'd1: begin + comb_rhs_array_muxed0 <= netv2_sdram_choose_cmd_valids[1]; + end + 2'd2: begin + comb_rhs_array_muxed0 <= netv2_sdram_choose_cmd_valids[2]; + end + 2'd3: begin + comb_rhs_array_muxed0 <= netv2_sdram_choose_cmd_valids[3]; + end + 3'd4: begin + comb_rhs_array_muxed0 <= netv2_sdram_choose_cmd_valids[4]; + end + 3'd5: begin + comb_rhs_array_muxed0 <= netv2_sdram_choose_cmd_valids[5]; + end + 3'd6: begin + comb_rhs_array_muxed0 <= netv2_sdram_choose_cmd_valids[6]; + end + default: begin + comb_rhs_array_muxed0 <= netv2_sdram_choose_cmd_valids[7]; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed1 <= 14'd0; + case (netv2_sdram_choose_cmd_grant) + 1'd0: begin + comb_rhs_array_muxed1 <= netv2_sdram_bankmachine0_cmd_payload_a; + end + 1'd1: begin + comb_rhs_array_muxed1 <= netv2_sdram_bankmachine1_cmd_payload_a; + end + 2'd2: begin + comb_rhs_array_muxed1 <= netv2_sdram_bankmachine2_cmd_payload_a; + end + 2'd3: begin + comb_rhs_array_muxed1 <= netv2_sdram_bankmachine3_cmd_payload_a; + end + 3'd4: begin + comb_rhs_array_muxed1 <= netv2_sdram_bankmachine4_cmd_payload_a; + end + 3'd5: begin + comb_rhs_array_muxed1 <= netv2_sdram_bankmachine5_cmd_payload_a; + end + 3'd6: begin + comb_rhs_array_muxed1 <= netv2_sdram_bankmachine6_cmd_payload_a; + end + default: begin + comb_rhs_array_muxed1 <= netv2_sdram_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed2 <= 3'd0; + case (netv2_sdram_choose_cmd_grant) + 1'd0: begin + comb_rhs_array_muxed2 <= netv2_sdram_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + comb_rhs_array_muxed2 <= netv2_sdram_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + comb_rhs_array_muxed2 <= netv2_sdram_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + comb_rhs_array_muxed2 <= netv2_sdram_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + comb_rhs_array_muxed2 <= netv2_sdram_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + comb_rhs_array_muxed2 <= netv2_sdram_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + comb_rhs_array_muxed2 <= netv2_sdram_bankmachine6_cmd_payload_ba; + end + default: begin + comb_rhs_array_muxed2 <= netv2_sdram_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed3 <= 1'd0; + case (netv2_sdram_choose_cmd_grant) + 1'd0: begin + comb_rhs_array_muxed3 <= netv2_sdram_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + comb_rhs_array_muxed3 <= netv2_sdram_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + comb_rhs_array_muxed3 <= netv2_sdram_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + comb_rhs_array_muxed3 <= netv2_sdram_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + comb_rhs_array_muxed3 <= netv2_sdram_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + comb_rhs_array_muxed3 <= netv2_sdram_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + comb_rhs_array_muxed3 <= netv2_sdram_bankmachine6_cmd_payload_is_read; + end + default: begin + comb_rhs_array_muxed3 <= netv2_sdram_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed4 <= 1'd0; + case (netv2_sdram_choose_cmd_grant) + 1'd0: begin + comb_rhs_array_muxed4 <= netv2_sdram_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + comb_rhs_array_muxed4 <= netv2_sdram_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + comb_rhs_array_muxed4 <= netv2_sdram_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + comb_rhs_array_muxed4 <= netv2_sdram_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + comb_rhs_array_muxed4 <= netv2_sdram_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + comb_rhs_array_muxed4 <= netv2_sdram_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + comb_rhs_array_muxed4 <= netv2_sdram_bankmachine6_cmd_payload_is_write; + end + default: begin + comb_rhs_array_muxed4 <= netv2_sdram_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed5 <= 1'd0; + case (netv2_sdram_choose_cmd_grant) + 1'd0: begin + comb_rhs_array_muxed5 <= netv2_sdram_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + comb_rhs_array_muxed5 <= netv2_sdram_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + comb_rhs_array_muxed5 <= netv2_sdram_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + comb_rhs_array_muxed5 <= netv2_sdram_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + comb_rhs_array_muxed5 <= netv2_sdram_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + comb_rhs_array_muxed5 <= netv2_sdram_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + comb_rhs_array_muxed5 <= netv2_sdram_bankmachine6_cmd_payload_is_cmd; + end + default: begin + comb_rhs_array_muxed5 <= netv2_sdram_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + comb_t_array_muxed0 <= 1'd0; + case (netv2_sdram_choose_cmd_grant) + 1'd0: begin + comb_t_array_muxed0 <= netv2_sdram_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + comb_t_array_muxed0 <= netv2_sdram_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + comb_t_array_muxed0 <= netv2_sdram_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + comb_t_array_muxed0 <= netv2_sdram_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + comb_t_array_muxed0 <= netv2_sdram_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + comb_t_array_muxed0 <= netv2_sdram_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + comb_t_array_muxed0 <= netv2_sdram_bankmachine6_cmd_payload_cas; + end + default: begin + comb_t_array_muxed0 <= netv2_sdram_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + comb_t_array_muxed1 <= 1'd0; + case (netv2_sdram_choose_cmd_grant) + 1'd0: begin + comb_t_array_muxed1 <= netv2_sdram_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + comb_t_array_muxed1 <= netv2_sdram_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + comb_t_array_muxed1 <= netv2_sdram_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + comb_t_array_muxed1 <= netv2_sdram_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + comb_t_array_muxed1 <= netv2_sdram_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + comb_t_array_muxed1 <= netv2_sdram_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + comb_t_array_muxed1 <= netv2_sdram_bankmachine6_cmd_payload_ras; + end + default: begin + comb_t_array_muxed1 <= netv2_sdram_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + comb_t_array_muxed2 <= 1'd0; + case (netv2_sdram_choose_cmd_grant) + 1'd0: begin + comb_t_array_muxed2 <= netv2_sdram_bankmachine0_cmd_payload_we; + end + 1'd1: begin + comb_t_array_muxed2 <= netv2_sdram_bankmachine1_cmd_payload_we; + end + 2'd2: begin + comb_t_array_muxed2 <= netv2_sdram_bankmachine2_cmd_payload_we; + end + 2'd3: begin + comb_t_array_muxed2 <= netv2_sdram_bankmachine3_cmd_payload_we; + end + 3'd4: begin + comb_t_array_muxed2 <= netv2_sdram_bankmachine4_cmd_payload_we; + end + 3'd5: begin + comb_t_array_muxed2 <= netv2_sdram_bankmachine5_cmd_payload_we; + end + 3'd6: begin + comb_t_array_muxed2 <= netv2_sdram_bankmachine6_cmd_payload_we; + end + default: begin + comb_t_array_muxed2 <= netv2_sdram_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed6 <= 1'd0; + case (netv2_sdram_choose_req_grant) + 1'd0: begin + comb_rhs_array_muxed6 <= netv2_sdram_choose_req_valids[0]; + end + 1'd1: begin + comb_rhs_array_muxed6 <= netv2_sdram_choose_req_valids[1]; + end + 2'd2: begin + comb_rhs_array_muxed6 <= netv2_sdram_choose_req_valids[2]; + end + 2'd3: begin + comb_rhs_array_muxed6 <= netv2_sdram_choose_req_valids[3]; + end + 3'd4: begin + comb_rhs_array_muxed6 <= netv2_sdram_choose_req_valids[4]; + end + 3'd5: begin + comb_rhs_array_muxed6 <= netv2_sdram_choose_req_valids[5]; + end + 3'd6: begin + comb_rhs_array_muxed6 <= netv2_sdram_choose_req_valids[6]; + end + default: begin + comb_rhs_array_muxed6 <= netv2_sdram_choose_req_valids[7]; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed7 <= 14'd0; + case (netv2_sdram_choose_req_grant) + 1'd0: begin + comb_rhs_array_muxed7 <= netv2_sdram_bankmachine0_cmd_payload_a; + end + 1'd1: begin + comb_rhs_array_muxed7 <= netv2_sdram_bankmachine1_cmd_payload_a; + end + 2'd2: begin + comb_rhs_array_muxed7 <= netv2_sdram_bankmachine2_cmd_payload_a; + end + 2'd3: begin + comb_rhs_array_muxed7 <= netv2_sdram_bankmachine3_cmd_payload_a; + end + 3'd4: begin + comb_rhs_array_muxed7 <= netv2_sdram_bankmachine4_cmd_payload_a; + end + 3'd5: begin + comb_rhs_array_muxed7 <= netv2_sdram_bankmachine5_cmd_payload_a; + end + 3'd6: begin + comb_rhs_array_muxed7 <= netv2_sdram_bankmachine6_cmd_payload_a; + end + default: begin + comb_rhs_array_muxed7 <= netv2_sdram_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed8 <= 3'd0; + case (netv2_sdram_choose_req_grant) + 1'd0: begin + comb_rhs_array_muxed8 <= netv2_sdram_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + comb_rhs_array_muxed8 <= netv2_sdram_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + comb_rhs_array_muxed8 <= netv2_sdram_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + comb_rhs_array_muxed8 <= netv2_sdram_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + comb_rhs_array_muxed8 <= netv2_sdram_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + comb_rhs_array_muxed8 <= netv2_sdram_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + comb_rhs_array_muxed8 <= netv2_sdram_bankmachine6_cmd_payload_ba; + end + default: begin + comb_rhs_array_muxed8 <= netv2_sdram_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed9 <= 1'd0; + case (netv2_sdram_choose_req_grant) + 1'd0: begin + comb_rhs_array_muxed9 <= netv2_sdram_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + comb_rhs_array_muxed9 <= netv2_sdram_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + comb_rhs_array_muxed9 <= netv2_sdram_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + comb_rhs_array_muxed9 <= netv2_sdram_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + comb_rhs_array_muxed9 <= netv2_sdram_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + comb_rhs_array_muxed9 <= netv2_sdram_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + comb_rhs_array_muxed9 <= netv2_sdram_bankmachine6_cmd_payload_is_read; + end + default: begin + comb_rhs_array_muxed9 <= netv2_sdram_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed10 <= 1'd0; + case (netv2_sdram_choose_req_grant) + 1'd0: begin + comb_rhs_array_muxed10 <= netv2_sdram_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + comb_rhs_array_muxed10 <= netv2_sdram_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + comb_rhs_array_muxed10 <= netv2_sdram_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + comb_rhs_array_muxed10 <= netv2_sdram_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + comb_rhs_array_muxed10 <= netv2_sdram_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + comb_rhs_array_muxed10 <= netv2_sdram_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + comb_rhs_array_muxed10 <= netv2_sdram_bankmachine6_cmd_payload_is_write; + end + default: begin + comb_rhs_array_muxed10 <= netv2_sdram_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed11 <= 1'd0; + case (netv2_sdram_choose_req_grant) + 1'd0: begin + comb_rhs_array_muxed11 <= netv2_sdram_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + comb_rhs_array_muxed11 <= netv2_sdram_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + comb_rhs_array_muxed11 <= netv2_sdram_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + comb_rhs_array_muxed11 <= netv2_sdram_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + comb_rhs_array_muxed11 <= netv2_sdram_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + comb_rhs_array_muxed11 <= netv2_sdram_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + comb_rhs_array_muxed11 <= netv2_sdram_bankmachine6_cmd_payload_is_cmd; + end + default: begin + comb_rhs_array_muxed11 <= netv2_sdram_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + comb_t_array_muxed3 <= 1'd0; + case (netv2_sdram_choose_req_grant) + 1'd0: begin + comb_t_array_muxed3 <= netv2_sdram_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + comb_t_array_muxed3 <= netv2_sdram_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + comb_t_array_muxed3 <= netv2_sdram_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + comb_t_array_muxed3 <= netv2_sdram_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + comb_t_array_muxed3 <= netv2_sdram_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + comb_t_array_muxed3 <= netv2_sdram_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + comb_t_array_muxed3 <= netv2_sdram_bankmachine6_cmd_payload_cas; + end + default: begin + comb_t_array_muxed3 <= netv2_sdram_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + comb_t_array_muxed4 <= 1'd0; + case (netv2_sdram_choose_req_grant) + 1'd0: begin + comb_t_array_muxed4 <= netv2_sdram_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + comb_t_array_muxed4 <= netv2_sdram_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + comb_t_array_muxed4 <= netv2_sdram_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + comb_t_array_muxed4 <= netv2_sdram_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + comb_t_array_muxed4 <= netv2_sdram_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + comb_t_array_muxed4 <= netv2_sdram_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + comb_t_array_muxed4 <= netv2_sdram_bankmachine6_cmd_payload_ras; + end + default: begin + comb_t_array_muxed4 <= netv2_sdram_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + comb_t_array_muxed5 <= 1'd0; + case (netv2_sdram_choose_req_grant) + 1'd0: begin + comb_t_array_muxed5 <= netv2_sdram_bankmachine0_cmd_payload_we; + end + 1'd1: begin + comb_t_array_muxed5 <= netv2_sdram_bankmachine1_cmd_payload_we; + end + 2'd2: begin + comb_t_array_muxed5 <= netv2_sdram_bankmachine2_cmd_payload_we; + end + 2'd3: begin + comb_t_array_muxed5 <= netv2_sdram_bankmachine3_cmd_payload_we; + end + 3'd4: begin + comb_t_array_muxed5 <= netv2_sdram_bankmachine4_cmd_payload_we; + end + 3'd5: begin + comb_t_array_muxed5 <= netv2_sdram_bankmachine5_cmd_payload_we; + end + 3'd6: begin + comb_t_array_muxed5 <= netv2_sdram_bankmachine6_cmd_payload_we; + end + default: begin + comb_t_array_muxed5 <= netv2_sdram_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed12 <= 21'd0; + case (litedramcore_roundrobin0_grant) + 1'd0: begin + comb_rhs_array_muxed12 <= {netv2_port_cmd_payload_addr[23:10], netv2_port_cmd_payload_addr[6:0]}; + end + 1'd1: begin + comb_rhs_array_muxed12 <= {litedramcrossbar_litedramnativeport0_cmd_payload_addr0[23:10], litedramcrossbar_litedramnativeport0_cmd_payload_addr0[6:0]}; + end + default: begin + comb_rhs_array_muxed12 <= {litedramcrossbar_litedramnativeport1_cmd_payload_addr0[23:10], litedramcrossbar_litedramnativeport1_cmd_payload_addr0[6:0]}; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed13 <= 1'd0; + case (litedramcore_roundrobin0_grant) + 1'd0: begin + comb_rhs_array_muxed13 <= netv2_port_cmd_payload_we; + end + 1'd1: begin + comb_rhs_array_muxed13 <= litedramcrossbar_litedramnativeport0_cmd_payload_we0; + end + default: begin + comb_rhs_array_muxed13 <= litedramcrossbar_litedramnativeport1_cmd_payload_we0; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed14 <= 1'd0; + case (litedramcore_roundrobin0_grant) + 1'd0: begin + comb_rhs_array_muxed14 <= (((netv2_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & netv2_port_cmd_valid); + end + 1'd1: begin + comb_rhs_array_muxed14 <= (((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 1'd0) & (~(((((((litedramcore_locked1 | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & litedramcrossbar_litedramnativeport0_cmd_valid0); + end + default: begin + comb_rhs_array_muxed14 <= (((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 1'd0) & (~(((((((litedramcore_locked2 | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2))))) & litedramcrossbar_litedramnativeport1_cmd_valid0); + end + endcase +end +always @(*) begin + comb_rhs_array_muxed15 <= 21'd0; + case (litedramcore_roundrobin1_grant) + 1'd0: begin + comb_rhs_array_muxed15 <= {netv2_port_cmd_payload_addr[23:10], netv2_port_cmd_payload_addr[6:0]}; + end + 1'd1: begin + comb_rhs_array_muxed15 <= {litedramcrossbar_litedramnativeport0_cmd_payload_addr0[23:10], litedramcrossbar_litedramnativeport0_cmd_payload_addr0[6:0]}; + end + default: begin + comb_rhs_array_muxed15 <= {litedramcrossbar_litedramnativeport1_cmd_payload_addr0[23:10], litedramcrossbar_litedramnativeport1_cmd_payload_addr0[6:0]}; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed16 <= 1'd0; + case (litedramcore_roundrobin1_grant) + 1'd0: begin + comb_rhs_array_muxed16 <= netv2_port_cmd_payload_we; + end + 1'd1: begin + comb_rhs_array_muxed16 <= litedramcrossbar_litedramnativeport0_cmd_payload_we0; + end + default: begin + comb_rhs_array_muxed16 <= litedramcrossbar_litedramnativeport1_cmd_payload_we0; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed17 <= 1'd0; + case (litedramcore_roundrobin1_grant) + 1'd0: begin + comb_rhs_array_muxed17 <= (((netv2_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked3 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & netv2_port_cmd_valid); + end + 1'd1: begin + comb_rhs_array_muxed17 <= (((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 1'd1) & (~(((((((litedramcore_locked4 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & litedramcrossbar_litedramnativeport0_cmd_valid0); + end + default: begin + comb_rhs_array_muxed17 <= (((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 1'd1) & (~(((((((litedramcore_locked5 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2))))) & litedramcrossbar_litedramnativeport1_cmd_valid0); + end + endcase +end +always @(*) begin + comb_rhs_array_muxed18 <= 21'd0; + case (litedramcore_roundrobin2_grant) + 1'd0: begin + comb_rhs_array_muxed18 <= {netv2_port_cmd_payload_addr[23:10], netv2_port_cmd_payload_addr[6:0]}; + end + 1'd1: begin + comb_rhs_array_muxed18 <= {litedramcrossbar_litedramnativeport0_cmd_payload_addr0[23:10], litedramcrossbar_litedramnativeport0_cmd_payload_addr0[6:0]}; + end + default: begin + comb_rhs_array_muxed18 <= {litedramcrossbar_litedramnativeport1_cmd_payload_addr0[23:10], litedramcrossbar_litedramnativeport1_cmd_payload_addr0[6:0]}; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed19 <= 1'd0; + case (litedramcore_roundrobin2_grant) + 1'd0: begin + comb_rhs_array_muxed19 <= netv2_port_cmd_payload_we; + end + 1'd1: begin + comb_rhs_array_muxed19 <= litedramcrossbar_litedramnativeport0_cmd_payload_we0; + end + default: begin + comb_rhs_array_muxed19 <= litedramcrossbar_litedramnativeport1_cmd_payload_we0; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed20 <= 1'd0; + case (litedramcore_roundrobin2_grant) + 1'd0: begin + comb_rhs_array_muxed20 <= (((netv2_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked6 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & netv2_port_cmd_valid); + end + 1'd1: begin + comb_rhs_array_muxed20 <= (((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 2'd2) & (~(((((((litedramcore_locked7 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & litedramcrossbar_litedramnativeport0_cmd_valid0); + end + default: begin + comb_rhs_array_muxed20 <= (((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 2'd2) & (~(((((((litedramcore_locked8 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2))))) & litedramcrossbar_litedramnativeport1_cmd_valid0); + end + endcase +end +always @(*) begin + comb_rhs_array_muxed21 <= 21'd0; + case (litedramcore_roundrobin3_grant) + 1'd0: begin + comb_rhs_array_muxed21 <= {netv2_port_cmd_payload_addr[23:10], netv2_port_cmd_payload_addr[6:0]}; + end + 1'd1: begin + comb_rhs_array_muxed21 <= {litedramcrossbar_litedramnativeport0_cmd_payload_addr0[23:10], litedramcrossbar_litedramnativeport0_cmd_payload_addr0[6:0]}; + end + default: begin + comb_rhs_array_muxed21 <= {litedramcrossbar_litedramnativeport1_cmd_payload_addr0[23:10], litedramcrossbar_litedramnativeport1_cmd_payload_addr0[6:0]}; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed22 <= 1'd0; + case (litedramcore_roundrobin3_grant) + 1'd0: begin + comb_rhs_array_muxed22 <= netv2_port_cmd_payload_we; + end + 1'd1: begin + comb_rhs_array_muxed22 <= litedramcrossbar_litedramnativeport0_cmd_payload_we0; + end + default: begin + comb_rhs_array_muxed22 <= litedramcrossbar_litedramnativeport1_cmd_payload_we0; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed23 <= 1'd0; + case (litedramcore_roundrobin3_grant) + 1'd0: begin + comb_rhs_array_muxed23 <= (((netv2_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked9 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & netv2_port_cmd_valid); + end + 1'd1: begin + comb_rhs_array_muxed23 <= (((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 2'd3) & (~(((((((litedramcore_locked10 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & litedramcrossbar_litedramnativeport0_cmd_valid0); + end + default: begin + comb_rhs_array_muxed23 <= (((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 2'd3) & (~(((((((litedramcore_locked11 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2))))) & litedramcrossbar_litedramnativeport1_cmd_valid0); + end + endcase +end +always @(*) begin + comb_rhs_array_muxed24 <= 21'd0; + case (litedramcore_roundrobin4_grant) + 1'd0: begin + comb_rhs_array_muxed24 <= {netv2_port_cmd_payload_addr[23:10], netv2_port_cmd_payload_addr[6:0]}; + end + 1'd1: begin + comb_rhs_array_muxed24 <= {litedramcrossbar_litedramnativeport0_cmd_payload_addr0[23:10], litedramcrossbar_litedramnativeport0_cmd_payload_addr0[6:0]}; + end + default: begin + comb_rhs_array_muxed24 <= {litedramcrossbar_litedramnativeport1_cmd_payload_addr0[23:10], litedramcrossbar_litedramnativeport1_cmd_payload_addr0[6:0]}; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed25 <= 1'd0; + case (litedramcore_roundrobin4_grant) + 1'd0: begin + comb_rhs_array_muxed25 <= netv2_port_cmd_payload_we; + end + 1'd1: begin + comb_rhs_array_muxed25 <= litedramcrossbar_litedramnativeport0_cmd_payload_we0; + end + default: begin + comb_rhs_array_muxed25 <= litedramcrossbar_litedramnativeport1_cmd_payload_we0; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed26 <= 1'd0; + case (litedramcore_roundrobin4_grant) + 1'd0: begin + comb_rhs_array_muxed26 <= (((netv2_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked12 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & netv2_port_cmd_valid); + end + 1'd1: begin + comb_rhs_array_muxed26 <= (((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 3'd4) & (~(((((((litedramcore_locked13 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & litedramcrossbar_litedramnativeport0_cmd_valid0); + end + default: begin + comb_rhs_array_muxed26 <= (((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 3'd4) & (~(((((((litedramcore_locked14 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2))))) & litedramcrossbar_litedramnativeport1_cmd_valid0); + end + endcase +end +always @(*) begin + comb_rhs_array_muxed27 <= 21'd0; + case (litedramcore_roundrobin5_grant) + 1'd0: begin + comb_rhs_array_muxed27 <= {netv2_port_cmd_payload_addr[23:10], netv2_port_cmd_payload_addr[6:0]}; + end + 1'd1: begin + comb_rhs_array_muxed27 <= {litedramcrossbar_litedramnativeport0_cmd_payload_addr0[23:10], litedramcrossbar_litedramnativeport0_cmd_payload_addr0[6:0]}; + end + default: begin + comb_rhs_array_muxed27 <= {litedramcrossbar_litedramnativeport1_cmd_payload_addr0[23:10], litedramcrossbar_litedramnativeport1_cmd_payload_addr0[6:0]}; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed28 <= 1'd0; + case (litedramcore_roundrobin5_grant) + 1'd0: begin + comb_rhs_array_muxed28 <= netv2_port_cmd_payload_we; + end + 1'd1: begin + comb_rhs_array_muxed28 <= litedramcrossbar_litedramnativeport0_cmd_payload_we0; + end + default: begin + comb_rhs_array_muxed28 <= litedramcrossbar_litedramnativeport1_cmd_payload_we0; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed29 <= 1'd0; + case (litedramcore_roundrobin5_grant) + 1'd0: begin + comb_rhs_array_muxed29 <= (((netv2_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked15 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & netv2_port_cmd_valid); + end + 1'd1: begin + comb_rhs_array_muxed29 <= (((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 3'd5) & (~(((((((litedramcore_locked16 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & litedramcrossbar_litedramnativeport0_cmd_valid0); + end + default: begin + comb_rhs_array_muxed29 <= (((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 3'd5) & (~(((((((litedramcore_locked17 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2))))) & litedramcrossbar_litedramnativeport1_cmd_valid0); + end + endcase +end +always @(*) begin + comb_rhs_array_muxed30 <= 21'd0; + case (litedramcore_roundrobin6_grant) + 1'd0: begin + comb_rhs_array_muxed30 <= {netv2_port_cmd_payload_addr[23:10], netv2_port_cmd_payload_addr[6:0]}; + end + 1'd1: begin + comb_rhs_array_muxed30 <= {litedramcrossbar_litedramnativeport0_cmd_payload_addr0[23:10], litedramcrossbar_litedramnativeport0_cmd_payload_addr0[6:0]}; + end + default: begin + comb_rhs_array_muxed30 <= {litedramcrossbar_litedramnativeport1_cmd_payload_addr0[23:10], litedramcrossbar_litedramnativeport1_cmd_payload_addr0[6:0]}; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed31 <= 1'd0; + case (litedramcore_roundrobin6_grant) + 1'd0: begin + comb_rhs_array_muxed31 <= netv2_port_cmd_payload_we; + end + 1'd1: begin + comb_rhs_array_muxed31 <= litedramcrossbar_litedramnativeport0_cmd_payload_we0; + end + default: begin + comb_rhs_array_muxed31 <= litedramcrossbar_litedramnativeport1_cmd_payload_we0; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed32 <= 1'd0; + case (litedramcore_roundrobin6_grant) + 1'd0: begin + comb_rhs_array_muxed32 <= (((netv2_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked18 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & netv2_port_cmd_valid); + end + 1'd1: begin + comb_rhs_array_muxed32 <= (((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 3'd6) & (~(((((((litedramcore_locked19 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & litedramcrossbar_litedramnativeport0_cmd_valid0); + end + default: begin + comb_rhs_array_muxed32 <= (((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 3'd6) & (~(((((((litedramcore_locked20 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 2'd2))))) & litedramcrossbar_litedramnativeport1_cmd_valid0); + end + endcase +end +always @(*) begin + comb_rhs_array_muxed33 <= 21'd0; + case (litedramcore_roundrobin7_grant) + 1'd0: begin + comb_rhs_array_muxed33 <= {netv2_port_cmd_payload_addr[23:10], netv2_port_cmd_payload_addr[6:0]}; + end + 1'd1: begin + comb_rhs_array_muxed33 <= {litedramcrossbar_litedramnativeport0_cmd_payload_addr0[23:10], litedramcrossbar_litedramnativeport0_cmd_payload_addr0[6:0]}; + end + default: begin + comb_rhs_array_muxed33 <= {litedramcrossbar_litedramnativeport1_cmd_payload_addr0[23:10], litedramcrossbar_litedramnativeport1_cmd_payload_addr0[6:0]}; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed34 <= 1'd0; + case (litedramcore_roundrobin7_grant) + 1'd0: begin + comb_rhs_array_muxed34 <= netv2_port_cmd_payload_we; + end + 1'd1: begin + comb_rhs_array_muxed34 <= litedramcrossbar_litedramnativeport0_cmd_payload_we0; + end + default: begin + comb_rhs_array_muxed34 <= litedramcrossbar_litedramnativeport1_cmd_payload_we0; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed35 <= 1'd0; + case (litedramcore_roundrobin7_grant) + 1'd0: begin + comb_rhs_array_muxed35 <= (((netv2_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked21 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & netv2_port_cmd_valid); + end + 1'd1: begin + comb_rhs_array_muxed35 <= (((litedramcrossbar_litedramnativeport0_cmd_payload_addr0[9:7] == 3'd7) & (~(((((((litedramcore_locked22 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))))) & litedramcrossbar_litedramnativeport0_cmd_valid0); + end + default: begin + comb_rhs_array_muxed35 <= (((litedramcrossbar_litedramnativeport1_cmd_payload_addr0[9:7] == 3'd7) & (~(((((((litedramcore_locked23 | (netv2_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 2'd2))) | (netv2_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 2'd2))) | (netv2_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 2'd2))) | (netv2_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 2'd2))) | (netv2_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 2'd2))) | (netv2_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 2'd2))) | (netv2_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 2'd2))))) & litedramcrossbar_litedramnativeport1_cmd_valid0); + end + endcase +end +always @(*) begin + comb_rhs_array_muxed36 <= 24'd0; + case (hdmi_in0_dma_slot_array_current_slot) + 1'd0: begin + comb_rhs_array_muxed36 <= hdmi_in0_dma_slot_array_slot0_address; + end + default: begin + comb_rhs_array_muxed36 <= hdmi_in0_dma_slot_array_slot1_address; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed37 <= 1'd0; + case (hdmi_in0_dma_slot_array_current_slot) + 1'd0: begin + comb_rhs_array_muxed37 <= hdmi_in0_dma_slot_array_slot0_address_valid; + end + default: begin + comb_rhs_array_muxed37 <= hdmi_in0_dma_slot_array_slot1_address_valid; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed38 <= 30'd0; + case (grant) + 1'd0: begin + comb_rhs_array_muxed38 <= netv2_cpu_ibus_adr; + end + 1'd1: begin + comb_rhs_array_muxed38 <= netv2_cpu_dbus_adr; + end + 2'd2: begin + comb_rhs_array_muxed38 <= etherbone_liteethetherbonewishbonemaster_bus_adr; + end + default: begin + comb_rhs_array_muxed38 <= pcie_bridge_wishbone_adr; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed39 <= 32'd0; + case (grant) + 1'd0: begin + comb_rhs_array_muxed39 <= netv2_cpu_ibus_dat_w; + end + 1'd1: begin + comb_rhs_array_muxed39 <= netv2_cpu_dbus_dat_w; + end + 2'd2: begin + comb_rhs_array_muxed39 <= etherbone_liteethetherbonewishbonemaster_bus_dat_w; + end + default: begin + comb_rhs_array_muxed39 <= pcie_bridge_wishbone_dat_w; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed40 <= 4'd0; + case (grant) + 1'd0: begin + comb_rhs_array_muxed40 <= netv2_cpu_ibus_sel; + end + 1'd1: begin + comb_rhs_array_muxed40 <= netv2_cpu_dbus_sel; + end + 2'd2: begin + comb_rhs_array_muxed40 <= etherbone_liteethetherbonewishbonemaster_bus_sel; + end + default: begin + comb_rhs_array_muxed40 <= pcie_bridge_wishbone_sel; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed41 <= 1'd0; + case (grant) + 1'd0: begin + comb_rhs_array_muxed41 <= netv2_cpu_ibus_cyc; + end + 1'd1: begin + comb_rhs_array_muxed41 <= netv2_cpu_dbus_cyc; + end + 2'd2: begin + comb_rhs_array_muxed41 <= etherbone_liteethetherbonewishbonemaster_bus_cyc; + end + default: begin + comb_rhs_array_muxed41 <= pcie_bridge_wishbone_cyc; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed42 <= 1'd0; + case (grant) + 1'd0: begin + comb_rhs_array_muxed42 <= netv2_cpu_ibus_stb; + end + 1'd1: begin + comb_rhs_array_muxed42 <= netv2_cpu_dbus_stb; + end + 2'd2: begin + comb_rhs_array_muxed42 <= etherbone_liteethetherbonewishbonemaster_bus_stb; + end + default: begin + comb_rhs_array_muxed42 <= pcie_bridge_wishbone_stb; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed43 <= 1'd0; + case (grant) + 1'd0: begin + comb_rhs_array_muxed43 <= netv2_cpu_ibus_we; + end + 1'd1: begin + comb_rhs_array_muxed43 <= netv2_cpu_dbus_we; + end + 2'd2: begin + comb_rhs_array_muxed43 <= etherbone_liteethetherbonewishbonemaster_bus_we; + end + default: begin + comb_rhs_array_muxed43 <= pcie_bridge_wishbone_we; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed44 <= 3'd0; + case (grant) + 1'd0: begin + comb_rhs_array_muxed44 <= netv2_cpu_ibus_cti; + end + 1'd1: begin + comb_rhs_array_muxed44 <= netv2_cpu_dbus_cti; + end + 2'd2: begin + comb_rhs_array_muxed44 <= etherbone_liteethetherbonewishbonemaster_bus_cti; + end + default: begin + comb_rhs_array_muxed44 <= pcie_bridge_wishbone_cti; + end + endcase +end +always @(*) begin + comb_rhs_array_muxed45 <= 2'd0; + case (grant) + 1'd0: begin + comb_rhs_array_muxed45 <= netv2_cpu_ibus_bte; + end + 1'd1: begin + comb_rhs_array_muxed45 <= netv2_cpu_dbus_bte; + end + 2'd2: begin + comb_rhs_array_muxed45 <= etherbone_liteethetherbonewishbonemaster_bus_bte; + end + default: begin + comb_rhs_array_muxed45 <= pcie_bridge_wishbone_bte; + end + endcase +end +always @(*) begin + sync_rhs_array_muxed0 <= 10'd0; + case (hdmi_out0_driver_hdmi_phy_es0_new_c2) + 1'd0: begin + sync_rhs_array_muxed0 <= 10'd852; + end + 1'd1: begin + sync_rhs_array_muxed0 <= 8'd171; + end + 2'd2: begin + sync_rhs_array_muxed0 <= 9'd340; + end + default: begin + sync_rhs_array_muxed0 <= 10'd683; + end + endcase +end +always @(*) begin + sync_rhs_array_muxed1 <= 10'd0; + case (hdmi_out0_driver_hdmi_phy_es1_new_c2) + 1'd0: begin + sync_rhs_array_muxed1 <= 10'd852; + end + 1'd1: begin + sync_rhs_array_muxed1 <= 8'd171; + end + 2'd2: begin + sync_rhs_array_muxed1 <= 9'd340; + end + default: begin + sync_rhs_array_muxed1 <= 10'd683; + end + endcase +end +always @(*) begin + sync_rhs_array_muxed2 <= 10'd0; + case (hdmi_out0_driver_hdmi_phy_es2_new_c2) + 1'd0: begin + sync_rhs_array_muxed2 <= 10'd852; + end + 1'd1: begin + sync_rhs_array_muxed2 <= 8'd171; + end + 2'd2: begin + sync_rhs_array_muxed2 <= 9'd340; + end + default: begin + sync_rhs_array_muxed2 <= 10'd683; + end + endcase +end +always @(*) begin + sync_t_array_muxed <= 1'd0; + case (flash_mosi_sel) + 1'd0: begin + sync_t_array_muxed <= flash_mosi_data[0]; + end + 1'd1: begin + sync_t_array_muxed <= flash_mosi_data[1]; + end + 2'd2: begin + sync_t_array_muxed <= flash_mosi_data[2]; + end + 2'd3: begin + sync_t_array_muxed <= flash_mosi_data[3]; + end + 3'd4: begin + sync_t_array_muxed <= flash_mosi_data[4]; + end + 3'd5: begin + sync_t_array_muxed <= flash_mosi_data[5]; + end + 3'd6: begin + sync_t_array_muxed <= flash_mosi_data[6]; + end + 3'd7: begin + sync_t_array_muxed <= flash_mosi_data[7]; + end + 4'd8: begin + sync_t_array_muxed <= flash_mosi_data[8]; + end + 4'd9: begin + sync_t_array_muxed <= flash_mosi_data[9]; + end + 4'd10: begin + sync_t_array_muxed <= flash_mosi_data[10]; + end + 4'd11: begin + sync_t_array_muxed <= flash_mosi_data[11]; + end + 4'd12: begin + sync_t_array_muxed <= flash_mosi_data[12]; + end + 4'd13: begin + sync_t_array_muxed <= flash_mosi_data[13]; + end + 4'd14: begin + sync_t_array_muxed <= flash_mosi_data[14]; + end + 4'd15: begin + sync_t_array_muxed <= flash_mosi_data[15]; + end + 5'd16: begin + sync_t_array_muxed <= flash_mosi_data[16]; + end + 5'd17: begin + sync_t_array_muxed <= flash_mosi_data[17]; + end + 5'd18: begin + sync_t_array_muxed <= flash_mosi_data[18]; + end + 5'd19: begin + sync_t_array_muxed <= flash_mosi_data[19]; + end + 5'd20: begin + sync_t_array_muxed <= flash_mosi_data[20]; + end + 5'd21: begin + sync_t_array_muxed <= flash_mosi_data[21]; + end + 5'd22: begin + sync_t_array_muxed <= flash_mosi_data[22]; + end + 5'd23: begin + sync_t_array_muxed <= flash_mosi_data[23]; + end + 5'd24: begin + sync_t_array_muxed <= flash_mosi_data[24]; + end + 5'd25: begin + sync_t_array_muxed <= flash_mosi_data[25]; + end + 5'd26: begin + sync_t_array_muxed <= flash_mosi_data[26]; + end + 5'd27: begin + sync_t_array_muxed <= flash_mosi_data[27]; + end + 5'd28: begin + sync_t_array_muxed <= flash_mosi_data[28]; + end + 5'd29: begin + sync_t_array_muxed <= flash_mosi_data[29]; + end + 5'd30: begin + sync_t_array_muxed <= flash_mosi_data[30]; + end + 5'd31: begin + sync_t_array_muxed <= flash_mosi_data[31]; + end + 6'd32: begin + sync_t_array_muxed <= flash_mosi_data[32]; + end + 6'd33: begin + sync_t_array_muxed <= flash_mosi_data[33]; + end + 6'd34: begin + sync_t_array_muxed <= flash_mosi_data[34]; + end + 6'd35: begin + sync_t_array_muxed <= flash_mosi_data[35]; + end + 6'd36: begin + sync_t_array_muxed <= flash_mosi_data[36]; + end + 6'd37: begin + sync_t_array_muxed <= flash_mosi_data[37]; + end + 6'd38: begin + sync_t_array_muxed <= flash_mosi_data[38]; + end + default: begin + sync_t_array_muxed <= flash_mosi_data[39]; + end + endcase +end +always @(*) begin + sync_array_muxed0 <= 3'd0; + case (netv2_sdram_steerer_sel0) + 1'd0: begin + sync_array_muxed0 <= netv2_sdram_nop_ba[2:0]; + end + 1'd1: begin + sync_array_muxed0 <= netv2_sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + sync_array_muxed0 <= netv2_sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + sync_array_muxed0 <= netv2_sdram_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + sync_array_muxed1 <= 14'd0; + case (netv2_sdram_steerer_sel0) + 1'd0: begin + sync_array_muxed1 <= netv2_sdram_nop_a; + end + 1'd1: begin + sync_array_muxed1 <= netv2_sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + sync_array_muxed1 <= netv2_sdram_choose_req_cmd_payload_a; + end + default: begin + sync_array_muxed1 <= netv2_sdram_cmd_payload_a; + end + endcase +end +always @(*) begin + sync_array_muxed2 <= 1'd0; + case (netv2_sdram_steerer_sel0) + 1'd0: begin + sync_array_muxed2 <= 1'd0; + end + 1'd1: begin + sync_array_muxed2 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + sync_array_muxed2 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_cas); + end + default: begin + sync_array_muxed2 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_cas); + end + endcase +end +always @(*) begin + sync_array_muxed3 <= 1'd0; + case (netv2_sdram_steerer_sel0) + 1'd0: begin + sync_array_muxed3 <= 1'd0; + end + 1'd1: begin + sync_array_muxed3 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + sync_array_muxed3 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_ras); + end + default: begin + sync_array_muxed3 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_ras); + end + endcase +end +always @(*) begin + sync_array_muxed4 <= 1'd0; + case (netv2_sdram_steerer_sel0) + 1'd0: begin + sync_array_muxed4 <= 1'd0; + end + 1'd1: begin + sync_array_muxed4 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + sync_array_muxed4 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_we); + end + default: begin + sync_array_muxed4 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_we); + end + endcase +end +always @(*) begin + sync_array_muxed5 <= 1'd0; + case (netv2_sdram_steerer_sel0) + 1'd0: begin + sync_array_muxed5 <= 1'd0; + end + 1'd1: begin + sync_array_muxed5 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + sync_array_muxed5 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_is_read); + end + default: begin + sync_array_muxed5 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_is_read); + end + endcase +end +always @(*) begin + sync_array_muxed6 <= 1'd0; + case (netv2_sdram_steerer_sel0) + 1'd0: begin + sync_array_muxed6 <= 1'd0; + end + 1'd1: begin + sync_array_muxed6 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + sync_array_muxed6 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_is_write); + end + default: begin + sync_array_muxed6 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_is_write); + end + endcase +end +always @(*) begin + sync_array_muxed7 <= 3'd0; + case (netv2_sdram_steerer_sel1) + 1'd0: begin + sync_array_muxed7 <= netv2_sdram_nop_ba[2:0]; + end + 1'd1: begin + sync_array_muxed7 <= netv2_sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + sync_array_muxed7 <= netv2_sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + sync_array_muxed7 <= netv2_sdram_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + sync_array_muxed8 <= 14'd0; + case (netv2_sdram_steerer_sel1) + 1'd0: begin + sync_array_muxed8 <= netv2_sdram_nop_a; + end + 1'd1: begin + sync_array_muxed8 <= netv2_sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + sync_array_muxed8 <= netv2_sdram_choose_req_cmd_payload_a; + end + default: begin + sync_array_muxed8 <= netv2_sdram_cmd_payload_a; + end + endcase +end +always @(*) begin + sync_array_muxed9 <= 1'd0; + case (netv2_sdram_steerer_sel1) + 1'd0: begin + sync_array_muxed9 <= 1'd0; + end + 1'd1: begin + sync_array_muxed9 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + sync_array_muxed9 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_cas); + end + default: begin + sync_array_muxed9 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_cas); + end + endcase +end +always @(*) begin + sync_array_muxed10 <= 1'd0; + case (netv2_sdram_steerer_sel1) + 1'd0: begin + sync_array_muxed10 <= 1'd0; + end + 1'd1: begin + sync_array_muxed10 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + sync_array_muxed10 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_ras); + end + default: begin + sync_array_muxed10 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_ras); + end + endcase +end +always @(*) begin + sync_array_muxed11 <= 1'd0; + case (netv2_sdram_steerer_sel1) + 1'd0: begin + sync_array_muxed11 <= 1'd0; + end + 1'd1: begin + sync_array_muxed11 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + sync_array_muxed11 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_we); + end + default: begin + sync_array_muxed11 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_we); + end + endcase +end +always @(*) begin + sync_array_muxed12 <= 1'd0; + case (netv2_sdram_steerer_sel1) + 1'd0: begin + sync_array_muxed12 <= 1'd0; + end + 1'd1: begin + sync_array_muxed12 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + sync_array_muxed12 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_is_read); + end + default: begin + sync_array_muxed12 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_is_read); + end + endcase +end +always @(*) begin + sync_array_muxed13 <= 1'd0; + case (netv2_sdram_steerer_sel1) + 1'd0: begin + sync_array_muxed13 <= 1'd0; + end + 1'd1: begin + sync_array_muxed13 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + sync_array_muxed13 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_is_write); + end + default: begin + sync_array_muxed13 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_is_write); + end + endcase +end +always @(*) begin + sync_array_muxed14 <= 3'd0; + case (netv2_sdram_steerer_sel2) + 1'd0: begin + sync_array_muxed14 <= netv2_sdram_nop_ba[2:0]; + end + 1'd1: begin + sync_array_muxed14 <= netv2_sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + sync_array_muxed14 <= netv2_sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + sync_array_muxed14 <= netv2_sdram_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + sync_array_muxed15 <= 14'd0; + case (netv2_sdram_steerer_sel2) + 1'd0: begin + sync_array_muxed15 <= netv2_sdram_nop_a; + end + 1'd1: begin + sync_array_muxed15 <= netv2_sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + sync_array_muxed15 <= netv2_sdram_choose_req_cmd_payload_a; + end + default: begin + sync_array_muxed15 <= netv2_sdram_cmd_payload_a; + end + endcase +end +always @(*) begin + sync_array_muxed16 <= 1'd0; + case (netv2_sdram_steerer_sel2) + 1'd0: begin + sync_array_muxed16 <= 1'd0; + end + 1'd1: begin + sync_array_muxed16 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + sync_array_muxed16 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_cas); + end + default: begin + sync_array_muxed16 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_cas); + end + endcase +end +always @(*) begin + sync_array_muxed17 <= 1'd0; + case (netv2_sdram_steerer_sel2) + 1'd0: begin + sync_array_muxed17 <= 1'd0; + end + 1'd1: begin + sync_array_muxed17 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + sync_array_muxed17 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_ras); + end + default: begin + sync_array_muxed17 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_ras); + end + endcase +end +always @(*) begin + sync_array_muxed18 <= 1'd0; + case (netv2_sdram_steerer_sel2) + 1'd0: begin + sync_array_muxed18 <= 1'd0; + end + 1'd1: begin + sync_array_muxed18 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + sync_array_muxed18 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_we); + end + default: begin + sync_array_muxed18 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_we); + end + endcase +end +always @(*) begin + sync_array_muxed19 <= 1'd0; + case (netv2_sdram_steerer_sel2) + 1'd0: begin + sync_array_muxed19 <= 1'd0; + end + 1'd1: begin + sync_array_muxed19 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + sync_array_muxed19 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_is_read); + end + default: begin + sync_array_muxed19 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_is_read); + end + endcase +end +always @(*) begin + sync_array_muxed20 <= 1'd0; + case (netv2_sdram_steerer_sel2) + 1'd0: begin + sync_array_muxed20 <= 1'd0; + end + 1'd1: begin + sync_array_muxed20 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + sync_array_muxed20 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_is_write); + end + default: begin + sync_array_muxed20 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_is_write); + end + endcase +end +always @(*) begin + sync_array_muxed21 <= 3'd0; + case (netv2_sdram_steerer_sel3) + 1'd0: begin + sync_array_muxed21 <= netv2_sdram_nop_ba[2:0]; + end + 1'd1: begin + sync_array_muxed21 <= netv2_sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + sync_array_muxed21 <= netv2_sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + sync_array_muxed21 <= netv2_sdram_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + sync_array_muxed22 <= 14'd0; + case (netv2_sdram_steerer_sel3) + 1'd0: begin + sync_array_muxed22 <= netv2_sdram_nop_a; + end + 1'd1: begin + sync_array_muxed22 <= netv2_sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + sync_array_muxed22 <= netv2_sdram_choose_req_cmd_payload_a; + end + default: begin + sync_array_muxed22 <= netv2_sdram_cmd_payload_a; + end + endcase +end +always @(*) begin + sync_array_muxed23 <= 1'd0; + case (netv2_sdram_steerer_sel3) + 1'd0: begin + sync_array_muxed23 <= 1'd0; + end + 1'd1: begin + sync_array_muxed23 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + sync_array_muxed23 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_cas); + end + default: begin + sync_array_muxed23 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_cas); + end + endcase +end +always @(*) begin + sync_array_muxed24 <= 1'd0; + case (netv2_sdram_steerer_sel3) + 1'd0: begin + sync_array_muxed24 <= 1'd0; + end + 1'd1: begin + sync_array_muxed24 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + sync_array_muxed24 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_ras); + end + default: begin + sync_array_muxed24 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_ras); + end + endcase +end +always @(*) begin + sync_array_muxed25 <= 1'd0; + case (netv2_sdram_steerer_sel3) + 1'd0: begin + sync_array_muxed25 <= 1'd0; + end + 1'd1: begin + sync_array_muxed25 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + sync_array_muxed25 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_we); + end + default: begin + sync_array_muxed25 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_we); + end + endcase +end +always @(*) begin + sync_array_muxed26 <= 1'd0; + case (netv2_sdram_steerer_sel3) + 1'd0: begin + sync_array_muxed26 <= 1'd0; + end + 1'd1: begin + sync_array_muxed26 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + sync_array_muxed26 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_is_read); + end + default: begin + sync_array_muxed26 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_is_read); + end + endcase +end +always @(*) begin + sync_array_muxed27 <= 1'd0; + case (netv2_sdram_steerer_sel3) + 1'd0: begin + sync_array_muxed27 <= 1'd0; + end + 1'd1: begin + sync_array_muxed27 <= ((netv2_sdram_choose_cmd_cmd_valid & netv2_sdram_choose_cmd_cmd_ready) & netv2_sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + sync_array_muxed27 <= ((netv2_sdram_choose_req_cmd_valid & netv2_sdram_choose_req_cmd_ready) & netv2_sdram_choose_req_cmd_payload_is_write); + end + default: begin + sync_array_muxed27 <= ((netv2_sdram_cmd_valid & netv2_sdram_cmd_ready) & netv2_sdram_cmd_payload_is_write); + end + endcase +end +assign xilinxasyncresetsynchronizerimpl0 = ((~crg_locked) | crg_reset); +assign xilinxasyncresetsynchronizerimpl1 = ((~crg_locked) | crg_reset); +assign xilinxasyncresetsynchronizerimpl2 = ((~crg_locked) | crg_reset); +assign xilinxasyncresetsynchronizerimpl3 = ((~crg_locked) | crg_reset); +assign xilinxasyncresetsynchronizerimpl4 = ((~crg_locked) | crg_reset); +assign xilinxasyncresetsynchronizerimpl5 = ((~crg_locked) | crg_reset); +assign icap_toggle_o = xilinxmultiregimpl0_regs1; +assign ethphy_liteethphyrmiirx_converter_sink_valid0 = xilinxmultiregimpl1_regs1; +assign ethphy_liteethphyrmiirx_converter_sink_payload_data = xilinxmultiregimpl2_regs1; +always @(*) begin + ethphy__r_status <= 1'd0; + ethphy__r_status <= ethphy_r; + ethphy__r_status <= xilinxmultiregimpl3_regs1; +end +assign ethcore_mac_ps_preamble_error_toggle_o = xilinxmultiregimpl4_regs1; +assign ethcore_mac_ps_crc_error_toggle_o = xilinxmultiregimpl5_regs1; +assign ethcore_mac_tx_cdc_produce_rdomain = xilinxmultiregimpl6_regs1; +assign ethcore_mac_tx_cdc_consume_wdomain = xilinxmultiregimpl7_regs1; +assign ethcore_mac_rx_cdc_produce_rdomain = xilinxmultiregimpl8_regs1; +assign ethcore_mac_rx_cdc_consume_wdomain = xilinxmultiregimpl9_regs1; +assign s7pciephy_tx_datapath_cdc_produce_rdomain = xilinxmultiregimpl10_regs1; +assign s7pciephy_tx_datapath_cdc_consume_wdomain = xilinxmultiregimpl11_regs1; +assign s7pciephy_rx_datapath_cdc_produce_rdomain = xilinxmultiregimpl12_regs1; +assign s7pciephy_rx_datapath_cdc_consume_wdomain = xilinxmultiregimpl13_regs1; +assign s7pciephy_msi_cdc_produce_rdomain = xilinxmultiregimpl14_regs1; +assign s7pciephy_msi_cdc_consume_wdomain = xilinxmultiregimpl15_regs1; +assign s7pciephy_bus_master_enable_status = xilinxmultiregimpl16_regs1; +assign xilinxmultiregimpl16 = s7pciephy_command[2]; +assign s7pciephy_max_request_size_status = xilinxmultiregimpl17_regs1; +assign s7pciephy_max_payload_size_status = xilinxmultiregimpl18_regs1; +assign freqmeter_gray_decoder_i = xilinxmultiregimpl19_regs1; +assign hdmi_in0_scl_raw = xilinxmultiregimpl20_regs1; +assign xilinxmultiregimpl20 = (~hdmi_in0_scl); +assign hdmi_in0_sda_raw = xilinxmultiregimpl21_regs1; +assign xilinxmultiregimpl21 = (~hdmi_in0_sda); +assign hdmi_in0_locked = xilinxmultiregimpl22_regs1; +assign xilinxasyncresetsynchronizerimpl8 = (~hdmi_in0_mmcm_locked); +assign xilinxasyncresetsynchronizerimpl9 = (~hdmi_in0_mmcm_locked); +assign xilinxasyncresetsynchronizerimpl10 = (~hdmi_in0_mmcm_locked_o); +assign hdmi_in0_s7datacapture0_sync_mcntvalue_ping_toggle_o = xilinxmultiregimpl23_regs1; +assign hdmi_in0_s7datacapture0_sync_mcntvalue_pong_toggle_o = xilinxmultiregimpl24_regs1; +assign hdmi_in0_s7datacapture0_sync_mcntvalue_obuffer = xilinxmultiregimpl25_regs1; +assign hdmi_in0_s7datacapture0_sync_scntvalue_ping_toggle_o = xilinxmultiregimpl26_regs1; +assign hdmi_in0_s7datacapture0_sync_scntvalue_pong_toggle_o = xilinxmultiregimpl27_regs1; +assign hdmi_in0_s7datacapture0_sync_scntvalue_obuffer = xilinxmultiregimpl28_regs1; +assign hdmi_in0_s7datacapture0_do_delay_rst_toggle_o = xilinxmultiregimpl29_regs1; +assign hdmi_in0_s7datacapture0_do_delay_master_inc_toggle_o = xilinxmultiregimpl30_regs1; +assign hdmi_in0_s7datacapture0_do_delay_master_dec_toggle_o = xilinxmultiregimpl31_regs1; +assign hdmi_in0_s7datacapture0_do_delay_slave_inc_toggle_o = xilinxmultiregimpl32_regs1; +assign hdmi_in0_s7datacapture0_do_delay_slave_dec_toggle_o = xilinxmultiregimpl33_regs1; +assign hdmi_in0_s7datacapture0_phase_status = xilinxmultiregimpl34_regs1; +assign xilinxmultiregimpl34 = {hdmi_in0_s7datacapture0_too_early, hdmi_in0_s7datacapture0_too_late}; +assign hdmi_in0_s7datacapture0_do_reset_lateness_toggle_o = xilinxmultiregimpl35_regs1; +assign hdmi_in0_charsync0_char_synced_status = xilinxmultiregimpl36_regs1; +assign hdmi_in0_charsync0_ctl_pos_status = xilinxmultiregimpl37_regs1; +assign hdmi_in0_wer0_toggle_o = xilinxmultiregimpl38_regs1; +assign hdmi_in0_s7datacapture1_sync_mcntvalue_ping_toggle_o = xilinxmultiregimpl39_regs1; +assign hdmi_in0_s7datacapture1_sync_mcntvalue_pong_toggle_o = xilinxmultiregimpl40_regs1; +assign hdmi_in0_s7datacapture1_sync_mcntvalue_obuffer = xilinxmultiregimpl41_regs1; +assign hdmi_in0_s7datacapture1_sync_scntvalue_ping_toggle_o = xilinxmultiregimpl42_regs1; +assign hdmi_in0_s7datacapture1_sync_scntvalue_pong_toggle_o = xilinxmultiregimpl43_regs1; +assign hdmi_in0_s7datacapture1_sync_scntvalue_obuffer = xilinxmultiregimpl44_regs1; +assign hdmi_in0_s7datacapture1_do_delay_rst_toggle_o = xilinxmultiregimpl45_regs1; +assign hdmi_in0_s7datacapture1_do_delay_master_inc_toggle_o = xilinxmultiregimpl46_regs1; +assign hdmi_in0_s7datacapture1_do_delay_master_dec_toggle_o = xilinxmultiregimpl47_regs1; +assign hdmi_in0_s7datacapture1_do_delay_slave_inc_toggle_o = xilinxmultiregimpl48_regs1; +assign hdmi_in0_s7datacapture1_do_delay_slave_dec_toggle_o = xilinxmultiregimpl49_regs1; +assign hdmi_in0_s7datacapture1_phase_status = xilinxmultiregimpl50_regs1; +assign xilinxmultiregimpl50 = {hdmi_in0_s7datacapture1_too_early, hdmi_in0_s7datacapture1_too_late}; +assign hdmi_in0_s7datacapture1_do_reset_lateness_toggle_o = xilinxmultiregimpl51_regs1; +assign hdmi_in0_charsync1_char_synced_status = xilinxmultiregimpl52_regs1; +assign hdmi_in0_charsync1_ctl_pos_status = xilinxmultiregimpl53_regs1; +assign hdmi_in0_wer1_toggle_o = xilinxmultiregimpl54_regs1; +assign hdmi_in0_s7datacapture2_sync_mcntvalue_ping_toggle_o = xilinxmultiregimpl55_regs1; +assign hdmi_in0_s7datacapture2_sync_mcntvalue_pong_toggle_o = xilinxmultiregimpl56_regs1; +assign hdmi_in0_s7datacapture2_sync_mcntvalue_obuffer = xilinxmultiregimpl57_regs1; +assign hdmi_in0_s7datacapture2_sync_scntvalue_ping_toggle_o = xilinxmultiregimpl58_regs1; +assign hdmi_in0_s7datacapture2_sync_scntvalue_pong_toggle_o = xilinxmultiregimpl59_regs1; +assign hdmi_in0_s7datacapture2_sync_scntvalue_obuffer = xilinxmultiregimpl60_regs1; +assign hdmi_in0_s7datacapture2_do_delay_rst_toggle_o = xilinxmultiregimpl61_regs1; +assign hdmi_in0_s7datacapture2_do_delay_master_inc_toggle_o = xilinxmultiregimpl62_regs1; +assign hdmi_in0_s7datacapture2_do_delay_master_dec_toggle_o = xilinxmultiregimpl63_regs1; +assign hdmi_in0_s7datacapture2_do_delay_slave_inc_toggle_o = xilinxmultiregimpl64_regs1; +assign hdmi_in0_s7datacapture2_do_delay_slave_dec_toggle_o = xilinxmultiregimpl65_regs1; +assign hdmi_in0_s7datacapture2_phase_status = xilinxmultiregimpl66_regs1; +assign xilinxmultiregimpl66 = {hdmi_in0_s7datacapture2_too_early, hdmi_in0_s7datacapture2_too_late}; +assign hdmi_in0_s7datacapture2_do_reset_lateness_toggle_o = xilinxmultiregimpl67_regs1; +assign hdmi_in0_charsync2_char_synced_status = xilinxmultiregimpl68_regs1; +assign hdmi_in0_charsync2_ctl_pos_status = xilinxmultiregimpl69_regs1; +assign hdmi_in0_wer2_toggle_o = xilinxmultiregimpl70_regs1; +assign hdmi_in0_chansync_status = xilinxmultiregimpl71_regs1; +assign hdmi_in0_resdetection_hres_status = xilinxmultiregimpl72_regs1; +assign hdmi_in0_resdetection_vres_status = xilinxmultiregimpl73_regs1; +assign hdmi_in0_frame_fifo_produce_rdomain = xilinxmultiregimpl74_regs1; +assign hdmi_in0_frame_fifo_consume_wdomain = xilinxmultiregimpl75_regs1; +assign hdmi_in0_frame_sys_overflow = xilinxmultiregimpl76_regs1; +assign hdmi_in0_frame_overflow_reset_toggle_o = xilinxmultiregimpl77_regs1; +assign hdmi_in0_frame_overflow_reset_ack_toggle_o = xilinxmultiregimpl78_regs1; +assign litedramcrossbar_cmd_cdc_cdc_produce_rdomain = xilinxmultiregimpl79_regs1; +assign litedramcrossbar_cmd_cdc_cdc_consume_wdomain = xilinxmultiregimpl80_regs1; +assign litedramcrossbar_rdata_cdc_cdc_produce_rdomain = xilinxmultiregimpl81_regs1; +assign litedramcrossbar_rdata_cdc_cdc_consume_wdomain = xilinxmultiregimpl82_regs1; +assign hdmi_out0_core_initiator_cdc_produce_rdomain = xilinxmultiregimpl83_regs1; +assign hdmi_out0_core_initiator_cdc_consume_wdomain = xilinxmultiregimpl84_regs1; +assign hdmi_out0_core_underflow_enable = xilinxmultiregimpl85_regs1; +assign hdmi_out0_core_toggle_o = xilinxmultiregimpl86_regs1; + +always @(posedge clk200_clk) begin + if ((crg_reset_counter != 1'd0)) begin + crg_reset_counter <= (crg_reset_counter - 1'd1); + end else begin + crg_ic_reset <= 1'd0; + end + if (clk200_rst) begin + crg_reset_counter <= 4'd15; + crg_ic_reset <= 1'd1; + end +end + +always @(posedge data0_cap_read_clk) begin + if ((hdmi_in0_s7datacapture0_gearbox_rdpointer == 3'd7)) begin + hdmi_in0_s7datacapture0_gearbox_rdpointer <= 1'd0; + end else begin + hdmi_in0_s7datacapture0_gearbox_rdpointer <= (hdmi_in0_s7datacapture0_gearbox_rdpointer + 1'd1); + end + case (hdmi_in0_s7datacapture0_gearbox_rdpointer) + 1'd0: begin + hdmi_in0_s7datacapture0_gearbox_o <= hdmi_in0_s7datacapture0_gearbox_storage[9:0]; + end + 1'd1: begin + hdmi_in0_s7datacapture0_gearbox_o <= hdmi_in0_s7datacapture0_gearbox_storage[19:10]; + end + 2'd2: begin + hdmi_in0_s7datacapture0_gearbox_o <= hdmi_in0_s7datacapture0_gearbox_storage[29:20]; + end + 2'd3: begin + hdmi_in0_s7datacapture0_gearbox_o <= hdmi_in0_s7datacapture0_gearbox_storage[39:30]; + end + 3'd4: begin + hdmi_in0_s7datacapture0_gearbox_o <= hdmi_in0_s7datacapture0_gearbox_storage[49:40]; + end + 3'd5: begin + hdmi_in0_s7datacapture0_gearbox_o <= hdmi_in0_s7datacapture0_gearbox_storage[59:50]; + end + 3'd6: begin + hdmi_in0_s7datacapture0_gearbox_o <= hdmi_in0_s7datacapture0_gearbox_storage[69:60]; + end + 3'd7: begin + hdmi_in0_s7datacapture0_gearbox_o <= hdmi_in0_s7datacapture0_gearbox_storage[79:70]; + end + endcase + if (data0_cap_read_rst) begin + hdmi_in0_s7datacapture0_gearbox_rdpointer <= 3'd0; + end +end + +always @(posedge data0_cap_write_clk) begin + if ((hdmi_in0_s7datacapture0_gearbox_wrpointer == 4'd9)) begin + hdmi_in0_s7datacapture0_gearbox_wrpointer <= 1'd0; + end else begin + hdmi_in0_s7datacapture0_gearbox_wrpointer <= (hdmi_in0_s7datacapture0_gearbox_wrpointer + 1'd1); + end + case (hdmi_in0_s7datacapture0_gearbox_wrpointer) + 1'd0: begin + hdmi_in0_s7datacapture0_gearbox_storage[7:0] <= hdmi_in0_s7datacapture0_gearbox_i; + end + 1'd1: begin + hdmi_in0_s7datacapture0_gearbox_storage[15:8] <= hdmi_in0_s7datacapture0_gearbox_i; + end + 2'd2: begin + hdmi_in0_s7datacapture0_gearbox_storage[23:16] <= hdmi_in0_s7datacapture0_gearbox_i; + end + 2'd3: begin + hdmi_in0_s7datacapture0_gearbox_storage[31:24] <= hdmi_in0_s7datacapture0_gearbox_i; + end + 3'd4: begin + hdmi_in0_s7datacapture0_gearbox_storage[39:32] <= hdmi_in0_s7datacapture0_gearbox_i; + end + 3'd5: begin + hdmi_in0_s7datacapture0_gearbox_storage[47:40] <= hdmi_in0_s7datacapture0_gearbox_i; + end + 3'd6: begin + hdmi_in0_s7datacapture0_gearbox_storage[55:48] <= hdmi_in0_s7datacapture0_gearbox_i; + end + 3'd7: begin + hdmi_in0_s7datacapture0_gearbox_storage[63:56] <= hdmi_in0_s7datacapture0_gearbox_i; + end + 4'd8: begin + hdmi_in0_s7datacapture0_gearbox_storage[71:64] <= hdmi_in0_s7datacapture0_gearbox_i; + end + 4'd9: begin + hdmi_in0_s7datacapture0_gearbox_storage[79:72] <= hdmi_in0_s7datacapture0_gearbox_i; + end + endcase + if (data0_cap_write_rst) begin + hdmi_in0_s7datacapture0_gearbox_wrpointer <= 4'd5; + end +end + +always @(posedge data1_cap_read_clk) begin + if ((hdmi_in0_s7datacapture1_gearbox_rdpointer == 3'd7)) begin + hdmi_in0_s7datacapture1_gearbox_rdpointer <= 1'd0; + end else begin + hdmi_in0_s7datacapture1_gearbox_rdpointer <= (hdmi_in0_s7datacapture1_gearbox_rdpointer + 1'd1); + end + case (hdmi_in0_s7datacapture1_gearbox_rdpointer) + 1'd0: begin + hdmi_in0_s7datacapture1_gearbox_o <= hdmi_in0_s7datacapture1_gearbox_storage[9:0]; + end + 1'd1: begin + hdmi_in0_s7datacapture1_gearbox_o <= hdmi_in0_s7datacapture1_gearbox_storage[19:10]; + end + 2'd2: begin + hdmi_in0_s7datacapture1_gearbox_o <= hdmi_in0_s7datacapture1_gearbox_storage[29:20]; + end + 2'd3: begin + hdmi_in0_s7datacapture1_gearbox_o <= hdmi_in0_s7datacapture1_gearbox_storage[39:30]; + end + 3'd4: begin + hdmi_in0_s7datacapture1_gearbox_o <= hdmi_in0_s7datacapture1_gearbox_storage[49:40]; + end + 3'd5: begin + hdmi_in0_s7datacapture1_gearbox_o <= hdmi_in0_s7datacapture1_gearbox_storage[59:50]; + end + 3'd6: begin + hdmi_in0_s7datacapture1_gearbox_o <= hdmi_in0_s7datacapture1_gearbox_storage[69:60]; + end + 3'd7: begin + hdmi_in0_s7datacapture1_gearbox_o <= hdmi_in0_s7datacapture1_gearbox_storage[79:70]; + end + endcase + if (data1_cap_read_rst) begin + hdmi_in0_s7datacapture1_gearbox_rdpointer <= 3'd0; + end +end + +always @(posedge data1_cap_write_clk) begin + if ((hdmi_in0_s7datacapture1_gearbox_wrpointer == 4'd9)) begin + hdmi_in0_s7datacapture1_gearbox_wrpointer <= 1'd0; + end else begin + hdmi_in0_s7datacapture1_gearbox_wrpointer <= (hdmi_in0_s7datacapture1_gearbox_wrpointer + 1'd1); + end + case (hdmi_in0_s7datacapture1_gearbox_wrpointer) + 1'd0: begin + hdmi_in0_s7datacapture1_gearbox_storage[7:0] <= hdmi_in0_s7datacapture1_gearbox_i; + end + 1'd1: begin + hdmi_in0_s7datacapture1_gearbox_storage[15:8] <= hdmi_in0_s7datacapture1_gearbox_i; + end + 2'd2: begin + hdmi_in0_s7datacapture1_gearbox_storage[23:16] <= hdmi_in0_s7datacapture1_gearbox_i; + end + 2'd3: begin + hdmi_in0_s7datacapture1_gearbox_storage[31:24] <= hdmi_in0_s7datacapture1_gearbox_i; + end + 3'd4: begin + hdmi_in0_s7datacapture1_gearbox_storage[39:32] <= hdmi_in0_s7datacapture1_gearbox_i; + end + 3'd5: begin + hdmi_in0_s7datacapture1_gearbox_storage[47:40] <= hdmi_in0_s7datacapture1_gearbox_i; + end + 3'd6: begin + hdmi_in0_s7datacapture1_gearbox_storage[55:48] <= hdmi_in0_s7datacapture1_gearbox_i; + end + 3'd7: begin + hdmi_in0_s7datacapture1_gearbox_storage[63:56] <= hdmi_in0_s7datacapture1_gearbox_i; + end + 4'd8: begin + hdmi_in0_s7datacapture1_gearbox_storage[71:64] <= hdmi_in0_s7datacapture1_gearbox_i; + end + 4'd9: begin + hdmi_in0_s7datacapture1_gearbox_storage[79:72] <= hdmi_in0_s7datacapture1_gearbox_i; + end + endcase + if (data1_cap_write_rst) begin + hdmi_in0_s7datacapture1_gearbox_wrpointer <= 4'd5; + end +end + +always @(posedge data2_cap_read_clk) begin + if ((hdmi_in0_s7datacapture2_gearbox_rdpointer == 3'd7)) begin + hdmi_in0_s7datacapture2_gearbox_rdpointer <= 1'd0; + end else begin + hdmi_in0_s7datacapture2_gearbox_rdpointer <= (hdmi_in0_s7datacapture2_gearbox_rdpointer + 1'd1); + end + case (hdmi_in0_s7datacapture2_gearbox_rdpointer) + 1'd0: begin + hdmi_in0_s7datacapture2_gearbox_o <= hdmi_in0_s7datacapture2_gearbox_storage[9:0]; + end + 1'd1: begin + hdmi_in0_s7datacapture2_gearbox_o <= hdmi_in0_s7datacapture2_gearbox_storage[19:10]; + end + 2'd2: begin + hdmi_in0_s7datacapture2_gearbox_o <= hdmi_in0_s7datacapture2_gearbox_storage[29:20]; + end + 2'd3: begin + hdmi_in0_s7datacapture2_gearbox_o <= hdmi_in0_s7datacapture2_gearbox_storage[39:30]; + end + 3'd4: begin + hdmi_in0_s7datacapture2_gearbox_o <= hdmi_in0_s7datacapture2_gearbox_storage[49:40]; + end + 3'd5: begin + hdmi_in0_s7datacapture2_gearbox_o <= hdmi_in0_s7datacapture2_gearbox_storage[59:50]; + end + 3'd6: begin + hdmi_in0_s7datacapture2_gearbox_o <= hdmi_in0_s7datacapture2_gearbox_storage[69:60]; + end + 3'd7: begin + hdmi_in0_s7datacapture2_gearbox_o <= hdmi_in0_s7datacapture2_gearbox_storage[79:70]; + end + endcase + if (data2_cap_read_rst) begin + hdmi_in0_s7datacapture2_gearbox_rdpointer <= 3'd0; + end +end + +always @(posedge data2_cap_write_clk) begin + if ((hdmi_in0_s7datacapture2_gearbox_wrpointer == 4'd9)) begin + hdmi_in0_s7datacapture2_gearbox_wrpointer <= 1'd0; + end else begin + hdmi_in0_s7datacapture2_gearbox_wrpointer <= (hdmi_in0_s7datacapture2_gearbox_wrpointer + 1'd1); + end + case (hdmi_in0_s7datacapture2_gearbox_wrpointer) + 1'd0: begin + hdmi_in0_s7datacapture2_gearbox_storage[7:0] <= hdmi_in0_s7datacapture2_gearbox_i; + end + 1'd1: begin + hdmi_in0_s7datacapture2_gearbox_storage[15:8] <= hdmi_in0_s7datacapture2_gearbox_i; + end + 2'd2: begin + hdmi_in0_s7datacapture2_gearbox_storage[23:16] <= hdmi_in0_s7datacapture2_gearbox_i; + end + 2'd3: begin + hdmi_in0_s7datacapture2_gearbox_storage[31:24] <= hdmi_in0_s7datacapture2_gearbox_i; + end + 3'd4: begin + hdmi_in0_s7datacapture2_gearbox_storage[39:32] <= hdmi_in0_s7datacapture2_gearbox_i; + end + 3'd5: begin + hdmi_in0_s7datacapture2_gearbox_storage[47:40] <= hdmi_in0_s7datacapture2_gearbox_i; + end + 3'd6: begin + hdmi_in0_s7datacapture2_gearbox_storage[55:48] <= hdmi_in0_s7datacapture2_gearbox_i; + end + 3'd7: begin + hdmi_in0_s7datacapture2_gearbox_storage[63:56] <= hdmi_in0_s7datacapture2_gearbox_i; + end + 4'd8: begin + hdmi_in0_s7datacapture2_gearbox_storage[71:64] <= hdmi_in0_s7datacapture2_gearbox_i; + end + 4'd9: begin + hdmi_in0_s7datacapture2_gearbox_storage[79:72] <= hdmi_in0_s7datacapture2_gearbox_i; + end + endcase + if (data2_cap_write_rst) begin + hdmi_in0_s7datacapture2_gearbox_wrpointer <= 4'd5; + end +end + +always @(posedge eth_rx_clk) begin + ethphy_liteethphyrmiirx_crs_dv <= eth_crs_dv; + ethphy_liteethphyrmiirx_crs_dv_d <= ethphy_liteethphyrmiirx_crs_dv; + ethphy_liteethphyrmiirx_rx_data <= eth_rx_data; + if (ethphy_liteethphyrmiirx_converter_converter_source_ready) begin + ethphy_liteethphyrmiirx_converter_converter_strobe_all <= 1'd0; + end + if (ethphy_liteethphyrmiirx_converter_converter_load_part) begin + if (((ethphy_liteethphyrmiirx_converter_converter_demux == 2'd3) | ethphy_liteethphyrmiirx_converter_converter_sink_last)) begin + ethphy_liteethphyrmiirx_converter_converter_demux <= 1'd0; + ethphy_liteethphyrmiirx_converter_converter_strobe_all <= 1'd1; + end else begin + ethphy_liteethphyrmiirx_converter_converter_demux <= (ethphy_liteethphyrmiirx_converter_converter_demux + 1'd1); + end + end + if ((ethphy_liteethphyrmiirx_converter_converter_source_valid & ethphy_liteethphyrmiirx_converter_converter_source_ready)) begin + if ((ethphy_liteethphyrmiirx_converter_converter_sink_valid & ethphy_liteethphyrmiirx_converter_converter_sink_ready)) begin + ethphy_liteethphyrmiirx_converter_converter_source_first <= ethphy_liteethphyrmiirx_converter_converter_sink_first; + ethphy_liteethphyrmiirx_converter_converter_source_last <= ethphy_liteethphyrmiirx_converter_converter_sink_last; + end else begin + ethphy_liteethphyrmiirx_converter_converter_source_first <= 1'd0; + ethphy_liteethphyrmiirx_converter_converter_source_last <= 1'd0; + end + end else begin + if ((ethphy_liteethphyrmiirx_converter_converter_sink_valid & ethphy_liteethphyrmiirx_converter_converter_sink_ready)) begin + ethphy_liteethphyrmiirx_converter_converter_source_first <= (ethphy_liteethphyrmiirx_converter_converter_sink_first | ethphy_liteethphyrmiirx_converter_converter_source_first); + ethphy_liteethphyrmiirx_converter_converter_source_last <= (ethphy_liteethphyrmiirx_converter_converter_sink_last | ethphy_liteethphyrmiirx_converter_converter_source_last); + end + end + if (ethphy_liteethphyrmiirx_converter_converter_load_part) begin + case (ethphy_liteethphyrmiirx_converter_converter_demux) + 1'd0: begin + ethphy_liteethphyrmiirx_converter_converter_source_payload_data[1:0] <= ethphy_liteethphyrmiirx_converter_converter_sink_payload_data; + end + 1'd1: begin + ethphy_liteethphyrmiirx_converter_converter_source_payload_data[3:2] <= ethphy_liteethphyrmiirx_converter_converter_sink_payload_data; + end + 2'd2: begin + ethphy_liteethphyrmiirx_converter_converter_source_payload_data[5:4] <= ethphy_liteethphyrmiirx_converter_converter_sink_payload_data; + end + 2'd3: begin + ethphy_liteethphyrmiirx_converter_converter_source_payload_data[7:6] <= ethphy_liteethphyrmiirx_converter_converter_sink_payload_data; + end + endcase + end + if (ethphy_liteethphyrmiirx_converter_converter_load_part) begin + ethphy_liteethphyrmiirx_converter_converter_source_payload_valid_token_count <= (ethphy_liteethphyrmiirx_converter_converter_demux + 1'd1); + end + if (ethphy_liteethphyrmiirx_converter_reset) begin + ethphy_liteethphyrmiirx_converter_converter_source_payload_data <= 8'd0; + ethphy_liteethphyrmiirx_converter_converter_source_payload_valid_token_count <= 3'd0; + ethphy_liteethphyrmiirx_converter_converter_demux <= 2'd0; + ethphy_liteethphyrmiirx_converter_converter_strobe_all <= 1'd0; + end + liteethphyrmii_state <= liteethphyrmii_next_state; + liteethudpipcore_liteethmac_liteethmacpreamblechecker_state <= liteethudpipcore_liteethmac_liteethmacpreamblechecker_next_state; + if (ethcore_mac_liteethmaccrc32checker_crc_ce) begin + ethcore_mac_liteethmaccrc32checker_crc_reg <= ethcore_mac_liteethmaccrc32checker_crc_next; + end + if (ethcore_mac_liteethmaccrc32checker_crc_reset) begin + ethcore_mac_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + end + if (((ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_we & ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~ethcore_mac_liteethmaccrc32checker_syncfifo_replace))) begin + if ((ethcore_mac_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin + ethcore_mac_liteethmaccrc32checker_syncfifo_produce <= 1'd0; + end else begin + ethcore_mac_liteethmaccrc32checker_syncfifo_produce <= (ethcore_mac_liteethmaccrc32checker_syncfifo_produce + 1'd1); + end + end + if (ethcore_mac_liteethmaccrc32checker_syncfifo_do_read) begin + if ((ethcore_mac_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin + ethcore_mac_liteethmaccrc32checker_syncfifo_consume <= 1'd0; + end else begin + ethcore_mac_liteethmaccrc32checker_syncfifo_consume <= (ethcore_mac_liteethmaccrc32checker_syncfifo_consume + 1'd1); + end + end + if (((ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_we & ethcore_mac_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~ethcore_mac_liteethmaccrc32checker_syncfifo_replace))) begin + if ((~ethcore_mac_liteethmaccrc32checker_syncfifo_do_read)) begin + ethcore_mac_liteethmaccrc32checker_syncfifo_level <= (ethcore_mac_liteethmaccrc32checker_syncfifo_level + 1'd1); + end + end else begin + if (ethcore_mac_liteethmaccrc32checker_syncfifo_do_read) begin + ethcore_mac_liteethmaccrc32checker_syncfifo_level <= (ethcore_mac_liteethmaccrc32checker_syncfifo_level - 1'd1); + end + end + if (ethcore_mac_liteethmaccrc32checker_fifo_reset) begin + ethcore_mac_liteethmaccrc32checker_syncfifo_level <= 3'd0; + ethcore_mac_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + ethcore_mac_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + end + liteethudpipcore_liteethmac_liteethmaccrc32checker_state <= liteethudpipcore_liteethmac_liteethmaccrc32checker_next_state; + if (((~ethcore_mac_crc32_checker_source_valid) | ethcore_mac_crc32_checker_source_ready)) begin + ethcore_mac_crc32_checker_source_valid <= ethcore_mac_crc32_checker_sink_valid; + ethcore_mac_crc32_checker_source_first <= ethcore_mac_crc32_checker_sink_first; + ethcore_mac_crc32_checker_source_last <= ethcore_mac_crc32_checker_sink_last; + ethcore_mac_crc32_checker_source_payload_data <= ethcore_mac_crc32_checker_sink_payload_data; + ethcore_mac_crc32_checker_source_payload_last_be <= ethcore_mac_crc32_checker_sink_payload_last_be; + ethcore_mac_crc32_checker_source_payload_error <= ethcore_mac_crc32_checker_sink_payload_error; + end + if (ethcore_mac_ps_preamble_error_i) begin + ethcore_mac_ps_preamble_error_toggle_i <= (~ethcore_mac_ps_preamble_error_toggle_i); + end + if (ethcore_mac_ps_crc_error_i) begin + ethcore_mac_ps_crc_error_toggle_i <= (~ethcore_mac_ps_crc_error_toggle_i); + end + ethcore_mac_rx_cdc_graycounter0_q_binary <= ethcore_mac_rx_cdc_graycounter0_q_next_binary; + ethcore_mac_rx_cdc_graycounter0_q <= ethcore_mac_rx_cdc_graycounter0_q_next; + if (eth_rx_rst) begin + ethphy_liteethphyrmiirx_converter_converter_source_payload_data <= 8'd0; + ethphy_liteethphyrmiirx_converter_converter_source_payload_valid_token_count <= 3'd0; + ethphy_liteethphyrmiirx_converter_converter_demux <= 2'd0; + ethphy_liteethphyrmiirx_converter_converter_strobe_all <= 1'd0; + ethphy_liteethphyrmiirx_crs_dv <= 1'd0; + ethphy_liteethphyrmiirx_crs_dv_d <= 1'd0; + ethphy_liteethphyrmiirx_rx_data <= 2'd0; + ethcore_mac_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + ethcore_mac_liteethmaccrc32checker_syncfifo_level <= 3'd0; + ethcore_mac_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + ethcore_mac_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + ethcore_mac_crc32_checker_source_valid <= 1'd0; + ethcore_mac_crc32_checker_source_payload_data <= 8'd0; + ethcore_mac_crc32_checker_source_payload_last_be <= 1'd0; + ethcore_mac_crc32_checker_source_payload_error <= 1'd0; + ethcore_mac_rx_cdc_graycounter0_q <= 7'd0; + ethcore_mac_rx_cdc_graycounter0_q_binary <= 7'd0; + liteethphyrmii_state <= 1'd0; + liteethudpipcore_liteethmac_liteethmacpreamblechecker_state <= 1'd0; + liteethudpipcore_liteethmac_liteethmaccrc32checker_state <= 2'd0; + end + xilinxmultiregimpl1_regs0 <= ethphy_liteethphyrmiirx_converter_sink_valid1; + xilinxmultiregimpl1_regs1 <= xilinxmultiregimpl1_regs0; + xilinxmultiregimpl2_regs0 <= ethphy_liteethphyrmiirx_converter_sink_data; + xilinxmultiregimpl2_regs1 <= xilinxmultiregimpl2_regs0; + xilinxmultiregimpl9_regs0 <= ethcore_mac_rx_cdc_graycounter1_q; + xilinxmultiregimpl9_regs1 <= xilinxmultiregimpl9_regs0; +end + +always @(posedge eth_tx_clk) begin + eth_tx_en <= ethphy_liteethphyrmiitx_converter_source_valid; + eth_tx_data <= ethphy_liteethphyrmiitx_converter_source_payload_data; + if ((ethphy_liteethphyrmiitx_converter_converter_source_valid & ethphy_liteethphyrmiitx_converter_converter_source_ready)) begin + if (ethphy_liteethphyrmiitx_converter_converter_last) begin + ethphy_liteethphyrmiitx_converter_converter_mux <= 1'd0; + end else begin + ethphy_liteethphyrmiitx_converter_converter_mux <= (ethphy_liteethphyrmiitx_converter_converter_mux + 1'd1); + end + end + liteethudpipcore_liteethmac_liteethmacgap_state <= liteethudpipcore_liteethmac_liteethmacgap_next_state; + if (ethcore_mac_tx_gap_inserter_counter_liteethmacgap_next_value_ce) begin + ethcore_mac_tx_gap_inserter_counter <= ethcore_mac_tx_gap_inserter_counter_liteethmacgap_next_value; + end + liteethudpipcore_liteethmac_liteethmacpreambleinserter_state <= liteethudpipcore_liteethmac_liteethmacpreambleinserter_next_state; + if (ethcore_mac_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce) begin + ethcore_mac_preamble_inserter_count <= ethcore_mac_preamble_inserter_count_liteethmacpreambleinserter_next_value; + end + if (ethcore_mac_liteethmaccrc32inserter_is_ongoing0) begin + ethcore_mac_liteethmaccrc32inserter_cnt <= 2'd3; + end else begin + if ((ethcore_mac_liteethmaccrc32inserter_is_ongoing1 & (~ethcore_mac_liteethmaccrc32inserter_cnt_done))) begin + ethcore_mac_liteethmaccrc32inserter_cnt <= (ethcore_mac_liteethmaccrc32inserter_cnt - ethcore_mac_liteethmaccrc32inserter_source_ready); + end + end + if (ethcore_mac_liteethmaccrc32inserter_ce) begin + ethcore_mac_liteethmaccrc32inserter_reg <= ethcore_mac_liteethmaccrc32inserter_next; + end + if (ethcore_mac_liteethmaccrc32inserter_reset) begin + ethcore_mac_liteethmaccrc32inserter_reg <= 32'd4294967295; + end + liteethudpipcore_liteethmac_liteethmaccrc32inserter_state <= liteethudpipcore_liteethmac_liteethmaccrc32inserter_next_state; + if (((~ethcore_mac_crc32_inserter_source_valid) | ethcore_mac_crc32_inserter_source_ready)) begin + ethcore_mac_crc32_inserter_source_valid <= ethcore_mac_crc32_inserter_sink_valid; + ethcore_mac_crc32_inserter_source_first <= ethcore_mac_crc32_inserter_sink_first; + ethcore_mac_crc32_inserter_source_last <= ethcore_mac_crc32_inserter_sink_last; + ethcore_mac_crc32_inserter_source_payload_data <= ethcore_mac_crc32_inserter_sink_payload_data; + ethcore_mac_crc32_inserter_source_payload_last_be <= ethcore_mac_crc32_inserter_sink_payload_last_be; + ethcore_mac_crc32_inserter_source_payload_error <= ethcore_mac_crc32_inserter_sink_payload_error; + end + liteethudpipcore_liteethmac_liteethmacpaddinginserter_state <= liteethudpipcore_liteethmac_liteethmacpaddinginserter_next_state; + if (ethcore_mac_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce) begin + ethcore_mac_padding_inserter_counter <= ethcore_mac_padding_inserter_counter_liteethmacpaddinginserter_next_value; + end + ethcore_mac_tx_cdc_graycounter1_q_binary <= ethcore_mac_tx_cdc_graycounter1_q_next_binary; + ethcore_mac_tx_cdc_graycounter1_q <= ethcore_mac_tx_cdc_graycounter1_q_next; + if (eth_tx_rst) begin + ethphy_liteethphyrmiitx_converter_converter_mux <= 2'd0; + ethcore_mac_liteethmaccrc32inserter_reg <= 32'd4294967295; + ethcore_mac_liteethmaccrc32inserter_cnt <= 2'd3; + ethcore_mac_crc32_inserter_source_valid <= 1'd0; + ethcore_mac_crc32_inserter_source_payload_data <= 8'd0; + ethcore_mac_crc32_inserter_source_payload_last_be <= 1'd0; + ethcore_mac_crc32_inserter_source_payload_error <= 1'd0; + ethcore_mac_padding_inserter_counter <= 16'd0; + ethcore_mac_tx_cdc_graycounter1_q <= 7'd0; + ethcore_mac_tx_cdc_graycounter1_q_binary <= 7'd0; + liteethudpipcore_liteethmac_liteethmacgap_state <= 1'd0; + liteethudpipcore_liteethmac_liteethmacpreambleinserter_state <= 2'd0; + liteethudpipcore_liteethmac_liteethmaccrc32inserter_state <= 2'd0; + liteethudpipcore_liteethmac_liteethmacpaddinginserter_state <= 1'd0; + end + xilinxmultiregimpl6_regs0 <= ethcore_mac_tx_cdc_graycounter0_q; + xilinxmultiregimpl6_regs1 <= xilinxmultiregimpl6_regs0; +end + +always @(posedge fmeter_clk) begin + freqmeter_q_binary <= freqmeter_q_next_binary; + freqmeter_q <= freqmeter_q_next; +end + +always @(posedge hdmi_in0_pix_clk) begin + hdmi_in0_charsync0_raw_data1 <= hdmi_in0_charsync0_raw_data; + hdmi_in0_charsync0_found_control <= 1'd0; + if (((((hdmi_in0_charsync0_raw[9:0] == 10'd852) | (hdmi_in0_charsync0_raw[9:0] == 8'd171)) | (hdmi_in0_charsync0_raw[9:0] == 9'd340)) | (hdmi_in0_charsync0_raw[9:0] == 10'd683))) begin + hdmi_in0_charsync0_found_control <= 1'd1; + hdmi_in0_charsync0_control_position <= 1'd0; + end + if (((((hdmi_in0_charsync0_raw[10:1] == 10'd852) | (hdmi_in0_charsync0_raw[10:1] == 8'd171)) | (hdmi_in0_charsync0_raw[10:1] == 9'd340)) | (hdmi_in0_charsync0_raw[10:1] == 10'd683))) begin + hdmi_in0_charsync0_found_control <= 1'd1; + hdmi_in0_charsync0_control_position <= 1'd1; + end + if (((((hdmi_in0_charsync0_raw[11:2] == 10'd852) | (hdmi_in0_charsync0_raw[11:2] == 8'd171)) | (hdmi_in0_charsync0_raw[11:2] == 9'd340)) | (hdmi_in0_charsync0_raw[11:2] == 10'd683))) begin + hdmi_in0_charsync0_found_control <= 1'd1; + hdmi_in0_charsync0_control_position <= 2'd2; + end + if (((((hdmi_in0_charsync0_raw[12:3] == 10'd852) | (hdmi_in0_charsync0_raw[12:3] == 8'd171)) | (hdmi_in0_charsync0_raw[12:3] == 9'd340)) | (hdmi_in0_charsync0_raw[12:3] == 10'd683))) begin + hdmi_in0_charsync0_found_control <= 1'd1; + hdmi_in0_charsync0_control_position <= 2'd3; + end + if (((((hdmi_in0_charsync0_raw[13:4] == 10'd852) | (hdmi_in0_charsync0_raw[13:4] == 8'd171)) | (hdmi_in0_charsync0_raw[13:4] == 9'd340)) | (hdmi_in0_charsync0_raw[13:4] == 10'd683))) begin + hdmi_in0_charsync0_found_control <= 1'd1; + hdmi_in0_charsync0_control_position <= 3'd4; + end + if (((((hdmi_in0_charsync0_raw[14:5] == 10'd852) | (hdmi_in0_charsync0_raw[14:5] == 8'd171)) | (hdmi_in0_charsync0_raw[14:5] == 9'd340)) | (hdmi_in0_charsync0_raw[14:5] == 10'd683))) begin + hdmi_in0_charsync0_found_control <= 1'd1; + hdmi_in0_charsync0_control_position <= 3'd5; + end + if (((((hdmi_in0_charsync0_raw[15:6] == 10'd852) | (hdmi_in0_charsync0_raw[15:6] == 8'd171)) | (hdmi_in0_charsync0_raw[15:6] == 9'd340)) | (hdmi_in0_charsync0_raw[15:6] == 10'd683))) begin + hdmi_in0_charsync0_found_control <= 1'd1; + hdmi_in0_charsync0_control_position <= 3'd6; + end + if (((((hdmi_in0_charsync0_raw[16:7] == 10'd852) | (hdmi_in0_charsync0_raw[16:7] == 8'd171)) | (hdmi_in0_charsync0_raw[16:7] == 9'd340)) | (hdmi_in0_charsync0_raw[16:7] == 10'd683))) begin + hdmi_in0_charsync0_found_control <= 1'd1; + hdmi_in0_charsync0_control_position <= 3'd7; + end + if (((((hdmi_in0_charsync0_raw[17:8] == 10'd852) | (hdmi_in0_charsync0_raw[17:8] == 8'd171)) | (hdmi_in0_charsync0_raw[17:8] == 9'd340)) | (hdmi_in0_charsync0_raw[17:8] == 10'd683))) begin + hdmi_in0_charsync0_found_control <= 1'd1; + hdmi_in0_charsync0_control_position <= 4'd8; + end + if (((((hdmi_in0_charsync0_raw[18:9] == 10'd852) | (hdmi_in0_charsync0_raw[18:9] == 8'd171)) | (hdmi_in0_charsync0_raw[18:9] == 9'd340)) | (hdmi_in0_charsync0_raw[18:9] == 10'd683))) begin + hdmi_in0_charsync0_found_control <= 1'd1; + hdmi_in0_charsync0_control_position <= 4'd9; + end + if ((hdmi_in0_charsync0_found_control & (hdmi_in0_charsync0_control_position == hdmi_in0_charsync0_previous_control_position))) begin + if ((hdmi_in0_charsync0_control_counter == 3'd7)) begin + hdmi_in0_charsync0_control_counter <= 1'd0; + hdmi_in0_charsync0_synced <= 1'd1; + hdmi_in0_charsync0_word_sel <= hdmi_in0_charsync0_control_position; + end else begin + hdmi_in0_charsync0_control_counter <= (hdmi_in0_charsync0_control_counter + 1'd1); + end + end else begin + hdmi_in0_charsync0_control_counter <= 1'd0; + end + hdmi_in0_charsync0_previous_control_position <= hdmi_in0_charsync0_control_position; + hdmi_in0_charsync0_data <= (hdmi_in0_charsync0_raw >>> hdmi_in0_charsync0_word_sel); + hdmi_in0_wer0_data_r <= hdmi_in0_wer0_data[8:0]; + hdmi_in0_wer0_transition_count <= (((((((hdmi_in0_wer0_transitions[0] + hdmi_in0_wer0_transitions[1]) + hdmi_in0_wer0_transitions[2]) + hdmi_in0_wer0_transitions[3]) + hdmi_in0_wer0_transitions[4]) + hdmi_in0_wer0_transitions[5]) + hdmi_in0_wer0_transitions[6]) + hdmi_in0_wer0_transitions[7]); + hdmi_in0_wer0_is_control <= ((((hdmi_in0_wer0_data_r == 10'd852) | (hdmi_in0_wer0_data_r == 8'd171)) | (hdmi_in0_wer0_data_r == 9'd340)) | (hdmi_in0_wer0_data_r == 10'd683)); + hdmi_in0_wer0_is_error <= ((hdmi_in0_wer0_transition_count > 3'd4) & (~hdmi_in0_wer0_is_control)); + {hdmi_in0_wer0_period_done, hdmi_in0_wer0_period_counter} <= (hdmi_in0_wer0_period_counter + 1'd1); + hdmi_in0_wer0_wer_counter_r_updated <= hdmi_in0_wer0_period_done; + if (hdmi_in0_wer0_period_done) begin + hdmi_in0_wer0_wer_counter_r <= hdmi_in0_wer0_wer_counter; + hdmi_in0_wer0_wer_counter <= 1'd0; + end else begin + if (hdmi_in0_wer0_is_error) begin + hdmi_in0_wer0_wer_counter <= (hdmi_in0_wer0_wer_counter + 1'd1); + end + end + if (hdmi_in0_wer0_i) begin + hdmi_in0_wer0_toggle_i <= (~hdmi_in0_wer0_toggle_i); + end + hdmi_in0_decoding0_output_de <= 1'd1; + if ((hdmi_in0_decoding0_input == 10'd852)) begin + hdmi_in0_decoding0_output_de <= 1'd0; + hdmi_in0_decoding0_output_c <= 1'd0; + end + if ((hdmi_in0_decoding0_input == 8'd171)) begin + hdmi_in0_decoding0_output_de <= 1'd0; + hdmi_in0_decoding0_output_c <= 1'd1; + end + if ((hdmi_in0_decoding0_input == 9'd340)) begin + hdmi_in0_decoding0_output_de <= 1'd0; + hdmi_in0_decoding0_output_c <= 2'd2; + end + if ((hdmi_in0_decoding0_input == 10'd683)) begin + hdmi_in0_decoding0_output_de <= 1'd0; + hdmi_in0_decoding0_output_c <= 2'd3; + end + hdmi_in0_decoding0_output_raw <= hdmi_in0_decoding0_input; + hdmi_in0_decoding0_output_d[0] <= (hdmi_in0_decoding0_input[0] ^ hdmi_in0_decoding0_input[9]); + hdmi_in0_decoding0_output_d[1] <= ((hdmi_in0_decoding0_input[1] ^ hdmi_in0_decoding0_input[0]) ^ (~hdmi_in0_decoding0_input[8])); + hdmi_in0_decoding0_output_d[2] <= ((hdmi_in0_decoding0_input[2] ^ hdmi_in0_decoding0_input[1]) ^ (~hdmi_in0_decoding0_input[8])); + hdmi_in0_decoding0_output_d[3] <= ((hdmi_in0_decoding0_input[3] ^ hdmi_in0_decoding0_input[2]) ^ (~hdmi_in0_decoding0_input[8])); + hdmi_in0_decoding0_output_d[4] <= ((hdmi_in0_decoding0_input[4] ^ hdmi_in0_decoding0_input[3]) ^ (~hdmi_in0_decoding0_input[8])); + hdmi_in0_decoding0_output_d[5] <= ((hdmi_in0_decoding0_input[5] ^ hdmi_in0_decoding0_input[4]) ^ (~hdmi_in0_decoding0_input[8])); + hdmi_in0_decoding0_output_d[6] <= ((hdmi_in0_decoding0_input[6] ^ hdmi_in0_decoding0_input[5]) ^ (~hdmi_in0_decoding0_input[8])); + hdmi_in0_decoding0_output_d[7] <= ((hdmi_in0_decoding0_input[7] ^ hdmi_in0_decoding0_input[6]) ^ (~hdmi_in0_decoding0_input[8])); + hdmi_in0_decoding0_valid_o <= hdmi_in0_decoding0_valid_i; + hdmi_in0_charsync1_raw_data1 <= hdmi_in0_charsync1_raw_data; + hdmi_in0_charsync1_found_control <= 1'd0; + if (((((hdmi_in0_charsync1_raw[9:0] == 10'd852) | (hdmi_in0_charsync1_raw[9:0] == 8'd171)) | (hdmi_in0_charsync1_raw[9:0] == 9'd340)) | (hdmi_in0_charsync1_raw[9:0] == 10'd683))) begin + hdmi_in0_charsync1_found_control <= 1'd1; + hdmi_in0_charsync1_control_position <= 1'd0; + end + if (((((hdmi_in0_charsync1_raw[10:1] == 10'd852) | (hdmi_in0_charsync1_raw[10:1] == 8'd171)) | (hdmi_in0_charsync1_raw[10:1] == 9'd340)) | (hdmi_in0_charsync1_raw[10:1] == 10'd683))) begin + hdmi_in0_charsync1_found_control <= 1'd1; + hdmi_in0_charsync1_control_position <= 1'd1; + end + if (((((hdmi_in0_charsync1_raw[11:2] == 10'd852) | (hdmi_in0_charsync1_raw[11:2] == 8'd171)) | (hdmi_in0_charsync1_raw[11:2] == 9'd340)) | (hdmi_in0_charsync1_raw[11:2] == 10'd683))) begin + hdmi_in0_charsync1_found_control <= 1'd1; + hdmi_in0_charsync1_control_position <= 2'd2; + end + if (((((hdmi_in0_charsync1_raw[12:3] == 10'd852) | (hdmi_in0_charsync1_raw[12:3] == 8'd171)) | (hdmi_in0_charsync1_raw[12:3] == 9'd340)) | (hdmi_in0_charsync1_raw[12:3] == 10'd683))) begin + hdmi_in0_charsync1_found_control <= 1'd1; + hdmi_in0_charsync1_control_position <= 2'd3; + end + if (((((hdmi_in0_charsync1_raw[13:4] == 10'd852) | (hdmi_in0_charsync1_raw[13:4] == 8'd171)) | (hdmi_in0_charsync1_raw[13:4] == 9'd340)) | (hdmi_in0_charsync1_raw[13:4] == 10'd683))) begin + hdmi_in0_charsync1_found_control <= 1'd1; + hdmi_in0_charsync1_control_position <= 3'd4; + end + if (((((hdmi_in0_charsync1_raw[14:5] == 10'd852) | (hdmi_in0_charsync1_raw[14:5] == 8'd171)) | (hdmi_in0_charsync1_raw[14:5] == 9'd340)) | (hdmi_in0_charsync1_raw[14:5] == 10'd683))) begin + hdmi_in0_charsync1_found_control <= 1'd1; + hdmi_in0_charsync1_control_position <= 3'd5; + end + if (((((hdmi_in0_charsync1_raw[15:6] == 10'd852) | (hdmi_in0_charsync1_raw[15:6] == 8'd171)) | (hdmi_in0_charsync1_raw[15:6] == 9'd340)) | (hdmi_in0_charsync1_raw[15:6] == 10'd683))) begin + hdmi_in0_charsync1_found_control <= 1'd1; + hdmi_in0_charsync1_control_position <= 3'd6; + end + if (((((hdmi_in0_charsync1_raw[16:7] == 10'd852) | (hdmi_in0_charsync1_raw[16:7] == 8'd171)) | (hdmi_in0_charsync1_raw[16:7] == 9'd340)) | (hdmi_in0_charsync1_raw[16:7] == 10'd683))) begin + hdmi_in0_charsync1_found_control <= 1'd1; + hdmi_in0_charsync1_control_position <= 3'd7; + end + if (((((hdmi_in0_charsync1_raw[17:8] == 10'd852) | (hdmi_in0_charsync1_raw[17:8] == 8'd171)) | (hdmi_in0_charsync1_raw[17:8] == 9'd340)) | (hdmi_in0_charsync1_raw[17:8] == 10'd683))) begin + hdmi_in0_charsync1_found_control <= 1'd1; + hdmi_in0_charsync1_control_position <= 4'd8; + end + if (((((hdmi_in0_charsync1_raw[18:9] == 10'd852) | (hdmi_in0_charsync1_raw[18:9] == 8'd171)) | (hdmi_in0_charsync1_raw[18:9] == 9'd340)) | (hdmi_in0_charsync1_raw[18:9] == 10'd683))) begin + hdmi_in0_charsync1_found_control <= 1'd1; + hdmi_in0_charsync1_control_position <= 4'd9; + end + if ((hdmi_in0_charsync1_found_control & (hdmi_in0_charsync1_control_position == hdmi_in0_charsync1_previous_control_position))) begin + if ((hdmi_in0_charsync1_control_counter == 3'd7)) begin + hdmi_in0_charsync1_control_counter <= 1'd0; + hdmi_in0_charsync1_synced <= 1'd1; + hdmi_in0_charsync1_word_sel <= hdmi_in0_charsync1_control_position; + end else begin + hdmi_in0_charsync1_control_counter <= (hdmi_in0_charsync1_control_counter + 1'd1); + end + end else begin + hdmi_in0_charsync1_control_counter <= 1'd0; + end + hdmi_in0_charsync1_previous_control_position <= hdmi_in0_charsync1_control_position; + hdmi_in0_charsync1_data <= (hdmi_in0_charsync1_raw >>> hdmi_in0_charsync1_word_sel); + hdmi_in0_wer1_data_r <= hdmi_in0_wer1_data[8:0]; + hdmi_in0_wer1_transition_count <= (((((((hdmi_in0_wer1_transitions[0] + hdmi_in0_wer1_transitions[1]) + hdmi_in0_wer1_transitions[2]) + hdmi_in0_wer1_transitions[3]) + hdmi_in0_wer1_transitions[4]) + hdmi_in0_wer1_transitions[5]) + hdmi_in0_wer1_transitions[6]) + hdmi_in0_wer1_transitions[7]); + hdmi_in0_wer1_is_control <= ((((hdmi_in0_wer1_data_r == 10'd852) | (hdmi_in0_wer1_data_r == 8'd171)) | (hdmi_in0_wer1_data_r == 9'd340)) | (hdmi_in0_wer1_data_r == 10'd683)); + hdmi_in0_wer1_is_error <= ((hdmi_in0_wer1_transition_count > 3'd4) & (~hdmi_in0_wer1_is_control)); + {hdmi_in0_wer1_period_done, hdmi_in0_wer1_period_counter} <= (hdmi_in0_wer1_period_counter + 1'd1); + hdmi_in0_wer1_wer_counter_r_updated <= hdmi_in0_wer1_period_done; + if (hdmi_in0_wer1_period_done) begin + hdmi_in0_wer1_wer_counter_r <= hdmi_in0_wer1_wer_counter; + hdmi_in0_wer1_wer_counter <= 1'd0; + end else begin + if (hdmi_in0_wer1_is_error) begin + hdmi_in0_wer1_wer_counter <= (hdmi_in0_wer1_wer_counter + 1'd1); + end + end + if (hdmi_in0_wer1_i) begin + hdmi_in0_wer1_toggle_i <= (~hdmi_in0_wer1_toggle_i); + end + hdmi_in0_decoding1_output_de <= 1'd1; + if ((hdmi_in0_decoding1_input == 10'd852)) begin + hdmi_in0_decoding1_output_de <= 1'd0; + hdmi_in0_decoding1_output_c <= 1'd0; + end + if ((hdmi_in0_decoding1_input == 8'd171)) begin + hdmi_in0_decoding1_output_de <= 1'd0; + hdmi_in0_decoding1_output_c <= 1'd1; + end + if ((hdmi_in0_decoding1_input == 9'd340)) begin + hdmi_in0_decoding1_output_de <= 1'd0; + hdmi_in0_decoding1_output_c <= 2'd2; + end + if ((hdmi_in0_decoding1_input == 10'd683)) begin + hdmi_in0_decoding1_output_de <= 1'd0; + hdmi_in0_decoding1_output_c <= 2'd3; + end + hdmi_in0_decoding1_output_raw <= hdmi_in0_decoding1_input; + hdmi_in0_decoding1_output_d[0] <= (hdmi_in0_decoding1_input[0] ^ hdmi_in0_decoding1_input[9]); + hdmi_in0_decoding1_output_d[1] <= ((hdmi_in0_decoding1_input[1] ^ hdmi_in0_decoding1_input[0]) ^ (~hdmi_in0_decoding1_input[8])); + hdmi_in0_decoding1_output_d[2] <= ((hdmi_in0_decoding1_input[2] ^ hdmi_in0_decoding1_input[1]) ^ (~hdmi_in0_decoding1_input[8])); + hdmi_in0_decoding1_output_d[3] <= ((hdmi_in0_decoding1_input[3] ^ hdmi_in0_decoding1_input[2]) ^ (~hdmi_in0_decoding1_input[8])); + hdmi_in0_decoding1_output_d[4] <= ((hdmi_in0_decoding1_input[4] ^ hdmi_in0_decoding1_input[3]) ^ (~hdmi_in0_decoding1_input[8])); + hdmi_in0_decoding1_output_d[5] <= ((hdmi_in0_decoding1_input[5] ^ hdmi_in0_decoding1_input[4]) ^ (~hdmi_in0_decoding1_input[8])); + hdmi_in0_decoding1_output_d[6] <= ((hdmi_in0_decoding1_input[6] ^ hdmi_in0_decoding1_input[5]) ^ (~hdmi_in0_decoding1_input[8])); + hdmi_in0_decoding1_output_d[7] <= ((hdmi_in0_decoding1_input[7] ^ hdmi_in0_decoding1_input[6]) ^ (~hdmi_in0_decoding1_input[8])); + hdmi_in0_decoding1_valid_o <= hdmi_in0_decoding1_valid_i; + hdmi_in0_charsync2_raw_data1 <= hdmi_in0_charsync2_raw_data; + hdmi_in0_charsync2_found_control <= 1'd0; + if (((((hdmi_in0_charsync2_raw[9:0] == 10'd852) | (hdmi_in0_charsync2_raw[9:0] == 8'd171)) | (hdmi_in0_charsync2_raw[9:0] == 9'd340)) | (hdmi_in0_charsync2_raw[9:0] == 10'd683))) begin + hdmi_in0_charsync2_found_control <= 1'd1; + hdmi_in0_charsync2_control_position <= 1'd0; + end + if (((((hdmi_in0_charsync2_raw[10:1] == 10'd852) | (hdmi_in0_charsync2_raw[10:1] == 8'd171)) | (hdmi_in0_charsync2_raw[10:1] == 9'd340)) | (hdmi_in0_charsync2_raw[10:1] == 10'd683))) begin + hdmi_in0_charsync2_found_control <= 1'd1; + hdmi_in0_charsync2_control_position <= 1'd1; + end + if (((((hdmi_in0_charsync2_raw[11:2] == 10'd852) | (hdmi_in0_charsync2_raw[11:2] == 8'd171)) | (hdmi_in0_charsync2_raw[11:2] == 9'd340)) | (hdmi_in0_charsync2_raw[11:2] == 10'd683))) begin + hdmi_in0_charsync2_found_control <= 1'd1; + hdmi_in0_charsync2_control_position <= 2'd2; + end + if (((((hdmi_in0_charsync2_raw[12:3] == 10'd852) | (hdmi_in0_charsync2_raw[12:3] == 8'd171)) | (hdmi_in0_charsync2_raw[12:3] == 9'd340)) | (hdmi_in0_charsync2_raw[12:3] == 10'd683))) begin + hdmi_in0_charsync2_found_control <= 1'd1; + hdmi_in0_charsync2_control_position <= 2'd3; + end + if (((((hdmi_in0_charsync2_raw[13:4] == 10'd852) | (hdmi_in0_charsync2_raw[13:4] == 8'd171)) | (hdmi_in0_charsync2_raw[13:4] == 9'd340)) | (hdmi_in0_charsync2_raw[13:4] == 10'd683))) begin + hdmi_in0_charsync2_found_control <= 1'd1; + hdmi_in0_charsync2_control_position <= 3'd4; + end + if (((((hdmi_in0_charsync2_raw[14:5] == 10'd852) | (hdmi_in0_charsync2_raw[14:5] == 8'd171)) | (hdmi_in0_charsync2_raw[14:5] == 9'd340)) | (hdmi_in0_charsync2_raw[14:5] == 10'd683))) begin + hdmi_in0_charsync2_found_control <= 1'd1; + hdmi_in0_charsync2_control_position <= 3'd5; + end + if (((((hdmi_in0_charsync2_raw[15:6] == 10'd852) | (hdmi_in0_charsync2_raw[15:6] == 8'd171)) | (hdmi_in0_charsync2_raw[15:6] == 9'd340)) | (hdmi_in0_charsync2_raw[15:6] == 10'd683))) begin + hdmi_in0_charsync2_found_control <= 1'd1; + hdmi_in0_charsync2_control_position <= 3'd6; + end + if (((((hdmi_in0_charsync2_raw[16:7] == 10'd852) | (hdmi_in0_charsync2_raw[16:7] == 8'd171)) | (hdmi_in0_charsync2_raw[16:7] == 9'd340)) | (hdmi_in0_charsync2_raw[16:7] == 10'd683))) begin + hdmi_in0_charsync2_found_control <= 1'd1; + hdmi_in0_charsync2_control_position <= 3'd7; + end + if (((((hdmi_in0_charsync2_raw[17:8] == 10'd852) | (hdmi_in0_charsync2_raw[17:8] == 8'd171)) | (hdmi_in0_charsync2_raw[17:8] == 9'd340)) | (hdmi_in0_charsync2_raw[17:8] == 10'd683))) begin + hdmi_in0_charsync2_found_control <= 1'd1; + hdmi_in0_charsync2_control_position <= 4'd8; + end + if (((((hdmi_in0_charsync2_raw[18:9] == 10'd852) | (hdmi_in0_charsync2_raw[18:9] == 8'd171)) | (hdmi_in0_charsync2_raw[18:9] == 9'd340)) | (hdmi_in0_charsync2_raw[18:9] == 10'd683))) begin + hdmi_in0_charsync2_found_control <= 1'd1; + hdmi_in0_charsync2_control_position <= 4'd9; + end + if ((hdmi_in0_charsync2_found_control & (hdmi_in0_charsync2_control_position == hdmi_in0_charsync2_previous_control_position))) begin + if ((hdmi_in0_charsync2_control_counter == 3'd7)) begin + hdmi_in0_charsync2_control_counter <= 1'd0; + hdmi_in0_charsync2_synced <= 1'd1; + hdmi_in0_charsync2_word_sel <= hdmi_in0_charsync2_control_position; + end else begin + hdmi_in0_charsync2_control_counter <= (hdmi_in0_charsync2_control_counter + 1'd1); + end + end else begin + hdmi_in0_charsync2_control_counter <= 1'd0; + end + hdmi_in0_charsync2_previous_control_position <= hdmi_in0_charsync2_control_position; + hdmi_in0_charsync2_data <= (hdmi_in0_charsync2_raw >>> hdmi_in0_charsync2_word_sel); + hdmi_in0_wer2_data_r <= hdmi_in0_wer2_data[8:0]; + hdmi_in0_wer2_transition_count <= (((((((hdmi_in0_wer2_transitions[0] + hdmi_in0_wer2_transitions[1]) + hdmi_in0_wer2_transitions[2]) + hdmi_in0_wer2_transitions[3]) + hdmi_in0_wer2_transitions[4]) + hdmi_in0_wer2_transitions[5]) + hdmi_in0_wer2_transitions[6]) + hdmi_in0_wer2_transitions[7]); + hdmi_in0_wer2_is_control <= ((((hdmi_in0_wer2_data_r == 10'd852) | (hdmi_in0_wer2_data_r == 8'd171)) | (hdmi_in0_wer2_data_r == 9'd340)) | (hdmi_in0_wer2_data_r == 10'd683)); + hdmi_in0_wer2_is_error <= ((hdmi_in0_wer2_transition_count > 3'd4) & (~hdmi_in0_wer2_is_control)); + {hdmi_in0_wer2_period_done, hdmi_in0_wer2_period_counter} <= (hdmi_in0_wer2_period_counter + 1'd1); + hdmi_in0_wer2_wer_counter_r_updated <= hdmi_in0_wer2_period_done; + if (hdmi_in0_wer2_period_done) begin + hdmi_in0_wer2_wer_counter_r <= hdmi_in0_wer2_wer_counter; + hdmi_in0_wer2_wer_counter <= 1'd0; + end else begin + if (hdmi_in0_wer2_is_error) begin + hdmi_in0_wer2_wer_counter <= (hdmi_in0_wer2_wer_counter + 1'd1); + end + end + if (hdmi_in0_wer2_i) begin + hdmi_in0_wer2_toggle_i <= (~hdmi_in0_wer2_toggle_i); + end + hdmi_in0_decoding2_output_de <= 1'd1; + if ((hdmi_in0_decoding2_input == 10'd852)) begin + hdmi_in0_decoding2_output_de <= 1'd0; + hdmi_in0_decoding2_output_c <= 1'd0; + end + if ((hdmi_in0_decoding2_input == 8'd171)) begin + hdmi_in0_decoding2_output_de <= 1'd0; + hdmi_in0_decoding2_output_c <= 1'd1; + end + if ((hdmi_in0_decoding2_input == 9'd340)) begin + hdmi_in0_decoding2_output_de <= 1'd0; + hdmi_in0_decoding2_output_c <= 2'd2; + end + if ((hdmi_in0_decoding2_input == 10'd683)) begin + hdmi_in0_decoding2_output_de <= 1'd0; + hdmi_in0_decoding2_output_c <= 2'd3; + end + hdmi_in0_decoding2_output_raw <= hdmi_in0_decoding2_input; + hdmi_in0_decoding2_output_d[0] <= (hdmi_in0_decoding2_input[0] ^ hdmi_in0_decoding2_input[9]); + hdmi_in0_decoding2_output_d[1] <= ((hdmi_in0_decoding2_input[1] ^ hdmi_in0_decoding2_input[0]) ^ (~hdmi_in0_decoding2_input[8])); + hdmi_in0_decoding2_output_d[2] <= ((hdmi_in0_decoding2_input[2] ^ hdmi_in0_decoding2_input[1]) ^ (~hdmi_in0_decoding2_input[8])); + hdmi_in0_decoding2_output_d[3] <= ((hdmi_in0_decoding2_input[3] ^ hdmi_in0_decoding2_input[2]) ^ (~hdmi_in0_decoding2_input[8])); + hdmi_in0_decoding2_output_d[4] <= ((hdmi_in0_decoding2_input[4] ^ hdmi_in0_decoding2_input[3]) ^ (~hdmi_in0_decoding2_input[8])); + hdmi_in0_decoding2_output_d[5] <= ((hdmi_in0_decoding2_input[5] ^ hdmi_in0_decoding2_input[4]) ^ (~hdmi_in0_decoding2_input[8])); + hdmi_in0_decoding2_output_d[6] <= ((hdmi_in0_decoding2_input[6] ^ hdmi_in0_decoding2_input[5]) ^ (~hdmi_in0_decoding2_input[8])); + hdmi_in0_decoding2_output_d[7] <= ((hdmi_in0_decoding2_input[7] ^ hdmi_in0_decoding2_input[6]) ^ (~hdmi_in0_decoding2_input[8])); + hdmi_in0_decoding2_valid_o <= hdmi_in0_decoding2_valid_i; + if ((~hdmi_in0_chansync_valid_i)) begin + hdmi_in0_chansync_chan_synced <= 1'd0; + end else begin + if (hdmi_in0_chansync_some_control) begin + if (hdmi_in0_chansync_all_control) begin + hdmi_in0_chansync_chan_synced <= 1'd1; + end else begin + hdmi_in0_chansync_chan_synced <= 1'd0; + end + end + end + hdmi_in0_chansync_syncbuffer0_produce <= (hdmi_in0_chansync_syncbuffer0_produce + 1'd1); + if (hdmi_in0_chansync_syncbuffer0_re) begin + hdmi_in0_chansync_syncbuffer0_consume <= (hdmi_in0_chansync_syncbuffer0_consume + 1'd1); + end + hdmi_in0_chansync_syncbuffer1_produce <= (hdmi_in0_chansync_syncbuffer1_produce + 1'd1); + if (hdmi_in0_chansync_syncbuffer1_re) begin + hdmi_in0_chansync_syncbuffer1_consume <= (hdmi_in0_chansync_syncbuffer1_consume + 1'd1); + end + hdmi_in0_chansync_syncbuffer2_produce <= (hdmi_in0_chansync_syncbuffer2_produce + 1'd1); + if (hdmi_in0_chansync_syncbuffer2_re) begin + hdmi_in0_chansync_syncbuffer2_consume <= (hdmi_in0_chansync_syncbuffer2_consume + 1'd1); + end + hdmi_in0_syncpol_valid_o <= hdmi_in0_syncpol_valid_i; + hdmi_in0_syncpol_r <= hdmi_in0_syncpol_data_in2_d; + hdmi_in0_syncpol_g <= hdmi_in0_syncpol_data_in1_d; + hdmi_in0_syncpol_b <= hdmi_in0_syncpol_data_in0_d; + hdmi_in0_syncpol_de_r <= hdmi_in0_syncpol_data_in0_de; + if (hdmi_in0_syncpol_de_rising) begin + hdmi_in0_syncpol_c_polarity <= hdmi_in0_syncpol_data_in0_c; + hdmi_in0_syncpol_c_out <= 1'd0; + end else begin + hdmi_in0_syncpol_c_out <= (hdmi_in0_syncpol_data_in0_c ^ hdmi_in0_syncpol_c_polarity); + end + hdmi_in0_resdetection_de_r <= hdmi_in0_resdetection_de; + if ((hdmi_in0_resdetection_valid_i & hdmi_in0_resdetection_de)) begin + hdmi_in0_resdetection_hcounter <= (hdmi_in0_resdetection_hcounter + 1'd1); + end else begin + hdmi_in0_resdetection_hcounter <= 1'd0; + end + if (hdmi_in0_resdetection_valid_i) begin + if (hdmi_in0_resdetection_pn_de) begin + hdmi_in0_resdetection_hcounter_st <= hdmi_in0_resdetection_hcounter; + end + end else begin + hdmi_in0_resdetection_hcounter_st <= 1'd0; + end + hdmi_in0_resdetection_vsync_r <= hdmi_in0_resdetection_vsync; + if ((hdmi_in0_resdetection_valid_i & hdmi_in0_resdetection_p_vsync)) begin + hdmi_in0_resdetection_vcounter <= 1'd0; + end else begin + if (hdmi_in0_resdetection_pn_de) begin + hdmi_in0_resdetection_vcounter <= (hdmi_in0_resdetection_vcounter + 1'd1); + end + end + if (hdmi_in0_resdetection_valid_i) begin + if (hdmi_in0_resdetection_p_vsync) begin + hdmi_in0_resdetection_vcounter_st <= hdmi_in0_resdetection_vcounter; + end + end else begin + hdmi_in0_resdetection_vcounter_st <= 1'd0; + end + hdmi_in0_frame_vsync_r <= hdmi_in0_frame_vsync; + hdmi_in0_frame_de_r <= hdmi_in0_frame_de; + hdmi_in0_frame_next_de0 <= hdmi_in0_frame_de; + hdmi_in0_frame_next_vsync0 <= hdmi_in0_frame_vsync; + hdmi_in0_frame_next_de1 <= hdmi_in0_frame_next_de0; + hdmi_in0_frame_next_vsync1 <= hdmi_in0_frame_next_vsync0; + hdmi_in0_frame_next_de2 <= hdmi_in0_frame_next_de1; + hdmi_in0_frame_next_vsync2 <= hdmi_in0_frame_next_vsync1; + hdmi_in0_frame_next_de3 <= hdmi_in0_frame_next_de2; + hdmi_in0_frame_next_vsync3 <= hdmi_in0_frame_next_vsync2; + hdmi_in0_frame_next_de4 <= hdmi_in0_frame_next_de3; + hdmi_in0_frame_next_vsync4 <= hdmi_in0_frame_next_vsync3; + hdmi_in0_frame_next_de5 <= hdmi_in0_frame_next_de4; + hdmi_in0_frame_next_vsync5 <= hdmi_in0_frame_next_vsync4; + hdmi_in0_frame_next_de6 <= hdmi_in0_frame_next_de5; + hdmi_in0_frame_next_vsync6 <= hdmi_in0_frame_next_vsync5; + hdmi_in0_frame_next_de7 <= hdmi_in0_frame_next_de6; + hdmi_in0_frame_next_vsync7 <= hdmi_in0_frame_next_vsync6; + hdmi_in0_frame_next_de8 <= hdmi_in0_frame_next_de7; + hdmi_in0_frame_next_vsync8 <= hdmi_in0_frame_next_vsync7; + hdmi_in0_frame_next_de9 <= hdmi_in0_frame_next_de8; + hdmi_in0_frame_next_vsync9 <= hdmi_in0_frame_next_vsync8; + hdmi_in0_frame_next_de10 <= hdmi_in0_frame_next_de9; + hdmi_in0_frame_next_vsync10 <= hdmi_in0_frame_next_vsync9; + hdmi_in0_frame_cur_word_valid <= 1'd0; + if (hdmi_in0_frame_new_frame) begin + hdmi_in0_frame_cur_word_valid <= (hdmi_in0_frame_pack_counter == 4'd15); + hdmi_in0_frame_pack_counter <= 1'd0; + end else begin + if ((hdmi_in0_frame_chroma_downsampler_source_valid & hdmi_in0_frame_next_de10)) begin + if ((hdmi_in0_frame_pack_counter == 4'd15)) begin + hdmi_in0_frame_cur_word[15:0] <= hdmi_in0_frame_encoded_pixel; + end + if ((hdmi_in0_frame_pack_counter == 4'd14)) begin + hdmi_in0_frame_cur_word[31:16] <= hdmi_in0_frame_encoded_pixel; + end + if ((hdmi_in0_frame_pack_counter == 4'd13)) begin + hdmi_in0_frame_cur_word[47:32] <= hdmi_in0_frame_encoded_pixel; + end + if ((hdmi_in0_frame_pack_counter == 4'd12)) begin + hdmi_in0_frame_cur_word[63:48] <= hdmi_in0_frame_encoded_pixel; + end + if ((hdmi_in0_frame_pack_counter == 4'd11)) begin + hdmi_in0_frame_cur_word[79:64] <= hdmi_in0_frame_encoded_pixel; + end + if ((hdmi_in0_frame_pack_counter == 4'd10)) begin + hdmi_in0_frame_cur_word[95:80] <= hdmi_in0_frame_encoded_pixel; + end + if ((hdmi_in0_frame_pack_counter == 4'd9)) begin + hdmi_in0_frame_cur_word[111:96] <= hdmi_in0_frame_encoded_pixel; + end + if ((hdmi_in0_frame_pack_counter == 4'd8)) begin + hdmi_in0_frame_cur_word[127:112] <= hdmi_in0_frame_encoded_pixel; + end + if ((hdmi_in0_frame_pack_counter == 3'd7)) begin + hdmi_in0_frame_cur_word[143:128] <= hdmi_in0_frame_encoded_pixel; + end + if ((hdmi_in0_frame_pack_counter == 3'd6)) begin + hdmi_in0_frame_cur_word[159:144] <= hdmi_in0_frame_encoded_pixel; + end + if ((hdmi_in0_frame_pack_counter == 3'd5)) begin + hdmi_in0_frame_cur_word[175:160] <= hdmi_in0_frame_encoded_pixel; + end + if ((hdmi_in0_frame_pack_counter == 3'd4)) begin + hdmi_in0_frame_cur_word[191:176] <= hdmi_in0_frame_encoded_pixel; + end + if ((hdmi_in0_frame_pack_counter == 2'd3)) begin + hdmi_in0_frame_cur_word[207:192] <= hdmi_in0_frame_encoded_pixel; + end + if ((hdmi_in0_frame_pack_counter == 2'd2)) begin + hdmi_in0_frame_cur_word[223:208] <= hdmi_in0_frame_encoded_pixel; + end + if ((hdmi_in0_frame_pack_counter == 1'd1)) begin + hdmi_in0_frame_cur_word[239:224] <= hdmi_in0_frame_encoded_pixel; + end + if ((hdmi_in0_frame_pack_counter == 1'd0)) begin + hdmi_in0_frame_cur_word[255:240] <= hdmi_in0_frame_encoded_pixel; + end + hdmi_in0_frame_cur_word_valid <= (hdmi_in0_frame_pack_counter == 4'd15); + hdmi_in0_frame_pack_counter <= (hdmi_in0_frame_pack_counter + 1'd1); + end + end + if (hdmi_in0_frame_new_frame) begin + hdmi_in0_frame_fifo_sink_payload_sof <= 1'd1; + end else begin + if (hdmi_in0_frame_cur_word_valid) begin + hdmi_in0_frame_fifo_sink_payload_sof <= 1'd0; + end + end + if ((hdmi_in0_frame_fifo_sink_valid & (~hdmi_in0_frame_fifo_sink_ready))) begin + hdmi_in0_frame_pix_overflow <= 1'd1; + end else begin + if (hdmi_in0_frame_pix_overflow_reset) begin + hdmi_in0_frame_pix_overflow <= 1'd0; + end + end + if (hdmi_in0_frame_rgb2ycbcr_pipe_ce) begin + hdmi_in0_frame_rgb2ycbcr_valid_n0 <= hdmi_in0_frame_rgb2ycbcr_sink_valid; + end + if (hdmi_in0_frame_rgb2ycbcr_pipe_ce) begin + hdmi_in0_frame_rgb2ycbcr_valid_n1 <= hdmi_in0_frame_rgb2ycbcr_valid_n0; + end + if (hdmi_in0_frame_rgb2ycbcr_pipe_ce) begin + hdmi_in0_frame_rgb2ycbcr_valid_n2 <= hdmi_in0_frame_rgb2ycbcr_valid_n1; + end + if (hdmi_in0_frame_rgb2ycbcr_pipe_ce) begin + hdmi_in0_frame_rgb2ycbcr_valid_n3 <= hdmi_in0_frame_rgb2ycbcr_valid_n2; + end + if (hdmi_in0_frame_rgb2ycbcr_pipe_ce) begin + hdmi_in0_frame_rgb2ycbcr_valid_n4 <= hdmi_in0_frame_rgb2ycbcr_valid_n3; + end + if (hdmi_in0_frame_rgb2ycbcr_pipe_ce) begin + hdmi_in0_frame_rgb2ycbcr_valid_n5 <= hdmi_in0_frame_rgb2ycbcr_valid_n4; + end + if (hdmi_in0_frame_rgb2ycbcr_pipe_ce) begin + hdmi_in0_frame_rgb2ycbcr_valid_n6 <= hdmi_in0_frame_rgb2ycbcr_valid_n5; + end + if (hdmi_in0_frame_rgb2ycbcr_pipe_ce) begin + hdmi_in0_frame_rgb2ycbcr_valid_n7 <= hdmi_in0_frame_rgb2ycbcr_valid_n6; + end + if (hdmi_in0_frame_rgb2ycbcr_pipe_ce) begin + hdmi_in0_frame_rgb2ycbcr_first_n0 <= (hdmi_in0_frame_rgb2ycbcr_sink_valid & hdmi_in0_frame_rgb2ycbcr_sink_first); + hdmi_in0_frame_rgb2ycbcr_last_n0 <= (hdmi_in0_frame_rgb2ycbcr_sink_valid & hdmi_in0_frame_rgb2ycbcr_sink_last); + end + if (hdmi_in0_frame_rgb2ycbcr_pipe_ce) begin + hdmi_in0_frame_rgb2ycbcr_first_n1 <= hdmi_in0_frame_rgb2ycbcr_first_n0; + hdmi_in0_frame_rgb2ycbcr_last_n1 <= hdmi_in0_frame_rgb2ycbcr_last_n0; + end + if (hdmi_in0_frame_rgb2ycbcr_pipe_ce) begin + hdmi_in0_frame_rgb2ycbcr_first_n2 <= hdmi_in0_frame_rgb2ycbcr_first_n1; + hdmi_in0_frame_rgb2ycbcr_last_n2 <= hdmi_in0_frame_rgb2ycbcr_last_n1; + end + if (hdmi_in0_frame_rgb2ycbcr_pipe_ce) begin + hdmi_in0_frame_rgb2ycbcr_first_n3 <= hdmi_in0_frame_rgb2ycbcr_first_n2; + hdmi_in0_frame_rgb2ycbcr_last_n3 <= hdmi_in0_frame_rgb2ycbcr_last_n2; + end + if (hdmi_in0_frame_rgb2ycbcr_pipe_ce) begin + hdmi_in0_frame_rgb2ycbcr_first_n4 <= hdmi_in0_frame_rgb2ycbcr_first_n3; + hdmi_in0_frame_rgb2ycbcr_last_n4 <= hdmi_in0_frame_rgb2ycbcr_last_n3; + end + if (hdmi_in0_frame_rgb2ycbcr_pipe_ce) begin + hdmi_in0_frame_rgb2ycbcr_first_n5 <= hdmi_in0_frame_rgb2ycbcr_first_n4; + hdmi_in0_frame_rgb2ycbcr_last_n5 <= hdmi_in0_frame_rgb2ycbcr_last_n4; + end + if (hdmi_in0_frame_rgb2ycbcr_pipe_ce) begin + hdmi_in0_frame_rgb2ycbcr_first_n6 <= hdmi_in0_frame_rgb2ycbcr_first_n5; + hdmi_in0_frame_rgb2ycbcr_last_n6 <= hdmi_in0_frame_rgb2ycbcr_last_n5; + end + if (hdmi_in0_frame_rgb2ycbcr_pipe_ce) begin + hdmi_in0_frame_rgb2ycbcr_first_n7 <= hdmi_in0_frame_rgb2ycbcr_first_n6; + hdmi_in0_frame_rgb2ycbcr_last_n7 <= hdmi_in0_frame_rgb2ycbcr_last_n6; + end + if (hdmi_in0_frame_rgb2ycbcr_ce) begin + hdmi_in0_frame_rgb2ycbcr_record0_rgb_n_r <= hdmi_in0_frame_rgb2ycbcr_sink_r; + hdmi_in0_frame_rgb2ycbcr_record0_rgb_n_g <= hdmi_in0_frame_rgb2ycbcr_sink_g; + hdmi_in0_frame_rgb2ycbcr_record0_rgb_n_b <= hdmi_in0_frame_rgb2ycbcr_sink_b; + hdmi_in0_frame_rgb2ycbcr_record1_rgb_n_r <= hdmi_in0_frame_rgb2ycbcr_record0_rgb_n_r; + hdmi_in0_frame_rgb2ycbcr_record1_rgb_n_g <= hdmi_in0_frame_rgb2ycbcr_record0_rgb_n_g; + hdmi_in0_frame_rgb2ycbcr_record1_rgb_n_b <= hdmi_in0_frame_rgb2ycbcr_record0_rgb_n_b; + hdmi_in0_frame_rgb2ycbcr_record2_rgb_n_r <= hdmi_in0_frame_rgb2ycbcr_record1_rgb_n_r; + hdmi_in0_frame_rgb2ycbcr_record2_rgb_n_g <= hdmi_in0_frame_rgb2ycbcr_record1_rgb_n_g; + hdmi_in0_frame_rgb2ycbcr_record2_rgb_n_b <= hdmi_in0_frame_rgb2ycbcr_record1_rgb_n_b; + hdmi_in0_frame_rgb2ycbcr_record3_rgb_n_r <= hdmi_in0_frame_rgb2ycbcr_record2_rgb_n_r; + hdmi_in0_frame_rgb2ycbcr_record3_rgb_n_g <= hdmi_in0_frame_rgb2ycbcr_record2_rgb_n_g; + hdmi_in0_frame_rgb2ycbcr_record3_rgb_n_b <= hdmi_in0_frame_rgb2ycbcr_record2_rgb_n_b; + hdmi_in0_frame_rgb2ycbcr_record4_rgb_n_r <= hdmi_in0_frame_rgb2ycbcr_record3_rgb_n_r; + hdmi_in0_frame_rgb2ycbcr_record4_rgb_n_g <= hdmi_in0_frame_rgb2ycbcr_record3_rgb_n_g; + hdmi_in0_frame_rgb2ycbcr_record4_rgb_n_b <= hdmi_in0_frame_rgb2ycbcr_record3_rgb_n_b; + hdmi_in0_frame_rgb2ycbcr_record5_rgb_n_r <= hdmi_in0_frame_rgb2ycbcr_record4_rgb_n_r; + hdmi_in0_frame_rgb2ycbcr_record5_rgb_n_g <= hdmi_in0_frame_rgb2ycbcr_record4_rgb_n_g; + hdmi_in0_frame_rgb2ycbcr_record5_rgb_n_b <= hdmi_in0_frame_rgb2ycbcr_record4_rgb_n_b; + hdmi_in0_frame_rgb2ycbcr_record6_rgb_n_r <= hdmi_in0_frame_rgb2ycbcr_record5_rgb_n_r; + hdmi_in0_frame_rgb2ycbcr_record6_rgb_n_g <= hdmi_in0_frame_rgb2ycbcr_record5_rgb_n_g; + hdmi_in0_frame_rgb2ycbcr_record6_rgb_n_b <= hdmi_in0_frame_rgb2ycbcr_record5_rgb_n_b; + hdmi_in0_frame_rgb2ycbcr_record7_rgb_n_r <= hdmi_in0_frame_rgb2ycbcr_record6_rgb_n_r; + hdmi_in0_frame_rgb2ycbcr_record7_rgb_n_g <= hdmi_in0_frame_rgb2ycbcr_record6_rgb_n_g; + hdmi_in0_frame_rgb2ycbcr_record7_rgb_n_b <= hdmi_in0_frame_rgb2ycbcr_record6_rgb_n_b; + hdmi_in0_frame_rgb2ycbcr_r_minus_g <= (hdmi_in0_frame_rgb2ycbcr_sink_r - hdmi_in0_frame_rgb2ycbcr_sink_g); + hdmi_in0_frame_rgb2ycbcr_b_minus_g <= (hdmi_in0_frame_rgb2ycbcr_sink_b - hdmi_in0_frame_rgb2ycbcr_sink_g); + hdmi_in0_frame_rgb2ycbcr_ca_mult_rg <= (hdmi_in0_frame_rgb2ycbcr_r_minus_g * $signed({1'd0, 6'd46})); + hdmi_in0_frame_rgb2ycbcr_cb_mult_bg <= (hdmi_in0_frame_rgb2ycbcr_b_minus_g * $signed({1'd0, 4'd15})); + hdmi_in0_frame_rgb2ycbcr_carg_plus_cbbg <= (hdmi_in0_frame_rgb2ycbcr_ca_mult_rg + hdmi_in0_frame_rgb2ycbcr_cb_mult_bg); + hdmi_in0_frame_rgb2ycbcr_yraw <= (hdmi_in0_frame_rgb2ycbcr_carg_plus_cbbg[24:8] + $signed({1'd0, hdmi_in0_frame_rgb2ycbcr_record2_rgb_n_g})); + hdmi_in0_frame_rgb2ycbcr_b_minus_yraw <= ($signed({1'd0, hdmi_in0_frame_rgb2ycbcr_record3_rgb_n_b}) - hdmi_in0_frame_rgb2ycbcr_yraw); + hdmi_in0_frame_rgb2ycbcr_r_minus_yraw <= ($signed({1'd0, hdmi_in0_frame_rgb2ycbcr_record3_rgb_n_r}) - hdmi_in0_frame_rgb2ycbcr_yraw); + hdmi_in0_frame_rgb2ycbcr_yraw_r0 <= hdmi_in0_frame_rgb2ycbcr_yraw; + hdmi_in0_frame_rgb2ycbcr_cc_mult_ryraw <= (hdmi_in0_frame_rgb2ycbcr_b_minus_yraw * $signed({1'd0, 8'd141})); + hdmi_in0_frame_rgb2ycbcr_cd_mult_byraw <= (hdmi_in0_frame_rgb2ycbcr_r_minus_yraw * $signed({1'd0, 8'd166})); + hdmi_in0_frame_rgb2ycbcr_yraw_r1 <= hdmi_in0_frame_rgb2ycbcr_yraw_r0; + hdmi_in0_frame_rgb2ycbcr_y <= (hdmi_in0_frame_rgb2ycbcr_yraw_r1 + $signed({1'd0, 5'd16})); + hdmi_in0_frame_rgb2ycbcr_cb <= (hdmi_in0_frame_rgb2ycbcr_cc_mult_ryraw[19:8] + $signed({1'd0, 8'd128})); + hdmi_in0_frame_rgb2ycbcr_cr <= (hdmi_in0_frame_rgb2ycbcr_cd_mult_byraw[19:8] + $signed({1'd0, 8'd128})); + if ((hdmi_in0_frame_rgb2ycbcr_y > $signed({1'd0, 8'd255}))) begin + hdmi_in0_frame_rgb2ycbcr_source_y <= 8'd255; + end else begin + if ((hdmi_in0_frame_rgb2ycbcr_y < $signed({1'd0, 1'd0}))) begin + hdmi_in0_frame_rgb2ycbcr_source_y <= 1'd0; + end else begin + hdmi_in0_frame_rgb2ycbcr_source_y <= hdmi_in0_frame_rgb2ycbcr_y; + end + end + if ((hdmi_in0_frame_rgb2ycbcr_cb > $signed({1'd0, 8'd255}))) begin + hdmi_in0_frame_rgb2ycbcr_source_cb <= 8'd255; + end else begin + if ((hdmi_in0_frame_rgb2ycbcr_cb < $signed({1'd0, 1'd0}))) begin + hdmi_in0_frame_rgb2ycbcr_source_cb <= 1'd0; + end else begin + hdmi_in0_frame_rgb2ycbcr_source_cb <= hdmi_in0_frame_rgb2ycbcr_cb; + end + end + if ((hdmi_in0_frame_rgb2ycbcr_cr > $signed({1'd0, 8'd255}))) begin + hdmi_in0_frame_rgb2ycbcr_source_cr <= 8'd255; + end else begin + if ((hdmi_in0_frame_rgb2ycbcr_cr < $signed({1'd0, 1'd0}))) begin + hdmi_in0_frame_rgb2ycbcr_source_cr <= 1'd0; + end else begin + hdmi_in0_frame_rgb2ycbcr_source_cr <= hdmi_in0_frame_rgb2ycbcr_cr; + end + end + end + if (hdmi_in0_frame_chroma_downsampler_pipe_ce) begin + hdmi_in0_frame_chroma_downsampler_valid_n0 <= hdmi_in0_frame_chroma_downsampler_sink_valid; + end + if (hdmi_in0_frame_chroma_downsampler_pipe_ce) begin + hdmi_in0_frame_chroma_downsampler_valid_n1 <= hdmi_in0_frame_chroma_downsampler_valid_n0; + end + if (hdmi_in0_frame_chroma_downsampler_pipe_ce) begin + hdmi_in0_frame_chroma_downsampler_valid_n2 <= hdmi_in0_frame_chroma_downsampler_valid_n1; + end + if (hdmi_in0_frame_chroma_downsampler_pipe_ce) begin + hdmi_in0_frame_chroma_downsampler_first_n0 <= (hdmi_in0_frame_chroma_downsampler_sink_valid & hdmi_in0_frame_chroma_downsampler_sink_first); + hdmi_in0_frame_chroma_downsampler_last_n0 <= (hdmi_in0_frame_chroma_downsampler_sink_valid & hdmi_in0_frame_chroma_downsampler_sink_last); + end + if (hdmi_in0_frame_chroma_downsampler_pipe_ce) begin + hdmi_in0_frame_chroma_downsampler_first_n1 <= hdmi_in0_frame_chroma_downsampler_first_n0; + hdmi_in0_frame_chroma_downsampler_last_n1 <= hdmi_in0_frame_chroma_downsampler_last_n0; + end + if (hdmi_in0_frame_chroma_downsampler_pipe_ce) begin + hdmi_in0_frame_chroma_downsampler_first_n2 <= hdmi_in0_frame_chroma_downsampler_first_n1; + hdmi_in0_frame_chroma_downsampler_last_n2 <= hdmi_in0_frame_chroma_downsampler_last_n1; + end + if (hdmi_in0_frame_chroma_downsampler_ce) begin + hdmi_in0_frame_chroma_downsampler_record0_ycbcr_n_y <= hdmi_in0_frame_chroma_downsampler_sink_y; + hdmi_in0_frame_chroma_downsampler_record0_ycbcr_n_cb <= hdmi_in0_frame_chroma_downsampler_sink_cb; + hdmi_in0_frame_chroma_downsampler_record0_ycbcr_n_cr <= hdmi_in0_frame_chroma_downsampler_sink_cr; + hdmi_in0_frame_chroma_downsampler_record1_ycbcr_n_y <= hdmi_in0_frame_chroma_downsampler_record0_ycbcr_n_y; + hdmi_in0_frame_chroma_downsampler_record1_ycbcr_n_cb <= hdmi_in0_frame_chroma_downsampler_record0_ycbcr_n_cb; + hdmi_in0_frame_chroma_downsampler_record1_ycbcr_n_cr <= hdmi_in0_frame_chroma_downsampler_record0_ycbcr_n_cr; + hdmi_in0_frame_chroma_downsampler_record2_ycbcr_n_y <= hdmi_in0_frame_chroma_downsampler_record1_ycbcr_n_y; + hdmi_in0_frame_chroma_downsampler_record2_ycbcr_n_cb <= hdmi_in0_frame_chroma_downsampler_record1_ycbcr_n_cb; + hdmi_in0_frame_chroma_downsampler_record2_ycbcr_n_cr <= hdmi_in0_frame_chroma_downsampler_record1_ycbcr_n_cr; + if ((hdmi_in0_frame_chroma_downsampler_first | (~hdmi_in0_frame_chroma_downsampler_parity))) begin + hdmi_in0_frame_chroma_downsampler_parity <= 1'd1; + end else begin + hdmi_in0_frame_chroma_downsampler_parity <= 1'd0; + end + if (hdmi_in0_frame_chroma_downsampler_parity) begin + hdmi_in0_frame_chroma_downsampler_cb_sum <= (hdmi_in0_frame_chroma_downsampler_sink_cb + hdmi_in0_frame_chroma_downsampler_record0_ycbcr_n_cb); + hdmi_in0_frame_chroma_downsampler_cr_sum <= (hdmi_in0_frame_chroma_downsampler_sink_cr + hdmi_in0_frame_chroma_downsampler_record0_ycbcr_n_cr); + end + if (hdmi_in0_frame_chroma_downsampler_parity) begin + hdmi_in0_frame_chroma_downsampler_source_y <= hdmi_in0_frame_chroma_downsampler_record1_ycbcr_n_y; + hdmi_in0_frame_chroma_downsampler_source_cb_cr <= hdmi_in0_frame_chroma_downsampler_cr_mean; + end else begin + hdmi_in0_frame_chroma_downsampler_source_y <= hdmi_in0_frame_chroma_downsampler_record1_ycbcr_n_y; + hdmi_in0_frame_chroma_downsampler_source_cb_cr <= hdmi_in0_frame_chroma_downsampler_cb_mean; + end + end + hdmi_in0_frame_fifo_graycounter0_q_binary <= hdmi_in0_frame_fifo_graycounter0_q_next_binary; + hdmi_in0_frame_fifo_graycounter0_q <= hdmi_in0_frame_fifo_graycounter0_q_next; + hdmi_in0_frame_overflow_reset_toggle_o_r <= hdmi_in0_frame_overflow_reset_toggle_o; + if (hdmi_in0_frame_overflow_reset_ack_i) begin + hdmi_in0_frame_overflow_reset_ack_toggle_i <= (~hdmi_in0_frame_overflow_reset_ack_toggle_i); + end + if (hdmi_in0_pix_rst) begin + hdmi_in0_charsync0_synced <= 1'd0; + hdmi_in0_charsync0_data <= 10'd0; + hdmi_in0_charsync0_raw_data1 <= 10'd0; + hdmi_in0_charsync0_found_control <= 1'd0; + hdmi_in0_charsync0_control_position <= 4'd0; + hdmi_in0_charsync0_control_counter <= 3'd0; + hdmi_in0_charsync0_previous_control_position <= 4'd0; + hdmi_in0_charsync0_word_sel <= 4'd0; + hdmi_in0_wer0_data_r <= 9'd0; + hdmi_in0_wer0_transition_count <= 4'd0; + hdmi_in0_wer0_is_control <= 1'd0; + hdmi_in0_wer0_is_error <= 1'd0; + hdmi_in0_wer0_period_counter <= 24'd0; + hdmi_in0_wer0_period_done <= 1'd0; + hdmi_in0_wer0_wer_counter <= 24'd0; + hdmi_in0_wer0_wer_counter_r <= 24'd0; + hdmi_in0_wer0_wer_counter_r_updated <= 1'd0; + hdmi_in0_decoding0_valid_o <= 1'd0; + hdmi_in0_decoding0_output_raw <= 10'd0; + hdmi_in0_decoding0_output_d <= 8'd0; + hdmi_in0_decoding0_output_c <= 2'd0; + hdmi_in0_decoding0_output_de <= 1'd0; + hdmi_in0_charsync1_synced <= 1'd0; + hdmi_in0_charsync1_data <= 10'd0; + hdmi_in0_charsync1_raw_data1 <= 10'd0; + hdmi_in0_charsync1_found_control <= 1'd0; + hdmi_in0_charsync1_control_position <= 4'd0; + hdmi_in0_charsync1_control_counter <= 3'd0; + hdmi_in0_charsync1_previous_control_position <= 4'd0; + hdmi_in0_charsync1_word_sel <= 4'd0; + hdmi_in0_wer1_data_r <= 9'd0; + hdmi_in0_wer1_transition_count <= 4'd0; + hdmi_in0_wer1_is_control <= 1'd0; + hdmi_in0_wer1_is_error <= 1'd0; + hdmi_in0_wer1_period_counter <= 24'd0; + hdmi_in0_wer1_period_done <= 1'd0; + hdmi_in0_wer1_wer_counter <= 24'd0; + hdmi_in0_wer1_wer_counter_r <= 24'd0; + hdmi_in0_wer1_wer_counter_r_updated <= 1'd0; + hdmi_in0_decoding1_valid_o <= 1'd0; + hdmi_in0_decoding1_output_raw <= 10'd0; + hdmi_in0_decoding1_output_d <= 8'd0; + hdmi_in0_decoding1_output_c <= 2'd0; + hdmi_in0_decoding1_output_de <= 1'd0; + hdmi_in0_charsync2_synced <= 1'd0; + hdmi_in0_charsync2_data <= 10'd0; + hdmi_in0_charsync2_raw_data1 <= 10'd0; + hdmi_in0_charsync2_found_control <= 1'd0; + hdmi_in0_charsync2_control_position <= 4'd0; + hdmi_in0_charsync2_control_counter <= 3'd0; + hdmi_in0_charsync2_previous_control_position <= 4'd0; + hdmi_in0_charsync2_word_sel <= 4'd0; + hdmi_in0_wer2_data_r <= 9'd0; + hdmi_in0_wer2_transition_count <= 4'd0; + hdmi_in0_wer2_is_control <= 1'd0; + hdmi_in0_wer2_is_error <= 1'd0; + hdmi_in0_wer2_period_counter <= 24'd0; + hdmi_in0_wer2_period_done <= 1'd0; + hdmi_in0_wer2_wer_counter <= 24'd0; + hdmi_in0_wer2_wer_counter_r <= 24'd0; + hdmi_in0_wer2_wer_counter_r_updated <= 1'd0; + hdmi_in0_decoding2_valid_o <= 1'd0; + hdmi_in0_decoding2_output_raw <= 10'd0; + hdmi_in0_decoding2_output_d <= 8'd0; + hdmi_in0_decoding2_output_c <= 2'd0; + hdmi_in0_decoding2_output_de <= 1'd0; + hdmi_in0_chansync_chan_synced <= 1'd0; + hdmi_in0_chansync_syncbuffer0_produce <= 3'd0; + hdmi_in0_chansync_syncbuffer0_consume <= 3'd0; + hdmi_in0_chansync_syncbuffer1_produce <= 3'd0; + hdmi_in0_chansync_syncbuffer1_consume <= 3'd0; + hdmi_in0_chansync_syncbuffer2_produce <= 3'd0; + hdmi_in0_chansync_syncbuffer2_consume <= 3'd0; + hdmi_in0_syncpol_valid_o <= 1'd0; + hdmi_in0_syncpol_r <= 8'd0; + hdmi_in0_syncpol_g <= 8'd0; + hdmi_in0_syncpol_b <= 8'd0; + hdmi_in0_syncpol_de_r <= 1'd0; + hdmi_in0_syncpol_c_polarity <= 2'd0; + hdmi_in0_syncpol_c_out <= 2'd0; + hdmi_in0_resdetection_de_r <= 1'd0; + hdmi_in0_resdetection_hcounter <= 11'd0; + hdmi_in0_resdetection_hcounter_st <= 11'd0; + hdmi_in0_resdetection_vsync_r <= 1'd0; + hdmi_in0_resdetection_vcounter <= 11'd0; + hdmi_in0_resdetection_vcounter_st <= 11'd0; + hdmi_in0_frame_vsync_r <= 1'd0; + hdmi_in0_frame_de_r <= 1'd0; + hdmi_in0_frame_rgb2ycbcr_source_y <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_source_cb <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_source_cr <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record0_rgb_n_r <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record0_rgb_n_g <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record0_rgb_n_b <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record1_rgb_n_r <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record1_rgb_n_g <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record1_rgb_n_b <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record2_rgb_n_r <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record2_rgb_n_g <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record2_rgb_n_b <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record3_rgb_n_r <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record3_rgb_n_g <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record3_rgb_n_b <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record4_rgb_n_r <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record4_rgb_n_g <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record4_rgb_n_b <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record5_rgb_n_r <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record5_rgb_n_g <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record5_rgb_n_b <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record6_rgb_n_r <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record6_rgb_n_g <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record6_rgb_n_b <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record7_rgb_n_r <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record7_rgb_n_g <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_record7_rgb_n_b <= 8'd0; + hdmi_in0_frame_rgb2ycbcr_r_minus_g <= 9'd0; + hdmi_in0_frame_rgb2ycbcr_b_minus_g <= 9'd0; + hdmi_in0_frame_rgb2ycbcr_ca_mult_rg <= 17'd0; + hdmi_in0_frame_rgb2ycbcr_cb_mult_bg <= 17'd0; + hdmi_in0_frame_rgb2ycbcr_carg_plus_cbbg <= 25'd0; + hdmi_in0_frame_rgb2ycbcr_yraw <= 11'd0; + hdmi_in0_frame_rgb2ycbcr_b_minus_yraw <= 12'd0; + hdmi_in0_frame_rgb2ycbcr_r_minus_yraw <= 12'd0; + hdmi_in0_frame_rgb2ycbcr_yraw_r0 <= 11'd0; + hdmi_in0_frame_rgb2ycbcr_cc_mult_ryraw <= 20'd0; + hdmi_in0_frame_rgb2ycbcr_cd_mult_byraw <= 20'd0; + hdmi_in0_frame_rgb2ycbcr_yraw_r1 <= 11'd0; + hdmi_in0_frame_rgb2ycbcr_y <= 11'd0; + hdmi_in0_frame_rgb2ycbcr_cb <= 12'd0; + hdmi_in0_frame_rgb2ycbcr_cr <= 12'd0; + hdmi_in0_frame_rgb2ycbcr_valid_n0 <= 1'd0; + hdmi_in0_frame_rgb2ycbcr_valid_n1 <= 1'd0; + hdmi_in0_frame_rgb2ycbcr_valid_n2 <= 1'd0; + hdmi_in0_frame_rgb2ycbcr_valid_n3 <= 1'd0; + hdmi_in0_frame_rgb2ycbcr_valid_n4 <= 1'd0; + hdmi_in0_frame_rgb2ycbcr_valid_n5 <= 1'd0; + hdmi_in0_frame_rgb2ycbcr_valid_n6 <= 1'd0; + hdmi_in0_frame_rgb2ycbcr_valid_n7 <= 1'd0; + hdmi_in0_frame_chroma_downsampler_source_y <= 8'd0; + hdmi_in0_frame_chroma_downsampler_source_cb_cr <= 8'd0; + hdmi_in0_frame_chroma_downsampler_record0_ycbcr_n_y <= 8'd0; + hdmi_in0_frame_chroma_downsampler_record0_ycbcr_n_cb <= 8'd0; + hdmi_in0_frame_chroma_downsampler_record0_ycbcr_n_cr <= 8'd0; + hdmi_in0_frame_chroma_downsampler_record1_ycbcr_n_y <= 8'd0; + hdmi_in0_frame_chroma_downsampler_record1_ycbcr_n_cb <= 8'd0; + hdmi_in0_frame_chroma_downsampler_record1_ycbcr_n_cr <= 8'd0; + hdmi_in0_frame_chroma_downsampler_record2_ycbcr_n_y <= 8'd0; + hdmi_in0_frame_chroma_downsampler_record2_ycbcr_n_cb <= 8'd0; + hdmi_in0_frame_chroma_downsampler_record2_ycbcr_n_cr <= 8'd0; + hdmi_in0_frame_chroma_downsampler_parity <= 1'd0; + hdmi_in0_frame_chroma_downsampler_cb_sum <= 9'd0; + hdmi_in0_frame_chroma_downsampler_cr_sum <= 9'd0; + hdmi_in0_frame_chroma_downsampler_valid_n0 <= 1'd0; + hdmi_in0_frame_chroma_downsampler_valid_n1 <= 1'd0; + hdmi_in0_frame_chroma_downsampler_valid_n2 <= 1'd0; + hdmi_in0_frame_next_de0 <= 1'd0; + hdmi_in0_frame_next_vsync0 <= 1'd0; + hdmi_in0_frame_next_de1 <= 1'd0; + hdmi_in0_frame_next_vsync1 <= 1'd0; + hdmi_in0_frame_next_de2 <= 1'd0; + hdmi_in0_frame_next_vsync2 <= 1'd0; + hdmi_in0_frame_next_de3 <= 1'd0; + hdmi_in0_frame_next_vsync3 <= 1'd0; + hdmi_in0_frame_next_de4 <= 1'd0; + hdmi_in0_frame_next_vsync4 <= 1'd0; + hdmi_in0_frame_next_de5 <= 1'd0; + hdmi_in0_frame_next_vsync5 <= 1'd0; + hdmi_in0_frame_next_de6 <= 1'd0; + hdmi_in0_frame_next_vsync6 <= 1'd0; + hdmi_in0_frame_next_de7 <= 1'd0; + hdmi_in0_frame_next_vsync7 <= 1'd0; + hdmi_in0_frame_next_de8 <= 1'd0; + hdmi_in0_frame_next_vsync8 <= 1'd0; + hdmi_in0_frame_next_de9 <= 1'd0; + hdmi_in0_frame_next_vsync9 <= 1'd0; + hdmi_in0_frame_next_de10 <= 1'd0; + hdmi_in0_frame_next_vsync10 <= 1'd0; + hdmi_in0_frame_cur_word <= 256'd0; + hdmi_in0_frame_cur_word_valid <= 1'd0; + hdmi_in0_frame_pack_counter <= 4'd0; + hdmi_in0_frame_fifo_sink_payload_sof <= 1'd0; + hdmi_in0_frame_fifo_graycounter0_q <= 10'd0; + hdmi_in0_frame_fifo_graycounter0_q_binary <= 10'd0; + hdmi_in0_frame_pix_overflow <= 1'd0; + end + xilinxmultiregimpl75_regs0 <= hdmi_in0_frame_fifo_graycounter1_q; + xilinxmultiregimpl75_regs1 <= xilinxmultiregimpl75_regs0; + xilinxmultiregimpl77_regs0 <= hdmi_in0_frame_overflow_reset_toggle_i; + xilinxmultiregimpl77_regs1 <= xilinxmultiregimpl77_regs0; +end + +always @(posedge hdmi_out0_pix_clk) begin + litedramcrossbar_cmd_cdc_cdc_graycounter0_q_binary <= litedramcrossbar_cmd_cdc_cdc_graycounter0_q_next_binary; + litedramcrossbar_cmd_cdc_cdc_graycounter0_q <= litedramcrossbar_cmd_cdc_cdc_graycounter0_q_next; + litedramcrossbar_rdata_cdc_cdc_graycounter1_q_binary <= litedramcrossbar_rdata_cdc_cdc_graycounter1_q_next_binary; + litedramcrossbar_rdata_cdc_cdc_graycounter1_q <= litedramcrossbar_rdata_cdc_cdc_graycounter1_q_next; + if (litedramcrossbar_wdata_finished) begin + litedramcrossbar_read_lock <= 1'd0; + litedramcrossbar_read_unlocked <= 1'd1; + end else begin + if (((litedramcrossbar_rw_collision & (~litedramcrossbar_litedramnativeport0_cmd_valid1)) & (~litedramcrossbar_read_unlocked))) begin + litedramcrossbar_read_lock <= 1'd1; + end + end + if ((litedramcrossbar_litedramnativeport1_cmd_valid1 & litedramcrossbar_litedramnativeport1_cmd_ready1)) begin + litedramcrossbar_read_unlocked <= 1'd0; + end + if ((litedramcrossbar_rdata_converter_source_valid & litedramcrossbar_rdata_converter_source_ready)) begin + litedramcrossbar_rdata_chunk <= {litedramcrossbar_rdata_chunk[14:0], litedramcrossbar_rdata_chunk[15]}; + end + litedramcore_state <= litedramcore_next_state; + if (litedramcrossbar_cmd_addr_litedramcore_next_value_ce0) begin + litedramcrossbar_cmd_addr <= litedramcrossbar_cmd_addr_litedramcore_next_value0; + end + if (litedramcrossbar_cmd_we_litedramcore_next_value_ce1) begin + litedramcrossbar_cmd_we <= litedramcrossbar_cmd_we_litedramcore_next_value1; + end + if (litedramcrossbar_cmd_last_litedramcore_next_value_ce2) begin + litedramcrossbar_cmd_last <= litedramcrossbar_cmd_last_litedramcore_next_value2; + end + if (litedramcrossbar_sel_litedramcore_next_value_ce3) begin + litedramcrossbar_sel <= litedramcrossbar_sel_litedramcore_next_value3; + end + if (((litedramcrossbar_rdata_fifo_syncfifo_we & litedramcrossbar_rdata_fifo_syncfifo_writable) & (~litedramcrossbar_rdata_fifo_replace))) begin + if ((litedramcrossbar_rdata_fifo_produce == 4'd14)) begin + litedramcrossbar_rdata_fifo_produce <= 1'd0; + end else begin + litedramcrossbar_rdata_fifo_produce <= (litedramcrossbar_rdata_fifo_produce + 1'd1); + end + end + if (litedramcrossbar_rdata_fifo_do_read) begin + if ((litedramcrossbar_rdata_fifo_consume == 4'd14)) begin + litedramcrossbar_rdata_fifo_consume <= 1'd0; + end else begin + litedramcrossbar_rdata_fifo_consume <= (litedramcrossbar_rdata_fifo_consume + 1'd1); + end + end + if (((litedramcrossbar_rdata_fifo_syncfifo_we & litedramcrossbar_rdata_fifo_syncfifo_writable) & (~litedramcrossbar_rdata_fifo_replace))) begin + if ((~litedramcrossbar_rdata_fifo_do_read)) begin + litedramcrossbar_rdata_fifo_level <= (litedramcrossbar_rdata_fifo_level + 1'd1); + end + end else begin + if (litedramcrossbar_rdata_fifo_do_read) begin + litedramcrossbar_rdata_fifo_level <= (litedramcrossbar_rdata_fifo_level - 1'd1); + end + end + if ((litedramcrossbar_rdata_converter_converter_source_valid & litedramcrossbar_rdata_converter_converter_source_ready)) begin + if (litedramcrossbar_rdata_converter_converter_last) begin + litedramcrossbar_rdata_converter_converter_mux <= 1'd0; + end else begin + litedramcrossbar_rdata_converter_converter_mux <= (litedramcrossbar_rdata_converter_converter_mux + 1'd1); + end + end + hdmi_out0_de_r <= hdmi_out0_core_source_source_param_de; + hdmi_out0_core_source_valid_d <= hdmi_out0_core_source_source_valid; + hdmi_out0_core_source_data_d <= hdmi_out0_core_source_source_payload_data; + if (hdmi_out0_core_underflow_enable) begin + if ((~hdmi_out0_core_source_source_valid)) begin + hdmi_out0_core_underflow_counter <= (hdmi_out0_core_underflow_counter + 1'd1); + end + end else begin + hdmi_out0_core_underflow_counter <= 1'd0; + end + if (hdmi_out0_core_underflow_update) begin + hdmi_out0_core_underflow_counter_status <= hdmi_out0_core_underflow_counter; + end + hdmi_out0_core_initiator_cdc_graycounter1_q_binary <= hdmi_out0_core_initiator_cdc_graycounter1_q_next_binary; + hdmi_out0_core_initiator_cdc_graycounter1_q <= hdmi_out0_core_initiator_cdc_graycounter1_q_next; + if ((~hdmi_out0_core_timinggenerator_sink_valid)) begin + hdmi_out0_core_timinggenerator_hactive <= 1'd0; + hdmi_out0_core_timinggenerator_vactive <= 1'd0; + hdmi_out0_core_timinggenerator_hcounter <= 1'd0; + hdmi_out0_core_timinggenerator_vcounter <= 1'd0; + end else begin + if (hdmi_out0_core_timinggenerator_source_ready) begin + hdmi_out0_core_timinggenerator_source_last <= 1'd0; + hdmi_out0_core_timinggenerator_hcounter <= (hdmi_out0_core_timinggenerator_hcounter + 1'd1); + if ((hdmi_out0_core_timinggenerator_hcounter == 1'd0)) begin + hdmi_out0_core_timinggenerator_hactive <= 1'd1; + end + if ((hdmi_out0_core_timinggenerator_hcounter == hdmi_out0_core_timinggenerator_sink_payload_hres)) begin + hdmi_out0_core_timinggenerator_hactive <= 1'd0; + end + if ((hdmi_out0_core_timinggenerator_hcounter == hdmi_out0_core_timinggenerator_sink_payload_hsync_start)) begin + hdmi_out0_core_timinggenerator_source_payload_hsync <= 1'd1; + end + if ((hdmi_out0_core_timinggenerator_hcounter == hdmi_out0_core_timinggenerator_sink_payload_hsync_end)) begin + hdmi_out0_core_timinggenerator_source_payload_hsync <= 1'd0; + end + if ((hdmi_out0_core_timinggenerator_hcounter == hdmi_out0_core_timinggenerator_sink_payload_hscan)) begin + hdmi_out0_core_timinggenerator_hcounter <= 1'd0; + if ((hdmi_out0_core_timinggenerator_vcounter == hdmi_out0_core_timinggenerator_sink_payload_vscan)) begin + hdmi_out0_core_timinggenerator_vcounter <= 1'd0; + hdmi_out0_core_timinggenerator_source_last <= 1'd1; + end else begin + hdmi_out0_core_timinggenerator_vcounter <= (hdmi_out0_core_timinggenerator_vcounter + 1'd1); + end + end + if ((hdmi_out0_core_timinggenerator_vcounter == 1'd0)) begin + hdmi_out0_core_timinggenerator_vactive <= 1'd1; + end + if ((hdmi_out0_core_timinggenerator_vcounter == hdmi_out0_core_timinggenerator_sink_payload_vres)) begin + hdmi_out0_core_timinggenerator_vactive <= 1'd0; + end + if ((hdmi_out0_core_timinggenerator_vcounter == hdmi_out0_core_timinggenerator_sink_payload_vsync_start)) begin + hdmi_out0_core_timinggenerator_source_payload_vsync <= 1'd1; + end + if ((hdmi_out0_core_timinggenerator_vcounter == hdmi_out0_core_timinggenerator_sink_payload_vsync_end)) begin + hdmi_out0_core_timinggenerator_source_payload_vsync <= 1'd0; + end + end + end + if (hdmi_out0_core_dmareader_request_issued) begin + if ((~hdmi_out0_core_dmareader_data_dequeued)) begin + hdmi_out0_core_dmareader_rsv_level <= (hdmi_out0_core_dmareader_rsv_level + 1'd1); + end + end else begin + if (hdmi_out0_core_dmareader_data_dequeued) begin + hdmi_out0_core_dmareader_rsv_level <= (hdmi_out0_core_dmareader_rsv_level - 1'd1); + end + end + if (hdmi_out0_core_dmareader_fifo_syncfifo_re) begin + hdmi_out0_core_dmareader_fifo_readable <= 1'd1; + end else begin + if (hdmi_out0_core_dmareader_fifo_re) begin + hdmi_out0_core_dmareader_fifo_readable <= 1'd0; + end + end + if (((hdmi_out0_core_dmareader_fifo_syncfifo_we & hdmi_out0_core_dmareader_fifo_syncfifo_writable) & (~hdmi_out0_core_dmareader_fifo_replace))) begin + hdmi_out0_core_dmareader_fifo_produce <= (hdmi_out0_core_dmareader_fifo_produce + 1'd1); + end + if (hdmi_out0_core_dmareader_fifo_do_read) begin + hdmi_out0_core_dmareader_fifo_consume <= (hdmi_out0_core_dmareader_fifo_consume + 1'd1); + end + if (((hdmi_out0_core_dmareader_fifo_syncfifo_we & hdmi_out0_core_dmareader_fifo_syncfifo_writable) & (~hdmi_out0_core_dmareader_fifo_replace))) begin + if ((~hdmi_out0_core_dmareader_fifo_do_read)) begin + hdmi_out0_core_dmareader_fifo_level0 <= (hdmi_out0_core_dmareader_fifo_level0 + 1'd1); + end + end else begin + if (hdmi_out0_core_dmareader_fifo_do_read) begin + hdmi_out0_core_dmareader_fifo_level0 <= (hdmi_out0_core_dmareader_fifo_level0 - 1'd1); + end + end + videoout_state <= videoout_next_state; + if (hdmi_out0_core_dmareader_offset_videoout_next_value_ce) begin + hdmi_out0_core_dmareader_offset <= hdmi_out0_core_dmareader_offset_videoout_next_value; + end + hdmi_out0_core_toggle_o_r <= hdmi_out0_core_toggle_o; + if ((hdmi_out0_resetinserter_sink_sink_valid & hdmi_out0_resetinserter_sink_sink_ready)) begin + hdmi_out0_resetinserter_parity_in <= (~hdmi_out0_resetinserter_parity_in); + end + if ((hdmi_out0_resetinserter_source_source_valid & hdmi_out0_resetinserter_source_source_ready)) begin + hdmi_out0_resetinserter_parity_out <= (~hdmi_out0_resetinserter_parity_out); + end + if (((hdmi_out0_resetinserter_y_fifo_syncfifo_we & hdmi_out0_resetinserter_y_fifo_syncfifo_writable) & (~hdmi_out0_resetinserter_y_fifo_replace))) begin + hdmi_out0_resetinserter_y_fifo_produce <= (hdmi_out0_resetinserter_y_fifo_produce + 1'd1); + end + if (hdmi_out0_resetinserter_y_fifo_do_read) begin + hdmi_out0_resetinserter_y_fifo_consume <= (hdmi_out0_resetinserter_y_fifo_consume + 1'd1); + end + if (((hdmi_out0_resetinserter_y_fifo_syncfifo_we & hdmi_out0_resetinserter_y_fifo_syncfifo_writable) & (~hdmi_out0_resetinserter_y_fifo_replace))) begin + if ((~hdmi_out0_resetinserter_y_fifo_do_read)) begin + hdmi_out0_resetinserter_y_fifo_level <= (hdmi_out0_resetinserter_y_fifo_level + 1'd1); + end + end else begin + if (hdmi_out0_resetinserter_y_fifo_do_read) begin + hdmi_out0_resetinserter_y_fifo_level <= (hdmi_out0_resetinserter_y_fifo_level - 1'd1); + end + end + if (((hdmi_out0_resetinserter_cb_fifo_syncfifo_we & hdmi_out0_resetinserter_cb_fifo_syncfifo_writable) & (~hdmi_out0_resetinserter_cb_fifo_replace))) begin + hdmi_out0_resetinserter_cb_fifo_produce <= (hdmi_out0_resetinserter_cb_fifo_produce + 1'd1); + end + if (hdmi_out0_resetinserter_cb_fifo_do_read) begin + hdmi_out0_resetinserter_cb_fifo_consume <= (hdmi_out0_resetinserter_cb_fifo_consume + 1'd1); + end + if (((hdmi_out0_resetinserter_cb_fifo_syncfifo_we & hdmi_out0_resetinserter_cb_fifo_syncfifo_writable) & (~hdmi_out0_resetinserter_cb_fifo_replace))) begin + if ((~hdmi_out0_resetinserter_cb_fifo_do_read)) begin + hdmi_out0_resetinserter_cb_fifo_level <= (hdmi_out0_resetinserter_cb_fifo_level + 1'd1); + end + end else begin + if (hdmi_out0_resetinserter_cb_fifo_do_read) begin + hdmi_out0_resetinserter_cb_fifo_level <= (hdmi_out0_resetinserter_cb_fifo_level - 1'd1); + end + end + if (((hdmi_out0_resetinserter_cr_fifo_syncfifo_we & hdmi_out0_resetinserter_cr_fifo_syncfifo_writable) & (~hdmi_out0_resetinserter_cr_fifo_replace))) begin + hdmi_out0_resetinserter_cr_fifo_produce <= (hdmi_out0_resetinserter_cr_fifo_produce + 1'd1); + end + if (hdmi_out0_resetinserter_cr_fifo_do_read) begin + hdmi_out0_resetinserter_cr_fifo_consume <= (hdmi_out0_resetinserter_cr_fifo_consume + 1'd1); + end + if (((hdmi_out0_resetinserter_cr_fifo_syncfifo_we & hdmi_out0_resetinserter_cr_fifo_syncfifo_writable) & (~hdmi_out0_resetinserter_cr_fifo_replace))) begin + if ((~hdmi_out0_resetinserter_cr_fifo_do_read)) begin + hdmi_out0_resetinserter_cr_fifo_level <= (hdmi_out0_resetinserter_cr_fifo_level + 1'd1); + end + end else begin + if (hdmi_out0_resetinserter_cr_fifo_do_read) begin + hdmi_out0_resetinserter_cr_fifo_level <= (hdmi_out0_resetinserter_cr_fifo_level - 1'd1); + end + end + if (hdmi_out0_resetinserter_reset) begin + hdmi_out0_resetinserter_y_fifo_level <= 3'd0; + hdmi_out0_resetinserter_y_fifo_produce <= 2'd0; + hdmi_out0_resetinserter_y_fifo_consume <= 2'd0; + hdmi_out0_resetinserter_cb_fifo_level <= 3'd0; + hdmi_out0_resetinserter_cb_fifo_produce <= 2'd0; + hdmi_out0_resetinserter_cb_fifo_consume <= 2'd0; + hdmi_out0_resetinserter_cr_fifo_level <= 3'd0; + hdmi_out0_resetinserter_cr_fifo_produce <= 2'd0; + hdmi_out0_resetinserter_cr_fifo_consume <= 2'd0; + hdmi_out0_resetinserter_parity_in <= 1'd0; + hdmi_out0_resetinserter_parity_out <= 1'd0; + end + if (hdmi_out0_pipe_ce) begin + hdmi_out0_valid_n0 <= hdmi_out0_sink_valid; + end + if (hdmi_out0_pipe_ce) begin + hdmi_out0_valid_n1 <= hdmi_out0_valid_n0; + end + if (hdmi_out0_pipe_ce) begin + hdmi_out0_valid_n2 <= hdmi_out0_valid_n1; + end + if (hdmi_out0_pipe_ce) begin + hdmi_out0_valid_n3 <= hdmi_out0_valid_n2; + end + if (hdmi_out0_pipe_ce) begin + hdmi_out0_first_n0 <= (hdmi_out0_sink_valid & hdmi_out0_sink_first); + hdmi_out0_last_n0 <= (hdmi_out0_sink_valid & hdmi_out0_sink_last); + end + if (hdmi_out0_pipe_ce) begin + hdmi_out0_first_n1 <= hdmi_out0_first_n0; + hdmi_out0_last_n1 <= hdmi_out0_last_n0; + end + if (hdmi_out0_pipe_ce) begin + hdmi_out0_first_n2 <= hdmi_out0_first_n1; + hdmi_out0_last_n2 <= hdmi_out0_last_n1; + end + if (hdmi_out0_pipe_ce) begin + hdmi_out0_first_n3 <= hdmi_out0_first_n2; + hdmi_out0_last_n3 <= hdmi_out0_last_n2; + end + if (hdmi_out0_ce) begin + hdmi_out0_record0_ycbcr_n_y <= hdmi_out0_sink_y; + hdmi_out0_record0_ycbcr_n_cb <= hdmi_out0_sink_cb; + hdmi_out0_record0_ycbcr_n_cr <= hdmi_out0_sink_cr; + hdmi_out0_record1_ycbcr_n_y <= hdmi_out0_record0_ycbcr_n_y; + hdmi_out0_record1_ycbcr_n_cb <= hdmi_out0_record0_ycbcr_n_cb; + hdmi_out0_record1_ycbcr_n_cr <= hdmi_out0_record0_ycbcr_n_cr; + hdmi_out0_record2_ycbcr_n_y <= hdmi_out0_record1_ycbcr_n_y; + hdmi_out0_record2_ycbcr_n_cb <= hdmi_out0_record1_ycbcr_n_cb; + hdmi_out0_record2_ycbcr_n_cr <= hdmi_out0_record1_ycbcr_n_cr; + hdmi_out0_record3_ycbcr_n_y <= hdmi_out0_record2_ycbcr_n_y; + hdmi_out0_record3_ycbcr_n_cb <= hdmi_out0_record2_ycbcr_n_cb; + hdmi_out0_record3_ycbcr_n_cr <= hdmi_out0_record2_ycbcr_n_cr; + hdmi_out0_cb_minus_coffset <= (hdmi_out0_sink_cb - 8'd128); + hdmi_out0_cr_minus_coffset <= (hdmi_out0_sink_cr - 8'd128); + hdmi_out0_y_minus_yoffset <= (hdmi_out0_record0_ycbcr_n_y - 5'd16); + hdmi_out0_cr_minus_coffset_mult_acoef <= (hdmi_out0_cr_minus_coffset * $signed({1'd0, 7'd98})); + hdmi_out0_cb_minus_coffset_mult_bcoef <= (hdmi_out0_cb_minus_coffset * -5'd9); + hdmi_out0_cr_minus_coffset_mult_ccoef <= (hdmi_out0_cr_minus_coffset * -6'd23); + hdmi_out0_cb_minus_coffset_mult_dcoef <= (hdmi_out0_cb_minus_coffset * $signed({1'd0, 7'd116})); + hdmi_out0_r <= (hdmi_out0_y_minus_yoffset + hdmi_out0_cr_minus_coffset_mult_acoef[19:6]); + hdmi_out0_g <= ((hdmi_out0_y_minus_yoffset + hdmi_out0_cb_minus_coffset_mult_bcoef[19:6]) + hdmi_out0_cr_minus_coffset_mult_ccoef[19:6]); + hdmi_out0_b <= (hdmi_out0_y_minus_yoffset + hdmi_out0_cb_minus_coffset_mult_dcoef[19:6]); + if ((hdmi_out0_r > $signed({1'd0, 8'd255}))) begin + hdmi_out0_source_r <= 8'd255; + end else begin + if ((hdmi_out0_r < $signed({1'd0, 1'd0}))) begin + hdmi_out0_source_r <= 1'd0; + end else begin + hdmi_out0_source_r <= hdmi_out0_r; + end + end + if ((hdmi_out0_g > $signed({1'd0, 8'd255}))) begin + hdmi_out0_source_g <= 8'd255; + end else begin + if ((hdmi_out0_g < $signed({1'd0, 1'd0}))) begin + hdmi_out0_source_g <= 1'd0; + end else begin + hdmi_out0_source_g <= hdmi_out0_g; + end + end + if ((hdmi_out0_b > $signed({1'd0, 8'd255}))) begin + hdmi_out0_source_b <= 8'd255; + end else begin + if ((hdmi_out0_b < $signed({1'd0, 1'd0}))) begin + hdmi_out0_source_b <= 1'd0; + end else begin + hdmi_out0_source_b <= hdmi_out0_b; + end + end + end + hdmi_out0_next_s0 <= hdmi_out0_sink_payload_hsync; + hdmi_out0_next_s1 <= hdmi_out0_next_s0; + hdmi_out0_next_s2 <= hdmi_out0_next_s1; + hdmi_out0_next_s3 <= hdmi_out0_next_s2; + hdmi_out0_next_s4 <= hdmi_out0_next_s3; + hdmi_out0_next_s5 <= hdmi_out0_next_s4; + hdmi_out0_next_s6 <= hdmi_out0_sink_payload_vsync; + hdmi_out0_next_s7 <= hdmi_out0_next_s6; + hdmi_out0_next_s8 <= hdmi_out0_next_s7; + hdmi_out0_next_s9 <= hdmi_out0_next_s8; + hdmi_out0_next_s10 <= hdmi_out0_next_s9; + hdmi_out0_next_s11 <= hdmi_out0_next_s10; + hdmi_out0_next_s12 <= hdmi_out0_sink_payload_de; + hdmi_out0_next_s13 <= hdmi_out0_next_s12; + hdmi_out0_next_s14 <= hdmi_out0_next_s13; + hdmi_out0_next_s15 <= hdmi_out0_next_s14; + hdmi_out0_next_s16 <= hdmi_out0_next_s15; + hdmi_out0_next_s17 <= hdmi_out0_next_s16; + hdmi_out0_driver_s7hdmioutclocking_ce <= (~hdmi_out0_pix_rst); + hdmi_out0_driver_hdmi_phy_es0_ce <= (~hdmi_out0_pix_rst); + hdmi_out0_driver_hdmi_phy_es0_n1d <= (((((((hdmi_out0_driver_hdmi_phy_es0_d0[0] + hdmi_out0_driver_hdmi_phy_es0_d0[1]) + hdmi_out0_driver_hdmi_phy_es0_d0[2]) + hdmi_out0_driver_hdmi_phy_es0_d0[3]) + hdmi_out0_driver_hdmi_phy_es0_d0[4]) + hdmi_out0_driver_hdmi_phy_es0_d0[5]) + hdmi_out0_driver_hdmi_phy_es0_d0[6]) + hdmi_out0_driver_hdmi_phy_es0_d0[7]); + hdmi_out0_driver_hdmi_phy_es0_d1 <= hdmi_out0_driver_hdmi_phy_es0_d0; + hdmi_out0_driver_hdmi_phy_es0_q_m[0] <= hdmi_out0_driver_hdmi_phy_es0_d1[0]; + hdmi_out0_driver_hdmi_phy_es0_q_m[1] <= ((hdmi_out0_driver_hdmi_phy_es0_d1[0] ^ hdmi_out0_driver_hdmi_phy_es0_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n); + hdmi_out0_driver_hdmi_phy_es0_q_m[2] <= ((((hdmi_out0_driver_hdmi_phy_es0_d1[0] ^ hdmi_out0_driver_hdmi_phy_es0_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[2]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n); + hdmi_out0_driver_hdmi_phy_es0_q_m[3] <= ((((((hdmi_out0_driver_hdmi_phy_es0_d1[0] ^ hdmi_out0_driver_hdmi_phy_es0_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[2]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[3]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n); + hdmi_out0_driver_hdmi_phy_es0_q_m[4] <= ((((((((hdmi_out0_driver_hdmi_phy_es0_d1[0] ^ hdmi_out0_driver_hdmi_phy_es0_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[2]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[3]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[4]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n); + hdmi_out0_driver_hdmi_phy_es0_q_m[5] <= ((((((((((hdmi_out0_driver_hdmi_phy_es0_d1[0] ^ hdmi_out0_driver_hdmi_phy_es0_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[2]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[3]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[4]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[5]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n); + hdmi_out0_driver_hdmi_phy_es0_q_m[6] <= ((((((((((((hdmi_out0_driver_hdmi_phy_es0_d1[0] ^ hdmi_out0_driver_hdmi_phy_es0_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[2]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[3]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[4]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[5]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[6]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n); + hdmi_out0_driver_hdmi_phy_es0_q_m[7] <= ((((((((((((((hdmi_out0_driver_hdmi_phy_es0_d1[0] ^ hdmi_out0_driver_hdmi_phy_es0_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[2]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[3]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[4]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[5]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[6]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es0_d1[7]) ^ hdmi_out0_driver_hdmi_phy_es0_q_m8_n); + hdmi_out0_driver_hdmi_phy_es0_q_m[8] <= (~hdmi_out0_driver_hdmi_phy_es0_q_m8_n); + hdmi_out0_driver_hdmi_phy_es0_n0q_m <= ((((((((~hdmi_out0_driver_hdmi_phy_es0_q_m[0]) + (~hdmi_out0_driver_hdmi_phy_es0_q_m[1])) + (~hdmi_out0_driver_hdmi_phy_es0_q_m[2])) + (~hdmi_out0_driver_hdmi_phy_es0_q_m[3])) + (~hdmi_out0_driver_hdmi_phy_es0_q_m[4])) + (~hdmi_out0_driver_hdmi_phy_es0_q_m[5])) + (~hdmi_out0_driver_hdmi_phy_es0_q_m[6])) + (~hdmi_out0_driver_hdmi_phy_es0_q_m[7])); + hdmi_out0_driver_hdmi_phy_es0_n1q_m <= (((((((hdmi_out0_driver_hdmi_phy_es0_q_m[0] + hdmi_out0_driver_hdmi_phy_es0_q_m[1]) + hdmi_out0_driver_hdmi_phy_es0_q_m[2]) + hdmi_out0_driver_hdmi_phy_es0_q_m[3]) + hdmi_out0_driver_hdmi_phy_es0_q_m[4]) + hdmi_out0_driver_hdmi_phy_es0_q_m[5]) + hdmi_out0_driver_hdmi_phy_es0_q_m[6]) + hdmi_out0_driver_hdmi_phy_es0_q_m[7]); + hdmi_out0_driver_hdmi_phy_es0_q_m_r <= hdmi_out0_driver_hdmi_phy_es0_q_m; + hdmi_out0_driver_hdmi_phy_es0_new_c0 <= hdmi_out0_driver_hdmi_phy_es0_c; + hdmi_out0_driver_hdmi_phy_es0_new_de0 <= hdmi_out0_driver_hdmi_phy_es0_de; + hdmi_out0_driver_hdmi_phy_es0_new_c1 <= hdmi_out0_driver_hdmi_phy_es0_new_c0; + hdmi_out0_driver_hdmi_phy_es0_new_de1 <= hdmi_out0_driver_hdmi_phy_es0_new_de0; + hdmi_out0_driver_hdmi_phy_es0_new_c2 <= hdmi_out0_driver_hdmi_phy_es0_new_c1; + hdmi_out0_driver_hdmi_phy_es0_new_de2 <= hdmi_out0_driver_hdmi_phy_es0_new_de1; + if (hdmi_out0_driver_hdmi_phy_es0_new_de2) begin + if (((hdmi_out0_driver_hdmi_phy_es0_cnt == $signed({1'd0, 1'd0})) | $signed({1'd0, (hdmi_out0_driver_hdmi_phy_es0_n1q_m == hdmi_out0_driver_hdmi_phy_es0_n0q_m)}))) begin + hdmi_out0_driver_hdmi_phy_es0_out[9] <= (~hdmi_out0_driver_hdmi_phy_es0_q_m_r[8]); + hdmi_out0_driver_hdmi_phy_es0_out[8] <= hdmi_out0_driver_hdmi_phy_es0_q_m_r[8]; + if (hdmi_out0_driver_hdmi_phy_es0_q_m_r[8]) begin + hdmi_out0_driver_hdmi_phy_es0_out[7:0] <= hdmi_out0_driver_hdmi_phy_es0_q_m_r[7:0]; + hdmi_out0_driver_hdmi_phy_es0_cnt <= ((hdmi_out0_driver_hdmi_phy_es0_cnt + $signed({1'd0, hdmi_out0_driver_hdmi_phy_es0_n1q_m})) - $signed({1'd0, hdmi_out0_driver_hdmi_phy_es0_n0q_m})); + end else begin + hdmi_out0_driver_hdmi_phy_es0_out[7:0] <= (~hdmi_out0_driver_hdmi_phy_es0_q_m_r[7:0]); + hdmi_out0_driver_hdmi_phy_es0_cnt <= ((hdmi_out0_driver_hdmi_phy_es0_cnt + $signed({1'd0, hdmi_out0_driver_hdmi_phy_es0_n0q_m})) - $signed({1'd0, hdmi_out0_driver_hdmi_phy_es0_n1q_m})); + end + end else begin + if ((((~hdmi_out0_driver_hdmi_phy_es0_cnt[5]) & $signed({1'd0, (hdmi_out0_driver_hdmi_phy_es0_n1q_m > hdmi_out0_driver_hdmi_phy_es0_n0q_m)})) | (hdmi_out0_driver_hdmi_phy_es0_cnt[5] & $signed({1'd0, (hdmi_out0_driver_hdmi_phy_es0_n0q_m > hdmi_out0_driver_hdmi_phy_es0_n1q_m)})))) begin + hdmi_out0_driver_hdmi_phy_es0_out[9] <= 1'd1; + hdmi_out0_driver_hdmi_phy_es0_out[8] <= hdmi_out0_driver_hdmi_phy_es0_q_m_r[8]; + hdmi_out0_driver_hdmi_phy_es0_out[7:0] <= (~hdmi_out0_driver_hdmi_phy_es0_q_m_r[7:0]); + hdmi_out0_driver_hdmi_phy_es0_cnt <= (((hdmi_out0_driver_hdmi_phy_es0_cnt + $signed({1'd0, {hdmi_out0_driver_hdmi_phy_es0_q_m_r[8], 1'd0}})) + $signed({1'd0, hdmi_out0_driver_hdmi_phy_es0_n0q_m})) - $signed({1'd0, hdmi_out0_driver_hdmi_phy_es0_n1q_m})); + end else begin + hdmi_out0_driver_hdmi_phy_es0_out[9] <= 1'd0; + hdmi_out0_driver_hdmi_phy_es0_out[8] <= hdmi_out0_driver_hdmi_phy_es0_q_m_r[8]; + hdmi_out0_driver_hdmi_phy_es0_out[7:0] <= hdmi_out0_driver_hdmi_phy_es0_q_m_r[7:0]; + hdmi_out0_driver_hdmi_phy_es0_cnt <= (((hdmi_out0_driver_hdmi_phy_es0_cnt - $signed({1'd0, {(~hdmi_out0_driver_hdmi_phy_es0_q_m_r[8]), 1'd0}})) + $signed({1'd0, hdmi_out0_driver_hdmi_phy_es0_n1q_m})) - $signed({1'd0, hdmi_out0_driver_hdmi_phy_es0_n0q_m})); + end + end + end else begin + hdmi_out0_driver_hdmi_phy_es0_out <= sync_rhs_array_muxed0; + hdmi_out0_driver_hdmi_phy_es0_cnt <= 1'd0; + end + hdmi_out0_driver_hdmi_phy_es1_ce <= (~hdmi_out0_pix_rst); + hdmi_out0_driver_hdmi_phy_es1_n1d <= (((((((hdmi_out0_driver_hdmi_phy_es1_d0[0] + hdmi_out0_driver_hdmi_phy_es1_d0[1]) + hdmi_out0_driver_hdmi_phy_es1_d0[2]) + hdmi_out0_driver_hdmi_phy_es1_d0[3]) + hdmi_out0_driver_hdmi_phy_es1_d0[4]) + hdmi_out0_driver_hdmi_phy_es1_d0[5]) + hdmi_out0_driver_hdmi_phy_es1_d0[6]) + hdmi_out0_driver_hdmi_phy_es1_d0[7]); + hdmi_out0_driver_hdmi_phy_es1_d1 <= hdmi_out0_driver_hdmi_phy_es1_d0; + hdmi_out0_driver_hdmi_phy_es1_q_m[0] <= hdmi_out0_driver_hdmi_phy_es1_d1[0]; + hdmi_out0_driver_hdmi_phy_es1_q_m[1] <= ((hdmi_out0_driver_hdmi_phy_es1_d1[0] ^ hdmi_out0_driver_hdmi_phy_es1_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n); + hdmi_out0_driver_hdmi_phy_es1_q_m[2] <= ((((hdmi_out0_driver_hdmi_phy_es1_d1[0] ^ hdmi_out0_driver_hdmi_phy_es1_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[2]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n); + hdmi_out0_driver_hdmi_phy_es1_q_m[3] <= ((((((hdmi_out0_driver_hdmi_phy_es1_d1[0] ^ hdmi_out0_driver_hdmi_phy_es1_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[2]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[3]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n); + hdmi_out0_driver_hdmi_phy_es1_q_m[4] <= ((((((((hdmi_out0_driver_hdmi_phy_es1_d1[0] ^ hdmi_out0_driver_hdmi_phy_es1_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[2]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[3]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[4]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n); + hdmi_out0_driver_hdmi_phy_es1_q_m[5] <= ((((((((((hdmi_out0_driver_hdmi_phy_es1_d1[0] ^ hdmi_out0_driver_hdmi_phy_es1_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[2]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[3]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[4]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[5]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n); + hdmi_out0_driver_hdmi_phy_es1_q_m[6] <= ((((((((((((hdmi_out0_driver_hdmi_phy_es1_d1[0] ^ hdmi_out0_driver_hdmi_phy_es1_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[2]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[3]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[4]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[5]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[6]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n); + hdmi_out0_driver_hdmi_phy_es1_q_m[7] <= ((((((((((((((hdmi_out0_driver_hdmi_phy_es1_d1[0] ^ hdmi_out0_driver_hdmi_phy_es1_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[2]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[3]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[4]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[5]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[6]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es1_d1[7]) ^ hdmi_out0_driver_hdmi_phy_es1_q_m8_n); + hdmi_out0_driver_hdmi_phy_es1_q_m[8] <= (~hdmi_out0_driver_hdmi_phy_es1_q_m8_n); + hdmi_out0_driver_hdmi_phy_es1_n0q_m <= ((((((((~hdmi_out0_driver_hdmi_phy_es1_q_m[0]) + (~hdmi_out0_driver_hdmi_phy_es1_q_m[1])) + (~hdmi_out0_driver_hdmi_phy_es1_q_m[2])) + (~hdmi_out0_driver_hdmi_phy_es1_q_m[3])) + (~hdmi_out0_driver_hdmi_phy_es1_q_m[4])) + (~hdmi_out0_driver_hdmi_phy_es1_q_m[5])) + (~hdmi_out0_driver_hdmi_phy_es1_q_m[6])) + (~hdmi_out0_driver_hdmi_phy_es1_q_m[7])); + hdmi_out0_driver_hdmi_phy_es1_n1q_m <= (((((((hdmi_out0_driver_hdmi_phy_es1_q_m[0] + hdmi_out0_driver_hdmi_phy_es1_q_m[1]) + hdmi_out0_driver_hdmi_phy_es1_q_m[2]) + hdmi_out0_driver_hdmi_phy_es1_q_m[3]) + hdmi_out0_driver_hdmi_phy_es1_q_m[4]) + hdmi_out0_driver_hdmi_phy_es1_q_m[5]) + hdmi_out0_driver_hdmi_phy_es1_q_m[6]) + hdmi_out0_driver_hdmi_phy_es1_q_m[7]); + hdmi_out0_driver_hdmi_phy_es1_q_m_r <= hdmi_out0_driver_hdmi_phy_es1_q_m; + hdmi_out0_driver_hdmi_phy_es1_new_c0 <= hdmi_out0_driver_hdmi_phy_es1_c; + hdmi_out0_driver_hdmi_phy_es1_new_de0 <= hdmi_out0_driver_hdmi_phy_es1_de; + hdmi_out0_driver_hdmi_phy_es1_new_c1 <= hdmi_out0_driver_hdmi_phy_es1_new_c0; + hdmi_out0_driver_hdmi_phy_es1_new_de1 <= hdmi_out0_driver_hdmi_phy_es1_new_de0; + hdmi_out0_driver_hdmi_phy_es1_new_c2 <= hdmi_out0_driver_hdmi_phy_es1_new_c1; + hdmi_out0_driver_hdmi_phy_es1_new_de2 <= hdmi_out0_driver_hdmi_phy_es1_new_de1; + if (hdmi_out0_driver_hdmi_phy_es1_new_de2) begin + if (((hdmi_out0_driver_hdmi_phy_es1_cnt == $signed({1'd0, 1'd0})) | $signed({1'd0, (hdmi_out0_driver_hdmi_phy_es1_n1q_m == hdmi_out0_driver_hdmi_phy_es1_n0q_m)}))) begin + hdmi_out0_driver_hdmi_phy_es1_out[9] <= (~hdmi_out0_driver_hdmi_phy_es1_q_m_r[8]); + hdmi_out0_driver_hdmi_phy_es1_out[8] <= hdmi_out0_driver_hdmi_phy_es1_q_m_r[8]; + if (hdmi_out0_driver_hdmi_phy_es1_q_m_r[8]) begin + hdmi_out0_driver_hdmi_phy_es1_out[7:0] <= hdmi_out0_driver_hdmi_phy_es1_q_m_r[7:0]; + hdmi_out0_driver_hdmi_phy_es1_cnt <= ((hdmi_out0_driver_hdmi_phy_es1_cnt + $signed({1'd0, hdmi_out0_driver_hdmi_phy_es1_n1q_m})) - $signed({1'd0, hdmi_out0_driver_hdmi_phy_es1_n0q_m})); + end else begin + hdmi_out0_driver_hdmi_phy_es1_out[7:0] <= (~hdmi_out0_driver_hdmi_phy_es1_q_m_r[7:0]); + hdmi_out0_driver_hdmi_phy_es1_cnt <= ((hdmi_out0_driver_hdmi_phy_es1_cnt + $signed({1'd0, hdmi_out0_driver_hdmi_phy_es1_n0q_m})) - $signed({1'd0, hdmi_out0_driver_hdmi_phy_es1_n1q_m})); + end + end else begin + if ((((~hdmi_out0_driver_hdmi_phy_es1_cnt[5]) & $signed({1'd0, (hdmi_out0_driver_hdmi_phy_es1_n1q_m > hdmi_out0_driver_hdmi_phy_es1_n0q_m)})) | (hdmi_out0_driver_hdmi_phy_es1_cnt[5] & $signed({1'd0, (hdmi_out0_driver_hdmi_phy_es1_n0q_m > hdmi_out0_driver_hdmi_phy_es1_n1q_m)})))) begin + hdmi_out0_driver_hdmi_phy_es1_out[9] <= 1'd1; + hdmi_out0_driver_hdmi_phy_es1_out[8] <= hdmi_out0_driver_hdmi_phy_es1_q_m_r[8]; + hdmi_out0_driver_hdmi_phy_es1_out[7:0] <= (~hdmi_out0_driver_hdmi_phy_es1_q_m_r[7:0]); + hdmi_out0_driver_hdmi_phy_es1_cnt <= (((hdmi_out0_driver_hdmi_phy_es1_cnt + $signed({1'd0, {hdmi_out0_driver_hdmi_phy_es1_q_m_r[8], 1'd0}})) + $signed({1'd0, hdmi_out0_driver_hdmi_phy_es1_n0q_m})) - $signed({1'd0, hdmi_out0_driver_hdmi_phy_es1_n1q_m})); + end else begin + hdmi_out0_driver_hdmi_phy_es1_out[9] <= 1'd0; + hdmi_out0_driver_hdmi_phy_es1_out[8] <= hdmi_out0_driver_hdmi_phy_es1_q_m_r[8]; + hdmi_out0_driver_hdmi_phy_es1_out[7:0] <= hdmi_out0_driver_hdmi_phy_es1_q_m_r[7:0]; + hdmi_out0_driver_hdmi_phy_es1_cnt <= (((hdmi_out0_driver_hdmi_phy_es1_cnt - $signed({1'd0, {(~hdmi_out0_driver_hdmi_phy_es1_q_m_r[8]), 1'd0}})) + $signed({1'd0, hdmi_out0_driver_hdmi_phy_es1_n1q_m})) - $signed({1'd0, hdmi_out0_driver_hdmi_phy_es1_n0q_m})); + end + end + end else begin + hdmi_out0_driver_hdmi_phy_es1_out <= sync_rhs_array_muxed1; + hdmi_out0_driver_hdmi_phy_es1_cnt <= 1'd0; + end + hdmi_out0_driver_hdmi_phy_es2_ce <= (~hdmi_out0_pix_rst); + hdmi_out0_driver_hdmi_phy_es2_n1d <= (((((((hdmi_out0_driver_hdmi_phy_es2_d0[0] + hdmi_out0_driver_hdmi_phy_es2_d0[1]) + hdmi_out0_driver_hdmi_phy_es2_d0[2]) + hdmi_out0_driver_hdmi_phy_es2_d0[3]) + hdmi_out0_driver_hdmi_phy_es2_d0[4]) + hdmi_out0_driver_hdmi_phy_es2_d0[5]) + hdmi_out0_driver_hdmi_phy_es2_d0[6]) + hdmi_out0_driver_hdmi_phy_es2_d0[7]); + hdmi_out0_driver_hdmi_phy_es2_d1 <= hdmi_out0_driver_hdmi_phy_es2_d0; + hdmi_out0_driver_hdmi_phy_es2_q_m[0] <= hdmi_out0_driver_hdmi_phy_es2_d1[0]; + hdmi_out0_driver_hdmi_phy_es2_q_m[1] <= ((hdmi_out0_driver_hdmi_phy_es2_d1[0] ^ hdmi_out0_driver_hdmi_phy_es2_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n); + hdmi_out0_driver_hdmi_phy_es2_q_m[2] <= ((((hdmi_out0_driver_hdmi_phy_es2_d1[0] ^ hdmi_out0_driver_hdmi_phy_es2_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[2]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n); + hdmi_out0_driver_hdmi_phy_es2_q_m[3] <= ((((((hdmi_out0_driver_hdmi_phy_es2_d1[0] ^ hdmi_out0_driver_hdmi_phy_es2_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[2]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[3]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n); + hdmi_out0_driver_hdmi_phy_es2_q_m[4] <= ((((((((hdmi_out0_driver_hdmi_phy_es2_d1[0] ^ hdmi_out0_driver_hdmi_phy_es2_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[2]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[3]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[4]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n); + hdmi_out0_driver_hdmi_phy_es2_q_m[5] <= ((((((((((hdmi_out0_driver_hdmi_phy_es2_d1[0] ^ hdmi_out0_driver_hdmi_phy_es2_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[2]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[3]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[4]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[5]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n); + hdmi_out0_driver_hdmi_phy_es2_q_m[6] <= ((((((((((((hdmi_out0_driver_hdmi_phy_es2_d1[0] ^ hdmi_out0_driver_hdmi_phy_es2_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[2]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[3]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[4]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[5]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[6]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n); + hdmi_out0_driver_hdmi_phy_es2_q_m[7] <= ((((((((((((((hdmi_out0_driver_hdmi_phy_es2_d1[0] ^ hdmi_out0_driver_hdmi_phy_es2_d1[1]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[2]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[3]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[4]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[5]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[6]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n) ^ hdmi_out0_driver_hdmi_phy_es2_d1[7]) ^ hdmi_out0_driver_hdmi_phy_es2_q_m8_n); + hdmi_out0_driver_hdmi_phy_es2_q_m[8] <= (~hdmi_out0_driver_hdmi_phy_es2_q_m8_n); + hdmi_out0_driver_hdmi_phy_es2_n0q_m <= ((((((((~hdmi_out0_driver_hdmi_phy_es2_q_m[0]) + (~hdmi_out0_driver_hdmi_phy_es2_q_m[1])) + (~hdmi_out0_driver_hdmi_phy_es2_q_m[2])) + (~hdmi_out0_driver_hdmi_phy_es2_q_m[3])) + (~hdmi_out0_driver_hdmi_phy_es2_q_m[4])) + (~hdmi_out0_driver_hdmi_phy_es2_q_m[5])) + (~hdmi_out0_driver_hdmi_phy_es2_q_m[6])) + (~hdmi_out0_driver_hdmi_phy_es2_q_m[7])); + hdmi_out0_driver_hdmi_phy_es2_n1q_m <= (((((((hdmi_out0_driver_hdmi_phy_es2_q_m[0] + hdmi_out0_driver_hdmi_phy_es2_q_m[1]) + hdmi_out0_driver_hdmi_phy_es2_q_m[2]) + hdmi_out0_driver_hdmi_phy_es2_q_m[3]) + hdmi_out0_driver_hdmi_phy_es2_q_m[4]) + hdmi_out0_driver_hdmi_phy_es2_q_m[5]) + hdmi_out0_driver_hdmi_phy_es2_q_m[6]) + hdmi_out0_driver_hdmi_phy_es2_q_m[7]); + hdmi_out0_driver_hdmi_phy_es2_q_m_r <= hdmi_out0_driver_hdmi_phy_es2_q_m; + hdmi_out0_driver_hdmi_phy_es2_new_c0 <= hdmi_out0_driver_hdmi_phy_es2_c; + hdmi_out0_driver_hdmi_phy_es2_new_de0 <= hdmi_out0_driver_hdmi_phy_es2_de; + hdmi_out0_driver_hdmi_phy_es2_new_c1 <= hdmi_out0_driver_hdmi_phy_es2_new_c0; + hdmi_out0_driver_hdmi_phy_es2_new_de1 <= hdmi_out0_driver_hdmi_phy_es2_new_de0; + hdmi_out0_driver_hdmi_phy_es2_new_c2 <= hdmi_out0_driver_hdmi_phy_es2_new_c1; + hdmi_out0_driver_hdmi_phy_es2_new_de2 <= hdmi_out0_driver_hdmi_phy_es2_new_de1; + if (hdmi_out0_driver_hdmi_phy_es2_new_de2) begin + if (((hdmi_out0_driver_hdmi_phy_es2_cnt == $signed({1'd0, 1'd0})) | $signed({1'd0, (hdmi_out0_driver_hdmi_phy_es2_n1q_m == hdmi_out0_driver_hdmi_phy_es2_n0q_m)}))) begin + hdmi_out0_driver_hdmi_phy_es2_out[9] <= (~hdmi_out0_driver_hdmi_phy_es2_q_m_r[8]); + hdmi_out0_driver_hdmi_phy_es2_out[8] <= hdmi_out0_driver_hdmi_phy_es2_q_m_r[8]; + if (hdmi_out0_driver_hdmi_phy_es2_q_m_r[8]) begin + hdmi_out0_driver_hdmi_phy_es2_out[7:0] <= hdmi_out0_driver_hdmi_phy_es2_q_m_r[7:0]; + hdmi_out0_driver_hdmi_phy_es2_cnt <= ((hdmi_out0_driver_hdmi_phy_es2_cnt + $signed({1'd0, hdmi_out0_driver_hdmi_phy_es2_n1q_m})) - $signed({1'd0, hdmi_out0_driver_hdmi_phy_es2_n0q_m})); + end else begin + hdmi_out0_driver_hdmi_phy_es2_out[7:0] <= (~hdmi_out0_driver_hdmi_phy_es2_q_m_r[7:0]); + hdmi_out0_driver_hdmi_phy_es2_cnt <= ((hdmi_out0_driver_hdmi_phy_es2_cnt + $signed({1'd0, hdmi_out0_driver_hdmi_phy_es2_n0q_m})) - $signed({1'd0, hdmi_out0_driver_hdmi_phy_es2_n1q_m})); + end + end else begin + if ((((~hdmi_out0_driver_hdmi_phy_es2_cnt[5]) & $signed({1'd0, (hdmi_out0_driver_hdmi_phy_es2_n1q_m > hdmi_out0_driver_hdmi_phy_es2_n0q_m)})) | (hdmi_out0_driver_hdmi_phy_es2_cnt[5] & $signed({1'd0, (hdmi_out0_driver_hdmi_phy_es2_n0q_m > hdmi_out0_driver_hdmi_phy_es2_n1q_m)})))) begin + hdmi_out0_driver_hdmi_phy_es2_out[9] <= 1'd1; + hdmi_out0_driver_hdmi_phy_es2_out[8] <= hdmi_out0_driver_hdmi_phy_es2_q_m_r[8]; + hdmi_out0_driver_hdmi_phy_es2_out[7:0] <= (~hdmi_out0_driver_hdmi_phy_es2_q_m_r[7:0]); + hdmi_out0_driver_hdmi_phy_es2_cnt <= (((hdmi_out0_driver_hdmi_phy_es2_cnt + $signed({1'd0, {hdmi_out0_driver_hdmi_phy_es2_q_m_r[8], 1'd0}})) + $signed({1'd0, hdmi_out0_driver_hdmi_phy_es2_n0q_m})) - $signed({1'd0, hdmi_out0_driver_hdmi_phy_es2_n1q_m})); + end else begin + hdmi_out0_driver_hdmi_phy_es2_out[9] <= 1'd0; + hdmi_out0_driver_hdmi_phy_es2_out[8] <= hdmi_out0_driver_hdmi_phy_es2_q_m_r[8]; + hdmi_out0_driver_hdmi_phy_es2_out[7:0] <= hdmi_out0_driver_hdmi_phy_es2_q_m_r[7:0]; + hdmi_out0_driver_hdmi_phy_es2_cnt <= (((hdmi_out0_driver_hdmi_phy_es2_cnt - $signed({1'd0, {(~hdmi_out0_driver_hdmi_phy_es2_q_m_r[8]), 1'd0}})) + $signed({1'd0, hdmi_out0_driver_hdmi_phy_es2_n1q_m})) - $signed({1'd0, hdmi_out0_driver_hdmi_phy_es2_n0q_m})); + end + end + end else begin + hdmi_out0_driver_hdmi_phy_es2_out <= sync_rhs_array_muxed2; + hdmi_out0_driver_hdmi_phy_es2_cnt <= 1'd0; + end + if (hdmi_out0_pix_rst) begin + litedramcrossbar_cmd_cdc_cdc_graycounter0_q <= 3'd0; + litedramcrossbar_cmd_cdc_cdc_graycounter0_q_binary <= 3'd0; + litedramcrossbar_rdata_cdc_cdc_graycounter1_q <= 5'd0; + litedramcrossbar_rdata_cdc_cdc_graycounter1_q_binary <= 5'd0; + litedramcrossbar_sel <= 16'd0; + litedramcrossbar_cmd_addr <= 28'd0; + litedramcrossbar_cmd_we <= 1'd0; + litedramcrossbar_cmd_last <= 1'd0; + litedramcrossbar_read_lock <= 1'd0; + litedramcrossbar_read_unlocked <= 1'd0; + litedramcrossbar_rdata_fifo_level <= 4'd0; + litedramcrossbar_rdata_fifo_produce <= 4'd0; + litedramcrossbar_rdata_fifo_consume <= 4'd0; + litedramcrossbar_rdata_converter_converter_mux <= 4'd0; + litedramcrossbar_rdata_chunk <= 16'd1; + hdmi_out0_core_underflow_counter_status <= 32'd0; + hdmi_out0_core_initiator_cdc_graycounter1_q <= 3'd0; + hdmi_out0_core_initiator_cdc_graycounter1_q_binary <= 3'd0; + hdmi_out0_core_timinggenerator_source_payload_hsync <= 1'd0; + hdmi_out0_core_timinggenerator_source_payload_vsync <= 1'd0; + hdmi_out0_core_timinggenerator_hactive <= 1'd0; + hdmi_out0_core_timinggenerator_vactive <= 1'd0; + hdmi_out0_core_timinggenerator_hcounter <= 12'd0; + hdmi_out0_core_timinggenerator_vcounter <= 12'd0; + hdmi_out0_core_dmareader_rsv_level <= 10'd0; + hdmi_out0_core_dmareader_fifo_readable <= 1'd0; + hdmi_out0_core_dmareader_fifo_level0 <= 10'd0; + hdmi_out0_core_dmareader_fifo_produce <= 9'd0; + hdmi_out0_core_dmareader_fifo_consume <= 9'd0; + hdmi_out0_core_dmareader_offset <= 28'd0; + hdmi_out0_core_underflow_counter <= 32'd0; + hdmi_out0_driver_s7hdmioutclocking_ce <= 1'd0; + hdmi_out0_driver_hdmi_phy_es0_out <= 10'd0; + hdmi_out0_driver_hdmi_phy_es0_d1 <= 8'd0; + hdmi_out0_driver_hdmi_phy_es0_n1d <= 4'd0; + hdmi_out0_driver_hdmi_phy_es0_q_m <= 9'd0; + hdmi_out0_driver_hdmi_phy_es0_q_m_r <= 9'd0; + hdmi_out0_driver_hdmi_phy_es0_n0q_m <= 4'd0; + hdmi_out0_driver_hdmi_phy_es0_n1q_m <= 4'd0; + hdmi_out0_driver_hdmi_phy_es0_cnt <= 6'd0; + hdmi_out0_driver_hdmi_phy_es0_new_c0 <= 2'd0; + hdmi_out0_driver_hdmi_phy_es0_new_de0 <= 1'd0; + hdmi_out0_driver_hdmi_phy_es0_new_c1 <= 2'd0; + hdmi_out0_driver_hdmi_phy_es0_new_de1 <= 1'd0; + hdmi_out0_driver_hdmi_phy_es0_new_c2 <= 2'd0; + hdmi_out0_driver_hdmi_phy_es0_new_de2 <= 1'd0; + hdmi_out0_driver_hdmi_phy_es0_ce <= 1'd0; + hdmi_out0_driver_hdmi_phy_es1_out <= 10'd0; + hdmi_out0_driver_hdmi_phy_es1_d1 <= 8'd0; + hdmi_out0_driver_hdmi_phy_es1_n1d <= 4'd0; + hdmi_out0_driver_hdmi_phy_es1_q_m <= 9'd0; + hdmi_out0_driver_hdmi_phy_es1_q_m_r <= 9'd0; + hdmi_out0_driver_hdmi_phy_es1_n0q_m <= 4'd0; + hdmi_out0_driver_hdmi_phy_es1_n1q_m <= 4'd0; + hdmi_out0_driver_hdmi_phy_es1_cnt <= 6'd0; + hdmi_out0_driver_hdmi_phy_es1_new_c0 <= 2'd0; + hdmi_out0_driver_hdmi_phy_es1_new_de0 <= 1'd0; + hdmi_out0_driver_hdmi_phy_es1_new_c1 <= 2'd0; + hdmi_out0_driver_hdmi_phy_es1_new_de1 <= 1'd0; + hdmi_out0_driver_hdmi_phy_es1_new_c2 <= 2'd0; + hdmi_out0_driver_hdmi_phy_es1_new_de2 <= 1'd0; + hdmi_out0_driver_hdmi_phy_es1_ce <= 1'd0; + hdmi_out0_driver_hdmi_phy_es2_out <= 10'd0; + hdmi_out0_driver_hdmi_phy_es2_d1 <= 8'd0; + hdmi_out0_driver_hdmi_phy_es2_n1d <= 4'd0; + hdmi_out0_driver_hdmi_phy_es2_q_m <= 9'd0; + hdmi_out0_driver_hdmi_phy_es2_q_m_r <= 9'd0; + hdmi_out0_driver_hdmi_phy_es2_n0q_m <= 4'd0; + hdmi_out0_driver_hdmi_phy_es2_n1q_m <= 4'd0; + hdmi_out0_driver_hdmi_phy_es2_cnt <= 6'd0; + hdmi_out0_driver_hdmi_phy_es2_new_c0 <= 2'd0; + hdmi_out0_driver_hdmi_phy_es2_new_de0 <= 1'd0; + hdmi_out0_driver_hdmi_phy_es2_new_c1 <= 2'd0; + hdmi_out0_driver_hdmi_phy_es2_new_de1 <= 1'd0; + hdmi_out0_driver_hdmi_phy_es2_new_c2 <= 2'd0; + hdmi_out0_driver_hdmi_phy_es2_new_de2 <= 1'd0; + hdmi_out0_driver_hdmi_phy_es2_ce <= 1'd0; + hdmi_out0_resetinserter_y_fifo_level <= 3'd0; + hdmi_out0_resetinserter_y_fifo_produce <= 2'd0; + hdmi_out0_resetinserter_y_fifo_consume <= 2'd0; + hdmi_out0_resetinserter_cb_fifo_level <= 3'd0; + hdmi_out0_resetinserter_cb_fifo_produce <= 2'd0; + hdmi_out0_resetinserter_cb_fifo_consume <= 2'd0; + hdmi_out0_resetinserter_cr_fifo_level <= 3'd0; + hdmi_out0_resetinserter_cr_fifo_produce <= 2'd0; + hdmi_out0_resetinserter_cr_fifo_consume <= 2'd0; + hdmi_out0_resetinserter_parity_in <= 1'd0; + hdmi_out0_resetinserter_parity_out <= 1'd0; + hdmi_out0_source_r <= 8'd0; + hdmi_out0_source_g <= 8'd0; + hdmi_out0_source_b <= 8'd0; + hdmi_out0_record0_ycbcr_n_y <= 8'd0; + hdmi_out0_record0_ycbcr_n_cb <= 8'd0; + hdmi_out0_record0_ycbcr_n_cr <= 8'd0; + hdmi_out0_record1_ycbcr_n_y <= 8'd0; + hdmi_out0_record1_ycbcr_n_cb <= 8'd0; + hdmi_out0_record1_ycbcr_n_cr <= 8'd0; + hdmi_out0_record2_ycbcr_n_y <= 8'd0; + hdmi_out0_record2_ycbcr_n_cb <= 8'd0; + hdmi_out0_record2_ycbcr_n_cr <= 8'd0; + hdmi_out0_record3_ycbcr_n_y <= 8'd0; + hdmi_out0_record3_ycbcr_n_cb <= 8'd0; + hdmi_out0_record3_ycbcr_n_cr <= 8'd0; + hdmi_out0_cb_minus_coffset <= 9'd0; + hdmi_out0_cr_minus_coffset <= 9'd0; + hdmi_out0_y_minus_yoffset <= 9'd0; + hdmi_out0_cr_minus_coffset_mult_acoef <= 20'd0; + hdmi_out0_cb_minus_coffset_mult_bcoef <= 20'd0; + hdmi_out0_cr_minus_coffset_mult_ccoef <= 20'd0; + hdmi_out0_cb_minus_coffset_mult_dcoef <= 20'd0; + hdmi_out0_r <= 12'd0; + hdmi_out0_g <= 12'd0; + hdmi_out0_b <= 12'd0; + hdmi_out0_valid_n0 <= 1'd0; + hdmi_out0_valid_n1 <= 1'd0; + hdmi_out0_valid_n2 <= 1'd0; + hdmi_out0_valid_n3 <= 1'd0; + hdmi_out0_next_s0 <= 1'd0; + hdmi_out0_next_s1 <= 1'd0; + hdmi_out0_next_s2 <= 1'd0; + hdmi_out0_next_s3 <= 1'd0; + hdmi_out0_next_s4 <= 1'd0; + hdmi_out0_next_s5 <= 1'd0; + hdmi_out0_next_s6 <= 1'd0; + hdmi_out0_next_s7 <= 1'd0; + hdmi_out0_next_s8 <= 1'd0; + hdmi_out0_next_s9 <= 1'd0; + hdmi_out0_next_s10 <= 1'd0; + hdmi_out0_next_s11 <= 1'd0; + hdmi_out0_next_s12 <= 1'd0; + hdmi_out0_next_s13 <= 1'd0; + hdmi_out0_next_s14 <= 1'd0; + hdmi_out0_next_s15 <= 1'd0; + hdmi_out0_next_s16 <= 1'd0; + hdmi_out0_next_s17 <= 1'd0; + hdmi_out0_de_r <= 1'd0; + hdmi_out0_core_source_valid_d <= 1'd0; + hdmi_out0_core_source_data_d <= 16'd0; + litedramcore_state <= 2'd0; + videoout_state <= 1'd0; + end + xilinxmultiregimpl80_regs0 <= litedramcrossbar_cmd_cdc_cdc_graycounter1_q; + xilinxmultiregimpl80_regs1 <= xilinxmultiregimpl80_regs0; + xilinxmultiregimpl81_regs0 <= litedramcrossbar_rdata_cdc_cdc_graycounter0_q; + xilinxmultiregimpl81_regs1 <= xilinxmultiregimpl81_regs0; + xilinxmultiregimpl83_regs0 <= hdmi_out0_core_initiator_cdc_graycounter0_q; + xilinxmultiregimpl83_regs1 <= xilinxmultiregimpl83_regs0; + xilinxmultiregimpl86_regs0 <= hdmi_out0_core_toggle_i; + xilinxmultiregimpl86_regs1 <= xilinxmultiregimpl86_regs0; +end + +always @(posedge icap_clk) begin + icap__i <= 32'd4294967295; + if ((icap_counter == 1'd1)) begin + icap_csib <= 1'd1; + icap_done <= 1'd0; + end + if ((icap_counter == 2'd2)) begin + icap_csib <= 1'd0; + icap__i <= 30'd536870912; + end + if ((icap_counter == 2'd3)) begin + icap_csib <= 1'd0; + icap__i <= 32'd2862175590; + end + if ((icap_counter == 3'd4)) begin + icap_csib <= 1'd0; + icap__i <= 30'd536870912; + end + if ((icap_counter == 3'd5)) begin + icap_csib <= 1'd0; + icap__i <= 30'd536870912; + end + if ((icap_counter == 3'd6)) begin + icap_csib <= 1'd0; + icap__i <= (30'd805306369 | (icap_addr <<< 4'd13)); + end + if ((icap_counter == 3'd7)) begin + icap_csib <= 1'd0; + icap__i <= icap_data; + end + if ((icap_counter == 4'd8)) begin + icap_csib <= 1'd0; + icap__i <= 30'd536870912; + end + if ((icap_counter == 4'd9)) begin + icap_csib <= 1'd0; + icap__i <= 30'd536870912; + end + if ((icap_counter == 4'd10)) begin + icap_csib <= 1'd0; + icap__i <= 30'd805339137; + end + if ((icap_counter == 4'd11)) begin + icap_csib <= 1'd0; + icap__i <= 4'd13; + end + if ((icap_counter == 4'd12)) begin + icap_csib <= 1'd0; + icap__i <= 30'd536870912; + end + if ((icap_counter == 4'd13)) begin + icap_csib <= 1'd0; + icap__i <= 30'd536870912; + end + if ((icap_counter == 4'd14)) begin + icap_csib <= 1'd1; + icap_done <= 1'd1; + end + if ((icap_counter == 4'd14)) begin + icap_counter <= 1'd0; + end else begin + if ((icap_counter != 1'd0)) begin + icap_counter <= (icap_counter + 1'd1); + end else begin + if (icap_o) begin + icap_counter <= 1'd1; + end + end + end + icap_toggle_o_r <= icap_toggle_o; + if (icap_rst) begin + icap_done <= 1'd0; + icap_csib <= 1'd1; + icap__i <= 32'd0; + icap_counter <= 4'd0; + end + xilinxmultiregimpl0_regs0 <= icap_toggle_i; + xilinxmultiregimpl0_regs1 <= xilinxmultiregimpl0_regs0; +end + +always @(posedge pcie_clk) begin + case (s7pciephy_dcommand[14:12]) + 1'd0: begin + s7pciephy_max_request_size <= 8'd128; + end + 1'd1: begin + s7pciephy_max_request_size <= 9'd256; + end + 2'd2: begin + s7pciephy_max_request_size <= 10'd512; + end + 2'd3: begin + s7pciephy_max_request_size <= 10'd512; + end + 3'd4: begin + s7pciephy_max_request_size <= 10'd512; + end + 3'd5: begin + s7pciephy_max_request_size <= 10'd512; + end + endcase + case (s7pciephy_dcommand[7:5]) + 1'd0: begin + s7pciephy_max_payload_size <= 8'd128; + end + 1'd1: begin + s7pciephy_max_payload_size <= 9'd256; + end + 2'd2: begin + s7pciephy_max_payload_size <= 10'd512; + end + 2'd3: begin + s7pciephy_max_payload_size <= 10'd512; + end + 3'd4: begin + s7pciephy_max_payload_size <= 10'd512; + end + 3'd5: begin + s7pciephy_max_payload_size <= 10'd512; + end + endcase + s7pciephy_id <= {s7pciephy_bus_number, s7pciephy_device_number, s7pciephy_function_number}; + s7pciephy_tx_datapath_cdc_graycounter1_q_binary <= s7pciephy_tx_datapath_cdc_graycounter1_q_next_binary; + s7pciephy_tx_datapath_cdc_graycounter1_q <= s7pciephy_tx_datapath_cdc_graycounter1_q_next; + if ((s7pciephy_tx_datapath_pipe_ready_sink_valid & (~s7pciephy_tx_datapath_pipe_ready_source_ready))) begin + s7pciephy_tx_datapath_pipe_ready_valid <= 1'd1; + end else begin + if (s7pciephy_tx_datapath_pipe_ready_source_ready) begin + s7pciephy_tx_datapath_pipe_ready_valid <= 1'd0; + end + end + if (((~s7pciephy_tx_datapath_pipe_ready_source_ready) & (~s7pciephy_tx_datapath_pipe_ready_valid))) begin + s7pciephy_tx_datapath_pipe_ready_sink_d_valid <= s7pciephy_tx_datapath_pipe_ready_sink_valid; + s7pciephy_tx_datapath_pipe_ready_sink_d_ready <= s7pciephy_tx_datapath_pipe_ready_sink_ready; + s7pciephy_tx_datapath_pipe_ready_sink_d_first <= s7pciephy_tx_datapath_pipe_ready_sink_first; + s7pciephy_tx_datapath_pipe_ready_sink_d_last <= s7pciephy_tx_datapath_pipe_ready_sink_last; + s7pciephy_tx_datapath_pipe_ready_sink_d_payload_dat <= s7pciephy_tx_datapath_pipe_ready_sink_payload_dat; + s7pciephy_tx_datapath_pipe_ready_sink_d_payload_be <= s7pciephy_tx_datapath_pipe_ready_sink_payload_be; + end + if ((s7pciephy_rx_datapath_pipe_ready_sink_valid & (~s7pciephy_rx_datapath_pipe_ready_source_ready))) begin + s7pciephy_rx_datapath_pipe_ready_valid <= 1'd1; + end else begin + if (s7pciephy_rx_datapath_pipe_ready_source_ready) begin + s7pciephy_rx_datapath_pipe_ready_valid <= 1'd0; + end + end + if (((~s7pciephy_rx_datapath_pipe_ready_source_ready) & (~s7pciephy_rx_datapath_pipe_ready_valid))) begin + s7pciephy_rx_datapath_pipe_ready_sink_d_valid <= s7pciephy_rx_datapath_pipe_ready_sink_valid; + s7pciephy_rx_datapath_pipe_ready_sink_d_ready <= s7pciephy_rx_datapath_pipe_ready_sink_ready; + s7pciephy_rx_datapath_pipe_ready_sink_d_first <= s7pciephy_rx_datapath_pipe_ready_sink_first; + s7pciephy_rx_datapath_pipe_ready_sink_d_last <= s7pciephy_rx_datapath_pipe_ready_sink_last; + s7pciephy_rx_datapath_pipe_ready_sink_d_payload_dat <= s7pciephy_rx_datapath_pipe_ready_sink_payload_dat; + s7pciephy_rx_datapath_pipe_ready_sink_d_payload_be <= s7pciephy_rx_datapath_pipe_ready_sink_payload_be; + end + s7pciephy_rx_datapath_cdc_graycounter0_q_binary <= s7pciephy_rx_datapath_cdc_graycounter0_q_next_binary; + s7pciephy_rx_datapath_cdc_graycounter0_q <= s7pciephy_rx_datapath_cdc_graycounter0_q_next; + s7pciephy_msi_cdc_graycounter1_q_binary <= s7pciephy_msi_cdc_graycounter1_q_next_binary; + s7pciephy_msi_cdc_graycounter1_q <= s7pciephy_msi_cdc_graycounter1_q_next; + if (pcie_rst) begin + s7pciephy_tx_datapath_cdc_graycounter1_q <= 3'd0; + s7pciephy_tx_datapath_cdc_graycounter1_q_binary <= 3'd0; + s7pciephy_tx_datapath_pipe_ready_valid <= 1'd0; + s7pciephy_tx_datapath_pipe_ready_sink_d_valid <= 1'd0; + s7pciephy_tx_datapath_pipe_ready_sink_d_ready <= 1'd0; + s7pciephy_tx_datapath_pipe_ready_sink_d_payload_dat <= 64'd0; + s7pciephy_tx_datapath_pipe_ready_sink_d_payload_be <= 8'd0; + s7pciephy_rx_datapath_pipe_ready_valid <= 1'd0; + s7pciephy_rx_datapath_pipe_ready_sink_d_valid <= 1'd0; + s7pciephy_rx_datapath_pipe_ready_sink_d_ready <= 1'd0; + s7pciephy_rx_datapath_pipe_ready_sink_d_payload_dat <= 64'd0; + s7pciephy_rx_datapath_pipe_ready_sink_d_payload_be <= 8'd0; + s7pciephy_rx_datapath_cdc_graycounter0_q <= 3'd0; + s7pciephy_rx_datapath_cdc_graycounter0_q_binary <= 3'd0; + s7pciephy_msi_cdc_graycounter1_q <= 3'd0; + s7pciephy_msi_cdc_graycounter1_q_binary <= 3'd0; + end + xilinxmultiregimpl10_regs0 <= s7pciephy_tx_datapath_cdc_graycounter0_q; + xilinxmultiregimpl10_regs1 <= xilinxmultiregimpl10_regs0; + xilinxmultiregimpl13_regs0 <= s7pciephy_rx_datapath_cdc_graycounter1_q; + xilinxmultiregimpl13_regs1 <= xilinxmultiregimpl13_regs0; + xilinxmultiregimpl14_regs0 <= s7pciephy_msi_cdc_graycounter0_q; + xilinxmultiregimpl14_regs1 <= xilinxmultiregimpl14_regs0; +end + +always @(posedge pix1p25x_clk) begin + if (hdmi_in0_s7datacapture0_reset_lateness) begin + hdmi_in0_s7datacapture0_lateness <= 8'd128; + end else begin + if (((~hdmi_in0_s7datacapture0_too_late) & (~hdmi_in0_s7datacapture0_too_early))) begin + if (hdmi_in0_s7datacapture0_dec) begin + hdmi_in0_s7datacapture0_lateness <= (hdmi_in0_s7datacapture0_lateness + 1'd1); + end + if (hdmi_in0_s7datacapture0_inc) begin + hdmi_in0_s7datacapture0_lateness <= (hdmi_in0_s7datacapture0_lateness - 1'd1); + end + end + end + hdmi_in0_s7datacapture0_sync_mcntvalue_starter <= 1'd0; + if (hdmi_in0_s7datacapture0_sync_mcntvalue_pong_o) begin + hdmi_in0_s7datacapture0_sync_mcntvalue_ibuffer <= hdmi_in0_s7datacapture0_sync_mcntvalue_i; + end + if (hdmi_in0_s7datacapture0_sync_mcntvalue_ping_i) begin + hdmi_in0_s7datacapture0_sync_mcntvalue_ping_toggle_i <= (~hdmi_in0_s7datacapture0_sync_mcntvalue_ping_toggle_i); + end + hdmi_in0_s7datacapture0_sync_mcntvalue_pong_toggle_o_r <= hdmi_in0_s7datacapture0_sync_mcntvalue_pong_toggle_o; + if (hdmi_in0_s7datacapture0_sync_mcntvalue_wait) begin + if ((~hdmi_in0_s7datacapture0_sync_mcntvalue_done)) begin + hdmi_in0_s7datacapture0_sync_mcntvalue_count <= (hdmi_in0_s7datacapture0_sync_mcntvalue_count - 1'd1); + end + end else begin + hdmi_in0_s7datacapture0_sync_mcntvalue_count <= 8'd128; + end + hdmi_in0_s7datacapture0_sync_scntvalue_starter <= 1'd0; + if (hdmi_in0_s7datacapture0_sync_scntvalue_pong_o) begin + hdmi_in0_s7datacapture0_sync_scntvalue_ibuffer <= hdmi_in0_s7datacapture0_sync_scntvalue_i; + end + if (hdmi_in0_s7datacapture0_sync_scntvalue_ping_i) begin + hdmi_in0_s7datacapture0_sync_scntvalue_ping_toggle_i <= (~hdmi_in0_s7datacapture0_sync_scntvalue_ping_toggle_i); + end + hdmi_in0_s7datacapture0_sync_scntvalue_pong_toggle_o_r <= hdmi_in0_s7datacapture0_sync_scntvalue_pong_toggle_o; + if (hdmi_in0_s7datacapture0_sync_scntvalue_wait) begin + if ((~hdmi_in0_s7datacapture0_sync_scntvalue_done)) begin + hdmi_in0_s7datacapture0_sync_scntvalue_count <= (hdmi_in0_s7datacapture0_sync_scntvalue_count - 1'd1); + end + end else begin + hdmi_in0_s7datacapture0_sync_scntvalue_count <= 8'd128; + end + hdmi_in0_s7datacapture0_mdata_d <= hdmi_in0_s7datacapture0_mdata; + hdmi_in0_s7datacapture0_do_delay_rst_toggle_o_r <= hdmi_in0_s7datacapture0_do_delay_rst_toggle_o; + hdmi_in0_s7datacapture0_do_delay_master_inc_toggle_o_r <= hdmi_in0_s7datacapture0_do_delay_master_inc_toggle_o; + hdmi_in0_s7datacapture0_do_delay_master_dec_toggle_o_r <= hdmi_in0_s7datacapture0_do_delay_master_dec_toggle_o; + hdmi_in0_s7datacapture0_do_delay_slave_inc_toggle_o_r <= hdmi_in0_s7datacapture0_do_delay_slave_inc_toggle_o; + hdmi_in0_s7datacapture0_do_delay_slave_dec_toggle_o_r <= hdmi_in0_s7datacapture0_do_delay_slave_dec_toggle_o; + hdmi_in0_s7datacapture0_do_reset_lateness_toggle_o_r <= hdmi_in0_s7datacapture0_do_reset_lateness_toggle_o; + if (hdmi_in0_s7datacapture1_reset_lateness) begin + hdmi_in0_s7datacapture1_lateness <= 8'd128; + end else begin + if (((~hdmi_in0_s7datacapture1_too_late) & (~hdmi_in0_s7datacapture1_too_early))) begin + if (hdmi_in0_s7datacapture1_dec) begin + hdmi_in0_s7datacapture1_lateness <= (hdmi_in0_s7datacapture1_lateness + 1'd1); + end + if (hdmi_in0_s7datacapture1_inc) begin + hdmi_in0_s7datacapture1_lateness <= (hdmi_in0_s7datacapture1_lateness - 1'd1); + end + end + end + hdmi_in0_s7datacapture1_sync_mcntvalue_starter <= 1'd0; + if (hdmi_in0_s7datacapture1_sync_mcntvalue_pong_o) begin + hdmi_in0_s7datacapture1_sync_mcntvalue_ibuffer <= hdmi_in0_s7datacapture1_sync_mcntvalue_i; + end + if (hdmi_in0_s7datacapture1_sync_mcntvalue_ping_i) begin + hdmi_in0_s7datacapture1_sync_mcntvalue_ping_toggle_i <= (~hdmi_in0_s7datacapture1_sync_mcntvalue_ping_toggle_i); + end + hdmi_in0_s7datacapture1_sync_mcntvalue_pong_toggle_o_r <= hdmi_in0_s7datacapture1_sync_mcntvalue_pong_toggle_o; + if (hdmi_in0_s7datacapture1_sync_mcntvalue_wait) begin + if ((~hdmi_in0_s7datacapture1_sync_mcntvalue_done)) begin + hdmi_in0_s7datacapture1_sync_mcntvalue_count <= (hdmi_in0_s7datacapture1_sync_mcntvalue_count - 1'd1); + end + end else begin + hdmi_in0_s7datacapture1_sync_mcntvalue_count <= 8'd128; + end + hdmi_in0_s7datacapture1_sync_scntvalue_starter <= 1'd0; + if (hdmi_in0_s7datacapture1_sync_scntvalue_pong_o) begin + hdmi_in0_s7datacapture1_sync_scntvalue_ibuffer <= hdmi_in0_s7datacapture1_sync_scntvalue_i; + end + if (hdmi_in0_s7datacapture1_sync_scntvalue_ping_i) begin + hdmi_in0_s7datacapture1_sync_scntvalue_ping_toggle_i <= (~hdmi_in0_s7datacapture1_sync_scntvalue_ping_toggle_i); + end + hdmi_in0_s7datacapture1_sync_scntvalue_pong_toggle_o_r <= hdmi_in0_s7datacapture1_sync_scntvalue_pong_toggle_o; + if (hdmi_in0_s7datacapture1_sync_scntvalue_wait) begin + if ((~hdmi_in0_s7datacapture1_sync_scntvalue_done)) begin + hdmi_in0_s7datacapture1_sync_scntvalue_count <= (hdmi_in0_s7datacapture1_sync_scntvalue_count - 1'd1); + end + end else begin + hdmi_in0_s7datacapture1_sync_scntvalue_count <= 8'd128; + end + hdmi_in0_s7datacapture1_mdata_d <= hdmi_in0_s7datacapture1_mdata; + hdmi_in0_s7datacapture1_do_delay_rst_toggle_o_r <= hdmi_in0_s7datacapture1_do_delay_rst_toggle_o; + hdmi_in0_s7datacapture1_do_delay_master_inc_toggle_o_r <= hdmi_in0_s7datacapture1_do_delay_master_inc_toggle_o; + hdmi_in0_s7datacapture1_do_delay_master_dec_toggle_o_r <= hdmi_in0_s7datacapture1_do_delay_master_dec_toggle_o; + hdmi_in0_s7datacapture1_do_delay_slave_inc_toggle_o_r <= hdmi_in0_s7datacapture1_do_delay_slave_inc_toggle_o; + hdmi_in0_s7datacapture1_do_delay_slave_dec_toggle_o_r <= hdmi_in0_s7datacapture1_do_delay_slave_dec_toggle_o; + hdmi_in0_s7datacapture1_do_reset_lateness_toggle_o_r <= hdmi_in0_s7datacapture1_do_reset_lateness_toggle_o; + if (hdmi_in0_s7datacapture2_reset_lateness) begin + hdmi_in0_s7datacapture2_lateness <= 8'd128; + end else begin + if (((~hdmi_in0_s7datacapture2_too_late) & (~hdmi_in0_s7datacapture2_too_early))) begin + if (hdmi_in0_s7datacapture2_dec) begin + hdmi_in0_s7datacapture2_lateness <= (hdmi_in0_s7datacapture2_lateness + 1'd1); + end + if (hdmi_in0_s7datacapture2_inc) begin + hdmi_in0_s7datacapture2_lateness <= (hdmi_in0_s7datacapture2_lateness - 1'd1); + end + end + end + hdmi_in0_s7datacapture2_sync_mcntvalue_starter <= 1'd0; + if (hdmi_in0_s7datacapture2_sync_mcntvalue_pong_o) begin + hdmi_in0_s7datacapture2_sync_mcntvalue_ibuffer <= hdmi_in0_s7datacapture2_sync_mcntvalue_i; + end + if (hdmi_in0_s7datacapture2_sync_mcntvalue_ping_i) begin + hdmi_in0_s7datacapture2_sync_mcntvalue_ping_toggle_i <= (~hdmi_in0_s7datacapture2_sync_mcntvalue_ping_toggle_i); + end + hdmi_in0_s7datacapture2_sync_mcntvalue_pong_toggle_o_r <= hdmi_in0_s7datacapture2_sync_mcntvalue_pong_toggle_o; + if (hdmi_in0_s7datacapture2_sync_mcntvalue_wait) begin + if ((~hdmi_in0_s7datacapture2_sync_mcntvalue_done)) begin + hdmi_in0_s7datacapture2_sync_mcntvalue_count <= (hdmi_in0_s7datacapture2_sync_mcntvalue_count - 1'd1); + end + end else begin + hdmi_in0_s7datacapture2_sync_mcntvalue_count <= 8'd128; + end + hdmi_in0_s7datacapture2_sync_scntvalue_starter <= 1'd0; + if (hdmi_in0_s7datacapture2_sync_scntvalue_pong_o) begin + hdmi_in0_s7datacapture2_sync_scntvalue_ibuffer <= hdmi_in0_s7datacapture2_sync_scntvalue_i; + end + if (hdmi_in0_s7datacapture2_sync_scntvalue_ping_i) begin + hdmi_in0_s7datacapture2_sync_scntvalue_ping_toggle_i <= (~hdmi_in0_s7datacapture2_sync_scntvalue_ping_toggle_i); + end + hdmi_in0_s7datacapture2_sync_scntvalue_pong_toggle_o_r <= hdmi_in0_s7datacapture2_sync_scntvalue_pong_toggle_o; + if (hdmi_in0_s7datacapture2_sync_scntvalue_wait) begin + if ((~hdmi_in0_s7datacapture2_sync_scntvalue_done)) begin + hdmi_in0_s7datacapture2_sync_scntvalue_count <= (hdmi_in0_s7datacapture2_sync_scntvalue_count - 1'd1); + end + end else begin + hdmi_in0_s7datacapture2_sync_scntvalue_count <= 8'd128; + end + hdmi_in0_s7datacapture2_mdata_d <= hdmi_in0_s7datacapture2_mdata; + hdmi_in0_s7datacapture2_do_delay_rst_toggle_o_r <= hdmi_in0_s7datacapture2_do_delay_rst_toggle_o; + hdmi_in0_s7datacapture2_do_delay_master_inc_toggle_o_r <= hdmi_in0_s7datacapture2_do_delay_master_inc_toggle_o; + hdmi_in0_s7datacapture2_do_delay_master_dec_toggle_o_r <= hdmi_in0_s7datacapture2_do_delay_master_dec_toggle_o; + hdmi_in0_s7datacapture2_do_delay_slave_inc_toggle_o_r <= hdmi_in0_s7datacapture2_do_delay_slave_inc_toggle_o; + hdmi_in0_s7datacapture2_do_delay_slave_dec_toggle_o_r <= hdmi_in0_s7datacapture2_do_delay_slave_dec_toggle_o; + hdmi_in0_s7datacapture2_do_reset_lateness_toggle_o_r <= hdmi_in0_s7datacapture2_do_reset_lateness_toggle_o; + if (pix1p25x_rst) begin + hdmi_in0_s7datacapture0_sync_mcntvalue_starter <= 1'd1; + hdmi_in0_s7datacapture0_sync_mcntvalue_count <= 8'd128; + hdmi_in0_s7datacapture0_sync_scntvalue_starter <= 1'd1; + hdmi_in0_s7datacapture0_sync_scntvalue_count <= 8'd128; + hdmi_in0_s7datacapture0_mdata_d <= 8'd0; + hdmi_in0_s7datacapture0_lateness <= 8'd128; + hdmi_in0_s7datacapture1_sync_mcntvalue_starter <= 1'd1; + hdmi_in0_s7datacapture1_sync_mcntvalue_count <= 8'd128; + hdmi_in0_s7datacapture1_sync_scntvalue_starter <= 1'd1; + hdmi_in0_s7datacapture1_sync_scntvalue_count <= 8'd128; + hdmi_in0_s7datacapture1_mdata_d <= 8'd0; + hdmi_in0_s7datacapture1_lateness <= 8'd128; + hdmi_in0_s7datacapture2_sync_mcntvalue_starter <= 1'd1; + hdmi_in0_s7datacapture2_sync_mcntvalue_count <= 8'd128; + hdmi_in0_s7datacapture2_sync_scntvalue_starter <= 1'd1; + hdmi_in0_s7datacapture2_sync_scntvalue_count <= 8'd128; + hdmi_in0_s7datacapture2_mdata_d <= 8'd0; + hdmi_in0_s7datacapture2_lateness <= 8'd128; + end + xilinxmultiregimpl24_regs0 <= hdmi_in0_s7datacapture0_sync_mcntvalue_pong_toggle_i; + xilinxmultiregimpl24_regs1 <= xilinxmultiregimpl24_regs0; + xilinxmultiregimpl27_regs0 <= hdmi_in0_s7datacapture0_sync_scntvalue_pong_toggle_i; + xilinxmultiregimpl27_regs1 <= xilinxmultiregimpl27_regs0; + xilinxmultiregimpl29_regs0 <= hdmi_in0_s7datacapture0_do_delay_rst_toggle_i; + xilinxmultiregimpl29_regs1 <= xilinxmultiregimpl29_regs0; + xilinxmultiregimpl30_regs0 <= hdmi_in0_s7datacapture0_do_delay_master_inc_toggle_i; + xilinxmultiregimpl30_regs1 <= xilinxmultiregimpl30_regs0; + xilinxmultiregimpl31_regs0 <= hdmi_in0_s7datacapture0_do_delay_master_dec_toggle_i; + xilinxmultiregimpl31_regs1 <= xilinxmultiregimpl31_regs0; + xilinxmultiregimpl32_regs0 <= hdmi_in0_s7datacapture0_do_delay_slave_inc_toggle_i; + xilinxmultiregimpl32_regs1 <= xilinxmultiregimpl32_regs0; + xilinxmultiregimpl33_regs0 <= hdmi_in0_s7datacapture0_do_delay_slave_dec_toggle_i; + xilinxmultiregimpl33_regs1 <= xilinxmultiregimpl33_regs0; + xilinxmultiregimpl35_regs0 <= hdmi_in0_s7datacapture0_do_reset_lateness_toggle_i; + xilinxmultiregimpl35_regs1 <= xilinxmultiregimpl35_regs0; + xilinxmultiregimpl40_regs0 <= hdmi_in0_s7datacapture1_sync_mcntvalue_pong_toggle_i; + xilinxmultiregimpl40_regs1 <= xilinxmultiregimpl40_regs0; + xilinxmultiregimpl43_regs0 <= hdmi_in0_s7datacapture1_sync_scntvalue_pong_toggle_i; + xilinxmultiregimpl43_regs1 <= xilinxmultiregimpl43_regs0; + xilinxmultiregimpl45_regs0 <= hdmi_in0_s7datacapture1_do_delay_rst_toggle_i; + xilinxmultiregimpl45_regs1 <= xilinxmultiregimpl45_regs0; + xilinxmultiregimpl46_regs0 <= hdmi_in0_s7datacapture1_do_delay_master_inc_toggle_i; + xilinxmultiregimpl46_regs1 <= xilinxmultiregimpl46_regs0; + xilinxmultiregimpl47_regs0 <= hdmi_in0_s7datacapture1_do_delay_master_dec_toggle_i; + xilinxmultiregimpl47_regs1 <= xilinxmultiregimpl47_regs0; + xilinxmultiregimpl48_regs0 <= hdmi_in0_s7datacapture1_do_delay_slave_inc_toggle_i; + xilinxmultiregimpl48_regs1 <= xilinxmultiregimpl48_regs0; + xilinxmultiregimpl49_regs0 <= hdmi_in0_s7datacapture1_do_delay_slave_dec_toggle_i; + xilinxmultiregimpl49_regs1 <= xilinxmultiregimpl49_regs0; + xilinxmultiregimpl51_regs0 <= hdmi_in0_s7datacapture1_do_reset_lateness_toggle_i; + xilinxmultiregimpl51_regs1 <= xilinxmultiregimpl51_regs0; + xilinxmultiregimpl56_regs0 <= hdmi_in0_s7datacapture2_sync_mcntvalue_pong_toggle_i; + xilinxmultiregimpl56_regs1 <= xilinxmultiregimpl56_regs0; + xilinxmultiregimpl59_regs0 <= hdmi_in0_s7datacapture2_sync_scntvalue_pong_toggle_i; + xilinxmultiregimpl59_regs1 <= xilinxmultiregimpl59_regs0; + xilinxmultiregimpl61_regs0 <= hdmi_in0_s7datacapture2_do_delay_rst_toggle_i; + xilinxmultiregimpl61_regs1 <= xilinxmultiregimpl61_regs0; + xilinxmultiregimpl62_regs0 <= hdmi_in0_s7datacapture2_do_delay_master_inc_toggle_i; + xilinxmultiregimpl62_regs1 <= xilinxmultiregimpl62_regs0; + xilinxmultiregimpl63_regs0 <= hdmi_in0_s7datacapture2_do_delay_master_dec_toggle_i; + xilinxmultiregimpl63_regs1 <= xilinxmultiregimpl63_regs0; + xilinxmultiregimpl64_regs0 <= hdmi_in0_s7datacapture2_do_delay_slave_inc_toggle_i; + xilinxmultiregimpl64_regs1 <= xilinxmultiregimpl64_regs0; + xilinxmultiregimpl65_regs0 <= hdmi_in0_s7datacapture2_do_delay_slave_dec_toggle_i; + xilinxmultiregimpl65_regs1 <= xilinxmultiregimpl65_regs0; + xilinxmultiregimpl67_regs0 <= hdmi_in0_s7datacapture2_do_reset_lateness_toggle_i; + xilinxmultiregimpl67_regs1 <= xilinxmultiregimpl67_regs0; +end + +always @(posedge pix_o_clk) begin + hdmi_in0_syncpol_c0 <= hdmi_in0_syncpol_data_in0_raw; + hdmi_in0_syncpol_c1 <= hdmi_in0_syncpol_data_in1_raw; + hdmi_in0_syncpol_c2 <= hdmi_in0_syncpol_data_in2_raw; + if (pix_o_rst) begin + hdmi_in0_syncpol_c0 <= 10'd0; + hdmi_in0_syncpol_c1 <= 10'd0; + hdmi_in0_syncpol_c2 <= 10'd0; + end +end + +always @(posedge sys_clk) begin + pcie_dma0_buffering_next_sink_valid <= 1'd1; + if (pcie_dma0_buffering_next_sink_ready) begin + pcie_dma0_counter <= (pcie_dma0_counter + 1'd1); + end + pcie_dma0_buffering_next_sink_payload_data <= pcie_dma0_counter; + pcie_dma1_buffering_next_sink_valid <= 1'd1; + if (pcie_dma1_buffering_next_sink_ready) begin + pcie_dma1_counter <= (pcie_dma1_counter + 2'd2); + end + pcie_dma1_buffering_next_sink_payload_data <= pcie_dma1_counter; + if ((netv2_soccontroller_bus_errors != 32'd4294967295)) begin + if (netv2_soccontroller_bus_error) begin + netv2_soccontroller_bus_errors <= (netv2_soccontroller_bus_errors + 1'd1); + end + end + netv2_netv2_ram_bus_ack <= 1'd0; + if (((netv2_netv2_ram_bus_cyc & netv2_netv2_ram_bus_stb) & (~netv2_netv2_ram_bus_ack))) begin + netv2_netv2_ram_bus_ack <= 1'd1; + end + netv2_ram_bus_ram_bus_ack <= 1'd0; + if (((netv2_ram_bus_ram_bus_cyc & netv2_ram_bus_ram_bus_stb) & (~netv2_ram_bus_ram_bus_ack))) begin + netv2_ram_bus_ram_bus_ack <= 1'd1; + end + if (netv2_uartcrossover_tx_clear) begin + netv2_uartcrossover_tx_pending <= 1'd0; + end + netv2_uartcrossover_tx_old_trigger <= netv2_uartcrossover_tx_trigger; + if (((~netv2_uartcrossover_tx_trigger) & netv2_uartcrossover_tx_old_trigger)) begin + netv2_uartcrossover_tx_pending <= 1'd1; + end + if (netv2_uartcrossover_rx_clear) begin + netv2_uartcrossover_rx_pending <= 1'd0; + end + netv2_uartcrossover_rx_old_trigger <= netv2_uartcrossover_rx_trigger; + if (((~netv2_uartcrossover_rx_trigger) & netv2_uartcrossover_rx_old_trigger)) begin + netv2_uartcrossover_rx_pending <= 1'd1; + end + if (netv2_uartcrossover_tx_fifo_syncfifo_re) begin + netv2_uartcrossover_tx_fifo_readable <= 1'd1; + end else begin + if (netv2_uartcrossover_tx_fifo_re) begin + netv2_uartcrossover_tx_fifo_readable <= 1'd0; + end + end + if (((netv2_uartcrossover_tx_fifo_syncfifo_we & netv2_uartcrossover_tx_fifo_syncfifo_writable) & (~netv2_uartcrossover_tx_fifo_replace))) begin + netv2_uartcrossover_tx_fifo_produce <= (netv2_uartcrossover_tx_fifo_produce + 1'd1); + end + if (netv2_uartcrossover_tx_fifo_do_read) begin + netv2_uartcrossover_tx_fifo_consume <= (netv2_uartcrossover_tx_fifo_consume + 1'd1); + end + if (((netv2_uartcrossover_tx_fifo_syncfifo_we & netv2_uartcrossover_tx_fifo_syncfifo_writable) & (~netv2_uartcrossover_tx_fifo_replace))) begin + if ((~netv2_uartcrossover_tx_fifo_do_read)) begin + netv2_uartcrossover_tx_fifo_level0 <= (netv2_uartcrossover_tx_fifo_level0 + 1'd1); + end + end else begin + if (netv2_uartcrossover_tx_fifo_do_read) begin + netv2_uartcrossover_tx_fifo_level0 <= (netv2_uartcrossover_tx_fifo_level0 - 1'd1); + end + end + if (netv2_uartcrossover_rx_fifo_syncfifo_re) begin + netv2_uartcrossover_rx_fifo_readable <= 1'd1; + end else begin + if (netv2_uartcrossover_rx_fifo_re) begin + netv2_uartcrossover_rx_fifo_readable <= 1'd0; + end + end + if (((netv2_uartcrossover_rx_fifo_syncfifo_we & netv2_uartcrossover_rx_fifo_syncfifo_writable) & (~netv2_uartcrossover_rx_fifo_replace))) begin + netv2_uartcrossover_rx_fifo_produce <= (netv2_uartcrossover_rx_fifo_produce + 1'd1); + end + if (netv2_uartcrossover_rx_fifo_do_read) begin + netv2_uartcrossover_rx_fifo_consume <= (netv2_uartcrossover_rx_fifo_consume + 1'd1); + end + if (((netv2_uartcrossover_rx_fifo_syncfifo_we & netv2_uartcrossover_rx_fifo_syncfifo_writable) & (~netv2_uartcrossover_rx_fifo_replace))) begin + if ((~netv2_uartcrossover_rx_fifo_do_read)) begin + netv2_uartcrossover_rx_fifo_level0 <= (netv2_uartcrossover_rx_fifo_level0 + 1'd1); + end + end else begin + if (netv2_uartcrossover_rx_fifo_do_read) begin + netv2_uartcrossover_rx_fifo_level0 <= (netv2_uartcrossover_rx_fifo_level0 - 1'd1); + end + end + if (netv2_xover_tx_clear) begin + netv2_xover_tx_pending <= 1'd0; + end + netv2_xover_tx_old_trigger <= netv2_xover_tx_trigger; + if (((~netv2_xover_tx_trigger) & netv2_xover_tx_old_trigger)) begin + netv2_xover_tx_pending <= 1'd1; + end + if (netv2_xover_rx_clear) begin + netv2_xover_rx_pending <= 1'd0; + end + netv2_xover_rx_old_trigger <= netv2_xover_rx_trigger; + if (((~netv2_xover_rx_trigger) & netv2_xover_rx_old_trigger)) begin + netv2_xover_rx_pending <= 1'd1; + end + if (((~netv2_xover_tx_fifo_source_valid) | netv2_xover_tx_fifo_source_ready)) begin + netv2_xover_tx_fifo_source_valid <= netv2_xover_tx_fifo_sink_valid; + netv2_xover_tx_fifo_source_first <= netv2_xover_tx_fifo_sink_first; + netv2_xover_tx_fifo_source_last <= netv2_xover_tx_fifo_sink_last; + netv2_xover_tx_fifo_source_payload_data <= netv2_xover_tx_fifo_sink_payload_data; + end + if (((~netv2_xover_rx_fifo_source_valid) | netv2_xover_rx_fifo_source_ready)) begin + netv2_xover_rx_fifo_source_valid <= netv2_xover_rx_fifo_sink_valid; + netv2_xover_rx_fifo_source_first <= netv2_xover_rx_fifo_sink_first; + netv2_xover_rx_fifo_source_last <= netv2_xover_rx_fifo_sink_last; + netv2_xover_rx_fifo_source_payload_data <= netv2_xover_rx_fifo_sink_payload_data; + end + if (netv2_en_storage) begin + if ((netv2_value == 1'd0)) begin + netv2_value <= netv2_reload_storage; + end else begin + netv2_value <= (netv2_value - 1'd1); + end + end else begin + netv2_value <= netv2_load_storage; + end + if (netv2_update_value_re) begin + netv2_value_status <= netv2_value; + end + if (netv2_zero_clear) begin + netv2_zero_pending <= 1'd0; + end + netv2_zero_old_trigger <= netv2_zero_trigger; + if (((~netv2_zero_trigger) & netv2_zero_old_trigger)) begin + netv2_zero_pending <= 1'd1; + end + if ((dna_count < 7'd114)) begin + dna_count <= (dna_count + 1'd1); + if (dna_clk) begin + dna_status <= {dna_status, dna_do}; + end + end + if (xadc_drdy) begin + case (xadc_channel) + 1'd0: begin + xadc_temperature_status <= (xadc_do >>> 3'd4); + end + 1'd1: begin + xadc_vccint_status <= (xadc_do >>> 3'd4); + end + 2'd2: begin + xadc_vccaux_status <= (xadc_do >>> 3'd4); + end + 3'd6: begin + xadc_vccbram_status <= (xadc_do >>> 3'd4); + end + endcase + end + xadc_eoc_status <= ((xadc_eoc_status & (~xadc_eoc_we)) | xadc_eoc); + xadc_eos_status <= ((xadc_eos_status & (~xadc_eos_we)) | xadc_eos); + icap_icap_clk_counter <= (icap_icap_clk_counter + 1'd1); + icap_clk <= icap_icap_clk_counter[3]; + if (icap_i) begin + icap_toggle_i <= (~icap_toggle_i); + end + flash_clk_divider1 <= (flash_clk_divider1 + 1'd1); + if (flash_clk_rise) begin + flash_pads_clk <= flash_clk_enable; + end else begin + if (flash_clk_fall) begin + flash_clk_divider1 <= 1'd0; + flash_pads_clk <= 1'd0; + end + end + flash_pads_cs_n <= ((~flash_cs) | (~flash_cs_enable)); + if (flash_mosi_latch) begin + flash_mosi_data <= flash_mosi1; + flash_mosi_sel <= 6'd39; + end else begin + if (flash_clk_fall) begin + if (flash_cs_enable) begin + flash_pads_mosi <= sync_t_array_muxed; + end + flash_mosi_sel <= (flash_mosi_sel - 1'd1); + end + end + if (flash_clk_rise) begin + if (flash_loopback) begin + flash_miso_data <= {flash_miso_data, flash_pads_mosi}; + end else begin + flash_miso_data <= {flash_miso_data, flash_pads_miso}; + end + end + if (flash_miso_latch) begin + flash_miso1 <= flash_miso_data; + end + s7spiflash_state <= s7spiflash_next_state; + if (flash_count_s7spiflash_next_value_ce) begin + flash_count <= flash_count_s7spiflash_next_value; + end + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline; + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; + a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value0 <= 3'd7; + end + a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value0 <= 3'd7; + end + a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip2_value0 <= 3'd7; + end + a7ddrphy_bitslip2_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip2_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip3_value0 <= 3'd7; + end + a7ddrphy_bitslip3_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip3_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value1 <= 3'd7; + end + a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[4], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[4], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[4], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[4], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value1 <= 3'd7; + end + a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[5], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[5], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[5], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[5], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip2_value1 <= 3'd7; + end + a7ddrphy_bitslip2_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[6], a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[6], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[6], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[6], a7ddrphy_dfi_p0_wrdata_mask[2]}, a7ddrphy_bitslip2_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip3_value1 <= 3'd7; + end + a7ddrphy_bitslip3_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[7], a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[7], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[7], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[7], a7ddrphy_dfi_p0_wrdata_mask[3]}, a7ddrphy_bitslip3_r1[15:8]}; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value2 <= 3'd7; + end + a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[32], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[32], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[32], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[32], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value3 <= 3'd7; + end + a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value2 <= 3'd7; + end + a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[33], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[33], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[33], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[33], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value3 <= 3'd7; + end + a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip2_value2 <= (a7ddrphy_bitslip2_value2 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip2_value2 <= 3'd7; + end + a7ddrphy_bitslip2_r2 <= {{a7ddrphy_dfi_p3_wrdata[34], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[34], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[34], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[34], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r2[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip2_value3 <= (a7ddrphy_bitslip2_value3 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip2_value3 <= 3'd7; + end + a7ddrphy_bitslip2_r3 <= {a7ddrphy_bitslip23, a7ddrphy_bitslip2_r3[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip3_value2 <= (a7ddrphy_bitslip3_value2 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip3_value2 <= 3'd7; + end + a7ddrphy_bitslip3_r2 <= {{a7ddrphy_dfi_p3_wrdata[35], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[35], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[35], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[35], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r2[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip3_value3 <= (a7ddrphy_bitslip3_value3 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip3_value3 <= 3'd7; + end + a7ddrphy_bitslip3_r3 <= {a7ddrphy_bitslip33, a7ddrphy_bitslip3_r3[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip4_value0 <= 3'd7; + end + a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[36], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[36], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[36], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[36], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip4_value1 <= 3'd7; + end + a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip5_value0 <= 3'd7; + end + a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[37], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[37], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[37], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[37], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip5_value1 <= 3'd7; + end + a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip6_value0 <= 3'd7; + end + a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[38], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[38], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[38], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[38], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip6_value1 <= 3'd7; + end + a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip7_value0 <= 3'd7; + end + a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[39], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[39], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[39], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[39], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip7_value1 <= 3'd7; + end + a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip8_value0 <= 3'd7; + end + a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[40], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[40], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[40], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[40], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip8_value1 <= 3'd7; + end + a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip9_value0 <= 3'd7; + end + a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[41], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[41], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[41], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[41], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip9_value1 <= 3'd7; + end + a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip10_value0 <= 3'd7; + end + a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[42], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[42], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[42], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[42], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip10_value1 <= 3'd7; + end + a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip11_value0 <= 3'd7; + end + a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[43], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[43], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[43], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[43], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip11_value1 <= 3'd7; + end + a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip12_value0 <= 3'd7; + end + a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[44], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[44], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[44], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[44], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip12_value1 <= 3'd7; + end + a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip13_value0 <= 3'd7; + end + a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[45], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[45], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[45], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[45], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip13_value1 <= 3'd7; + end + a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip14_value0 <= 3'd7; + end + a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[46], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[46], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[46], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[46], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip14_value1 <= 3'd7; + end + a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip15_value0 <= 3'd7; + end + a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[47], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[47], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[47], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[47], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip15_value1 <= 3'd7; + end + a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip16_value0 <= (a7ddrphy_bitslip16_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip16_value0 <= 3'd7; + end + a7ddrphy_bitslip16_r0 <= {{a7ddrphy_dfi_p3_wrdata[48], a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p2_wrdata[48], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p1_wrdata[48], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p0_wrdata[48], a7ddrphy_dfi_p0_wrdata[16]}, a7ddrphy_bitslip16_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip16_value1 <= (a7ddrphy_bitslip16_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip16_value1 <= 3'd7; + end + a7ddrphy_bitslip16_r1 <= {a7ddrphy_bitslip161, a7ddrphy_bitslip16_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip17_value0 <= (a7ddrphy_bitslip17_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip17_value0 <= 3'd7; + end + a7ddrphy_bitslip17_r0 <= {{a7ddrphy_dfi_p3_wrdata[49], a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p2_wrdata[49], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p1_wrdata[49], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p0_wrdata[49], a7ddrphy_dfi_p0_wrdata[17]}, a7ddrphy_bitslip17_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip17_value1 <= (a7ddrphy_bitslip17_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip17_value1 <= 3'd7; + end + a7ddrphy_bitslip17_r1 <= {a7ddrphy_bitslip171, a7ddrphy_bitslip17_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip18_value0 <= (a7ddrphy_bitslip18_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip18_value0 <= 3'd7; + end + a7ddrphy_bitslip18_r0 <= {{a7ddrphy_dfi_p3_wrdata[50], a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p2_wrdata[50], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p1_wrdata[50], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p0_wrdata[50], a7ddrphy_dfi_p0_wrdata[18]}, a7ddrphy_bitslip18_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip18_value1 <= (a7ddrphy_bitslip18_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip18_value1 <= 3'd7; + end + a7ddrphy_bitslip18_r1 <= {a7ddrphy_bitslip181, a7ddrphy_bitslip18_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip19_value0 <= (a7ddrphy_bitslip19_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip19_value0 <= 3'd7; + end + a7ddrphy_bitslip19_r0 <= {{a7ddrphy_dfi_p3_wrdata[51], a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p2_wrdata[51], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p1_wrdata[51], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p0_wrdata[51], a7ddrphy_dfi_p0_wrdata[19]}, a7ddrphy_bitslip19_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip19_value1 <= (a7ddrphy_bitslip19_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip19_value1 <= 3'd7; + end + a7ddrphy_bitslip19_r1 <= {a7ddrphy_bitslip191, a7ddrphy_bitslip19_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip20_value0 <= (a7ddrphy_bitslip20_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip20_value0 <= 3'd7; + end + a7ddrphy_bitslip20_r0 <= {{a7ddrphy_dfi_p3_wrdata[52], a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p2_wrdata[52], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p1_wrdata[52], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p0_wrdata[52], a7ddrphy_dfi_p0_wrdata[20]}, a7ddrphy_bitslip20_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip20_value1 <= (a7ddrphy_bitslip20_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip20_value1 <= 3'd7; + end + a7ddrphy_bitslip20_r1 <= {a7ddrphy_bitslip201, a7ddrphy_bitslip20_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip21_value0 <= (a7ddrphy_bitslip21_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip21_value0 <= 3'd7; + end + a7ddrphy_bitslip21_r0 <= {{a7ddrphy_dfi_p3_wrdata[53], a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p2_wrdata[53], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p1_wrdata[53], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p0_wrdata[53], a7ddrphy_dfi_p0_wrdata[21]}, a7ddrphy_bitslip21_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip21_value1 <= (a7ddrphy_bitslip21_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip21_value1 <= 3'd7; + end + a7ddrphy_bitslip21_r1 <= {a7ddrphy_bitslip211, a7ddrphy_bitslip21_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip22_value0 <= (a7ddrphy_bitslip22_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip22_value0 <= 3'd7; + end + a7ddrphy_bitslip22_r0 <= {{a7ddrphy_dfi_p3_wrdata[54], a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p2_wrdata[54], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p1_wrdata[54], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p0_wrdata[54], a7ddrphy_dfi_p0_wrdata[22]}, a7ddrphy_bitslip22_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip22_value1 <= (a7ddrphy_bitslip22_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip22_value1 <= 3'd7; + end + a7ddrphy_bitslip22_r1 <= {a7ddrphy_bitslip221, a7ddrphy_bitslip22_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip23_value0 <= (a7ddrphy_bitslip23_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[2] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip23_value0 <= 3'd7; + end + a7ddrphy_bitslip23_r0 <= {{a7ddrphy_dfi_p3_wrdata[55], a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p2_wrdata[55], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p1_wrdata[55], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p0_wrdata[55], a7ddrphy_dfi_p0_wrdata[23]}, a7ddrphy_bitslip23_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip23_value1 <= (a7ddrphy_bitslip23_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip23_value1 <= 3'd7; + end + a7ddrphy_bitslip23_r1 <= {a7ddrphy_bitslip231, a7ddrphy_bitslip23_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip24_value0 <= (a7ddrphy_bitslip24_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip24_value0 <= 3'd7; + end + a7ddrphy_bitslip24_r0 <= {{a7ddrphy_dfi_p3_wrdata[56], a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p2_wrdata[56], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p1_wrdata[56], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p0_wrdata[56], a7ddrphy_dfi_p0_wrdata[24]}, a7ddrphy_bitslip24_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip24_value1 <= (a7ddrphy_bitslip24_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip24_value1 <= 3'd7; + end + a7ddrphy_bitslip24_r1 <= {a7ddrphy_bitslip241, a7ddrphy_bitslip24_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip25_value0 <= (a7ddrphy_bitslip25_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip25_value0 <= 3'd7; + end + a7ddrphy_bitslip25_r0 <= {{a7ddrphy_dfi_p3_wrdata[57], a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p2_wrdata[57], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p1_wrdata[57], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p0_wrdata[57], a7ddrphy_dfi_p0_wrdata[25]}, a7ddrphy_bitslip25_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip25_value1 <= (a7ddrphy_bitslip25_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip25_value1 <= 3'd7; + end + a7ddrphy_bitslip25_r1 <= {a7ddrphy_bitslip251, a7ddrphy_bitslip25_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip26_value0 <= (a7ddrphy_bitslip26_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip26_value0 <= 3'd7; + end + a7ddrphy_bitslip26_r0 <= {{a7ddrphy_dfi_p3_wrdata[58], a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p2_wrdata[58], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p1_wrdata[58], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p0_wrdata[58], a7ddrphy_dfi_p0_wrdata[26]}, a7ddrphy_bitslip26_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip26_value1 <= (a7ddrphy_bitslip26_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip26_value1 <= 3'd7; + end + a7ddrphy_bitslip26_r1 <= {a7ddrphy_bitslip261, a7ddrphy_bitslip26_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip27_value0 <= (a7ddrphy_bitslip27_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip27_value0 <= 3'd7; + end + a7ddrphy_bitslip27_r0 <= {{a7ddrphy_dfi_p3_wrdata[59], a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p2_wrdata[59], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p1_wrdata[59], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p0_wrdata[59], a7ddrphy_dfi_p0_wrdata[27]}, a7ddrphy_bitslip27_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip27_value1 <= (a7ddrphy_bitslip27_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip27_value1 <= 3'd7; + end + a7ddrphy_bitslip27_r1 <= {a7ddrphy_bitslip271, a7ddrphy_bitslip27_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip28_value0 <= (a7ddrphy_bitslip28_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip28_value0 <= 3'd7; + end + a7ddrphy_bitslip28_r0 <= {{a7ddrphy_dfi_p3_wrdata[60], a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p2_wrdata[60], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p1_wrdata[60], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p0_wrdata[60], a7ddrphy_dfi_p0_wrdata[28]}, a7ddrphy_bitslip28_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip28_value1 <= (a7ddrphy_bitslip28_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip28_value1 <= 3'd7; + end + a7ddrphy_bitslip28_r1 <= {a7ddrphy_bitslip281, a7ddrphy_bitslip28_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip29_value0 <= (a7ddrphy_bitslip29_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip29_value0 <= 3'd7; + end + a7ddrphy_bitslip29_r0 <= {{a7ddrphy_dfi_p3_wrdata[61], a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p2_wrdata[61], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p1_wrdata[61], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p0_wrdata[61], a7ddrphy_dfi_p0_wrdata[29]}, a7ddrphy_bitslip29_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip29_value1 <= (a7ddrphy_bitslip29_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip29_value1 <= 3'd7; + end + a7ddrphy_bitslip29_r1 <= {a7ddrphy_bitslip291, a7ddrphy_bitslip29_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip30_value0 <= (a7ddrphy_bitslip30_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip30_value0 <= 3'd7; + end + a7ddrphy_bitslip30_r0 <= {{a7ddrphy_dfi_p3_wrdata[62], a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p2_wrdata[62], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p1_wrdata[62], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p0_wrdata[62], a7ddrphy_dfi_p0_wrdata[30]}, a7ddrphy_bitslip30_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip30_value1 <= (a7ddrphy_bitslip30_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip30_value1 <= 3'd7; + end + a7ddrphy_bitslip30_r1 <= {a7ddrphy_bitslip301, a7ddrphy_bitslip30_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip31_value0 <= (a7ddrphy_bitslip31_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[3] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip31_value0 <= 3'd7; + end + a7ddrphy_bitslip31_r0 <= {{a7ddrphy_dfi_p3_wrdata[63], a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p2_wrdata[63], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p1_wrdata[63], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p0_wrdata[63], a7ddrphy_dfi_p0_wrdata[31]}, a7ddrphy_bitslip31_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip31_value1 <= (a7ddrphy_bitslip31_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip31_value1 <= 3'd7; + end + a7ddrphy_bitslip31_r1 <= {a7ddrphy_bitslip311, a7ddrphy_bitslip31_r1[15:8]}; + a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en); + a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0; + a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1; + a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2; + a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3; + a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4; + a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5; + a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6; + a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en); + a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0; + a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1; + if (netv2_sdram_inti_p0_rddata_valid) begin + netv2_sdram_phaseinjector0_rddata_status <= netv2_sdram_inti_p0_rddata; + end + if (netv2_sdram_inti_p1_rddata_valid) begin + netv2_sdram_phaseinjector1_rddata_status <= netv2_sdram_inti_p1_rddata; + end + if (netv2_sdram_inti_p2_rddata_valid) begin + netv2_sdram_phaseinjector2_rddata_status <= netv2_sdram_inti_p2_rddata; + end + if (netv2_sdram_inti_p3_rddata_valid) begin + netv2_sdram_phaseinjector3_rddata_status <= netv2_sdram_inti_p3_rddata; + end + if ((netv2_sdram_timer_wait & (~netv2_sdram_timer_done0))) begin + netv2_sdram_timer_count1 <= (netv2_sdram_timer_count1 - 1'd1); + end else begin + netv2_sdram_timer_count1 <= 10'd781; + end + netv2_sdram_postponer_req_o <= 1'd0; + if (netv2_sdram_postponer_req_i) begin + netv2_sdram_postponer_count <= (netv2_sdram_postponer_count - 1'd1); + if ((netv2_sdram_postponer_count == 1'd0)) begin + netv2_sdram_postponer_count <= 1'd0; + netv2_sdram_postponer_req_o <= 1'd1; + end + end + if (netv2_sdram_sequencer_start0) begin + netv2_sdram_sequencer_count <= 1'd0; + end else begin + if (netv2_sdram_sequencer_done1) begin + if ((netv2_sdram_sequencer_count != 1'd0)) begin + netv2_sdram_sequencer_count <= (netv2_sdram_sequencer_count - 1'd1); + end + end + end + netv2_sdram_cmd_payload_a <= 1'd0; + netv2_sdram_cmd_payload_ba <= 1'd0; + netv2_sdram_cmd_payload_cas <= 1'd0; + netv2_sdram_cmd_payload_ras <= 1'd0; + netv2_sdram_cmd_payload_we <= 1'd0; + netv2_sdram_sequencer_done1 <= 1'd0; + if ((netv2_sdram_sequencer_start1 & (netv2_sdram_sequencer_counter == 1'd0))) begin + netv2_sdram_cmd_payload_a <= 11'd1024; + netv2_sdram_cmd_payload_ba <= 1'd0; + netv2_sdram_cmd_payload_cas <= 1'd0; + netv2_sdram_cmd_payload_ras <= 1'd1; + netv2_sdram_cmd_payload_we <= 1'd1; + end + if ((netv2_sdram_sequencer_counter == 2'd3)) begin + netv2_sdram_cmd_payload_a <= 1'd0; + netv2_sdram_cmd_payload_ba <= 1'd0; + netv2_sdram_cmd_payload_cas <= 1'd1; + netv2_sdram_cmd_payload_ras <= 1'd1; + netv2_sdram_cmd_payload_we <= 1'd0; + end + if ((netv2_sdram_sequencer_counter == 6'd55)) begin + netv2_sdram_cmd_payload_a <= 1'd0; + netv2_sdram_cmd_payload_ba <= 1'd0; + netv2_sdram_cmd_payload_cas <= 1'd0; + netv2_sdram_cmd_payload_ras <= 1'd0; + netv2_sdram_cmd_payload_we <= 1'd0; + netv2_sdram_sequencer_done1 <= 1'd1; + end + if ((netv2_sdram_sequencer_counter == 6'd55)) begin + netv2_sdram_sequencer_counter <= 1'd0; + end else begin + if ((netv2_sdram_sequencer_counter != 1'd0)) begin + netv2_sdram_sequencer_counter <= (netv2_sdram_sequencer_counter + 1'd1); + end else begin + if (netv2_sdram_sequencer_start1) begin + netv2_sdram_sequencer_counter <= 1'd1; + end + end + end + if ((netv2_sdram_zqcs_timer_wait & (~netv2_sdram_zqcs_timer_done0))) begin + netv2_sdram_zqcs_timer_count1 <= (netv2_sdram_zqcs_timer_count1 - 1'd1); + end else begin + netv2_sdram_zqcs_timer_count1 <= 27'd99999999; + end + netv2_sdram_zqcs_executer_done <= 1'd0; + if ((netv2_sdram_zqcs_executer_start & (netv2_sdram_zqcs_executer_counter == 1'd0))) begin + netv2_sdram_cmd_payload_a <= 11'd1024; + netv2_sdram_cmd_payload_ba <= 1'd0; + netv2_sdram_cmd_payload_cas <= 1'd0; + netv2_sdram_cmd_payload_ras <= 1'd1; + netv2_sdram_cmd_payload_we <= 1'd1; + end + if ((netv2_sdram_zqcs_executer_counter == 2'd3)) begin + netv2_sdram_cmd_payload_a <= 1'd0; + netv2_sdram_cmd_payload_ba <= 1'd0; + netv2_sdram_cmd_payload_cas <= 1'd0; + netv2_sdram_cmd_payload_ras <= 1'd0; + netv2_sdram_cmd_payload_we <= 1'd1; + end + if ((netv2_sdram_zqcs_executer_counter == 5'd19)) begin + netv2_sdram_cmd_payload_a <= 1'd0; + netv2_sdram_cmd_payload_ba <= 1'd0; + netv2_sdram_cmd_payload_cas <= 1'd0; + netv2_sdram_cmd_payload_ras <= 1'd0; + netv2_sdram_cmd_payload_we <= 1'd0; + netv2_sdram_zqcs_executer_done <= 1'd1; + end + if ((netv2_sdram_zqcs_executer_counter == 5'd19)) begin + netv2_sdram_zqcs_executer_counter <= 1'd0; + end else begin + if ((netv2_sdram_zqcs_executer_counter != 1'd0)) begin + netv2_sdram_zqcs_executer_counter <= (netv2_sdram_zqcs_executer_counter + 1'd1); + end else begin + if (netv2_sdram_zqcs_executer_start) begin + netv2_sdram_zqcs_executer_counter <= 1'd1; + end + end + end + litedramcore_refresher_state <= litedramcore_refresher_next_state; + if (netv2_sdram_bankmachine0_row_close) begin + netv2_sdram_bankmachine0_row_opened <= 1'd0; + end else begin + if (netv2_sdram_bankmachine0_row_open) begin + netv2_sdram_bankmachine0_row_opened <= 1'd1; + netv2_sdram_bankmachine0_row <= netv2_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~netv2_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin + netv2_sdram_bankmachine0_cmd_buffer_lookahead_produce <= (netv2_sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); + end + if (netv2_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin + netv2_sdram_bankmachine0_cmd_buffer_lookahead_consume <= (netv2_sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); + end + if (((netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & netv2_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~netv2_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin + if ((~netv2_sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin + netv2_sdram_bankmachine0_cmd_buffer_lookahead_level <= (netv2_sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (netv2_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin + netv2_sdram_bankmachine0_cmd_buffer_lookahead_level <= (netv2_sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~netv2_sdram_bankmachine0_cmd_buffer_source_valid) | netv2_sdram_bankmachine0_cmd_buffer_source_ready)) begin + netv2_sdram_bankmachine0_cmd_buffer_source_valid <= netv2_sdram_bankmachine0_cmd_buffer_sink_valid; + netv2_sdram_bankmachine0_cmd_buffer_source_first <= netv2_sdram_bankmachine0_cmd_buffer_sink_first; + netv2_sdram_bankmachine0_cmd_buffer_source_last <= netv2_sdram_bankmachine0_cmd_buffer_sink_last; + netv2_sdram_bankmachine0_cmd_buffer_source_payload_we <= netv2_sdram_bankmachine0_cmd_buffer_sink_payload_we; + netv2_sdram_bankmachine0_cmd_buffer_source_payload_addr <= netv2_sdram_bankmachine0_cmd_buffer_sink_payload_addr; + end + if (netv2_sdram_bankmachine0_twtpcon_valid) begin + netv2_sdram_bankmachine0_twtpcon_count <= 3'd5; + if (1'd0) begin + netv2_sdram_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine0_twtpcon_ready)) begin + netv2_sdram_bankmachine0_twtpcon_count <= (netv2_sdram_bankmachine0_twtpcon_count - 1'd1); + if ((netv2_sdram_bankmachine0_twtpcon_count == 1'd1)) begin + netv2_sdram_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + if (netv2_sdram_bankmachine0_trccon_valid) begin + netv2_sdram_bankmachine0_trccon_count <= 3'd5; + if (1'd0) begin + netv2_sdram_bankmachine0_trccon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine0_trccon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine0_trccon_ready)) begin + netv2_sdram_bankmachine0_trccon_count <= (netv2_sdram_bankmachine0_trccon_count - 1'd1); + if ((netv2_sdram_bankmachine0_trccon_count == 1'd1)) begin + netv2_sdram_bankmachine0_trccon_ready <= 1'd1; + end + end + end + if (netv2_sdram_bankmachine0_trascon_valid) begin + netv2_sdram_bankmachine0_trascon_count <= 3'd4; + if (1'd0) begin + netv2_sdram_bankmachine0_trascon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine0_trascon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine0_trascon_ready)) begin + netv2_sdram_bankmachine0_trascon_count <= (netv2_sdram_bankmachine0_trascon_count - 1'd1); + if ((netv2_sdram_bankmachine0_trascon_count == 1'd1)) begin + netv2_sdram_bankmachine0_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; + if (netv2_sdram_bankmachine1_row_close) begin + netv2_sdram_bankmachine1_row_opened <= 1'd0; + end else begin + if (netv2_sdram_bankmachine1_row_open) begin + netv2_sdram_bankmachine1_row_opened <= 1'd1; + netv2_sdram_bankmachine1_row <= netv2_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~netv2_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin + netv2_sdram_bankmachine1_cmd_buffer_lookahead_produce <= (netv2_sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); + end + if (netv2_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin + netv2_sdram_bankmachine1_cmd_buffer_lookahead_consume <= (netv2_sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); + end + if (((netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & netv2_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~netv2_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin + if ((~netv2_sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin + netv2_sdram_bankmachine1_cmd_buffer_lookahead_level <= (netv2_sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (netv2_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin + netv2_sdram_bankmachine1_cmd_buffer_lookahead_level <= (netv2_sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~netv2_sdram_bankmachine1_cmd_buffer_source_valid) | netv2_sdram_bankmachine1_cmd_buffer_source_ready)) begin + netv2_sdram_bankmachine1_cmd_buffer_source_valid <= netv2_sdram_bankmachine1_cmd_buffer_sink_valid; + netv2_sdram_bankmachine1_cmd_buffer_source_first <= netv2_sdram_bankmachine1_cmd_buffer_sink_first; + netv2_sdram_bankmachine1_cmd_buffer_source_last <= netv2_sdram_bankmachine1_cmd_buffer_sink_last; + netv2_sdram_bankmachine1_cmd_buffer_source_payload_we <= netv2_sdram_bankmachine1_cmd_buffer_sink_payload_we; + netv2_sdram_bankmachine1_cmd_buffer_source_payload_addr <= netv2_sdram_bankmachine1_cmd_buffer_sink_payload_addr; + end + if (netv2_sdram_bankmachine1_twtpcon_valid) begin + netv2_sdram_bankmachine1_twtpcon_count <= 3'd5; + if (1'd0) begin + netv2_sdram_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine1_twtpcon_ready)) begin + netv2_sdram_bankmachine1_twtpcon_count <= (netv2_sdram_bankmachine1_twtpcon_count - 1'd1); + if ((netv2_sdram_bankmachine1_twtpcon_count == 1'd1)) begin + netv2_sdram_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + if (netv2_sdram_bankmachine1_trccon_valid) begin + netv2_sdram_bankmachine1_trccon_count <= 3'd5; + if (1'd0) begin + netv2_sdram_bankmachine1_trccon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine1_trccon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine1_trccon_ready)) begin + netv2_sdram_bankmachine1_trccon_count <= (netv2_sdram_bankmachine1_trccon_count - 1'd1); + if ((netv2_sdram_bankmachine1_trccon_count == 1'd1)) begin + netv2_sdram_bankmachine1_trccon_ready <= 1'd1; + end + end + end + if (netv2_sdram_bankmachine1_trascon_valid) begin + netv2_sdram_bankmachine1_trascon_count <= 3'd4; + if (1'd0) begin + netv2_sdram_bankmachine1_trascon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine1_trascon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine1_trascon_ready)) begin + netv2_sdram_bankmachine1_trascon_count <= (netv2_sdram_bankmachine1_trascon_count - 1'd1); + if ((netv2_sdram_bankmachine1_trascon_count == 1'd1)) begin + netv2_sdram_bankmachine1_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; + if (netv2_sdram_bankmachine2_row_close) begin + netv2_sdram_bankmachine2_row_opened <= 1'd0; + end else begin + if (netv2_sdram_bankmachine2_row_open) begin + netv2_sdram_bankmachine2_row_opened <= 1'd1; + netv2_sdram_bankmachine2_row <= netv2_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~netv2_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin + netv2_sdram_bankmachine2_cmd_buffer_lookahead_produce <= (netv2_sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); + end + if (netv2_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin + netv2_sdram_bankmachine2_cmd_buffer_lookahead_consume <= (netv2_sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); + end + if (((netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & netv2_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~netv2_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin + if ((~netv2_sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin + netv2_sdram_bankmachine2_cmd_buffer_lookahead_level <= (netv2_sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (netv2_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin + netv2_sdram_bankmachine2_cmd_buffer_lookahead_level <= (netv2_sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~netv2_sdram_bankmachine2_cmd_buffer_source_valid) | netv2_sdram_bankmachine2_cmd_buffer_source_ready)) begin + netv2_sdram_bankmachine2_cmd_buffer_source_valid <= netv2_sdram_bankmachine2_cmd_buffer_sink_valid; + netv2_sdram_bankmachine2_cmd_buffer_source_first <= netv2_sdram_bankmachine2_cmd_buffer_sink_first; + netv2_sdram_bankmachine2_cmd_buffer_source_last <= netv2_sdram_bankmachine2_cmd_buffer_sink_last; + netv2_sdram_bankmachine2_cmd_buffer_source_payload_we <= netv2_sdram_bankmachine2_cmd_buffer_sink_payload_we; + netv2_sdram_bankmachine2_cmd_buffer_source_payload_addr <= netv2_sdram_bankmachine2_cmd_buffer_sink_payload_addr; + end + if (netv2_sdram_bankmachine2_twtpcon_valid) begin + netv2_sdram_bankmachine2_twtpcon_count <= 3'd5; + if (1'd0) begin + netv2_sdram_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine2_twtpcon_ready)) begin + netv2_sdram_bankmachine2_twtpcon_count <= (netv2_sdram_bankmachine2_twtpcon_count - 1'd1); + if ((netv2_sdram_bankmachine2_twtpcon_count == 1'd1)) begin + netv2_sdram_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + if (netv2_sdram_bankmachine2_trccon_valid) begin + netv2_sdram_bankmachine2_trccon_count <= 3'd5; + if (1'd0) begin + netv2_sdram_bankmachine2_trccon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine2_trccon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine2_trccon_ready)) begin + netv2_sdram_bankmachine2_trccon_count <= (netv2_sdram_bankmachine2_trccon_count - 1'd1); + if ((netv2_sdram_bankmachine2_trccon_count == 1'd1)) begin + netv2_sdram_bankmachine2_trccon_ready <= 1'd1; + end + end + end + if (netv2_sdram_bankmachine2_trascon_valid) begin + netv2_sdram_bankmachine2_trascon_count <= 3'd4; + if (1'd0) begin + netv2_sdram_bankmachine2_trascon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine2_trascon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine2_trascon_ready)) begin + netv2_sdram_bankmachine2_trascon_count <= (netv2_sdram_bankmachine2_trascon_count - 1'd1); + if ((netv2_sdram_bankmachine2_trascon_count == 1'd1)) begin + netv2_sdram_bankmachine2_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; + if (netv2_sdram_bankmachine3_row_close) begin + netv2_sdram_bankmachine3_row_opened <= 1'd0; + end else begin + if (netv2_sdram_bankmachine3_row_open) begin + netv2_sdram_bankmachine3_row_opened <= 1'd1; + netv2_sdram_bankmachine3_row <= netv2_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~netv2_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin + netv2_sdram_bankmachine3_cmd_buffer_lookahead_produce <= (netv2_sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); + end + if (netv2_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin + netv2_sdram_bankmachine3_cmd_buffer_lookahead_consume <= (netv2_sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); + end + if (((netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & netv2_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~netv2_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin + if ((~netv2_sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin + netv2_sdram_bankmachine3_cmd_buffer_lookahead_level <= (netv2_sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (netv2_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin + netv2_sdram_bankmachine3_cmd_buffer_lookahead_level <= (netv2_sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~netv2_sdram_bankmachine3_cmd_buffer_source_valid) | netv2_sdram_bankmachine3_cmd_buffer_source_ready)) begin + netv2_sdram_bankmachine3_cmd_buffer_source_valid <= netv2_sdram_bankmachine3_cmd_buffer_sink_valid; + netv2_sdram_bankmachine3_cmd_buffer_source_first <= netv2_sdram_bankmachine3_cmd_buffer_sink_first; + netv2_sdram_bankmachine3_cmd_buffer_source_last <= netv2_sdram_bankmachine3_cmd_buffer_sink_last; + netv2_sdram_bankmachine3_cmd_buffer_source_payload_we <= netv2_sdram_bankmachine3_cmd_buffer_sink_payload_we; + netv2_sdram_bankmachine3_cmd_buffer_source_payload_addr <= netv2_sdram_bankmachine3_cmd_buffer_sink_payload_addr; + end + if (netv2_sdram_bankmachine3_twtpcon_valid) begin + netv2_sdram_bankmachine3_twtpcon_count <= 3'd5; + if (1'd0) begin + netv2_sdram_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine3_twtpcon_ready)) begin + netv2_sdram_bankmachine3_twtpcon_count <= (netv2_sdram_bankmachine3_twtpcon_count - 1'd1); + if ((netv2_sdram_bankmachine3_twtpcon_count == 1'd1)) begin + netv2_sdram_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + if (netv2_sdram_bankmachine3_trccon_valid) begin + netv2_sdram_bankmachine3_trccon_count <= 3'd5; + if (1'd0) begin + netv2_sdram_bankmachine3_trccon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine3_trccon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine3_trccon_ready)) begin + netv2_sdram_bankmachine3_trccon_count <= (netv2_sdram_bankmachine3_trccon_count - 1'd1); + if ((netv2_sdram_bankmachine3_trccon_count == 1'd1)) begin + netv2_sdram_bankmachine3_trccon_ready <= 1'd1; + end + end + end + if (netv2_sdram_bankmachine3_trascon_valid) begin + netv2_sdram_bankmachine3_trascon_count <= 3'd4; + if (1'd0) begin + netv2_sdram_bankmachine3_trascon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine3_trascon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine3_trascon_ready)) begin + netv2_sdram_bankmachine3_trascon_count <= (netv2_sdram_bankmachine3_trascon_count - 1'd1); + if ((netv2_sdram_bankmachine3_trascon_count == 1'd1)) begin + netv2_sdram_bankmachine3_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; + if (netv2_sdram_bankmachine4_row_close) begin + netv2_sdram_bankmachine4_row_opened <= 1'd0; + end else begin + if (netv2_sdram_bankmachine4_row_open) begin + netv2_sdram_bankmachine4_row_opened <= 1'd1; + netv2_sdram_bankmachine4_row <= netv2_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~netv2_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin + netv2_sdram_bankmachine4_cmd_buffer_lookahead_produce <= (netv2_sdram_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); + end + if (netv2_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin + netv2_sdram_bankmachine4_cmd_buffer_lookahead_consume <= (netv2_sdram_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); + end + if (((netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & netv2_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~netv2_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin + if ((~netv2_sdram_bankmachine4_cmd_buffer_lookahead_do_read)) begin + netv2_sdram_bankmachine4_cmd_buffer_lookahead_level <= (netv2_sdram_bankmachine4_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (netv2_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin + netv2_sdram_bankmachine4_cmd_buffer_lookahead_level <= (netv2_sdram_bankmachine4_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~netv2_sdram_bankmachine4_cmd_buffer_source_valid) | netv2_sdram_bankmachine4_cmd_buffer_source_ready)) begin + netv2_sdram_bankmachine4_cmd_buffer_source_valid <= netv2_sdram_bankmachine4_cmd_buffer_sink_valid; + netv2_sdram_bankmachine4_cmd_buffer_source_first <= netv2_sdram_bankmachine4_cmd_buffer_sink_first; + netv2_sdram_bankmachine4_cmd_buffer_source_last <= netv2_sdram_bankmachine4_cmd_buffer_sink_last; + netv2_sdram_bankmachine4_cmd_buffer_source_payload_we <= netv2_sdram_bankmachine4_cmd_buffer_sink_payload_we; + netv2_sdram_bankmachine4_cmd_buffer_source_payload_addr <= netv2_sdram_bankmachine4_cmd_buffer_sink_payload_addr; + end + if (netv2_sdram_bankmachine4_twtpcon_valid) begin + netv2_sdram_bankmachine4_twtpcon_count <= 3'd5; + if (1'd0) begin + netv2_sdram_bankmachine4_twtpcon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine4_twtpcon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine4_twtpcon_ready)) begin + netv2_sdram_bankmachine4_twtpcon_count <= (netv2_sdram_bankmachine4_twtpcon_count - 1'd1); + if ((netv2_sdram_bankmachine4_twtpcon_count == 1'd1)) begin + netv2_sdram_bankmachine4_twtpcon_ready <= 1'd1; + end + end + end + if (netv2_sdram_bankmachine4_trccon_valid) begin + netv2_sdram_bankmachine4_trccon_count <= 3'd5; + if (1'd0) begin + netv2_sdram_bankmachine4_trccon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine4_trccon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine4_trccon_ready)) begin + netv2_sdram_bankmachine4_trccon_count <= (netv2_sdram_bankmachine4_trccon_count - 1'd1); + if ((netv2_sdram_bankmachine4_trccon_count == 1'd1)) begin + netv2_sdram_bankmachine4_trccon_ready <= 1'd1; + end + end + end + if (netv2_sdram_bankmachine4_trascon_valid) begin + netv2_sdram_bankmachine4_trascon_count <= 3'd4; + if (1'd0) begin + netv2_sdram_bankmachine4_trascon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine4_trascon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine4_trascon_ready)) begin + netv2_sdram_bankmachine4_trascon_count <= (netv2_sdram_bankmachine4_trascon_count - 1'd1); + if ((netv2_sdram_bankmachine4_trascon_count == 1'd1)) begin + netv2_sdram_bankmachine4_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; + if (netv2_sdram_bankmachine5_row_close) begin + netv2_sdram_bankmachine5_row_opened <= 1'd0; + end else begin + if (netv2_sdram_bankmachine5_row_open) begin + netv2_sdram_bankmachine5_row_opened <= 1'd1; + netv2_sdram_bankmachine5_row <= netv2_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~netv2_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin + netv2_sdram_bankmachine5_cmd_buffer_lookahead_produce <= (netv2_sdram_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); + end + if (netv2_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin + netv2_sdram_bankmachine5_cmd_buffer_lookahead_consume <= (netv2_sdram_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); + end + if (((netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & netv2_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~netv2_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin + if ((~netv2_sdram_bankmachine5_cmd_buffer_lookahead_do_read)) begin + netv2_sdram_bankmachine5_cmd_buffer_lookahead_level <= (netv2_sdram_bankmachine5_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (netv2_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin + netv2_sdram_bankmachine5_cmd_buffer_lookahead_level <= (netv2_sdram_bankmachine5_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~netv2_sdram_bankmachine5_cmd_buffer_source_valid) | netv2_sdram_bankmachine5_cmd_buffer_source_ready)) begin + netv2_sdram_bankmachine5_cmd_buffer_source_valid <= netv2_sdram_bankmachine5_cmd_buffer_sink_valid; + netv2_sdram_bankmachine5_cmd_buffer_source_first <= netv2_sdram_bankmachine5_cmd_buffer_sink_first; + netv2_sdram_bankmachine5_cmd_buffer_source_last <= netv2_sdram_bankmachine5_cmd_buffer_sink_last; + netv2_sdram_bankmachine5_cmd_buffer_source_payload_we <= netv2_sdram_bankmachine5_cmd_buffer_sink_payload_we; + netv2_sdram_bankmachine5_cmd_buffer_source_payload_addr <= netv2_sdram_bankmachine5_cmd_buffer_sink_payload_addr; + end + if (netv2_sdram_bankmachine5_twtpcon_valid) begin + netv2_sdram_bankmachine5_twtpcon_count <= 3'd5; + if (1'd0) begin + netv2_sdram_bankmachine5_twtpcon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine5_twtpcon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine5_twtpcon_ready)) begin + netv2_sdram_bankmachine5_twtpcon_count <= (netv2_sdram_bankmachine5_twtpcon_count - 1'd1); + if ((netv2_sdram_bankmachine5_twtpcon_count == 1'd1)) begin + netv2_sdram_bankmachine5_twtpcon_ready <= 1'd1; + end + end + end + if (netv2_sdram_bankmachine5_trccon_valid) begin + netv2_sdram_bankmachine5_trccon_count <= 3'd5; + if (1'd0) begin + netv2_sdram_bankmachine5_trccon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine5_trccon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine5_trccon_ready)) begin + netv2_sdram_bankmachine5_trccon_count <= (netv2_sdram_bankmachine5_trccon_count - 1'd1); + if ((netv2_sdram_bankmachine5_trccon_count == 1'd1)) begin + netv2_sdram_bankmachine5_trccon_ready <= 1'd1; + end + end + end + if (netv2_sdram_bankmachine5_trascon_valid) begin + netv2_sdram_bankmachine5_trascon_count <= 3'd4; + if (1'd0) begin + netv2_sdram_bankmachine5_trascon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine5_trascon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine5_trascon_ready)) begin + netv2_sdram_bankmachine5_trascon_count <= (netv2_sdram_bankmachine5_trascon_count - 1'd1); + if ((netv2_sdram_bankmachine5_trascon_count == 1'd1)) begin + netv2_sdram_bankmachine5_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; + if (netv2_sdram_bankmachine6_row_close) begin + netv2_sdram_bankmachine6_row_opened <= 1'd0; + end else begin + if (netv2_sdram_bankmachine6_row_open) begin + netv2_sdram_bankmachine6_row_opened <= 1'd1; + netv2_sdram_bankmachine6_row <= netv2_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~netv2_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin + netv2_sdram_bankmachine6_cmd_buffer_lookahead_produce <= (netv2_sdram_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); + end + if (netv2_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin + netv2_sdram_bankmachine6_cmd_buffer_lookahead_consume <= (netv2_sdram_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); + end + if (((netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & netv2_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~netv2_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin + if ((~netv2_sdram_bankmachine6_cmd_buffer_lookahead_do_read)) begin + netv2_sdram_bankmachine6_cmd_buffer_lookahead_level <= (netv2_sdram_bankmachine6_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (netv2_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin + netv2_sdram_bankmachine6_cmd_buffer_lookahead_level <= (netv2_sdram_bankmachine6_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~netv2_sdram_bankmachine6_cmd_buffer_source_valid) | netv2_sdram_bankmachine6_cmd_buffer_source_ready)) begin + netv2_sdram_bankmachine6_cmd_buffer_source_valid <= netv2_sdram_bankmachine6_cmd_buffer_sink_valid; + netv2_sdram_bankmachine6_cmd_buffer_source_first <= netv2_sdram_bankmachine6_cmd_buffer_sink_first; + netv2_sdram_bankmachine6_cmd_buffer_source_last <= netv2_sdram_bankmachine6_cmd_buffer_sink_last; + netv2_sdram_bankmachine6_cmd_buffer_source_payload_we <= netv2_sdram_bankmachine6_cmd_buffer_sink_payload_we; + netv2_sdram_bankmachine6_cmd_buffer_source_payload_addr <= netv2_sdram_bankmachine6_cmd_buffer_sink_payload_addr; + end + if (netv2_sdram_bankmachine6_twtpcon_valid) begin + netv2_sdram_bankmachine6_twtpcon_count <= 3'd5; + if (1'd0) begin + netv2_sdram_bankmachine6_twtpcon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine6_twtpcon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine6_twtpcon_ready)) begin + netv2_sdram_bankmachine6_twtpcon_count <= (netv2_sdram_bankmachine6_twtpcon_count - 1'd1); + if ((netv2_sdram_bankmachine6_twtpcon_count == 1'd1)) begin + netv2_sdram_bankmachine6_twtpcon_ready <= 1'd1; + end + end + end + if (netv2_sdram_bankmachine6_trccon_valid) begin + netv2_sdram_bankmachine6_trccon_count <= 3'd5; + if (1'd0) begin + netv2_sdram_bankmachine6_trccon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine6_trccon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine6_trccon_ready)) begin + netv2_sdram_bankmachine6_trccon_count <= (netv2_sdram_bankmachine6_trccon_count - 1'd1); + if ((netv2_sdram_bankmachine6_trccon_count == 1'd1)) begin + netv2_sdram_bankmachine6_trccon_ready <= 1'd1; + end + end + end + if (netv2_sdram_bankmachine6_trascon_valid) begin + netv2_sdram_bankmachine6_trascon_count <= 3'd4; + if (1'd0) begin + netv2_sdram_bankmachine6_trascon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine6_trascon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine6_trascon_ready)) begin + netv2_sdram_bankmachine6_trascon_count <= (netv2_sdram_bankmachine6_trascon_count - 1'd1); + if ((netv2_sdram_bankmachine6_trascon_count == 1'd1)) begin + netv2_sdram_bankmachine6_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; + if (netv2_sdram_bankmachine7_row_close) begin + netv2_sdram_bankmachine7_row_opened <= 1'd0; + end else begin + if (netv2_sdram_bankmachine7_row_open) begin + netv2_sdram_bankmachine7_row_opened <= 1'd1; + netv2_sdram_bankmachine7_row <= netv2_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~netv2_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin + netv2_sdram_bankmachine7_cmd_buffer_lookahead_produce <= (netv2_sdram_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); + end + if (netv2_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin + netv2_sdram_bankmachine7_cmd_buffer_lookahead_consume <= (netv2_sdram_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); + end + if (((netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & netv2_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~netv2_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin + if ((~netv2_sdram_bankmachine7_cmd_buffer_lookahead_do_read)) begin + netv2_sdram_bankmachine7_cmd_buffer_lookahead_level <= (netv2_sdram_bankmachine7_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (netv2_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin + netv2_sdram_bankmachine7_cmd_buffer_lookahead_level <= (netv2_sdram_bankmachine7_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~netv2_sdram_bankmachine7_cmd_buffer_source_valid) | netv2_sdram_bankmachine7_cmd_buffer_source_ready)) begin + netv2_sdram_bankmachine7_cmd_buffer_source_valid <= netv2_sdram_bankmachine7_cmd_buffer_sink_valid; + netv2_sdram_bankmachine7_cmd_buffer_source_first <= netv2_sdram_bankmachine7_cmd_buffer_sink_first; + netv2_sdram_bankmachine7_cmd_buffer_source_last <= netv2_sdram_bankmachine7_cmd_buffer_sink_last; + netv2_sdram_bankmachine7_cmd_buffer_source_payload_we <= netv2_sdram_bankmachine7_cmd_buffer_sink_payload_we; + netv2_sdram_bankmachine7_cmd_buffer_source_payload_addr <= netv2_sdram_bankmachine7_cmd_buffer_sink_payload_addr; + end + if (netv2_sdram_bankmachine7_twtpcon_valid) begin + netv2_sdram_bankmachine7_twtpcon_count <= 3'd5; + if (1'd0) begin + netv2_sdram_bankmachine7_twtpcon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine7_twtpcon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine7_twtpcon_ready)) begin + netv2_sdram_bankmachine7_twtpcon_count <= (netv2_sdram_bankmachine7_twtpcon_count - 1'd1); + if ((netv2_sdram_bankmachine7_twtpcon_count == 1'd1)) begin + netv2_sdram_bankmachine7_twtpcon_ready <= 1'd1; + end + end + end + if (netv2_sdram_bankmachine7_trccon_valid) begin + netv2_sdram_bankmachine7_trccon_count <= 3'd5; + if (1'd0) begin + netv2_sdram_bankmachine7_trccon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine7_trccon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine7_trccon_ready)) begin + netv2_sdram_bankmachine7_trccon_count <= (netv2_sdram_bankmachine7_trccon_count - 1'd1); + if ((netv2_sdram_bankmachine7_trccon_count == 1'd1)) begin + netv2_sdram_bankmachine7_trccon_ready <= 1'd1; + end + end + end + if (netv2_sdram_bankmachine7_trascon_valid) begin + netv2_sdram_bankmachine7_trascon_count <= 3'd4; + if (1'd0) begin + netv2_sdram_bankmachine7_trascon_ready <= 1'd1; + end else begin + netv2_sdram_bankmachine7_trascon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_bankmachine7_trascon_ready)) begin + netv2_sdram_bankmachine7_trascon_count <= (netv2_sdram_bankmachine7_trascon_count - 1'd1); + if ((netv2_sdram_bankmachine7_trascon_count == 1'd1)) begin + netv2_sdram_bankmachine7_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; + if ((~netv2_sdram_en0)) begin + netv2_sdram_time0 <= 5'd31; + end else begin + if ((~netv2_sdram_max_time0)) begin + netv2_sdram_time0 <= (netv2_sdram_time0 - 1'd1); + end + end + if ((~netv2_sdram_en1)) begin + netv2_sdram_time1 <= 4'd15; + end else begin + if ((~netv2_sdram_max_time1)) begin + netv2_sdram_time1 <= (netv2_sdram_time1 - 1'd1); + end + end + if (netv2_sdram_choose_cmd_ce) begin + case (netv2_sdram_choose_cmd_grant) + 1'd0: begin + if (netv2_sdram_choose_cmd_request[1]) begin + netv2_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (netv2_sdram_choose_cmd_request[2]) begin + netv2_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (netv2_sdram_choose_cmd_request[3]) begin + netv2_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (netv2_sdram_choose_cmd_request[4]) begin + netv2_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (netv2_sdram_choose_cmd_request[5]) begin + netv2_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (netv2_sdram_choose_cmd_request[6]) begin + netv2_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (netv2_sdram_choose_cmd_request[7]) begin + netv2_sdram_choose_cmd_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (netv2_sdram_choose_cmd_request[2]) begin + netv2_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (netv2_sdram_choose_cmd_request[3]) begin + netv2_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (netv2_sdram_choose_cmd_request[4]) begin + netv2_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (netv2_sdram_choose_cmd_request[5]) begin + netv2_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (netv2_sdram_choose_cmd_request[6]) begin + netv2_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (netv2_sdram_choose_cmd_request[7]) begin + netv2_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (netv2_sdram_choose_cmd_request[0]) begin + netv2_sdram_choose_cmd_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (netv2_sdram_choose_cmd_request[3]) begin + netv2_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (netv2_sdram_choose_cmd_request[4]) begin + netv2_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (netv2_sdram_choose_cmd_request[5]) begin + netv2_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (netv2_sdram_choose_cmd_request[6]) begin + netv2_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (netv2_sdram_choose_cmd_request[7]) begin + netv2_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (netv2_sdram_choose_cmd_request[0]) begin + netv2_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (netv2_sdram_choose_cmd_request[1]) begin + netv2_sdram_choose_cmd_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (netv2_sdram_choose_cmd_request[4]) begin + netv2_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (netv2_sdram_choose_cmd_request[5]) begin + netv2_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (netv2_sdram_choose_cmd_request[6]) begin + netv2_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (netv2_sdram_choose_cmd_request[7]) begin + netv2_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (netv2_sdram_choose_cmd_request[0]) begin + netv2_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (netv2_sdram_choose_cmd_request[1]) begin + netv2_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (netv2_sdram_choose_cmd_request[2]) begin + netv2_sdram_choose_cmd_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (netv2_sdram_choose_cmd_request[5]) begin + netv2_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (netv2_sdram_choose_cmd_request[6]) begin + netv2_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (netv2_sdram_choose_cmd_request[7]) begin + netv2_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (netv2_sdram_choose_cmd_request[0]) begin + netv2_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (netv2_sdram_choose_cmd_request[1]) begin + netv2_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (netv2_sdram_choose_cmd_request[2]) begin + netv2_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (netv2_sdram_choose_cmd_request[3]) begin + netv2_sdram_choose_cmd_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (netv2_sdram_choose_cmd_request[6]) begin + netv2_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (netv2_sdram_choose_cmd_request[7]) begin + netv2_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (netv2_sdram_choose_cmd_request[0]) begin + netv2_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (netv2_sdram_choose_cmd_request[1]) begin + netv2_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (netv2_sdram_choose_cmd_request[2]) begin + netv2_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (netv2_sdram_choose_cmd_request[3]) begin + netv2_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (netv2_sdram_choose_cmd_request[4]) begin + netv2_sdram_choose_cmd_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (netv2_sdram_choose_cmd_request[7]) begin + netv2_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (netv2_sdram_choose_cmd_request[0]) begin + netv2_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (netv2_sdram_choose_cmd_request[1]) begin + netv2_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (netv2_sdram_choose_cmd_request[2]) begin + netv2_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (netv2_sdram_choose_cmd_request[3]) begin + netv2_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (netv2_sdram_choose_cmd_request[4]) begin + netv2_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (netv2_sdram_choose_cmd_request[5]) begin + netv2_sdram_choose_cmd_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (netv2_sdram_choose_cmd_request[0]) begin + netv2_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (netv2_sdram_choose_cmd_request[1]) begin + netv2_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (netv2_sdram_choose_cmd_request[2]) begin + netv2_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (netv2_sdram_choose_cmd_request[3]) begin + netv2_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (netv2_sdram_choose_cmd_request[4]) begin + netv2_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (netv2_sdram_choose_cmd_request[5]) begin + netv2_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (netv2_sdram_choose_cmd_request[6]) begin + netv2_sdram_choose_cmd_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + if (netv2_sdram_choose_req_ce) begin + case (netv2_sdram_choose_req_grant) + 1'd0: begin + if (netv2_sdram_choose_req_request[1]) begin + netv2_sdram_choose_req_grant <= 1'd1; + end else begin + if (netv2_sdram_choose_req_request[2]) begin + netv2_sdram_choose_req_grant <= 2'd2; + end else begin + if (netv2_sdram_choose_req_request[3]) begin + netv2_sdram_choose_req_grant <= 2'd3; + end else begin + if (netv2_sdram_choose_req_request[4]) begin + netv2_sdram_choose_req_grant <= 3'd4; + end else begin + if (netv2_sdram_choose_req_request[5]) begin + netv2_sdram_choose_req_grant <= 3'd5; + end else begin + if (netv2_sdram_choose_req_request[6]) begin + netv2_sdram_choose_req_grant <= 3'd6; + end else begin + if (netv2_sdram_choose_req_request[7]) begin + netv2_sdram_choose_req_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (netv2_sdram_choose_req_request[2]) begin + netv2_sdram_choose_req_grant <= 2'd2; + end else begin + if (netv2_sdram_choose_req_request[3]) begin + netv2_sdram_choose_req_grant <= 2'd3; + end else begin + if (netv2_sdram_choose_req_request[4]) begin + netv2_sdram_choose_req_grant <= 3'd4; + end else begin + if (netv2_sdram_choose_req_request[5]) begin + netv2_sdram_choose_req_grant <= 3'd5; + end else begin + if (netv2_sdram_choose_req_request[6]) begin + netv2_sdram_choose_req_grant <= 3'd6; + end else begin + if (netv2_sdram_choose_req_request[7]) begin + netv2_sdram_choose_req_grant <= 3'd7; + end else begin + if (netv2_sdram_choose_req_request[0]) begin + netv2_sdram_choose_req_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (netv2_sdram_choose_req_request[3]) begin + netv2_sdram_choose_req_grant <= 2'd3; + end else begin + if (netv2_sdram_choose_req_request[4]) begin + netv2_sdram_choose_req_grant <= 3'd4; + end else begin + if (netv2_sdram_choose_req_request[5]) begin + netv2_sdram_choose_req_grant <= 3'd5; + end else begin + if (netv2_sdram_choose_req_request[6]) begin + netv2_sdram_choose_req_grant <= 3'd6; + end else begin + if (netv2_sdram_choose_req_request[7]) begin + netv2_sdram_choose_req_grant <= 3'd7; + end else begin + if (netv2_sdram_choose_req_request[0]) begin + netv2_sdram_choose_req_grant <= 1'd0; + end else begin + if (netv2_sdram_choose_req_request[1]) begin + netv2_sdram_choose_req_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (netv2_sdram_choose_req_request[4]) begin + netv2_sdram_choose_req_grant <= 3'd4; + end else begin + if (netv2_sdram_choose_req_request[5]) begin + netv2_sdram_choose_req_grant <= 3'd5; + end else begin + if (netv2_sdram_choose_req_request[6]) begin + netv2_sdram_choose_req_grant <= 3'd6; + end else begin + if (netv2_sdram_choose_req_request[7]) begin + netv2_sdram_choose_req_grant <= 3'd7; + end else begin + if (netv2_sdram_choose_req_request[0]) begin + netv2_sdram_choose_req_grant <= 1'd0; + end else begin + if (netv2_sdram_choose_req_request[1]) begin + netv2_sdram_choose_req_grant <= 1'd1; + end else begin + if (netv2_sdram_choose_req_request[2]) begin + netv2_sdram_choose_req_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (netv2_sdram_choose_req_request[5]) begin + netv2_sdram_choose_req_grant <= 3'd5; + end else begin + if (netv2_sdram_choose_req_request[6]) begin + netv2_sdram_choose_req_grant <= 3'd6; + end else begin + if (netv2_sdram_choose_req_request[7]) begin + netv2_sdram_choose_req_grant <= 3'd7; + end else begin + if (netv2_sdram_choose_req_request[0]) begin + netv2_sdram_choose_req_grant <= 1'd0; + end else begin + if (netv2_sdram_choose_req_request[1]) begin + netv2_sdram_choose_req_grant <= 1'd1; + end else begin + if (netv2_sdram_choose_req_request[2]) begin + netv2_sdram_choose_req_grant <= 2'd2; + end else begin + if (netv2_sdram_choose_req_request[3]) begin + netv2_sdram_choose_req_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (netv2_sdram_choose_req_request[6]) begin + netv2_sdram_choose_req_grant <= 3'd6; + end else begin + if (netv2_sdram_choose_req_request[7]) begin + netv2_sdram_choose_req_grant <= 3'd7; + end else begin + if (netv2_sdram_choose_req_request[0]) begin + netv2_sdram_choose_req_grant <= 1'd0; + end else begin + if (netv2_sdram_choose_req_request[1]) begin + netv2_sdram_choose_req_grant <= 1'd1; + end else begin + if (netv2_sdram_choose_req_request[2]) begin + netv2_sdram_choose_req_grant <= 2'd2; + end else begin + if (netv2_sdram_choose_req_request[3]) begin + netv2_sdram_choose_req_grant <= 2'd3; + end else begin + if (netv2_sdram_choose_req_request[4]) begin + netv2_sdram_choose_req_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (netv2_sdram_choose_req_request[7]) begin + netv2_sdram_choose_req_grant <= 3'd7; + end else begin + if (netv2_sdram_choose_req_request[0]) begin + netv2_sdram_choose_req_grant <= 1'd0; + end else begin + if (netv2_sdram_choose_req_request[1]) begin + netv2_sdram_choose_req_grant <= 1'd1; + end else begin + if (netv2_sdram_choose_req_request[2]) begin + netv2_sdram_choose_req_grant <= 2'd2; + end else begin + if (netv2_sdram_choose_req_request[3]) begin + netv2_sdram_choose_req_grant <= 2'd3; + end else begin + if (netv2_sdram_choose_req_request[4]) begin + netv2_sdram_choose_req_grant <= 3'd4; + end else begin + if (netv2_sdram_choose_req_request[5]) begin + netv2_sdram_choose_req_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (netv2_sdram_choose_req_request[0]) begin + netv2_sdram_choose_req_grant <= 1'd0; + end else begin + if (netv2_sdram_choose_req_request[1]) begin + netv2_sdram_choose_req_grant <= 1'd1; + end else begin + if (netv2_sdram_choose_req_request[2]) begin + netv2_sdram_choose_req_grant <= 2'd2; + end else begin + if (netv2_sdram_choose_req_request[3]) begin + netv2_sdram_choose_req_grant <= 2'd3; + end else begin + if (netv2_sdram_choose_req_request[4]) begin + netv2_sdram_choose_req_grant <= 3'd4; + end else begin + if (netv2_sdram_choose_req_request[5]) begin + netv2_sdram_choose_req_grant <= 3'd5; + end else begin + if (netv2_sdram_choose_req_request[6]) begin + netv2_sdram_choose_req_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + netv2_sdram_dfi_p0_cs_n <= 1'd0; + netv2_sdram_dfi_p0_bank <= sync_array_muxed0; + netv2_sdram_dfi_p0_address <= sync_array_muxed1; + netv2_sdram_dfi_p0_cas_n <= (~sync_array_muxed2); + netv2_sdram_dfi_p0_ras_n <= (~sync_array_muxed3); + netv2_sdram_dfi_p0_we_n <= (~sync_array_muxed4); + netv2_sdram_dfi_p0_rddata_en <= sync_array_muxed5; + netv2_sdram_dfi_p0_wrdata_en <= sync_array_muxed6; + netv2_sdram_dfi_p1_cs_n <= 1'd0; + netv2_sdram_dfi_p1_bank <= sync_array_muxed7; + netv2_sdram_dfi_p1_address <= sync_array_muxed8; + netv2_sdram_dfi_p1_cas_n <= (~sync_array_muxed9); + netv2_sdram_dfi_p1_ras_n <= (~sync_array_muxed10); + netv2_sdram_dfi_p1_we_n <= (~sync_array_muxed11); + netv2_sdram_dfi_p1_rddata_en <= sync_array_muxed12; + netv2_sdram_dfi_p1_wrdata_en <= sync_array_muxed13; + netv2_sdram_dfi_p2_cs_n <= 1'd0; + netv2_sdram_dfi_p2_bank <= sync_array_muxed14; + netv2_sdram_dfi_p2_address <= sync_array_muxed15; + netv2_sdram_dfi_p2_cas_n <= (~sync_array_muxed16); + netv2_sdram_dfi_p2_ras_n <= (~sync_array_muxed17); + netv2_sdram_dfi_p2_we_n <= (~sync_array_muxed18); + netv2_sdram_dfi_p2_rddata_en <= sync_array_muxed19; + netv2_sdram_dfi_p2_wrdata_en <= sync_array_muxed20; + netv2_sdram_dfi_p3_cs_n <= 1'd0; + netv2_sdram_dfi_p3_bank <= sync_array_muxed21; + netv2_sdram_dfi_p3_address <= sync_array_muxed22; + netv2_sdram_dfi_p3_cas_n <= (~sync_array_muxed23); + netv2_sdram_dfi_p3_ras_n <= (~sync_array_muxed24); + netv2_sdram_dfi_p3_we_n <= (~sync_array_muxed25); + netv2_sdram_dfi_p3_rddata_en <= sync_array_muxed26; + netv2_sdram_dfi_p3_wrdata_en <= sync_array_muxed27; + if (netv2_sdram_trrdcon_valid) begin + netv2_sdram_trrdcon_count <= 1'd1; + if (1'd0) begin + netv2_sdram_trrdcon_ready <= 1'd1; + end else begin + netv2_sdram_trrdcon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_trrdcon_ready)) begin + netv2_sdram_trrdcon_count <= (netv2_sdram_trrdcon_count - 1'd1); + if ((netv2_sdram_trrdcon_count == 1'd1)) begin + netv2_sdram_trrdcon_ready <= 1'd1; + end + end + end + netv2_sdram_tfawcon_window <= {netv2_sdram_tfawcon_window, netv2_sdram_tfawcon_valid}; + if ((netv2_sdram_tfawcon_count < 3'd4)) begin + if ((netv2_sdram_tfawcon_count == 2'd3)) begin + netv2_sdram_tfawcon_ready <= (~netv2_sdram_tfawcon_valid); + end else begin + netv2_sdram_tfawcon_ready <= 1'd1; + end + end + if (netv2_sdram_tccdcon_valid) begin + netv2_sdram_tccdcon_count <= 1'd0; + if (1'd1) begin + netv2_sdram_tccdcon_ready <= 1'd1; + end else begin + netv2_sdram_tccdcon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_tccdcon_ready)) begin + netv2_sdram_tccdcon_count <= (netv2_sdram_tccdcon_count - 1'd1); + if ((netv2_sdram_tccdcon_count == 1'd1)) begin + netv2_sdram_tccdcon_ready <= 1'd1; + end + end + end + if (netv2_sdram_twtrcon_valid) begin + netv2_sdram_twtrcon_count <= 3'd4; + if (1'd0) begin + netv2_sdram_twtrcon_ready <= 1'd1; + end else begin + netv2_sdram_twtrcon_ready <= 1'd0; + end + end else begin + if ((~netv2_sdram_twtrcon_ready)) begin + netv2_sdram_twtrcon_count <= (netv2_sdram_twtrcon_count - 1'd1); + if ((netv2_sdram_twtrcon_count == 1'd1)) begin + netv2_sdram_twtrcon_ready <= 1'd1; + end + end + end + litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; + litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & netv2_sdram_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & netv2_sdram_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & netv2_sdram_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & netv2_sdram_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & netv2_sdram_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & netv2_sdram_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & netv2_sdram_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & netv2_sdram_interface_bank7_wdata_ready)); + litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; + litedramcore_new_master_wdata_ready2 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd1) & netv2_sdram_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd1) & netv2_sdram_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd1) & netv2_sdram_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd1) & netv2_sdram_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd1) & netv2_sdram_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd1) & netv2_sdram_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd1) & netv2_sdram_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd1) & netv2_sdram_interface_bank7_wdata_ready)); + litedramcore_new_master_wdata_ready3 <= litedramcore_new_master_wdata_ready2; + litedramcore_new_master_wdata_ready4 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 2'd2) & netv2_sdram_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 2'd2) & netv2_sdram_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 2'd2) & netv2_sdram_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 2'd2) & netv2_sdram_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 2'd2) & netv2_sdram_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 2'd2) & netv2_sdram_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 2'd2) & netv2_sdram_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 2'd2) & netv2_sdram_interface_bank7_wdata_ready)); + litedramcore_new_master_wdata_ready5 <= litedramcore_new_master_wdata_ready4; + litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & netv2_sdram_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & netv2_sdram_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & netv2_sdram_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & netv2_sdram_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & netv2_sdram_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & netv2_sdram_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & netv2_sdram_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & netv2_sdram_interface_bank7_rdata_valid)); + litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; + litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; + litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; + litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; + litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; + litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; + litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; + litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; + litedramcore_new_master_rdata_valid9 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd1) & netv2_sdram_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd1) & netv2_sdram_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd1) & netv2_sdram_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd1) & netv2_sdram_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd1) & netv2_sdram_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd1) & netv2_sdram_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd1) & netv2_sdram_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd1) & netv2_sdram_interface_bank7_rdata_valid)); + litedramcore_new_master_rdata_valid10 <= litedramcore_new_master_rdata_valid9; + litedramcore_new_master_rdata_valid11 <= litedramcore_new_master_rdata_valid10; + litedramcore_new_master_rdata_valid12 <= litedramcore_new_master_rdata_valid11; + litedramcore_new_master_rdata_valid13 <= litedramcore_new_master_rdata_valid12; + litedramcore_new_master_rdata_valid14 <= litedramcore_new_master_rdata_valid13; + litedramcore_new_master_rdata_valid15 <= litedramcore_new_master_rdata_valid14; + litedramcore_new_master_rdata_valid16 <= litedramcore_new_master_rdata_valid15; + litedramcore_new_master_rdata_valid17 <= litedramcore_new_master_rdata_valid16; + litedramcore_new_master_rdata_valid18 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 2'd2) & netv2_sdram_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 2'd2) & netv2_sdram_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 2'd2) & netv2_sdram_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 2'd2) & netv2_sdram_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 2'd2) & netv2_sdram_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 2'd2) & netv2_sdram_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 2'd2) & netv2_sdram_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 2'd2) & netv2_sdram_interface_bank7_rdata_valid)); + litedramcore_new_master_rdata_valid19 <= litedramcore_new_master_rdata_valid18; + litedramcore_new_master_rdata_valid20 <= litedramcore_new_master_rdata_valid19; + litedramcore_new_master_rdata_valid21 <= litedramcore_new_master_rdata_valid20; + litedramcore_new_master_rdata_valid22 <= litedramcore_new_master_rdata_valid21; + litedramcore_new_master_rdata_valid23 <= litedramcore_new_master_rdata_valid22; + litedramcore_new_master_rdata_valid24 <= litedramcore_new_master_rdata_valid23; + litedramcore_new_master_rdata_valid25 <= litedramcore_new_master_rdata_valid24; + litedramcore_new_master_rdata_valid26 <= litedramcore_new_master_rdata_valid25; + litedramcrossbar_cmd_cdc_cdc_graycounter1_q_binary <= litedramcrossbar_cmd_cdc_cdc_graycounter1_q_next_binary; + litedramcrossbar_cmd_cdc_cdc_graycounter1_q <= litedramcrossbar_cmd_cdc_cdc_graycounter1_q_next; + litedramcrossbar_rdata_cdc_cdc_graycounter0_q_binary <= litedramcrossbar_rdata_cdc_cdc_graycounter0_q_next_binary; + litedramcrossbar_rdata_cdc_cdc_graycounter0_q <= litedramcrossbar_rdata_cdc_cdc_graycounter0_q_next; + if (litedramcore_roundrobin0_ce) begin + case (litedramcore_roundrobin0_grant) + 1'd0: begin + if (litedramcore_roundrobin0_request[1]) begin + litedramcore_roundrobin0_grant <= 1'd1; + end else begin + if (litedramcore_roundrobin0_request[2]) begin + litedramcore_roundrobin0_grant <= 2'd2; + end + end + end + 1'd1: begin + if (litedramcore_roundrobin0_request[2]) begin + litedramcore_roundrobin0_grant <= 2'd2; + end else begin + if (litedramcore_roundrobin0_request[0]) begin + litedramcore_roundrobin0_grant <= 1'd0; + end + end + end + 2'd2: begin + if (litedramcore_roundrobin0_request[0]) begin + litedramcore_roundrobin0_grant <= 1'd0; + end else begin + if (litedramcore_roundrobin0_request[1]) begin + litedramcore_roundrobin0_grant <= 1'd1; + end + end + end + endcase + end + if (litedramcore_roundrobin1_ce) begin + case (litedramcore_roundrobin1_grant) + 1'd0: begin + if (litedramcore_roundrobin1_request[1]) begin + litedramcore_roundrobin1_grant <= 1'd1; + end else begin + if (litedramcore_roundrobin1_request[2]) begin + litedramcore_roundrobin1_grant <= 2'd2; + end + end + end + 1'd1: begin + if (litedramcore_roundrobin1_request[2]) begin + litedramcore_roundrobin1_grant <= 2'd2; + end else begin + if (litedramcore_roundrobin1_request[0]) begin + litedramcore_roundrobin1_grant <= 1'd0; + end + end + end + 2'd2: begin + if (litedramcore_roundrobin1_request[0]) begin + litedramcore_roundrobin1_grant <= 1'd0; + end else begin + if (litedramcore_roundrobin1_request[1]) begin + litedramcore_roundrobin1_grant <= 1'd1; + end + end + end + endcase + end + if (litedramcore_roundrobin2_ce) begin + case (litedramcore_roundrobin2_grant) + 1'd0: begin + if (litedramcore_roundrobin2_request[1]) begin + litedramcore_roundrobin2_grant <= 1'd1; + end else begin + if (litedramcore_roundrobin2_request[2]) begin + litedramcore_roundrobin2_grant <= 2'd2; + end + end + end + 1'd1: begin + if (litedramcore_roundrobin2_request[2]) begin + litedramcore_roundrobin2_grant <= 2'd2; + end else begin + if (litedramcore_roundrobin2_request[0]) begin + litedramcore_roundrobin2_grant <= 1'd0; + end + end + end + 2'd2: begin + if (litedramcore_roundrobin2_request[0]) begin + litedramcore_roundrobin2_grant <= 1'd0; + end else begin + if (litedramcore_roundrobin2_request[1]) begin + litedramcore_roundrobin2_grant <= 1'd1; + end + end + end + endcase + end + if (litedramcore_roundrobin3_ce) begin + case (litedramcore_roundrobin3_grant) + 1'd0: begin + if (litedramcore_roundrobin3_request[1]) begin + litedramcore_roundrobin3_grant <= 1'd1; + end else begin + if (litedramcore_roundrobin3_request[2]) begin + litedramcore_roundrobin3_grant <= 2'd2; + end + end + end + 1'd1: begin + if (litedramcore_roundrobin3_request[2]) begin + litedramcore_roundrobin3_grant <= 2'd2; + end else begin + if (litedramcore_roundrobin3_request[0]) begin + litedramcore_roundrobin3_grant <= 1'd0; + end + end + end + 2'd2: begin + if (litedramcore_roundrobin3_request[0]) begin + litedramcore_roundrobin3_grant <= 1'd0; + end else begin + if (litedramcore_roundrobin3_request[1]) begin + litedramcore_roundrobin3_grant <= 1'd1; + end + end + end + endcase + end + if (litedramcore_roundrobin4_ce) begin + case (litedramcore_roundrobin4_grant) + 1'd0: begin + if (litedramcore_roundrobin4_request[1]) begin + litedramcore_roundrobin4_grant <= 1'd1; + end else begin + if (litedramcore_roundrobin4_request[2]) begin + litedramcore_roundrobin4_grant <= 2'd2; + end + end + end + 1'd1: begin + if (litedramcore_roundrobin4_request[2]) begin + litedramcore_roundrobin4_grant <= 2'd2; + end else begin + if (litedramcore_roundrobin4_request[0]) begin + litedramcore_roundrobin4_grant <= 1'd0; + end + end + end + 2'd2: begin + if (litedramcore_roundrobin4_request[0]) begin + litedramcore_roundrobin4_grant <= 1'd0; + end else begin + if (litedramcore_roundrobin4_request[1]) begin + litedramcore_roundrobin4_grant <= 1'd1; + end + end + end + endcase + end + if (litedramcore_roundrobin5_ce) begin + case (litedramcore_roundrobin5_grant) + 1'd0: begin + if (litedramcore_roundrobin5_request[1]) begin + litedramcore_roundrobin5_grant <= 1'd1; + end else begin + if (litedramcore_roundrobin5_request[2]) begin + litedramcore_roundrobin5_grant <= 2'd2; + end + end + end + 1'd1: begin + if (litedramcore_roundrobin5_request[2]) begin + litedramcore_roundrobin5_grant <= 2'd2; + end else begin + if (litedramcore_roundrobin5_request[0]) begin + litedramcore_roundrobin5_grant <= 1'd0; + end + end + end + 2'd2: begin + if (litedramcore_roundrobin5_request[0]) begin + litedramcore_roundrobin5_grant <= 1'd0; + end else begin + if (litedramcore_roundrobin5_request[1]) begin + litedramcore_roundrobin5_grant <= 1'd1; + end + end + end + endcase + end + if (litedramcore_roundrobin6_ce) begin + case (litedramcore_roundrobin6_grant) + 1'd0: begin + if (litedramcore_roundrobin6_request[1]) begin + litedramcore_roundrobin6_grant <= 1'd1; + end else begin + if (litedramcore_roundrobin6_request[2]) begin + litedramcore_roundrobin6_grant <= 2'd2; + end + end + end + 1'd1: begin + if (litedramcore_roundrobin6_request[2]) begin + litedramcore_roundrobin6_grant <= 2'd2; + end else begin + if (litedramcore_roundrobin6_request[0]) begin + litedramcore_roundrobin6_grant <= 1'd0; + end + end + end + 2'd2: begin + if (litedramcore_roundrobin6_request[0]) begin + litedramcore_roundrobin6_grant <= 1'd0; + end else begin + if (litedramcore_roundrobin6_request[1]) begin + litedramcore_roundrobin6_grant <= 1'd1; + end + end + end + endcase + end + if (litedramcore_roundrobin7_ce) begin + case (litedramcore_roundrobin7_grant) + 1'd0: begin + if (litedramcore_roundrobin7_request[1]) begin + litedramcore_roundrobin7_grant <= 1'd1; + end else begin + if (litedramcore_roundrobin7_request[2]) begin + litedramcore_roundrobin7_grant <= 2'd2; + end + end + end + 1'd1: begin + if (litedramcore_roundrobin7_request[2]) begin + litedramcore_roundrobin7_grant <= 2'd2; + end else begin + if (litedramcore_roundrobin7_request[0]) begin + litedramcore_roundrobin7_grant <= 1'd0; + end + end + end + 2'd2: begin + if (litedramcore_roundrobin7_request[0]) begin + litedramcore_roundrobin7_grant <= 1'd0; + end else begin + if (litedramcore_roundrobin7_request[1]) begin + litedramcore_roundrobin7_grant <= 1'd1; + end + end + end + endcase + end + netv2_adr_offset_r <= netv2_wb_sdram_adr[2:0]; + fullmemorywe_state <= fullmemorywe_next_state; + if (netv2_interface_ack) begin + netv2_cmd_consumed <= 1'd0; + netv2_wdata_consumed <= 1'd0; + end else begin + if ((netv2_port_cmd_valid & netv2_port_cmd_ready)) begin + netv2_cmd_consumed <= 1'd1; + end + if ((netv2_port_wdata_valid & netv2_port_wdata_ready)) begin + netv2_wdata_consumed <= 1'd1; + end + end + if (ethphy_counter_ce) begin + ethphy_counter <= (ethphy_counter + 1'd1); + end + if (ethcore_mac_ps_preamble_error_o) begin + ethcore_mac_preamble_errors_status <= (ethcore_mac_preamble_errors_status + 1'd1); + end + if (ethcore_mac_ps_crc_error_o) begin + ethcore_mac_crc_errors_status <= (ethcore_mac_crc_errors_status + 1'd1); + end + ethcore_mac_ps_preamble_error_toggle_o_r <= ethcore_mac_ps_preamble_error_toggle_o; + ethcore_mac_ps_crc_error_toggle_o_r <= ethcore_mac_ps_crc_error_toggle_o; + ethcore_mac_tx_cdc_graycounter0_q_binary <= ethcore_mac_tx_cdc_graycounter0_q_next_binary; + ethcore_mac_tx_cdc_graycounter0_q <= ethcore_mac_tx_cdc_graycounter0_q_next; + ethcore_mac_rx_cdc_graycounter1_q_binary <= ethcore_mac_rx_cdc_graycounter1_q_next_binary; + ethcore_mac_rx_cdc_graycounter1_q <= ethcore_mac_rx_cdc_graycounter1_q_next; + case (liteethudpipcore_liteethmac_grant) + 1'd0: begin + if ((~liteethudpipcore_liteethmac_request[0])) begin + if (liteethudpipcore_liteethmac_request[1]) begin + liteethudpipcore_liteethmac_grant <= 1'd1; + end + end + end + 1'd1: begin + if ((~liteethudpipcore_liteethmac_request[1])) begin + if (liteethudpipcore_liteethmac_request[0]) begin + liteethudpipcore_liteethmac_grant <= 1'd0; + end + end + end + endcase + liteethudpipcore_liteethmac_status0_ongoing1 <= ((ethcore_arp_mac_port_sink_valid | liteethudpipcore_liteethmac_status0_ongoing1) & (~liteethudpipcore_liteethmac_status0_last)); + if (liteethudpipcore_liteethmac_status0_last) begin + liteethudpipcore_liteethmac_status0_first <= 1'd1; + end else begin + if ((ethcore_arp_mac_port_sink_valid & ethcore_arp_mac_port_sink_ready)) begin + liteethudpipcore_liteethmac_status0_first <= 1'd0; + end + end + liteethudpipcore_liteethmac_status1_ongoing1 <= ((ethcore_ip_mac_port_sink_valid | liteethudpipcore_liteethmac_status1_ongoing1) & (~liteethudpipcore_liteethmac_status1_last)); + if (liteethudpipcore_liteethmac_status1_last) begin + liteethudpipcore_liteethmac_status1_first <= 1'd1; + end else begin + if ((ethcore_ip_mac_port_sink_valid & ethcore_ip_mac_port_sink_ready)) begin + liteethudpipcore_liteethmac_status1_first <= 1'd0; + end + end + if (liteethudpipcore_liteethmac_first) begin + liteethudpipcore_liteethmac_sel_ongoing <= liteethudpipcore_liteethmac_sel0; + end + liteethudpipcore_liteethmac_ongoing1 <= ((ethcore_mac_crossbar_sink_valid | liteethudpipcore_liteethmac_ongoing1) & (~liteethudpipcore_liteethmac_last)); + if (liteethudpipcore_liteethmac_last) begin + liteethudpipcore_liteethmac_first <= 1'd1; + end else begin + if ((ethcore_mac_crossbar_sink_valid & ethcore_mac_crossbar_sink_ready)) begin + liteethudpipcore_liteethmac_first <= 1'd0; + end + end + if (ethcore_mac_packetizer_sr_load) begin + ethcore_mac_packetizer_sr <= ethcore_mac_packetizer_header; + end + if (ethcore_mac_packetizer_sr_shift) begin + ethcore_mac_packetizer_sr <= ethcore_mac_packetizer_sr[111:8]; + end + if (ethcore_mac_packetizer_source_ready) begin + ethcore_mac_packetizer_sink_d_valid <= ethcore_mac_packetizer_sink_valid; + ethcore_mac_packetizer_sink_d_ready <= ethcore_mac_packetizer_sink_ready; + ethcore_mac_packetizer_sink_d_first <= ethcore_mac_packetizer_sink_first; + ethcore_mac_packetizer_sink_d_last <= ethcore_mac_packetizer_sink_last; + ethcore_mac_packetizer_sink_d_payload_ethernet_type <= ethcore_mac_packetizer_sink_payload_ethernet_type; + ethcore_mac_packetizer_sink_d_payload_sender_mac <= ethcore_mac_packetizer_sink_payload_sender_mac; + ethcore_mac_packetizer_sink_d_payload_target_mac <= ethcore_mac_packetizer_sink_payload_target_mac; + ethcore_mac_packetizer_sink_d_payload_data <= ethcore_mac_packetizer_sink_payload_data; + ethcore_mac_packetizer_sink_d_payload_last_be <= ethcore_mac_packetizer_sink_payload_last_be; + ethcore_mac_packetizer_sink_d_payload_error <= ethcore_mac_packetizer_sink_payload_error; + end + liteethudpipcore_liteethmac_liteethmacpacketizer_state <= liteethudpipcore_liteethmac_liteethmacpacketizer_next_state; + if (ethcore_mac_packetizer_count_liteethmacpacketizer_next_value_ce0) begin + ethcore_mac_packetizer_count <= ethcore_mac_packetizer_count_liteethmacpacketizer_next_value0; + end + if (ethcore_mac_packetizer_fsm_from_idle_liteethmacpacketizer_next_value_ce1) begin + ethcore_mac_packetizer_fsm_from_idle <= ethcore_mac_packetizer_fsm_from_idle_liteethmacpacketizer_next_value1; + end + if (ethcore_mac_depacketizer_sr_shift) begin + ethcore_mac_depacketizer_sr <= {ethcore_mac_depacketizer_sink_payload_data, ethcore_mac_depacketizer_sr[111:8]}; + end + if (ethcore_mac_depacketizer_sr_shift_leftover) begin + ethcore_mac_depacketizer_sr <= {ethcore_mac_depacketizer_sink_payload_data, ethcore_mac_depacketizer_sr[111:0]}; + end + if ((ethcore_mac_depacketizer_sink_valid & ethcore_mac_depacketizer_sink_ready)) begin + ethcore_mac_depacketizer_sink_d_valid <= ethcore_mac_depacketizer_sink_valid; + ethcore_mac_depacketizer_sink_d_ready <= ethcore_mac_depacketizer_sink_ready; + ethcore_mac_depacketizer_sink_d_first <= ethcore_mac_depacketizer_sink_first; + ethcore_mac_depacketizer_sink_d_last <= ethcore_mac_depacketizer_sink_last; + ethcore_mac_depacketizer_sink_d_payload_data <= ethcore_mac_depacketizer_sink_payload_data; + ethcore_mac_depacketizer_sink_d_payload_last_be <= ethcore_mac_depacketizer_sink_payload_last_be; + ethcore_mac_depacketizer_sink_d_payload_error <= ethcore_mac_depacketizer_sink_payload_error; + end + liteethudpipcore_liteethmac_liteethmacdepacketizer_state <= liteethudpipcore_liteethmac_liteethmacdepacketizer_next_state; + if (ethcore_mac_depacketizer_count_liteethmacdepacketizer_next_value_ce0) begin + ethcore_mac_depacketizer_count <= ethcore_mac_depacketizer_count_liteethmacdepacketizer_next_value0; + end + if (ethcore_mac_depacketizer_fsm_from_idle_liteethmacdepacketizer_next_value_ce1) begin + ethcore_mac_depacketizer_fsm_from_idle <= ethcore_mac_depacketizer_fsm_from_idle_liteethmacdepacketizer_next_value1; + end + if (ethcore_arp_tx_packetizer_sr_load) begin + ethcore_arp_tx_packetizer_sr <= ethcore_arp_tx_packetizer_header; + end + if (ethcore_arp_tx_packetizer_sr_shift) begin + ethcore_arp_tx_packetizer_sr <= ethcore_arp_tx_packetizer_sr[223:8]; + end + if (ethcore_arp_tx_packetizer_source_ready) begin + ethcore_arp_tx_packetizer_sink_d_valid <= ethcore_arp_tx_packetizer_sink_valid; + ethcore_arp_tx_packetizer_sink_d_ready <= ethcore_arp_tx_packetizer_sink_ready; + ethcore_arp_tx_packetizer_sink_d_first <= ethcore_arp_tx_packetizer_sink_first; + ethcore_arp_tx_packetizer_sink_d_last <= ethcore_arp_tx_packetizer_sink_last; + ethcore_arp_tx_packetizer_sink_d_payload_data <= ethcore_arp_tx_packetizer_sink_payload_data; + ethcore_arp_tx_packetizer_sink_d_payload_error <= ethcore_arp_tx_packetizer_sink_payload_error; + ethcore_arp_tx_packetizer_sink_d_param_hwsize <= ethcore_arp_tx_packetizer_sink_param_hwsize; + ethcore_arp_tx_packetizer_sink_d_param_hwtype <= ethcore_arp_tx_packetizer_sink_param_hwtype; + ethcore_arp_tx_packetizer_sink_d_param_opcode <= ethcore_arp_tx_packetizer_sink_param_opcode; + ethcore_arp_tx_packetizer_sink_d_param_proto <= ethcore_arp_tx_packetizer_sink_param_proto; + ethcore_arp_tx_packetizer_sink_d_param_protosize <= ethcore_arp_tx_packetizer_sink_param_protosize; + ethcore_arp_tx_packetizer_sink_d_param_sender_ip <= ethcore_arp_tx_packetizer_sink_param_sender_ip; + ethcore_arp_tx_packetizer_sink_d_param_sender_mac <= ethcore_arp_tx_packetizer_sink_param_sender_mac; + ethcore_arp_tx_packetizer_sink_d_param_target_ip <= ethcore_arp_tx_packetizer_sink_param_target_ip; + ethcore_arp_tx_packetizer_sink_d_param_target_mac <= ethcore_arp_tx_packetizer_sink_param_target_mac; + end + liteethudpipcore_liteetharptx_liteetharppacketizer_state <= liteethudpipcore_liteetharptx_liteetharppacketizer_next_state; + if (ethcore_arp_tx_packetizer_count_liteetharp_liteetharppacketizer_next_value_ce0) begin + ethcore_arp_tx_packetizer_count <= ethcore_arp_tx_packetizer_count_liteetharp_liteetharppacketizer_next_value0; + end + if (ethcore_arp_tx_packetizer_fsm_from_idle_liteetharp_liteetharppacketizer_next_value_ce1) begin + ethcore_arp_tx_packetizer_fsm_from_idle <= ethcore_arp_tx_packetizer_fsm_from_idle_liteetharp_liteetharppacketizer_next_value1; + end + liteethudpipcore_liteetharptx_fsm_state <= liteethudpipcore_liteetharptx_fsm_next_state; + if (ethcore_arp_tx_counter_liteetharp_fsm_next_value_ce) begin + ethcore_arp_tx_counter <= ethcore_arp_tx_counter_liteetharp_fsm_next_value; + end + ethcore_arp_rx_valid <= (((((ethcore_arp_rx_depacketizer_source_valid & (ethcore_arp_rx_depacketizer_source_param_hwtype == 1'd1)) & (ethcore_arp_rx_depacketizer_source_param_proto == 12'd2048)) & (ethcore_arp_rx_depacketizer_source_param_hwsize == 3'd6)) & (ethcore_arp_rx_depacketizer_source_param_protosize == 3'd4)) & (ethcore_arp_rx_depacketizer_source_param_target_ip == 32'd3232235826)); + if (ethcore_arp_rx_depacketizer_sr_shift) begin + ethcore_arp_rx_depacketizer_sr <= {ethcore_arp_rx_depacketizer_sink_payload_data, ethcore_arp_rx_depacketizer_sr[223:8]}; + end + if (ethcore_arp_rx_depacketizer_sr_shift_leftover) begin + ethcore_arp_rx_depacketizer_sr <= {ethcore_arp_rx_depacketizer_sink_payload_data, ethcore_arp_rx_depacketizer_sr[223:0]}; + end + if ((ethcore_arp_rx_depacketizer_sink_valid & ethcore_arp_rx_depacketizer_sink_ready)) begin + ethcore_arp_rx_depacketizer_sink_d_valid <= ethcore_arp_rx_depacketizer_sink_valid; + ethcore_arp_rx_depacketizer_sink_d_ready <= ethcore_arp_rx_depacketizer_sink_ready; + ethcore_arp_rx_depacketizer_sink_d_first <= ethcore_arp_rx_depacketizer_sink_first; + ethcore_arp_rx_depacketizer_sink_d_last <= ethcore_arp_rx_depacketizer_sink_last; + ethcore_arp_rx_depacketizer_sink_d_payload_ethernet_type <= ethcore_arp_rx_depacketizer_sink_payload_ethernet_type; + ethcore_arp_rx_depacketizer_sink_d_payload_sender_mac <= ethcore_arp_rx_depacketizer_sink_payload_sender_mac; + ethcore_arp_rx_depacketizer_sink_d_payload_target_mac <= ethcore_arp_rx_depacketizer_sink_payload_target_mac; + ethcore_arp_rx_depacketizer_sink_d_payload_data <= ethcore_arp_rx_depacketizer_sink_payload_data; + ethcore_arp_rx_depacketizer_sink_d_payload_last_be <= ethcore_arp_rx_depacketizer_sink_payload_last_be; + ethcore_arp_rx_depacketizer_sink_d_payload_error <= ethcore_arp_rx_depacketizer_sink_payload_error; + end + liteethudpipcore_liteetharprx_liteetharpdepacketizer_state <= liteethudpipcore_liteetharprx_liteetharpdepacketizer_next_state; + if (ethcore_arp_rx_depacketizer_count_liteetharp_next_value_ce0) begin + ethcore_arp_rx_depacketizer_count <= ethcore_arp_rx_depacketizer_count_liteetharp_next_value0; + end + if (ethcore_arp_rx_depacketizer_fsm_from_idle_liteetharp_next_value_ce1) begin + ethcore_arp_rx_depacketizer_fsm_from_idle <= ethcore_arp_rx_depacketizer_fsm_from_idle_liteetharp_next_value1; + end + liteethudpipcore_liteetharprx_fsm_state <= liteethudpipcore_liteetharprx_fsm_next_state; + if (ethcore_arp_table_request_pending_clr) begin + ethcore_arp_table_request_pending <= 1'd0; + end else begin + if (ethcore_arp_table_request_pending_set) begin + ethcore_arp_table_request_pending <= 1'd1; + end + end + if (ethcore_arp_table_request_ip_address_reset) begin + ethcore_arp_table_request_ip_address <= 1'd0; + end else begin + if (ethcore_arp_table_request_ip_address_update) begin + ethcore_arp_table_request_ip_address <= ethcore_arp_table_request_payload_ip_address; + end + end + if (ethcore_arp_table_request_counter_reset) begin + ethcore_arp_table_request_counter <= 1'd0; + end else begin + if (ethcore_arp_table_request_counter_ce) begin + ethcore_arp_table_request_counter <= (ethcore_arp_table_request_counter + 1'd1); + end + end + if (ethcore_arp_table_update) begin + ethcore_arp_table_cached_valid <= 1'd1; + ethcore_arp_table_cached_ip_address <= ethcore_arp_table_sink_payload_ip_address; + ethcore_arp_table_cached_mac_address <= ethcore_arp_table_sink_payload_mac_address; + end else begin + if (ethcore_arp_table_cached_timer_done) begin + ethcore_arp_table_cached_valid <= 1'd0; + end + end + if (ethcore_arp_table_request_timer_wait) begin + if ((~ethcore_arp_table_request_timer_done)) begin + ethcore_arp_table_request_timer_count <= (ethcore_arp_table_request_timer_count - 1'd1); + end + end else begin + ethcore_arp_table_request_timer_count <= 24'd10000000; + end + if (ethcore_arp_table_cached_timer_wait) begin + if ((~ethcore_arp_table_cached_timer_done)) begin + ethcore_arp_table_cached_timer_count <= (ethcore_arp_table_cached_timer_count - 1'd1); + end + end else begin + ethcore_arp_table_cached_timer_count <= 30'd1000000000; + end + liteethudpipcore_state <= liteethudpipcore_next_state; + if (ethcore_ip_tx_ce) begin + if ((~ethcore_ip_tx_liteethipv4checksum_done)) begin + ethcore_ip_tx_liteethipv4checksum_r_next0 <= {ethcore_ip_tx_liteethipv4checksum0, (ethcore_ip_tx_liteethipv4checksum_s_next0[15:0] + ethcore_ip_tx_liteethipv4checksum_s_next0[16])}; + end + if ((~ethcore_ip_tx_liteethipv4checksum_done)) begin + ethcore_ip_tx_liteethipv4checksum_r_next1 <= {ethcore_ip_tx_liteethipv4checksum1, (ethcore_ip_tx_liteethipv4checksum_s_next1[15:0] + ethcore_ip_tx_liteethipv4checksum_s_next1[16])}; + end + if ((~ethcore_ip_tx_liteethipv4checksum_done)) begin + ethcore_ip_tx_liteethipv4checksum_r_next2 <= {ethcore_ip_tx_liteethipv4checksum2, (ethcore_ip_tx_liteethipv4checksum_s_next2[15:0] + ethcore_ip_tx_liteethipv4checksum_s_next2[16])}; + end + if ((~ethcore_ip_tx_liteethipv4checksum_done)) begin + ethcore_ip_tx_liteethipv4checksum_r_next3 <= {ethcore_ip_tx_liteethipv4checksum3, (ethcore_ip_tx_liteethipv4checksum_s_next3[15:0] + ethcore_ip_tx_liteethipv4checksum_s_next3[16])}; + end + if ((~ethcore_ip_tx_liteethipv4checksum_done)) begin + ethcore_ip_tx_liteethipv4checksum_r_next4 <= {ethcore_ip_tx_liteethipv4checksum4, (ethcore_ip_tx_liteethipv4checksum_s_next4[15:0] + ethcore_ip_tx_liteethipv4checksum_s_next4[16])}; + end + if ((~ethcore_ip_tx_liteethipv4checksum_done)) begin + ethcore_ip_tx_liteethipv4checksum_r_next5 <= {ethcore_ip_tx_liteethipv4checksum5, (ethcore_ip_tx_liteethipv4checksum_s_next5[15:0] + ethcore_ip_tx_liteethipv4checksum_s_next5[16])}; + end + if ((~ethcore_ip_tx_liteethipv4checksum_done)) begin + ethcore_ip_tx_liteethipv4checksum_r_next6 <= {ethcore_ip_tx_liteethipv4checksum6, (ethcore_ip_tx_liteethipv4checksum_s_next6[15:0] + ethcore_ip_tx_liteethipv4checksum_s_next6[16])}; + end + if ((~ethcore_ip_tx_liteethipv4checksum_done)) begin + ethcore_ip_tx_liteethipv4checksum_r_next7 <= {ethcore_ip_tx_liteethipv4checksum7, (ethcore_ip_tx_liteethipv4checksum_s_next7[15:0] + ethcore_ip_tx_liteethipv4checksum_s_next7[16])}; + end + if ((~ethcore_ip_tx_liteethipv4checksum_done)) begin + ethcore_ip_tx_liteethipv4checksum_r_next8 <= {ethcore_ip_tx_liteethipv4checksum8, (ethcore_ip_tx_liteethipv4checksum_s_next8[15:0] + ethcore_ip_tx_liteethipv4checksum_s_next8[16])}; + end + if (ethcore_ip_tx_liteethipv4checksum_counter_ce) begin + ethcore_ip_tx_liteethipv4checksum_counter <= (ethcore_ip_tx_liteethipv4checksum_counter + 1'd1); + end + end + if (ethcore_ip_tx_reset) begin + ethcore_ip_tx_liteethipv4checksum_counter <= 4'd0; + end + if (ethcore_ip_tx_packetizer_sr_load) begin + ethcore_ip_tx_packetizer_sr <= ethcore_ip_tx_packetizer_header; + end + if (ethcore_ip_tx_packetizer_sr_shift) begin + ethcore_ip_tx_packetizer_sr <= ethcore_ip_tx_packetizer_sr[159:8]; + end + if (ethcore_ip_tx_packetizer_source_ready) begin + ethcore_ip_tx_packetizer_sink_d_valid <= ethcore_ip_tx_packetizer_sink_valid; + ethcore_ip_tx_packetizer_sink_d_ready <= ethcore_ip_tx_packetizer_sink_ready; + ethcore_ip_tx_packetizer_sink_d_first <= ethcore_ip_tx_packetizer_sink_first; + ethcore_ip_tx_packetizer_sink_d_last <= ethcore_ip_tx_packetizer_sink_last; + ethcore_ip_tx_packetizer_sink_d_payload_data <= ethcore_ip_tx_packetizer_sink_payload_data; + ethcore_ip_tx_packetizer_sink_d_payload_error <= ethcore_ip_tx_packetizer_sink_payload_error; + ethcore_ip_tx_packetizer_sink_d_param_checksum <= ethcore_ip_tx_packetizer_sink_param_checksum; + ethcore_ip_tx_packetizer_sink_d_param_identification <= ethcore_ip_tx_packetizer_sink_param_identification; + ethcore_ip_tx_packetizer_sink_d_param_ihl <= ethcore_ip_tx_packetizer_sink_param_ihl; + ethcore_ip_tx_packetizer_sink_d_param_protocol <= ethcore_ip_tx_packetizer_sink_param_protocol; + ethcore_ip_tx_packetizer_sink_d_param_sender_ip <= ethcore_ip_tx_packetizer_sink_param_sender_ip; + ethcore_ip_tx_packetizer_sink_d_param_target_ip <= ethcore_ip_tx_packetizer_sink_param_target_ip; + ethcore_ip_tx_packetizer_sink_d_param_total_length <= ethcore_ip_tx_packetizer_sink_param_total_length; + ethcore_ip_tx_packetizer_sink_d_param_ttl <= ethcore_ip_tx_packetizer_sink_param_ttl; + ethcore_ip_tx_packetizer_sink_d_param_version <= ethcore_ip_tx_packetizer_sink_param_version; + end + liteethudpipcore_liteethip_liteethiptx_liteethipv4packetizer_state <= liteethudpipcore_liteethip_liteethiptx_liteethipv4packetizer_next_state; + if (ethcore_ip_tx_packetizer_count_liteethip_liteethipv4packetizer_next_value_ce0) begin + ethcore_ip_tx_packetizer_count <= ethcore_ip_tx_packetizer_count_liteethip_liteethipv4packetizer_next_value0; + end + if (ethcore_ip_tx_packetizer_fsm_from_idle_liteethip_liteethipv4packetizer_next_value_ce1) begin + ethcore_ip_tx_packetizer_fsm_from_idle <= ethcore_ip_tx_packetizer_fsm_from_idle_liteethip_liteethipv4packetizer_next_value1; + end + liteethudpipcore_liteethip_liteethiptx_fsm_state <= liteethudpipcore_liteethip_liteethiptx_fsm_next_state; + if (ethcore_ip_tx_target_mac_liteethip_fsm_next_value_ce) begin + ethcore_ip_tx_target_mac <= ethcore_ip_tx_target_mac_liteethip_fsm_next_value; + end + ethcore_ip_rx_valid <= ((((ethcore_ip_rx_depacketizer_source_valid & (ethcore_ip_rx_depacketizer_source_param_target_ip == 32'd3232235826)) & (ethcore_ip_rx_depacketizer_source_param_version == 3'd4)) & (ethcore_ip_rx_depacketizer_source_param_ihl == 3'd5)) & (ethcore_ip_rx_liteethipv4checksum_value == 1'd0)); + if (ethcore_ip_rx_depacketizer_sr_shift) begin + ethcore_ip_rx_depacketizer_sr <= {ethcore_ip_rx_depacketizer_sink_payload_data, ethcore_ip_rx_depacketizer_sr[159:8]}; + end + if (ethcore_ip_rx_depacketizer_sr_shift_leftover) begin + ethcore_ip_rx_depacketizer_sr <= {ethcore_ip_rx_depacketizer_sink_payload_data, ethcore_ip_rx_depacketizer_sr[159:0]}; + end + if ((ethcore_ip_rx_depacketizer_sink_valid & ethcore_ip_rx_depacketizer_sink_ready)) begin + ethcore_ip_rx_depacketizer_sink_d_valid <= ethcore_ip_rx_depacketizer_sink_valid; + ethcore_ip_rx_depacketizer_sink_d_ready <= ethcore_ip_rx_depacketizer_sink_ready; + ethcore_ip_rx_depacketizer_sink_d_first <= ethcore_ip_rx_depacketizer_sink_first; + ethcore_ip_rx_depacketizer_sink_d_last <= ethcore_ip_rx_depacketizer_sink_last; + ethcore_ip_rx_depacketizer_sink_d_payload_ethernet_type <= ethcore_ip_rx_depacketizer_sink_payload_ethernet_type; + ethcore_ip_rx_depacketizer_sink_d_payload_sender_mac <= ethcore_ip_rx_depacketizer_sink_payload_sender_mac; + ethcore_ip_rx_depacketizer_sink_d_payload_target_mac <= ethcore_ip_rx_depacketizer_sink_payload_target_mac; + ethcore_ip_rx_depacketizer_sink_d_payload_data <= ethcore_ip_rx_depacketizer_sink_payload_data; + ethcore_ip_rx_depacketizer_sink_d_payload_last_be <= ethcore_ip_rx_depacketizer_sink_payload_last_be; + ethcore_ip_rx_depacketizer_sink_d_payload_error <= ethcore_ip_rx_depacketizer_sink_payload_error; + end + liteethudpipcore_liteethip_liteethiprx_liteethipv4depacketizer_state <= liteethudpipcore_liteethip_liteethiprx_liteethipv4depacketizer_next_state; + if (ethcore_ip_rx_depacketizer_count_liteethip_next_value_ce0) begin + ethcore_ip_rx_depacketizer_count <= ethcore_ip_rx_depacketizer_count_liteethip_next_value0; + end + if (ethcore_ip_rx_depacketizer_fsm_from_idle_liteethip_next_value_ce1) begin + ethcore_ip_rx_depacketizer_fsm_from_idle <= ethcore_ip_rx_depacketizer_fsm_from_idle_liteethip_next_value1; + end + if (ethcore_ip_rx_ce) begin + if ((~ethcore_ip_rx_liteethipv4checksum_done)) begin + ethcore_ip_rx_liteethipv4checksum_r_next0 <= {ethcore_ip_rx_liteethipv4checksum0, (ethcore_ip_rx_liteethipv4checksum_s_next0[15:0] + ethcore_ip_rx_liteethipv4checksum_s_next0[16])}; + end + if ((~ethcore_ip_rx_liteethipv4checksum_done)) begin + ethcore_ip_rx_liteethipv4checksum_r_next1 <= {ethcore_ip_rx_liteethipv4checksum1, (ethcore_ip_rx_liteethipv4checksum_s_next1[15:0] + ethcore_ip_rx_liteethipv4checksum_s_next1[16])}; + end + if ((~ethcore_ip_rx_liteethipv4checksum_done)) begin + ethcore_ip_rx_liteethipv4checksum_r_next2 <= {ethcore_ip_rx_liteethipv4checksum2, (ethcore_ip_rx_liteethipv4checksum_s_next2[15:0] + ethcore_ip_rx_liteethipv4checksum_s_next2[16])}; + end + if ((~ethcore_ip_rx_liteethipv4checksum_done)) begin + ethcore_ip_rx_liteethipv4checksum_r_next3 <= {ethcore_ip_rx_liteethipv4checksum3, (ethcore_ip_rx_liteethipv4checksum_s_next3[15:0] + ethcore_ip_rx_liteethipv4checksum_s_next3[16])}; + end + if ((~ethcore_ip_rx_liteethipv4checksum_done)) begin + ethcore_ip_rx_liteethipv4checksum_r_next4 <= {ethcore_ip_rx_liteethipv4checksum4, (ethcore_ip_rx_liteethipv4checksum_s_next4[15:0] + ethcore_ip_rx_liteethipv4checksum_s_next4[16])}; + end + if ((~ethcore_ip_rx_liteethipv4checksum_done)) begin + ethcore_ip_rx_liteethipv4checksum_r_next5 <= {ethcore_ip_rx_liteethipv4checksum5, (ethcore_ip_rx_liteethipv4checksum_s_next5[15:0] + ethcore_ip_rx_liteethipv4checksum_s_next5[16])}; + end + if ((~ethcore_ip_rx_liteethipv4checksum_done)) begin + ethcore_ip_rx_liteethipv4checksum_r_next6 <= {ethcore_ip_rx_liteethipv4checksum6, (ethcore_ip_rx_liteethipv4checksum_s_next6[15:0] + ethcore_ip_rx_liteethipv4checksum_s_next6[16])}; + end + if ((~ethcore_ip_rx_liteethipv4checksum_done)) begin + ethcore_ip_rx_liteethipv4checksum_r_next7 <= {ethcore_ip_rx_liteethipv4checksum7, (ethcore_ip_rx_liteethipv4checksum_s_next7[15:0] + ethcore_ip_rx_liteethipv4checksum_s_next7[16])}; + end + if ((~ethcore_ip_rx_liteethipv4checksum_done)) begin + ethcore_ip_rx_liteethipv4checksum_r_next8 <= {ethcore_ip_rx_liteethipv4checksum8, (ethcore_ip_rx_liteethipv4checksum_s_next8[15:0] + ethcore_ip_rx_liteethipv4checksum_s_next8[16])}; + end + if ((~ethcore_ip_rx_liteethipv4checksum_done)) begin + ethcore_ip_rx_liteethipv4checksum_r_next9 <= {ethcore_ip_rx_liteethipv4checksum9, (ethcore_ip_rx_liteethipv4checksum_s_next9[15:0] + ethcore_ip_rx_liteethipv4checksum_s_next9[16])}; + end + if (ethcore_ip_rx_liteethipv4checksum_counter_ce) begin + ethcore_ip_rx_liteethipv4checksum_counter <= (ethcore_ip_rx_liteethipv4checksum_counter + 1'd1); + end + end + if (ethcore_ip_rx_reset) begin + ethcore_ip_rx_liteethipv4checksum_counter <= 4'd0; + end + liteethudpipcore_liteethip_liteethiprx_fsm_state <= liteethudpipcore_liteethip_liteethiprx_fsm_next_state; + case (liteethudpipcore_liteethip_grant) + 1'd0: begin + if ((~liteethudpipcore_liteethip_request[0])) begin + if (liteethudpipcore_liteethip_request[1]) begin + liteethudpipcore_liteethip_grant <= 1'd1; + end + end + end + 1'd1: begin + if ((~liteethudpipcore_liteethip_request[1])) begin + if (liteethudpipcore_liteethip_request[0]) begin + liteethudpipcore_liteethip_grant <= 1'd0; + end + end + end + endcase + liteethudpipcore_liteethip_status0_ongoing1 <= ((ethcore_icmp_sink_valid | liteethudpipcore_liteethip_status0_ongoing1) & (~liteethudpipcore_liteethip_status0_last)); + if (liteethudpipcore_liteethip_status0_last) begin + liteethudpipcore_liteethip_status0_first <= 1'd1; + end else begin + if ((ethcore_icmp_sink_valid & ethcore_icmp_sink_ready)) begin + liteethudpipcore_liteethip_status0_first <= 1'd0; + end + end + liteethudpipcore_liteethip_status1_ongoing1 <= ((ethcore_ip_port_sink_valid | liteethudpipcore_liteethip_status1_ongoing1) & (~liteethudpipcore_liteethip_status1_last)); + if (liteethudpipcore_liteethip_status1_last) begin + liteethudpipcore_liteethip_status1_first <= 1'd1; + end else begin + if ((ethcore_ip_port_sink_valid & ethcore_ip_port_sink_ready)) begin + liteethudpipcore_liteethip_status1_first <= 1'd0; + end + end + if (liteethudpipcore_liteethip_first) begin + liteethudpipcore_liteethip_sel_ongoing <= liteethudpipcore_liteethip_sel0; + end + liteethudpipcore_liteethip_ongoing1 <= ((ethcore_ip_crossbar_sink_valid | liteethudpipcore_liteethip_ongoing1) & (~liteethudpipcore_liteethip_last)); + if (liteethudpipcore_liteethip_last) begin + liteethudpipcore_liteethip_first <= 1'd1; + end else begin + if ((ethcore_ip_crossbar_sink_valid & ethcore_ip_crossbar_sink_ready)) begin + liteethudpipcore_liteethip_first <= 1'd0; + end + end + if (ethcore_icmp_tx_packetizer_sr_load) begin + ethcore_icmp_tx_packetizer_sr <= ethcore_icmp_tx_packetizer_header; + end + if (ethcore_icmp_tx_packetizer_sr_shift) begin + ethcore_icmp_tx_packetizer_sr <= ethcore_icmp_tx_packetizer_sr[63:8]; + end + if (ethcore_icmp_tx_packetizer_source_ready) begin + ethcore_icmp_tx_packetizer_sink_d_valid <= ethcore_icmp_tx_packetizer_sink_valid; + ethcore_icmp_tx_packetizer_sink_d_ready <= ethcore_icmp_tx_packetizer_sink_ready; + ethcore_icmp_tx_packetizer_sink_d_first <= ethcore_icmp_tx_packetizer_sink_first; + ethcore_icmp_tx_packetizer_sink_d_last <= ethcore_icmp_tx_packetizer_sink_last; + ethcore_icmp_tx_packetizer_sink_d_payload_data <= ethcore_icmp_tx_packetizer_sink_payload_data; + ethcore_icmp_tx_packetizer_sink_d_payload_error <= ethcore_icmp_tx_packetizer_sink_payload_error; + ethcore_icmp_tx_packetizer_sink_d_param_checksum <= ethcore_icmp_tx_packetizer_sink_param_checksum; + ethcore_icmp_tx_packetizer_sink_d_param_code <= ethcore_icmp_tx_packetizer_sink_param_code; + ethcore_icmp_tx_packetizer_sink_d_param_msgtype <= ethcore_icmp_tx_packetizer_sink_param_msgtype; + ethcore_icmp_tx_packetizer_sink_d_param_quench <= ethcore_icmp_tx_packetizer_sink_param_quench; + end + liteethudpipcore_liteethicmptx_liteethicmppacketizer_state <= liteethudpipcore_liteethicmptx_liteethicmppacketizer_next_state; + if (ethcore_icmp_tx_packetizer_count_liteethicmptx_next_value_ce0) begin + ethcore_icmp_tx_packetizer_count <= ethcore_icmp_tx_packetizer_count_liteethicmptx_next_value0; + end + if (ethcore_icmp_tx_packetizer_fsm_from_idle_liteethicmptx_next_value_ce1) begin + ethcore_icmp_tx_packetizer_fsm_from_idle <= ethcore_icmp_tx_packetizer_fsm_from_idle_liteethicmptx_next_value1; + end + liteethudpipcore_liteethicmptx_fsm_state <= liteethudpipcore_liteethicmptx_fsm_next_state; + ethcore_icmp_rx_valid <= (ethcore_icmp_rx_depacketizer_source_valid & (ethcore_icmp_rx_sink_sink_param_protocol == 1'd1)); + if (ethcore_icmp_rx_depacketizer_sr_shift) begin + ethcore_icmp_rx_depacketizer_sr <= {ethcore_icmp_rx_depacketizer_sink_payload_data, ethcore_icmp_rx_depacketizer_sr[63:8]}; + end + if (ethcore_icmp_rx_depacketizer_sr_shift_leftover) begin + ethcore_icmp_rx_depacketizer_sr <= {ethcore_icmp_rx_depacketizer_sink_payload_data, ethcore_icmp_rx_depacketizer_sr[63:0]}; + end + if ((ethcore_icmp_rx_depacketizer_sink_valid & ethcore_icmp_rx_depacketizer_sink_ready)) begin + ethcore_icmp_rx_depacketizer_sink_d_valid <= ethcore_icmp_rx_depacketizer_sink_valid; + ethcore_icmp_rx_depacketizer_sink_d_ready <= ethcore_icmp_rx_depacketizer_sink_ready; + ethcore_icmp_rx_depacketizer_sink_d_first <= ethcore_icmp_rx_depacketizer_sink_first; + ethcore_icmp_rx_depacketizer_sink_d_last <= ethcore_icmp_rx_depacketizer_sink_last; + ethcore_icmp_rx_depacketizer_sink_d_payload_data <= ethcore_icmp_rx_depacketizer_sink_payload_data; + ethcore_icmp_rx_depacketizer_sink_d_payload_error <= ethcore_icmp_rx_depacketizer_sink_payload_error; + ethcore_icmp_rx_depacketizer_sink_d_param_length <= ethcore_icmp_rx_depacketizer_sink_param_length; + ethcore_icmp_rx_depacketizer_sink_d_param_protocol <= ethcore_icmp_rx_depacketizer_sink_param_protocol; + ethcore_icmp_rx_depacketizer_sink_d_param_ip_address <= ethcore_icmp_rx_depacketizer_sink_param_ip_address; + end + liteethudpipcore_liteethicmprx_liteethicmpdepacketizer_state <= liteethudpipcore_liteethicmprx_liteethicmpdepacketizer_next_state; + if (ethcore_icmp_rx_depacketizer_count_liteethicmprx_next_value_ce0) begin + ethcore_icmp_rx_depacketizer_count <= ethcore_icmp_rx_depacketizer_count_liteethicmprx_next_value0; + end + if (ethcore_icmp_rx_depacketizer_fsm_from_idle_liteethicmprx_next_value_ce1) begin + ethcore_icmp_rx_depacketizer_fsm_from_idle <= ethcore_icmp_rx_depacketizer_fsm_from_idle_liteethicmprx_next_value1; + end + liteethudpipcore_liteethicmprx_fsm_state <= liteethudpipcore_liteethicmprx_fsm_next_state; + if (ethcore_icmp_echo_buffer_syncfifo_re) begin + ethcore_icmp_echo_buffer_readable <= 1'd1; + end else begin + if (ethcore_icmp_echo_buffer_re) begin + ethcore_icmp_echo_buffer_readable <= 1'd0; + end + end + if (((ethcore_icmp_echo_buffer_syncfifo_we & ethcore_icmp_echo_buffer_syncfifo_writable) & (~ethcore_icmp_echo_buffer_replace))) begin + ethcore_icmp_echo_buffer_produce <= (ethcore_icmp_echo_buffer_produce + 1'd1); + end + if (ethcore_icmp_echo_buffer_do_read) begin + ethcore_icmp_echo_buffer_consume <= (ethcore_icmp_echo_buffer_consume + 1'd1); + end + if (((ethcore_icmp_echo_buffer_syncfifo_we & ethcore_icmp_echo_buffer_syncfifo_writable) & (~ethcore_icmp_echo_buffer_replace))) begin + if ((~ethcore_icmp_echo_buffer_do_read)) begin + ethcore_icmp_echo_buffer_level0 <= (ethcore_icmp_echo_buffer_level0 + 1'd1); + end + end else begin + if (ethcore_icmp_echo_buffer_do_read) begin + ethcore_icmp_echo_buffer_level0 <= (ethcore_icmp_echo_buffer_level0 - 1'd1); + end + end + if (ethcore_tx_packetizer_sr_load) begin + ethcore_tx_packetizer_sr <= ethcore_tx_packetizer_header; + end + if (ethcore_tx_packetizer_sr_shift) begin + ethcore_tx_packetizer_sr <= ethcore_tx_packetizer_sr[63:8]; + end + if (ethcore_tx_packetizer_source_ready) begin + ethcore_tx_packetizer_sink_d_valid <= ethcore_tx_packetizer_sink_valid; + ethcore_tx_packetizer_sink_d_ready <= ethcore_tx_packetizer_sink_ready; + ethcore_tx_packetizer_sink_d_first <= ethcore_tx_packetizer_sink_first; + ethcore_tx_packetizer_sink_d_last <= ethcore_tx_packetizer_sink_last; + ethcore_tx_packetizer_sink_d_payload_data <= ethcore_tx_packetizer_sink_payload_data; + ethcore_tx_packetizer_sink_d_payload_error <= ethcore_tx_packetizer_sink_payload_error; + ethcore_tx_packetizer_sink_d_param_checksum <= ethcore_tx_packetizer_sink_param_checksum; + ethcore_tx_packetizer_sink_d_param_dst_port <= ethcore_tx_packetizer_sink_param_dst_port; + ethcore_tx_packetizer_sink_d_param_length <= ethcore_tx_packetizer_sink_param_length; + ethcore_tx_packetizer_sink_d_param_src_port <= ethcore_tx_packetizer_sink_param_src_port; + end + liteethudpipcore_liteethudp_liteethudptx_liteethudppacketizer_state <= liteethudpipcore_liteethudp_liteethudptx_liteethudppacketizer_next_state; + if (ethcore_tx_packetizer_count_liteethudptx_next_value_ce0) begin + ethcore_tx_packetizer_count <= ethcore_tx_packetizer_count_liteethudptx_next_value0; + end + if (ethcore_tx_packetizer_fsm_from_idle_liteethudptx_next_value_ce1) begin + ethcore_tx_packetizer_fsm_from_idle <= ethcore_tx_packetizer_fsm_from_idle_liteethudptx_next_value1; + end + liteethudpipcore_liteethudp_liteethudptx_fsm_state <= liteethudpipcore_liteethudp_liteethudptx_fsm_next_state; + ethcore_rx_valid <= (ethcore_rx_depacketizer_source_valid & (ethcore_rx_sink_sink_param_protocol == 5'd17)); + if (ethcore_rx_depacketizer_sr_shift) begin + ethcore_rx_depacketizer_sr <= {ethcore_rx_depacketizer_sink_payload_data, ethcore_rx_depacketizer_sr[63:8]}; + end + if (ethcore_rx_depacketizer_sr_shift_leftover) begin + ethcore_rx_depacketizer_sr <= {ethcore_rx_depacketizer_sink_payload_data, ethcore_rx_depacketizer_sr[63:0]}; + end + if ((ethcore_rx_depacketizer_sink_valid & ethcore_rx_depacketizer_sink_ready)) begin + ethcore_rx_depacketizer_sink_d_valid <= ethcore_rx_depacketizer_sink_valid; + ethcore_rx_depacketizer_sink_d_ready <= ethcore_rx_depacketizer_sink_ready; + ethcore_rx_depacketizer_sink_d_first <= ethcore_rx_depacketizer_sink_first; + ethcore_rx_depacketizer_sink_d_last <= ethcore_rx_depacketizer_sink_last; + ethcore_rx_depacketizer_sink_d_payload_data <= ethcore_rx_depacketizer_sink_payload_data; + ethcore_rx_depacketizer_sink_d_payload_error <= ethcore_rx_depacketizer_sink_payload_error; + ethcore_rx_depacketizer_sink_d_param_length <= ethcore_rx_depacketizer_sink_param_length; + ethcore_rx_depacketizer_sink_d_param_protocol <= ethcore_rx_depacketizer_sink_param_protocol; + ethcore_rx_depacketizer_sink_d_param_ip_address <= ethcore_rx_depacketizer_sink_param_ip_address; + end + liteethudpipcore_liteethudp_liteethudprx_liteethudpdepacketizer_state <= liteethudpipcore_liteethudp_liteethudprx_liteethudpdepacketizer_next_state; + if (ethcore_rx_depacketizer_count_liteethudprx_next_value_ce0) begin + ethcore_rx_depacketizer_count <= ethcore_rx_depacketizer_count_liteethudprx_next_value0; + end + if (ethcore_rx_depacketizer_fsm_from_idle_liteethudprx_next_value_ce1) begin + ethcore_rx_depacketizer_fsm_from_idle <= ethcore_rx_depacketizer_fsm_from_idle_liteethudprx_next_value1; + end + liteethudpipcore_liteethudp_liteethudprx_fsm_state <= liteethudpipcore_liteethudp_liteethudprx_fsm_next_state; + if ((etherbone_tx_converter_converter_source_valid & etherbone_tx_converter_converter_source_ready)) begin + if (etherbone_tx_converter_converter_last) begin + etherbone_tx_converter_converter_mux <= 1'd0; + end else begin + etherbone_tx_converter_converter_mux <= (etherbone_tx_converter_converter_mux + 1'd1); + end + end + etherbone_rx_converter_source_param_src_port <= etherbone_rx_converter_sink_param_src_port; + etherbone_rx_converter_source_param_dst_port <= etherbone_rx_converter_sink_param_dst_port; + etherbone_rx_converter_source_param_ip_address <= etherbone_rx_converter_sink_param_ip_address; + etherbone_rx_converter_source_param_length <= etherbone_rx_converter_sink_param_length; + if (etherbone_rx_converter_converter_source_ready) begin + etherbone_rx_converter_converter_strobe_all <= 1'd0; + end + if (etherbone_rx_converter_converter_load_part) begin + if (((etherbone_rx_converter_converter_demux == 2'd3) | etherbone_rx_converter_converter_sink_last)) begin + etherbone_rx_converter_converter_demux <= 1'd0; + etherbone_rx_converter_converter_strobe_all <= 1'd1; + end else begin + etherbone_rx_converter_converter_demux <= (etherbone_rx_converter_converter_demux + 1'd1); + end + end + if ((etherbone_rx_converter_converter_source_valid & etherbone_rx_converter_converter_source_ready)) begin + if ((etherbone_rx_converter_converter_sink_valid & etherbone_rx_converter_converter_sink_ready)) begin + etherbone_rx_converter_converter_source_first <= etherbone_rx_converter_converter_sink_first; + etherbone_rx_converter_converter_source_last <= etherbone_rx_converter_converter_sink_last; + end else begin + etherbone_rx_converter_converter_source_first <= 1'd0; + etherbone_rx_converter_converter_source_last <= 1'd0; + end + end else begin + if ((etherbone_rx_converter_converter_sink_valid & etherbone_rx_converter_converter_sink_ready)) begin + etherbone_rx_converter_converter_source_first <= (etherbone_rx_converter_converter_sink_first | etherbone_rx_converter_converter_source_first); + etherbone_rx_converter_converter_source_last <= (etherbone_rx_converter_converter_sink_last | etherbone_rx_converter_converter_source_last); + end + end + if (etherbone_rx_converter_converter_load_part) begin + case (etherbone_rx_converter_converter_demux) + 1'd0: begin + etherbone_rx_converter_converter_source_payload_data[8:0] <= etherbone_rx_converter_converter_sink_payload_data; + end + 1'd1: begin + etherbone_rx_converter_converter_source_payload_data[17:9] <= etherbone_rx_converter_converter_sink_payload_data; + end + 2'd2: begin + etherbone_rx_converter_converter_source_payload_data[26:18] <= etherbone_rx_converter_converter_sink_payload_data; + end + 2'd3: begin + etherbone_rx_converter_converter_source_payload_data[35:27] <= etherbone_rx_converter_converter_sink_payload_data; + end + endcase + end + if (etherbone_rx_converter_converter_load_part) begin + etherbone_rx_converter_converter_source_payload_valid_token_count <= (etherbone_rx_converter_converter_demux + 1'd1); + end + if (etherbone_tx_packetizer_sr_load) begin + etherbone_tx_packetizer_sr <= etherbone_tx_packetizer_header; + end + if (etherbone_tx_packetizer_sr_shift) begin + etherbone_tx_packetizer_sr <= etherbone_tx_packetizer_sr[63:32]; + end + if (etherbone_tx_packetizer_source_ready) begin + etherbone_tx_packetizer_sink_d_valid <= etherbone_tx_packetizer_sink_valid; + etherbone_tx_packetizer_sink_d_ready <= etherbone_tx_packetizer_sink_ready; + etherbone_tx_packetizer_sink_d_first <= etherbone_tx_packetizer_sink_first; + etherbone_tx_packetizer_sink_d_last <= etherbone_tx_packetizer_sink_last; + etherbone_tx_packetizer_sink_d_payload_data <= etherbone_tx_packetizer_sink_payload_data; + etherbone_tx_packetizer_sink_d_payload_error <= etherbone_tx_packetizer_sink_payload_error; + etherbone_tx_packetizer_sink_d_param_addr_size <= etherbone_tx_packetizer_sink_param_addr_size; + etherbone_tx_packetizer_sink_d_param_magic <= etherbone_tx_packetizer_sink_param_magic; + etherbone_tx_packetizer_sink_d_param_nr <= etherbone_tx_packetizer_sink_param_nr; + etherbone_tx_packetizer_sink_d_param_pf <= etherbone_tx_packetizer_sink_param_pf; + etherbone_tx_packetizer_sink_d_param_port_size <= etherbone_tx_packetizer_sink_param_port_size; + etherbone_tx_packetizer_sink_d_param_pr <= etherbone_tx_packetizer_sink_param_pr; + etherbone_tx_packetizer_sink_d_param_version <= etherbone_tx_packetizer_sink_param_version; + end + liteethetherbonepackettx_liteethetherbonepacketpacketizer_state <= liteethetherbonepackettx_liteethetherbonepacketpacketizer_next_state; + if (etherbone_tx_packetizer_count_liteethetherbonepackettx_next_value_ce0) begin + etherbone_tx_packetizer_count <= etherbone_tx_packetizer_count_liteethetherbonepackettx_next_value0; + end + if (etherbone_tx_packetizer_fsm_from_idle_liteethetherbonepackettx_next_value_ce1) begin + etherbone_tx_packetizer_fsm_from_idle <= etherbone_tx_packetizer_fsm_from_idle_liteethetherbonepackettx_next_value1; + end + liteethetherbonepackettx_fsm_state <= liteethetherbonepackettx_fsm_next_state; + etherbone_rx_valid <= (etherbone_rx_depacketizer_source_valid & (etherbone_rx_depacketizer_source_param_magic == 15'd20079)); + if (etherbone_rx_depacketizer_sr_shift) begin + etherbone_rx_depacketizer_sr <= {etherbone_rx_depacketizer_sink_payload_data, etherbone_rx_depacketizer_sr[63:32]}; + end + if (etherbone_rx_depacketizer_sr_shift_leftover) begin + etherbone_rx_depacketizer_sr <= {etherbone_rx_depacketizer_sink_payload_data, etherbone_rx_depacketizer_sr[63:0]}; + end + if ((etherbone_rx_depacketizer_sink_valid & etherbone_rx_depacketizer_sink_ready)) begin + etherbone_rx_depacketizer_sink_d_valid <= etherbone_rx_depacketizer_sink_valid; + etherbone_rx_depacketizer_sink_d_ready <= etherbone_rx_depacketizer_sink_ready; + etherbone_rx_depacketizer_sink_d_first <= etherbone_rx_depacketizer_sink_first; + etherbone_rx_depacketizer_sink_d_last <= etherbone_rx_depacketizer_sink_last; + etherbone_rx_depacketizer_sink_d_payload_data <= etherbone_rx_depacketizer_sink_payload_data; + etherbone_rx_depacketizer_sink_d_payload_error <= etherbone_rx_depacketizer_sink_payload_error; + etherbone_rx_depacketizer_sink_d_param_src_port <= etherbone_rx_depacketizer_sink_param_src_port; + etherbone_rx_depacketizer_sink_d_param_dst_port <= etherbone_rx_depacketizer_sink_param_dst_port; + etherbone_rx_depacketizer_sink_d_param_ip_address <= etherbone_rx_depacketizer_sink_param_ip_address; + etherbone_rx_depacketizer_sink_d_param_length <= etherbone_rx_depacketizer_sink_param_length; + end + liteethetherbonepacketrx_liteethetherbonepacketdepacketizer_state <= liteethetherbonepacketrx_liteethetherbonepacketdepacketizer_next_state; + if (etherbone_rx_depacketizer_count_liteethetherbonepacketrx_next_value_ce0) begin + etherbone_rx_depacketizer_count <= etherbone_rx_depacketizer_count_liteethetherbonepacketrx_next_value0; + end + if (etherbone_rx_depacketizer_fsm_from_idle_liteethetherbonepacketrx_next_value_ce1) begin + etherbone_rx_depacketizer_fsm_from_idle <= etherbone_rx_depacketizer_fsm_from_idle_liteethetherbonepacketrx_next_value1; + end + liteethetherbonepacketrx_fsm_state <= liteethetherbonepacketrx_fsm_next_state; + liteethetherboneprobe_state <= liteethetherboneprobe_next_state; + if ((etherbone_record_sink_sink_valid & etherbone_record_sink_sink_ready)) begin + if (etherbone_record_first) begin + etherbone_record_last_ip_address <= etherbone_record_sink_sink_param_ip_address; + end + etherbone_record_first <= etherbone_record_sink_sink_last; + end + if (etherbone_record_depacketizer_sr_shift) begin + etherbone_record_depacketizer_sr <= etherbone_record_depacketizer_sink_payload_data; + end + if ((etherbone_record_depacketizer_sink_valid & etherbone_record_depacketizer_sink_ready)) begin + etherbone_record_depacketizer_sink_d_valid <= etherbone_record_depacketizer_sink_valid; + etherbone_record_depacketizer_sink_d_ready <= etherbone_record_depacketizer_sink_ready; + etherbone_record_depacketizer_sink_d_first <= etherbone_record_depacketizer_sink_first; + etherbone_record_depacketizer_sink_d_last <= etherbone_record_depacketizer_sink_last; + etherbone_record_depacketizer_sink_d_payload_data <= etherbone_record_depacketizer_sink_payload_data; + etherbone_record_depacketizer_sink_d_payload_error <= etherbone_record_depacketizer_sink_payload_error; + etherbone_record_depacketizer_sink_d_param_addr_size <= etherbone_record_depacketizer_sink_param_addr_size; + etherbone_record_depacketizer_sink_d_param_nr <= etherbone_record_depacketizer_sink_param_nr; + etherbone_record_depacketizer_sink_d_param_pf <= etherbone_record_depacketizer_sink_param_pf; + etherbone_record_depacketizer_sink_d_param_port_size <= etherbone_record_depacketizer_sink_param_port_size; + etherbone_record_depacketizer_sink_d_param_pr <= etherbone_record_depacketizer_sink_param_pr; + etherbone_record_depacketizer_sink_d_param_src_port <= etherbone_record_depacketizer_sink_param_src_port; + etherbone_record_depacketizer_sink_d_param_dst_port <= etherbone_record_depacketizer_sink_param_dst_port; + etherbone_record_depacketizer_sink_d_param_ip_address <= etherbone_record_depacketizer_sink_param_ip_address; + etherbone_record_depacketizer_sink_d_param_length <= etherbone_record_depacketizer_sink_param_length; + end + liteethetherbonerecorddepacketizer_state <= liteethetherbonerecorddepacketizer_next_state; + if (etherbone_record_depacketizer_count_liteethetherbonerecorddepacketizer_next_value_ce0) begin + etherbone_record_depacketizer_count <= etherbone_record_depacketizer_count_liteethetherbonerecorddepacketizer_next_value0; + end + if (etherbone_record_depacketizer_fsm_from_idle_liteethetherbonerecorddepacketizer_next_value_ce1) begin + etherbone_record_depacketizer_fsm_from_idle <= etherbone_record_depacketizer_fsm_from_idle_liteethetherbonerecorddepacketizer_next_value1; + end + if (etherbone_record_receiver_base_addr_update) begin + etherbone_record_receiver_base_addr <= etherbone_record_receiver_fifo_source_payload_data; + end + if (etherbone_record_receiver_counter_reset) begin + etherbone_record_receiver_counter <= 1'd0; + end else begin + if (etherbone_record_receiver_counter_ce) begin + etherbone_record_receiver_counter <= (etherbone_record_receiver_counter + 1'd1); + end + end + if (etherbone_record_receiver_fifo_syncfifo_re) begin + etherbone_record_receiver_fifo_readable <= 1'd1; + end else begin + if (etherbone_record_receiver_fifo_re) begin + etherbone_record_receiver_fifo_readable <= 1'd0; + end + end + if (((etherbone_record_receiver_fifo_syncfifo_we & etherbone_record_receiver_fifo_syncfifo_writable) & (~etherbone_record_receiver_fifo_replace))) begin + etherbone_record_receiver_fifo_produce <= (etherbone_record_receiver_fifo_produce + 1'd1); + end + if (etherbone_record_receiver_fifo_do_read) begin + etherbone_record_receiver_fifo_consume <= (etherbone_record_receiver_fifo_consume + 1'd1); + end + if (((etherbone_record_receiver_fifo_syncfifo_we & etherbone_record_receiver_fifo_syncfifo_writable) & (~etherbone_record_receiver_fifo_replace))) begin + if ((~etherbone_record_receiver_fifo_do_read)) begin + etherbone_record_receiver_fifo_level0 <= (etherbone_record_receiver_fifo_level0 + 1'd1); + end + end else begin + if (etherbone_record_receiver_fifo_do_read) begin + etherbone_record_receiver_fifo_level0 <= (etherbone_record_receiver_fifo_level0 - 1'd1); + end + end + liteethetherbonerecordreceiver_state <= liteethetherbonerecordreceiver_next_state; + etherbone_record_sender_source_source_param_byte_enable <= etherbone_record_sender_fifo_source_param_be; + if (etherbone_record_sender_fifo_source_param_we) begin + etherbone_record_sender_source_source_param_wcount <= etherbone_record_sender_fifo_source_param_count; + end else begin + etherbone_record_sender_source_source_param_rcount <= etherbone_record_sender_fifo_source_param_count; + end + if (etherbone_record_sender_data_sel) begin + etherbone_record_sender_source_source_payload_data <= etherbone_record_sender_fifo_source_payload_data; + end else begin + etherbone_record_sender_source_source_payload_data <= etherbone_record_sender_fifo_source_param_base_addr; + end + if (etherbone_record_sender_fifo_syncfifo_re) begin + etherbone_record_sender_fifo_readable <= 1'd1; + end else begin + if (etherbone_record_sender_fifo_re) begin + etherbone_record_sender_fifo_readable <= 1'd0; + end + end + if (((etherbone_record_sender_fifo_syncfifo_we & etherbone_record_sender_fifo_syncfifo_writable) & (~etherbone_record_sender_fifo_replace))) begin + etherbone_record_sender_fifo_produce <= (etherbone_record_sender_fifo_produce + 1'd1); + end + if (etherbone_record_sender_fifo_do_read) begin + etherbone_record_sender_fifo_consume <= (etherbone_record_sender_fifo_consume + 1'd1); + end + if (((etherbone_record_sender_fifo_syncfifo_we & etherbone_record_sender_fifo_syncfifo_writable) & (~etherbone_record_sender_fifo_replace))) begin + if ((~etherbone_record_sender_fifo_do_read)) begin + etherbone_record_sender_fifo_level0 <= (etherbone_record_sender_fifo_level0 + 1'd1); + end + end else begin + if (etherbone_record_sender_fifo_do_read) begin + etherbone_record_sender_fifo_level0 <= (etherbone_record_sender_fifo_level0 - 1'd1); + end + end + liteethetherbonerecordsender_state <= liteethetherbonerecordsender_next_state; + if (etherbone_record_packetizer_sr_load) begin + etherbone_record_packetizer_sr <= etherbone_record_packetizer_header; + end + if (etherbone_record_packetizer_source_ready) begin + etherbone_record_packetizer_sink_d_valid <= etherbone_record_packetizer_sink_valid; + etherbone_record_packetizer_sink_d_ready <= etherbone_record_packetizer_sink_ready; + etherbone_record_packetizer_sink_d_first <= etherbone_record_packetizer_sink_first; + etherbone_record_packetizer_sink_d_last <= etherbone_record_packetizer_sink_last; + etherbone_record_packetizer_sink_d_payload_data <= etherbone_record_packetizer_sink_payload_data; + etherbone_record_packetizer_sink_d_payload_error <= etherbone_record_packetizer_sink_payload_error; + etherbone_record_packetizer_sink_d_param_bca <= etherbone_record_packetizer_sink_param_bca; + etherbone_record_packetizer_sink_d_param_byte_enable <= etherbone_record_packetizer_sink_param_byte_enable; + etherbone_record_packetizer_sink_d_param_cyc <= etherbone_record_packetizer_sink_param_cyc; + etherbone_record_packetizer_sink_d_param_rca <= etherbone_record_packetizer_sink_param_rca; + etherbone_record_packetizer_sink_d_param_rcount <= etherbone_record_packetizer_sink_param_rcount; + etherbone_record_packetizer_sink_d_param_rff <= etherbone_record_packetizer_sink_param_rff; + etherbone_record_packetizer_sink_d_param_wca <= etherbone_record_packetizer_sink_param_wca; + etherbone_record_packetizer_sink_d_param_wcount <= etherbone_record_packetizer_sink_param_wcount; + etherbone_record_packetizer_sink_d_param_wff <= etherbone_record_packetizer_sink_param_wff; + end + liteethetherbonerecordpacketizer_state <= liteethetherbonerecordpacketizer_next_state; + if (etherbone_record_packetizer_count_liteethetherbonerecordpacketizer_next_value_ce0) begin + etherbone_record_packetizer_count <= etherbone_record_packetizer_count_liteethetherbonerecordpacketizer_next_value0; + end + if (etherbone_record_packetizer_fsm_from_idle_liteethetherbonerecordpacketizer_next_value_ce1) begin + etherbone_record_packetizer_fsm_from_idle <= etherbone_record_packetizer_fsm_from_idle_liteethetherbonerecordpacketizer_next_value1; + end + if (etherbone_dispatcher_first) begin + etherbone_dispatcher_sel_ongoing <= etherbone_dispatcher_sel0; + end + etherbone_dispatcher_ongoing1 <= ((etherbone_rx_source_source_valid | etherbone_dispatcher_ongoing1) & (~etherbone_dispatcher_last)); + if (etherbone_dispatcher_last) begin + etherbone_dispatcher_first <= 1'd1; + end else begin + if ((etherbone_rx_source_source_valid & etherbone_rx_source_source_ready)) begin + etherbone_dispatcher_first <= 1'd0; + end + end + case (etherbone_grant) + 1'd0: begin + if ((~etherbone_request[0])) begin + if (etherbone_request[1]) begin + etherbone_grant <= 1'd1; + end + end + end + 1'd1: begin + if ((~etherbone_request[1])) begin + if (etherbone_request[0]) begin + etherbone_grant <= 1'd0; + end + end + end + endcase + etherbone_status0_ongoing1 <= ((etherbone_probe_source_valid | etherbone_status0_ongoing1) & (~etherbone_status0_last)); + if (etherbone_status0_last) begin + etherbone_status0_first <= 1'd1; + end else begin + if ((etherbone_probe_source_valid & etherbone_probe_source_ready)) begin + etherbone_status0_first <= 1'd0; + end + end + etherbone_status1_ongoing1 <= ((etherbone_record_source_source_valid | etherbone_status1_ongoing1) & (~etherbone_status1_last)); + if (etherbone_status1_last) begin + etherbone_status1_first <= 1'd1; + end else begin + if ((etherbone_record_source_source_valid & etherbone_record_source_source_ready)) begin + etherbone_status1_first <= 1'd0; + end + end + etherbone_liteethetherbonewishbonemaster_source_param_base_addr <= etherbone_liteethetherbonewishbonemaster_sink_param_base_addr; + etherbone_liteethetherbonewishbonemaster_source_payload_addr <= etherbone_liteethetherbonewishbonemaster_sink_payload_addr; + etherbone_liteethetherbonewishbonemaster_source_param_count <= etherbone_liteethetherbonewishbonemaster_sink_param_count; + etherbone_liteethetherbonewishbonemaster_source_param_be <= etherbone_liteethetherbonewishbonemaster_sink_param_be; + etherbone_liteethetherbonewishbonemaster_source_param_we <= 1'd1; + if (etherbone_liteethetherbonewishbonemaster_data_update) begin + etherbone_liteethetherbonewishbonemaster_source_payload_data <= etherbone_liteethetherbonewishbonemaster_bus_dat_r; + end + liteethetherbonewishbonemaster_state <= liteethetherbonewishbonemaster_next_state; + if (((~s7pciephy_tx_datapath_pipe_valid_source_valid) | s7pciephy_tx_datapath_pipe_valid_source_ready)) begin + s7pciephy_tx_datapath_pipe_valid_source_valid <= s7pciephy_tx_datapath_pipe_valid_sink_valid; + s7pciephy_tx_datapath_pipe_valid_source_first <= s7pciephy_tx_datapath_pipe_valid_sink_first; + s7pciephy_tx_datapath_pipe_valid_source_last <= s7pciephy_tx_datapath_pipe_valid_sink_last; + s7pciephy_tx_datapath_pipe_valid_source_payload_dat <= s7pciephy_tx_datapath_pipe_valid_sink_payload_dat; + s7pciephy_tx_datapath_pipe_valid_source_payload_be <= s7pciephy_tx_datapath_pipe_valid_sink_payload_be; + end + s7pciephy_tx_datapath_cdc_graycounter0_q_binary <= s7pciephy_tx_datapath_cdc_graycounter0_q_next_binary; + s7pciephy_tx_datapath_cdc_graycounter0_q <= s7pciephy_tx_datapath_cdc_graycounter0_q_next; + s7pciephy_rx_datapath_cdc_graycounter1_q_binary <= s7pciephy_rx_datapath_cdc_graycounter1_q_next_binary; + s7pciephy_rx_datapath_cdc_graycounter1_q <= s7pciephy_rx_datapath_cdc_graycounter1_q_next; + if (((~s7pciephy_rx_datapath_pipe_valid_source_valid) | s7pciephy_rx_datapath_pipe_valid_source_ready)) begin + s7pciephy_rx_datapath_pipe_valid_source_valid <= s7pciephy_rx_datapath_pipe_valid_sink_valid; + s7pciephy_rx_datapath_pipe_valid_source_first <= s7pciephy_rx_datapath_pipe_valid_sink_first; + s7pciephy_rx_datapath_pipe_valid_source_last <= s7pciephy_rx_datapath_pipe_valid_sink_last; + s7pciephy_rx_datapath_pipe_valid_source_payload_dat <= s7pciephy_rx_datapath_pipe_valid_sink_payload_dat; + s7pciephy_rx_datapath_pipe_valid_source_payload_be <= s7pciephy_rx_datapath_pipe_valid_sink_payload_be; + end + s7pciephy_msi_cdc_graycounter0_q_binary <= s7pciephy_msi_cdc_graycounter0_q_next_binary; + s7pciephy_msi_cdc_graycounter0_q <= s7pciephy_msi_cdc_graycounter0_q_next; + if ((depacketizer_header_extracter_sink_valid & depacketizer_header_extracter_sink_ready)) begin + depacketizer_header_extracter_dat <= depacketizer_header_extracter_sink_payload_dat; + depacketizer_header_extracter_be <= depacketizer_header_extracter_sink_payload_be; + end + litepcietlpdepacketizer_state <= litepcietlpdepacketizer_next_state; + if (depacketizer_header_extracter_first_litepcietlpdepacketizer_next_value_ce0) begin + depacketizer_header_extracter_first <= depacketizer_header_extracter_first_litepcietlpdepacketizer_next_value0; + end + if (depacketizer_header_extracter_last_litepcietlpdepacketizer_next_value_ce1) begin + depacketizer_header_extracter_last <= depacketizer_header_extracter_last_litepcietlpdepacketizer_next_value1; + end + if (depacketizer_header_extracter_count_litepcietlpdepacketizer_next_value_ce2) begin + depacketizer_header_extracter_count <= depacketizer_header_extracter_count_litepcietlpdepacketizer_next_value2; + end + if (litepcietlpdepacketizer_next_value_ce0) begin + depacketizer_header_extracter_source_payload_header[31:0] <= litepcietlpdepacketizer_next_value0; + end + if (litepcietlpdepacketizer_next_value_ce1) begin + depacketizer_header_extracter_source_payload_header[63:32] <= litepcietlpdepacketizer_next_value1; + end + if (litepcietlpdepacketizer_next_value_ce2) begin + depacketizer_header_extracter_source_payload_header[95:64] <= litepcietlpdepacketizer_next_value2; + end + if (litepcietlpdepacketizer_next_value_ce3) begin + depacketizer_header_extracter_source_payload_header[127:96] <= litepcietlpdepacketizer_next_value3; + end + if (depacketizer_dispatcher_first) begin + depacketizer_dispatcher_sel_ongoing <= depacketizer_dispatcher_sel0; + end + depacketizer_dispatcher_ongoing1 <= ((depacketizer_dispatch_source_valid | depacketizer_dispatcher_ongoing1) & (~depacketizer_dispatcher_last)); + if (depacketizer_dispatcher_last) begin + depacketizer_dispatcher_first <= 1'd1; + end else begin + if ((depacketizer_dispatch_source_valid & depacketizer_dispatch_source_ready)) begin + depacketizer_dispatcher_first <= 1'd0; + end + end + case (packetizer_grant) + 1'd0: begin + if ((~packetizer_request[0])) begin + if (packetizer_request[1]) begin + packetizer_grant <= 1'd1; + end + end + end + 1'd1: begin + if ((~packetizer_request[1])) begin + if (packetizer_request[0]) begin + packetizer_grant <= 1'd0; + end + end + end + endcase + packetizer_status0_ongoing1 <= ((packetizer_tlp_raw_req_valid | packetizer_status0_ongoing1) & (~packetizer_status0_last)); + if (packetizer_status0_last) begin + packetizer_status0_first <= 1'd1; + end else begin + if ((packetizer_tlp_raw_req_valid & packetizer_tlp_raw_req_ready)) begin + packetizer_status0_first <= 1'd0; + end + end + packetizer_status1_ongoing1 <= ((packetizer_tlp_raw_cmp_valid | packetizer_status1_ongoing1) & (~packetizer_status1_last)); + if (packetizer_status1_last) begin + packetizer_status1_first <= 1'd1; + end else begin + if ((packetizer_tlp_raw_cmp_valid & packetizer_tlp_raw_cmp_ready)) begin + packetizer_status1_first <= 1'd0; + end + end + if ((packetizer_header_inserter_sink_valid & packetizer_header_inserter_sink_ready)) begin + packetizer_header_inserter_dat <= packetizer_header_inserter_sink_payload_dat; + packetizer_header_inserter_last <= packetizer_header_inserter_sink_last; + end + litepcietlppacketizer_state <= litepcietlppacketizer_next_state; + if (tags_queue_syncfifo_re) begin + tags_queue_readable <= 1'd1; + end else begin + if (tags_queue_re) begin + tags_queue_readable <= 1'd0; + end + end + if (((tags_queue_syncfifo_we & tags_queue_syncfifo_writable) & (~tags_queue_replace))) begin + tags_queue_produce <= (tags_queue_produce + 1'd1); + end + if (tags_queue_do_read) begin + tags_queue_consume <= (tags_queue_consume + 1'd1); + end + if (((tags_queue_syncfifo_we & tags_queue_syncfifo_writable) & (~tags_queue_replace))) begin + if ((~tags_queue_do_read)) begin + tags_queue_level0 <= (tags_queue_level0 + 1'd1); + end + end else begin + if (tags_queue_do_read) begin + tags_queue_level0 <= (tags_queue_level0 - 1'd1); + end + end + if (requests_queue_syncfifo_re) begin + requests_queue_readable <= 1'd1; + end else begin + if (requests_queue_re) begin + requests_queue_readable <= 1'd0; + end + end + if (((requests_queue_syncfifo_we & requests_queue_syncfifo_writable) & (~requests_queue_replace))) begin + requests_queue_produce <= (requests_queue_produce + 1'd1); + end + if (requests_queue_do_read) begin + requests_queue_consume <= (requests_queue_consume + 1'd1); + end + if (((requests_queue_syncfifo_we & requests_queue_syncfifo_writable) & (~requests_queue_replace))) begin + if ((~requests_queue_do_read)) begin + requests_queue_level0 <= (requests_queue_level0 + 1'd1); + end + end else begin + if (requests_queue_do_read) begin + requests_queue_level0 <= (requests_queue_level0 - 1'd1); + end + end + fsm0_state0 <= fsm0_next_state0; + if (syncfifo0_syncfifo0_re) begin + syncfifo0_readable <= 1'd1; + end else begin + if (syncfifo0_re) begin + syncfifo0_readable <= 1'd0; + end + end + if (((syncfifo0_syncfifo0_we & syncfifo0_syncfifo0_writable) & (~syncfifo0_replace))) begin + syncfifo0_produce <= (syncfifo0_produce + 1'd1); + end + if (syncfifo0_do_read) begin + syncfifo0_consume <= (syncfifo0_consume + 1'd1); + end + if (((syncfifo0_syncfifo0_we & syncfifo0_syncfifo0_writable) & (~syncfifo0_replace))) begin + if ((~syncfifo0_do_read)) begin + syncfifo0_level0 <= (syncfifo0_level0 + 1'd1); + end + end else begin + if (syncfifo0_do_read) begin + syncfifo0_level0 <= (syncfifo0_level0 - 1'd1); + end + end + if (syncfifo1_syncfifo1_re) begin + syncfifo1_readable <= 1'd1; + end else begin + if (syncfifo1_re) begin + syncfifo1_readable <= 1'd0; + end + end + if (((syncfifo1_syncfifo1_we & syncfifo1_syncfifo1_writable) & (~syncfifo1_replace))) begin + syncfifo1_produce <= (syncfifo1_produce + 1'd1); + end + if (syncfifo1_do_read) begin + syncfifo1_consume <= (syncfifo1_consume + 1'd1); + end + if (((syncfifo1_syncfifo1_we & syncfifo1_syncfifo1_writable) & (~syncfifo1_replace))) begin + if ((~syncfifo1_do_read)) begin + syncfifo1_level0 <= (syncfifo1_level0 + 1'd1); + end + end else begin + if (syncfifo1_do_read) begin + syncfifo1_level0 <= (syncfifo1_level0 - 1'd1); + end + end + if (syncfifo2_syncfifo2_re) begin + syncfifo2_readable <= 1'd1; + end else begin + if (syncfifo2_re) begin + syncfifo2_readable <= 1'd0; + end + end + if (((syncfifo2_syncfifo2_we & syncfifo2_syncfifo2_writable) & (~syncfifo2_replace))) begin + syncfifo2_produce <= (syncfifo2_produce + 1'd1); + end + if (syncfifo2_do_read) begin + syncfifo2_consume <= (syncfifo2_consume + 1'd1); + end + if (((syncfifo2_syncfifo2_we & syncfifo2_syncfifo2_writable) & (~syncfifo2_replace))) begin + if ((~syncfifo2_do_read)) begin + syncfifo2_level0 <= (syncfifo2_level0 + 1'd1); + end + end else begin + if (syncfifo2_do_read) begin + syncfifo2_level0 <= (syncfifo2_level0 - 1'd1); + end + end + if (syncfifo3_syncfifo3_re) begin + syncfifo3_readable <= 1'd1; + end else begin + if (syncfifo3_re) begin + syncfifo3_readable <= 1'd0; + end + end + if (((syncfifo3_syncfifo3_we & syncfifo3_syncfifo3_writable) & (~syncfifo3_replace))) begin + syncfifo3_produce <= (syncfifo3_produce + 1'd1); + end + if (syncfifo3_do_read) begin + syncfifo3_consume <= (syncfifo3_consume + 1'd1); + end + if (((syncfifo3_syncfifo3_we & syncfifo3_syncfifo3_writable) & (~syncfifo3_replace))) begin + if ((~syncfifo3_do_read)) begin + syncfifo3_level0 <= (syncfifo3_level0 + 1'd1); + end + end else begin + if (syncfifo3_do_read) begin + syncfifo3_level0 <= (syncfifo3_level0 - 1'd1); + end + end + fsm1_state0 <= fsm1_next_state0; + if (fill_tag_litepciecrossbar_next_value_ce) begin + fill_tag <= fill_tag_litepciecrossbar_next_value; + end + case (arbiter0_grant) + 1'd0: begin + if ((~arbiter0_request[0])) begin + if (arbiter0_request[1]) begin + arbiter0_grant <= 1'd1; + end + end + end + 1'd1: begin + if ((~arbiter0_request[1])) begin + if (arbiter0_request[0]) begin + arbiter0_grant <= 1'd0; + end + end + end + endcase + arbiter0_status0_ongoing1 <= ((pcie_dma0_litepciemasterinternalport1_sink_valid | arbiter0_status0_ongoing1) & (~arbiter0_status0_last)); + if (arbiter0_status0_last) begin + arbiter0_status0_first <= 1'd1; + end else begin + if ((pcie_dma0_litepciemasterinternalport1_sink_valid & pcie_dma0_litepciemasterinternalport1_sink_ready)) begin + arbiter0_status0_first <= 1'd0; + end + end + arbiter0_status1_ongoing1 <= ((pcie_dma1_litepciemasterinternalport1_sink_valid | arbiter0_status1_ongoing1) & (~arbiter0_status1_last)); + if (arbiter0_status1_last) begin + arbiter0_status1_first <= 1'd1; + end else begin + if ((pcie_dma1_litepciemasterinternalport1_sink_valid & pcie_dma1_litepciemasterinternalport1_sink_ready)) begin + arbiter0_status1_first <= 1'd0; + end + end + if (dispatcher0_first) begin + dispatcher0_sel_ongoing <= dispatcher0_sel0; + end + dispatcher0_ongoing1 <= ((master_in_source_valid | dispatcher0_ongoing1) & (~dispatcher0_last)); + if (dispatcher0_last) begin + dispatcher0_first <= 1'd1; + end else begin + if ((master_in_source_valid & master_in_source_ready)) begin + dispatcher0_first <= 1'd0; + end + end + case (arbiter1_grant) + 1'd0: begin + if ((~arbiter1_request[0])) begin + if (arbiter1_request[1]) begin + arbiter1_grant <= 1'd1; + end + end + end + 1'd1: begin + if ((~arbiter1_request[1])) begin + if (arbiter1_request[0]) begin + arbiter1_grant <= 1'd0; + end + end + end + endcase + arbiter1_status2_ongoing1 <= ((pcie_dma0_litepciemasterinternalport0_sink_valid | arbiter1_status2_ongoing1) & (~arbiter1_status2_last)); + if (arbiter1_status2_last) begin + arbiter1_status2_first <= 1'd1; + end else begin + if ((pcie_dma0_litepciemasterinternalport0_sink_valid & pcie_dma0_litepciemasterinternalport0_sink_ready)) begin + arbiter1_status2_first <= 1'd0; + end + end + arbiter1_status3_ongoing1 <= ((pcie_dma1_litepciemasterinternalport0_sink_valid | arbiter1_status3_ongoing1) & (~arbiter1_status3_last)); + if (arbiter1_status3_last) begin + arbiter1_status3_first <= 1'd1; + end else begin + if ((pcie_dma1_litepciemasterinternalport0_sink_valid & pcie_dma1_litepciemasterinternalport0_sink_ready)) begin + arbiter1_status3_first <= 1'd0; + end + end + if (dispatcher1_first) begin + dispatcher1_sel_ongoing <= dispatcher1_sel0; + end + dispatcher1_ongoing1 <= ((source_valid | dispatcher1_ongoing1) & (~dispatcher1_last)); + if (dispatcher1_last) begin + dispatcher1_first <= 1'd1; + end else begin + if ((source_valid & source_ready)) begin + dispatcher1_first <= 1'd0; + end + end + case (arbiter2_grant) + 1'd0: begin + if ((~arbiter2_request[0])) begin + if (arbiter2_request[1]) begin + arbiter2_grant <= 1'd1; + end + end + end + 1'd1: begin + if ((~arbiter2_request[1])) begin + if (arbiter2_request[0]) begin + arbiter2_grant <= 1'd0; + end + end + end + endcase + arbiter2_status4_ongoing1 <= ((master_out_sink_valid | arbiter2_status4_ongoing1) & (~arbiter2_status4_last)); + if (arbiter2_status4_last) begin + arbiter2_status4_first <= 1'd1; + end else begin + if ((master_out_sink_valid & master_out_sink_ready)) begin + arbiter2_status4_first <= 1'd0; + end + end + arbiter2_status5_ongoing1 <= ((sink_valid | arbiter2_status5_ongoing1) & (~arbiter2_status5_last)); + if (arbiter2_status5_last) begin + arbiter2_status5_first <= 1'd1; + end else begin + if ((sink_valid & sink_ready)) begin + arbiter2_status5_first <= 1'd0; + end + end + pcie_bridge_wishbone_sel <= 4'd15; + pcie_bridge_wishbone_adr <= (pcie_bridge_source_payload_adr[31:2] + 30'd545259520); + if (1'd0) begin + if (pcie_bridge_source_payload_adr[2]) begin + pcie_bridge_wishbone_dat_w <= pcie_bridge_source_payload_dat[31:0]; + end else begin + pcie_bridge_wishbone_dat_w <= pcie_bridge_source_payload_dat[63:32]; + end + end else begin + pcie_bridge_wishbone_dat_w <= pcie_bridge_source_payload_dat[31:0]; + end + pcie_bridge_sink_first <= 1'd1; + pcie_bridge_sink_last <= 1'd1; + pcie_bridge_sink_payload_len <= 1'd1; + pcie_bridge_sink_payload_err <= 1'd0; + pcie_bridge_sink_payload_tag <= pcie_bridge_source_payload_tag; + pcie_bridge_sink_payload_adr <= pcie_bridge_source_payload_adr; + pcie_bridge_sink_payload_cmp_id <= s7pciephy_id; + pcie_bridge_sink_payload_req_id <= pcie_bridge_source_payload_req_id; + if (pcie_bridge_update_dat) begin + pcie_bridge_sink_payload_dat <= pcie_bridge_wishbone_dat_r; + end + litepciewishbonebridge_state <= litepciewishbonebridge_next_state; + if (pcie_dma0_writer_loop_prog_n_storage) begin + pcie_dma0_writer_fifo_sink_payload_address <= pcie_dma0_writer_fifo_source_payload_address; + pcie_dma0_writer_fifo_sink_payload_length <= pcie_dma0_writer_fifo_source_payload_length; + pcie_dma0_writer_fifo_sink_payload_control <= pcie_dma0_writer_fifo_source_payload_control; + pcie_dma0_writer_fifo_sink_first <= pcie_dma0_writer_fifo_source_first; + pcie_dma0_writer_fifo_sink_valid <= pcie_dma0_writer_fifo_source_ready; + end else begin + pcie_dma0_writer_fifo_sink_payload_address <= pcie_dma0_writer_address; + pcie_dma0_writer_fifo_sink_payload_length <= pcie_dma0_writer_length; + pcie_dma0_writer_fifo_sink_payload_control <= {pcie_dma0_writer_last_disable, pcie_dma0_writer_irq_disable}; + pcie_dma0_writer_fifo_sink_first <= (~pcie_dma0_writer_fifo_source_valid); + pcie_dma0_writer_fifo_sink_valid <= (pcie_dma0_writer_we_storage & pcie_dma0_writer_we_re); + end + if ((pcie_dma0_writer_flush_storage & pcie_dma0_writer_flush_re)) begin + pcie_dma0_writer_loop_first <= 1'd1; + pcie_dma0_writer_loop_index <= 1'd0; + pcie_dma0_writer_loop_count <= 1'd0; + pcie_dma0_writer_index <= 1'd0; + pcie_dma0_writer_count <= 1'd0; + end else begin + if ((pcie_dma0_writer_source_source_valid & pcie_dma0_writer_source_source_ready)) begin + pcie_dma0_writer_index <= pcie_dma0_writer_loop_index; + pcie_dma0_writer_count <= pcie_dma0_writer_loop_count; + if (pcie_dma0_writer_source_source_first) begin + pcie_dma0_writer_loop_first <= 1'd0; + pcie_dma0_writer_loop_index <= 1'd0; + if ((~pcie_dma0_writer_loop_first)) begin + pcie_dma0_writer_loop_count <= (pcie_dma0_writer_loop_count + 1'd1); + end + end else begin + pcie_dma0_writer_loop_index <= (pcie_dma0_writer_loop_index + 1'd1); + end + end + end + if (((pcie_dma0_writer_fifo_syncfifo_we0 & pcie_dma0_writer_fifo_syncfifo_writable0) & (~pcie_dma0_writer_fifo_replace0))) begin + pcie_dma0_writer_fifo_produce0 <= (pcie_dma0_writer_fifo_produce0 + 1'd1); + end + if (pcie_dma0_writer_fifo_do_read0) begin + pcie_dma0_writer_fifo_consume0 <= (pcie_dma0_writer_fifo_consume0 + 1'd1); + end + if (((pcie_dma0_writer_fifo_syncfifo_we0 & pcie_dma0_writer_fifo_syncfifo_writable0) & (~pcie_dma0_writer_fifo_replace0))) begin + if ((~pcie_dma0_writer_fifo_do_read0)) begin + pcie_dma0_writer_fifo_level0 <= (pcie_dma0_writer_fifo_level0 + 1'd1); + end + end else begin + if (pcie_dma0_writer_fifo_do_read0) begin + pcie_dma0_writer_fifo_level0 <= (pcie_dma0_writer_fifo_level0 - 1'd1); + end + end + if (pcie_dma0_writer_fifo_reset) begin + pcie_dma0_writer_fifo_level0 <= 9'd0; + pcie_dma0_writer_fifo_produce0 <= 8'd0; + pcie_dma0_writer_fifo_consume0 <= 8'd0; + end + bufferizeendpoints0_state0 <= bufferizeendpoints0_next_state0; + if (pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_bufferizeendpoints0_next_value_ce0) begin + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_offset <= pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_bufferizeendpoints0_next_value0; + end + if (pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_user_id_litepciedma0_bufferizeendpoints0_next_value_ce1) begin + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_user_id <= pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_user_id_litepciedma0_bufferizeendpoints0_next_value1; + end + if (((~pcie_dma0_writer_splitter_bufferizeendpoints_source_valid) | pcie_dma0_writer_splitter_bufferizeendpoints_source_ready)) begin + pcie_dma0_writer_splitter_bufferizeendpoints_source_valid <= pcie_dma0_writer_splitter_bufferizeendpoints_sink_valid; + pcie_dma0_writer_splitter_bufferizeendpoints_source_first <= pcie_dma0_writer_splitter_bufferizeendpoints_sink_first; + pcie_dma0_writer_splitter_bufferizeendpoints_source_last <= pcie_dma0_writer_splitter_bufferizeendpoints_sink_last; + pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_address <= pcie_dma0_writer_splitter_bufferizeendpoints_sink_payload_address; + pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_length <= pcie_dma0_writer_splitter_bufferizeendpoints_sink_payload_length; + pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_control <= pcie_dma0_writer_splitter_bufferizeendpoints_sink_payload_control; + pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_user_id <= pcie_dma0_writer_splitter_bufferizeendpoints_sink_payload_user_id; + end + if (pcie_dma0_writer_splitter_reset) begin + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_offset <= 32'd0; + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_user_id <= 32'd0; + pcie_dma0_writer_splitter_bufferizeendpoints_source_valid <= 1'd0; + pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_address <= 32'd0; + pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_length <= 24'd0; + pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_control <= 8'd0; + pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_user_id <= 8'd0; + bufferizeendpoints0_state0 <= 2'd0; + end + if (pcie_dma0_writer_fifo_syncfifo_re1) begin + pcie_dma0_writer_fifo_readable <= 1'd1; + end else begin + if (pcie_dma0_writer_fifo_re) begin + pcie_dma0_writer_fifo_readable <= 1'd0; + end + end + if (((pcie_dma0_writer_fifo_syncfifo_we1 & pcie_dma0_writer_fifo_syncfifo_writable1) & (~pcie_dma0_writer_fifo_replace1))) begin + pcie_dma0_writer_fifo_produce1 <= (pcie_dma0_writer_fifo_produce1 + 1'd1); + end + if (pcie_dma0_writer_fifo_do_read1) begin + pcie_dma0_writer_fifo_consume1 <= (pcie_dma0_writer_fifo_consume1 + 1'd1); + end + if (((pcie_dma0_writer_fifo_syncfifo_we1 & pcie_dma0_writer_fifo_syncfifo_writable1) & (~pcie_dma0_writer_fifo_replace1))) begin + if ((~pcie_dma0_writer_fifo_do_read1)) begin + pcie_dma0_writer_fifo_level1 <= (pcie_dma0_writer_fifo_level1 + 1'd1); + end + end else begin + if (pcie_dma0_writer_fifo_do_read1) begin + pcie_dma0_writer_fifo_level1 <= (pcie_dma0_writer_fifo_level1 - 1'd1); + end + end + if (pcie_dma0_writer_resetinserter_reset) begin + pcie_dma0_writer_fifo_readable <= 1'd0; + pcie_dma0_writer_fifo_level1 <= 9'd0; + pcie_dma0_writer_fifo_produce1 <= 8'd0; + pcie_dma0_writer_fifo_consume1 <= 8'd0; + end + fsm0_state1 <= fsm0_next_state1; + if (pcie_dma0_writer_counter_litepciedma0_fsm0_next_value_ce) begin + pcie_dma0_writer_counter <= pcie_dma0_writer_counter_litepciedma0_fsm0_next_value; + end + if (((pcie_dma0_litepciemasterinternalport1_source_valid & pcie_dma0_litepciemasterinternalport1_source_first) & pcie_dma0_litepciemasterinternalport1_source_ready)) begin + pcie_dma0_reader_last_user_id <= pcie_dma0_litepciemasterinternalport1_source_payload_user_id; + end + if ((~pcie_dma0_reader_enable_storage)) begin + pcie_dma0_reader_pending_words <= 1'd0; + end else begin + pcie_dma0_reader_pending_words <= ((pcie_dma0_reader_pending_words + pcie_dma0_reader_pending_words_queue) - pcie_dma0_reader_pending_words_dequeue); + end + if (pcie_dma0_reader_loop_prog_n_storage) begin + pcie_dma0_reader_fifo_sink_payload_address <= pcie_dma0_reader_fifo_source_payload_address; + pcie_dma0_reader_fifo_sink_payload_length <= pcie_dma0_reader_fifo_source_payload_length; + pcie_dma0_reader_fifo_sink_payload_control <= pcie_dma0_reader_fifo_source_payload_control; + pcie_dma0_reader_fifo_sink_first0 <= pcie_dma0_reader_fifo_source_first0; + pcie_dma0_reader_fifo_sink_valid0 <= pcie_dma0_reader_fifo_source_ready0; + end else begin + pcie_dma0_reader_fifo_sink_payload_address <= pcie_dma0_reader_address; + pcie_dma0_reader_fifo_sink_payload_length <= pcie_dma0_reader_length; + pcie_dma0_reader_fifo_sink_payload_control <= {pcie_dma0_reader_last_disable, pcie_dma0_reader_irq_disable}; + pcie_dma0_reader_fifo_sink_first0 <= (~pcie_dma0_reader_fifo_source_valid0); + pcie_dma0_reader_fifo_sink_valid0 <= (pcie_dma0_reader_we_storage & pcie_dma0_reader_we_re); + end + if ((pcie_dma0_reader_flush_storage & pcie_dma0_reader_flush_re)) begin + pcie_dma0_reader_loop_first <= 1'd1; + pcie_dma0_reader_loop_index <= 1'd0; + pcie_dma0_reader_loop_count <= 1'd0; + pcie_dma0_reader_index <= 1'd0; + pcie_dma0_reader_count <= 1'd0; + end else begin + if ((pcie_dma0_reader_source_source_valid1 & pcie_dma0_reader_source_source_ready1)) begin + pcie_dma0_reader_index <= pcie_dma0_reader_loop_index; + pcie_dma0_reader_count <= pcie_dma0_reader_loop_count; + if (pcie_dma0_reader_source_source_first1) begin + pcie_dma0_reader_loop_first <= 1'd0; + pcie_dma0_reader_loop_index <= 1'd0; + if ((~pcie_dma0_reader_loop_first)) begin + pcie_dma0_reader_loop_count <= (pcie_dma0_reader_loop_count + 1'd1); + end + end else begin + pcie_dma0_reader_loop_index <= (pcie_dma0_reader_loop_index + 1'd1); + end + end + end + if (((pcie_dma0_reader_fifo_syncfifo_we0 & pcie_dma0_reader_fifo_syncfifo_writable0) & (~pcie_dma0_reader_fifo_replace0))) begin + pcie_dma0_reader_fifo_produce0 <= (pcie_dma0_reader_fifo_produce0 + 1'd1); + end + if (pcie_dma0_reader_fifo_do_read0) begin + pcie_dma0_reader_fifo_consume0 <= (pcie_dma0_reader_fifo_consume0 + 1'd1); + end + if (((pcie_dma0_reader_fifo_syncfifo_we0 & pcie_dma0_reader_fifo_syncfifo_writable0) & (~pcie_dma0_reader_fifo_replace0))) begin + if ((~pcie_dma0_reader_fifo_do_read0)) begin + pcie_dma0_reader_fifo_level0 <= (pcie_dma0_reader_fifo_level0 + 1'd1); + end + end else begin + if (pcie_dma0_reader_fifo_do_read0) begin + pcie_dma0_reader_fifo_level0 <= (pcie_dma0_reader_fifo_level0 - 1'd1); + end + end + if (pcie_dma0_reader_fifo_reset0) begin + pcie_dma0_reader_fifo_level0 <= 9'd0; + pcie_dma0_reader_fifo_produce0 <= 8'd0; + pcie_dma0_reader_fifo_consume0 <= 8'd0; + end + bufferizeendpoints0_state1 <= bufferizeendpoints0_next_state1; + if (pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_next_value_ce0) begin + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_offset <= pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma0_next_value0; + end + if (pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_user_id_litepciedma0_next_value_ce1) begin + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_user_id <= pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_user_id_litepciedma0_next_value1; + end + if (((~pcie_dma0_reader_splitter_bufferizeendpoints_source_valid) | pcie_dma0_reader_splitter_bufferizeendpoints_source_ready)) begin + pcie_dma0_reader_splitter_bufferizeendpoints_source_valid <= pcie_dma0_reader_splitter_bufferizeendpoints_sink_valid; + pcie_dma0_reader_splitter_bufferizeendpoints_source_first <= pcie_dma0_reader_splitter_bufferizeendpoints_sink_first; + pcie_dma0_reader_splitter_bufferizeendpoints_source_last <= pcie_dma0_reader_splitter_bufferizeendpoints_sink_last; + pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_address <= pcie_dma0_reader_splitter_bufferizeendpoints_sink_payload_address; + pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_length <= pcie_dma0_reader_splitter_bufferizeendpoints_sink_payload_length; + pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_control <= pcie_dma0_reader_splitter_bufferizeendpoints_sink_payload_control; + pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_user_id <= pcie_dma0_reader_splitter_bufferizeendpoints_sink_payload_user_id; + end + if (pcie_dma0_reader_splitter_reset) begin + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_offset <= 32'd0; + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_user_id <= 32'd0; + pcie_dma0_reader_splitter_bufferizeendpoints_source_valid <= 1'd0; + pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_address <= 32'd0; + pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_length <= 24'd0; + pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_control <= 8'd0; + pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_user_id <= 8'd0; + bufferizeendpoints0_state1 <= 2'd0; + end + if (pcie_dma0_reader_fifo_syncfifo_re1) begin + pcie_dma0_reader_fifo_readable <= 1'd1; + end else begin + if (pcie_dma0_reader_fifo_re) begin + pcie_dma0_reader_fifo_readable <= 1'd0; + end + end + if (((pcie_dma0_reader_fifo_syncfifo_we1 & pcie_dma0_reader_fifo_syncfifo_writable1) & (~pcie_dma0_reader_fifo_replace1))) begin + pcie_dma0_reader_fifo_produce1 <= (pcie_dma0_reader_fifo_produce1 + 1'd1); + end + if (pcie_dma0_reader_fifo_do_read1) begin + pcie_dma0_reader_fifo_consume1 <= (pcie_dma0_reader_fifo_consume1 + 1'd1); + end + if (((pcie_dma0_reader_fifo_syncfifo_we1 & pcie_dma0_reader_fifo_syncfifo_writable1) & (~pcie_dma0_reader_fifo_replace1))) begin + if ((~pcie_dma0_reader_fifo_do_read1)) begin + pcie_dma0_reader_fifo_level1 <= (pcie_dma0_reader_fifo_level1 + 1'd1); + end + end else begin + if (pcie_dma0_reader_fifo_do_read1) begin + pcie_dma0_reader_fifo_level1 <= (pcie_dma0_reader_fifo_level1 - 1'd1); + end + end + if (pcie_dma0_reader_fifo_reset1) begin + pcie_dma0_reader_fifo_readable <= 1'd0; + pcie_dma0_reader_fifo_level1 <= 11'd0; + pcie_dma0_reader_fifo_produce1 <= 10'd0; + pcie_dma0_reader_fifo_consume1 <= 10'd0; + end + fsm0_state2 <= fsm0_next_state2; + if (pcie_dma0_buffering_reader_fifo_syncfifo_re) begin + pcie_dma0_buffering_reader_fifo_readable <= 1'd1; + end else begin + if (pcie_dma0_buffering_reader_fifo_re) begin + pcie_dma0_buffering_reader_fifo_readable <= 1'd0; + end + end + if (((pcie_dma0_buffering_reader_fifo_syncfifo_we & pcie_dma0_buffering_reader_fifo_syncfifo_writable) & (~pcie_dma0_buffering_reader_fifo_replace))) begin + pcie_dma0_buffering_reader_fifo_produce <= (pcie_dma0_buffering_reader_fifo_produce + 1'd1); + end + if (pcie_dma0_buffering_reader_fifo_do_read) begin + pcie_dma0_buffering_reader_fifo_consume <= (pcie_dma0_buffering_reader_fifo_consume + 1'd1); + end + if (((pcie_dma0_buffering_reader_fifo_syncfifo_we & pcie_dma0_buffering_reader_fifo_syncfifo_writable) & (~pcie_dma0_buffering_reader_fifo_replace))) begin + if ((~pcie_dma0_buffering_reader_fifo_do_read)) begin + pcie_dma0_buffering_reader_fifo_level0 <= (pcie_dma0_buffering_reader_fifo_level0 + 1'd1); + end + end else begin + if (pcie_dma0_buffering_reader_fifo_do_read) begin + pcie_dma0_buffering_reader_fifo_level0 <= (pcie_dma0_buffering_reader_fifo_level0 - 1'd1); + end + end + if (pcie_dma0_buffering_writer_fifo_syncfifo_re) begin + pcie_dma0_buffering_writer_fifo_readable <= 1'd1; + end else begin + if (pcie_dma0_buffering_writer_fifo_re) begin + pcie_dma0_buffering_writer_fifo_readable <= 1'd0; + end + end + if (((pcie_dma0_buffering_writer_fifo_syncfifo_we & pcie_dma0_buffering_writer_fifo_syncfifo_writable) & (~pcie_dma0_buffering_writer_fifo_replace))) begin + pcie_dma0_buffering_writer_fifo_produce <= (pcie_dma0_buffering_writer_fifo_produce + 1'd1); + end + if (pcie_dma0_buffering_writer_fifo_do_read) begin + pcie_dma0_buffering_writer_fifo_consume <= (pcie_dma0_buffering_writer_fifo_consume + 1'd1); + end + if (((pcie_dma0_buffering_writer_fifo_syncfifo_we & pcie_dma0_buffering_writer_fifo_syncfifo_writable) & (~pcie_dma0_buffering_writer_fifo_replace))) begin + if ((~pcie_dma0_buffering_writer_fifo_do_read)) begin + pcie_dma0_buffering_writer_fifo_level0 <= (pcie_dma0_buffering_writer_fifo_level0 + 1'd1); + end + end else begin + if (pcie_dma0_buffering_writer_fifo_do_read) begin + pcie_dma0_buffering_writer_fifo_level0 <= (pcie_dma0_buffering_writer_fifo_level0 - 1'd1); + end + end + if (pcie_dma1_writer_loop_prog_n_storage) begin + pcie_dma1_writer_fifo_sink_payload_address <= pcie_dma1_writer_fifo_source_payload_address; + pcie_dma1_writer_fifo_sink_payload_length <= pcie_dma1_writer_fifo_source_payload_length; + pcie_dma1_writer_fifo_sink_payload_control <= pcie_dma1_writer_fifo_source_payload_control; + pcie_dma1_writer_fifo_sink_first <= pcie_dma1_writer_fifo_source_first; + pcie_dma1_writer_fifo_sink_valid <= pcie_dma1_writer_fifo_source_ready; + end else begin + pcie_dma1_writer_fifo_sink_payload_address <= pcie_dma1_writer_address; + pcie_dma1_writer_fifo_sink_payload_length <= pcie_dma1_writer_length; + pcie_dma1_writer_fifo_sink_payload_control <= {pcie_dma1_writer_last_disable, pcie_dma1_writer_irq_disable}; + pcie_dma1_writer_fifo_sink_first <= (~pcie_dma1_writer_fifo_source_valid); + pcie_dma1_writer_fifo_sink_valid <= (pcie_dma1_writer_we_storage & pcie_dma1_writer_we_re); + end + if ((pcie_dma1_writer_flush_storage & pcie_dma1_writer_flush_re)) begin + pcie_dma1_writer_loop_first <= 1'd1; + pcie_dma1_writer_loop_index <= 1'd0; + pcie_dma1_writer_loop_count <= 1'd0; + pcie_dma1_writer_index <= 1'd0; + pcie_dma1_writer_count <= 1'd0; + end else begin + if ((pcie_dma1_writer_source_source_valid & pcie_dma1_writer_source_source_ready)) begin + pcie_dma1_writer_index <= pcie_dma1_writer_loop_index; + pcie_dma1_writer_count <= pcie_dma1_writer_loop_count; + if (pcie_dma1_writer_source_source_first) begin + pcie_dma1_writer_loop_first <= 1'd0; + pcie_dma1_writer_loop_index <= 1'd0; + if ((~pcie_dma1_writer_loop_first)) begin + pcie_dma1_writer_loop_count <= (pcie_dma1_writer_loop_count + 1'd1); + end + end else begin + pcie_dma1_writer_loop_index <= (pcie_dma1_writer_loop_index + 1'd1); + end + end + end + if (((pcie_dma1_writer_fifo_syncfifo_we0 & pcie_dma1_writer_fifo_syncfifo_writable0) & (~pcie_dma1_writer_fifo_replace0))) begin + pcie_dma1_writer_fifo_produce0 <= (pcie_dma1_writer_fifo_produce0 + 1'd1); + end + if (pcie_dma1_writer_fifo_do_read0) begin + pcie_dma1_writer_fifo_consume0 <= (pcie_dma1_writer_fifo_consume0 + 1'd1); + end + if (((pcie_dma1_writer_fifo_syncfifo_we0 & pcie_dma1_writer_fifo_syncfifo_writable0) & (~pcie_dma1_writer_fifo_replace0))) begin + if ((~pcie_dma1_writer_fifo_do_read0)) begin + pcie_dma1_writer_fifo_level0 <= (pcie_dma1_writer_fifo_level0 + 1'd1); + end + end else begin + if (pcie_dma1_writer_fifo_do_read0) begin + pcie_dma1_writer_fifo_level0 <= (pcie_dma1_writer_fifo_level0 - 1'd1); + end + end + if (pcie_dma1_writer_fifo_reset) begin + pcie_dma1_writer_fifo_level0 <= 9'd0; + pcie_dma1_writer_fifo_produce0 <= 8'd0; + pcie_dma1_writer_fifo_consume0 <= 8'd0; + end + bufferizeendpoints1_state0 <= bufferizeendpoints1_next_state0; + if (pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_bufferizeendpoints1_next_value_ce0) begin + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_offset <= pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_bufferizeendpoints1_next_value0; + end + if (pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_user_id_litepciedma1_bufferizeendpoints1_next_value_ce1) begin + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_user_id <= pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_user_id_litepciedma1_bufferizeendpoints1_next_value1; + end + if (((~pcie_dma1_writer_splitter_bufferizeendpoints_source_valid) | pcie_dma1_writer_splitter_bufferizeendpoints_source_ready)) begin + pcie_dma1_writer_splitter_bufferizeendpoints_source_valid <= pcie_dma1_writer_splitter_bufferizeendpoints_sink_valid; + pcie_dma1_writer_splitter_bufferizeendpoints_source_first <= pcie_dma1_writer_splitter_bufferizeendpoints_sink_first; + pcie_dma1_writer_splitter_bufferizeendpoints_source_last <= pcie_dma1_writer_splitter_bufferizeendpoints_sink_last; + pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_address <= pcie_dma1_writer_splitter_bufferizeendpoints_sink_payload_address; + pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_length <= pcie_dma1_writer_splitter_bufferizeendpoints_sink_payload_length; + pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_control <= pcie_dma1_writer_splitter_bufferizeendpoints_sink_payload_control; + pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_user_id <= pcie_dma1_writer_splitter_bufferizeendpoints_sink_payload_user_id; + end + if (pcie_dma1_writer_splitter_reset) begin + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_offset <= 32'd0; + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_user_id <= 32'd0; + pcie_dma1_writer_splitter_bufferizeendpoints_source_valid <= 1'd0; + pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_address <= 32'd0; + pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_length <= 24'd0; + pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_control <= 8'd0; + pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_user_id <= 8'd0; + bufferizeendpoints1_state0 <= 2'd0; + end + if (pcie_dma1_writer_fifo_syncfifo_re1) begin + pcie_dma1_writer_fifo_readable <= 1'd1; + end else begin + if (pcie_dma1_writer_fifo_re) begin + pcie_dma1_writer_fifo_readable <= 1'd0; + end + end + if (((pcie_dma1_writer_fifo_syncfifo_we1 & pcie_dma1_writer_fifo_syncfifo_writable1) & (~pcie_dma1_writer_fifo_replace1))) begin + pcie_dma1_writer_fifo_produce1 <= (pcie_dma1_writer_fifo_produce1 + 1'd1); + end + if (pcie_dma1_writer_fifo_do_read1) begin + pcie_dma1_writer_fifo_consume1 <= (pcie_dma1_writer_fifo_consume1 + 1'd1); + end + if (((pcie_dma1_writer_fifo_syncfifo_we1 & pcie_dma1_writer_fifo_syncfifo_writable1) & (~pcie_dma1_writer_fifo_replace1))) begin + if ((~pcie_dma1_writer_fifo_do_read1)) begin + pcie_dma1_writer_fifo_level1 <= (pcie_dma1_writer_fifo_level1 + 1'd1); + end + end else begin + if (pcie_dma1_writer_fifo_do_read1) begin + pcie_dma1_writer_fifo_level1 <= (pcie_dma1_writer_fifo_level1 - 1'd1); + end + end + if (pcie_dma1_writer_resetinserter_reset) begin + pcie_dma1_writer_fifo_readable <= 1'd0; + pcie_dma1_writer_fifo_level1 <= 9'd0; + pcie_dma1_writer_fifo_produce1 <= 8'd0; + pcie_dma1_writer_fifo_consume1 <= 8'd0; + end + fsm1_state1 <= fsm1_next_state1; + if (pcie_dma1_writer_counter_litepciedma1_fsm1_next_value_ce) begin + pcie_dma1_writer_counter <= pcie_dma1_writer_counter_litepciedma1_fsm1_next_value; + end + if (((pcie_dma1_litepciemasterinternalport1_source_valid & pcie_dma1_litepciemasterinternalport1_source_first) & pcie_dma1_litepciemasterinternalport1_source_ready)) begin + pcie_dma1_reader_last_user_id <= pcie_dma1_litepciemasterinternalport1_source_payload_user_id; + end + if ((~pcie_dma1_reader_enable_storage)) begin + pcie_dma1_reader_pending_words <= 1'd0; + end else begin + pcie_dma1_reader_pending_words <= ((pcie_dma1_reader_pending_words + pcie_dma1_reader_pending_words_queue) - pcie_dma1_reader_pending_words_dequeue); + end + if (pcie_dma1_reader_loop_prog_n_storage) begin + pcie_dma1_reader_fifo_sink_payload_address <= pcie_dma1_reader_fifo_source_payload_address; + pcie_dma1_reader_fifo_sink_payload_length <= pcie_dma1_reader_fifo_source_payload_length; + pcie_dma1_reader_fifo_sink_payload_control <= pcie_dma1_reader_fifo_source_payload_control; + pcie_dma1_reader_fifo_sink_first0 <= pcie_dma1_reader_fifo_source_first0; + pcie_dma1_reader_fifo_sink_valid0 <= pcie_dma1_reader_fifo_source_ready0; + end else begin + pcie_dma1_reader_fifo_sink_payload_address <= pcie_dma1_reader_address; + pcie_dma1_reader_fifo_sink_payload_length <= pcie_dma1_reader_length; + pcie_dma1_reader_fifo_sink_payload_control <= {pcie_dma1_reader_last_disable, pcie_dma1_reader_irq_disable}; + pcie_dma1_reader_fifo_sink_first0 <= (~pcie_dma1_reader_fifo_source_valid0); + pcie_dma1_reader_fifo_sink_valid0 <= (pcie_dma1_reader_we_storage & pcie_dma1_reader_we_re); + end + if ((pcie_dma1_reader_flush_storage & pcie_dma1_reader_flush_re)) begin + pcie_dma1_reader_loop_first <= 1'd1; + pcie_dma1_reader_loop_index <= 1'd0; + pcie_dma1_reader_loop_count <= 1'd0; + pcie_dma1_reader_index <= 1'd0; + pcie_dma1_reader_count <= 1'd0; + end else begin + if ((pcie_dma1_reader_source_source_valid1 & pcie_dma1_reader_source_source_ready1)) begin + pcie_dma1_reader_index <= pcie_dma1_reader_loop_index; + pcie_dma1_reader_count <= pcie_dma1_reader_loop_count; + if (pcie_dma1_reader_source_source_first1) begin + pcie_dma1_reader_loop_first <= 1'd0; + pcie_dma1_reader_loop_index <= 1'd0; + if ((~pcie_dma1_reader_loop_first)) begin + pcie_dma1_reader_loop_count <= (pcie_dma1_reader_loop_count + 1'd1); + end + end else begin + pcie_dma1_reader_loop_index <= (pcie_dma1_reader_loop_index + 1'd1); + end + end + end + if (((pcie_dma1_reader_fifo_syncfifo_we0 & pcie_dma1_reader_fifo_syncfifo_writable0) & (~pcie_dma1_reader_fifo_replace0))) begin + pcie_dma1_reader_fifo_produce0 <= (pcie_dma1_reader_fifo_produce0 + 1'd1); + end + if (pcie_dma1_reader_fifo_do_read0) begin + pcie_dma1_reader_fifo_consume0 <= (pcie_dma1_reader_fifo_consume0 + 1'd1); + end + if (((pcie_dma1_reader_fifo_syncfifo_we0 & pcie_dma1_reader_fifo_syncfifo_writable0) & (~pcie_dma1_reader_fifo_replace0))) begin + if ((~pcie_dma1_reader_fifo_do_read0)) begin + pcie_dma1_reader_fifo_level0 <= (pcie_dma1_reader_fifo_level0 + 1'd1); + end + end else begin + if (pcie_dma1_reader_fifo_do_read0) begin + pcie_dma1_reader_fifo_level0 <= (pcie_dma1_reader_fifo_level0 - 1'd1); + end + end + if (pcie_dma1_reader_fifo_reset0) begin + pcie_dma1_reader_fifo_level0 <= 9'd0; + pcie_dma1_reader_fifo_produce0 <= 8'd0; + pcie_dma1_reader_fifo_consume0 <= 8'd0; + end + bufferizeendpoints1_state1 <= bufferizeendpoints1_next_state1; + if (pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_next_value_ce0) begin + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_offset <= pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_offset_litepciedma1_next_value0; + end + if (pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_user_id_litepciedma1_next_value_ce1) begin + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_user_id <= pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_user_id_litepciedma1_next_value1; + end + if (((~pcie_dma1_reader_splitter_bufferizeendpoints_source_valid) | pcie_dma1_reader_splitter_bufferizeendpoints_source_ready)) begin + pcie_dma1_reader_splitter_bufferizeendpoints_source_valid <= pcie_dma1_reader_splitter_bufferizeendpoints_sink_valid; + pcie_dma1_reader_splitter_bufferizeendpoints_source_first <= pcie_dma1_reader_splitter_bufferizeendpoints_sink_first; + pcie_dma1_reader_splitter_bufferizeendpoints_source_last <= pcie_dma1_reader_splitter_bufferizeendpoints_sink_last; + pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_address <= pcie_dma1_reader_splitter_bufferizeendpoints_sink_payload_address; + pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_length <= pcie_dma1_reader_splitter_bufferizeendpoints_sink_payload_length; + pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_control <= pcie_dma1_reader_splitter_bufferizeendpoints_sink_payload_control; + pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_user_id <= pcie_dma1_reader_splitter_bufferizeendpoints_sink_payload_user_id; + end + if (pcie_dma1_reader_splitter_reset) begin + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_offset <= 32'd0; + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_user_id <= 32'd0; + pcie_dma1_reader_splitter_bufferizeendpoints_source_valid <= 1'd0; + pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_address <= 32'd0; + pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_length <= 24'd0; + pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_control <= 8'd0; + pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_user_id <= 8'd0; + bufferizeendpoints1_state1 <= 2'd0; + end + if (pcie_dma1_reader_fifo_syncfifo_re1) begin + pcie_dma1_reader_fifo_readable <= 1'd1; + end else begin + if (pcie_dma1_reader_fifo_re) begin + pcie_dma1_reader_fifo_readable <= 1'd0; + end + end + if (((pcie_dma1_reader_fifo_syncfifo_we1 & pcie_dma1_reader_fifo_syncfifo_writable1) & (~pcie_dma1_reader_fifo_replace1))) begin + pcie_dma1_reader_fifo_produce1 <= (pcie_dma1_reader_fifo_produce1 + 1'd1); + end + if (pcie_dma1_reader_fifo_do_read1) begin + pcie_dma1_reader_fifo_consume1 <= (pcie_dma1_reader_fifo_consume1 + 1'd1); + end + if (((pcie_dma1_reader_fifo_syncfifo_we1 & pcie_dma1_reader_fifo_syncfifo_writable1) & (~pcie_dma1_reader_fifo_replace1))) begin + if ((~pcie_dma1_reader_fifo_do_read1)) begin + pcie_dma1_reader_fifo_level1 <= (pcie_dma1_reader_fifo_level1 + 1'd1); + end + end else begin + if (pcie_dma1_reader_fifo_do_read1) begin + pcie_dma1_reader_fifo_level1 <= (pcie_dma1_reader_fifo_level1 - 1'd1); + end + end + if (pcie_dma1_reader_fifo_reset1) begin + pcie_dma1_reader_fifo_readable <= 1'd0; + pcie_dma1_reader_fifo_level1 <= 11'd0; + pcie_dma1_reader_fifo_produce1 <= 10'd0; + pcie_dma1_reader_fifo_consume1 <= 10'd0; + end + fsm1_state2 <= fsm1_next_state2; + if (pcie_dma1_buffering_reader_fifo_syncfifo_re) begin + pcie_dma1_buffering_reader_fifo_readable <= 1'd1; + end else begin + if (pcie_dma1_buffering_reader_fifo_re) begin + pcie_dma1_buffering_reader_fifo_readable <= 1'd0; + end + end + if (((pcie_dma1_buffering_reader_fifo_syncfifo_we & pcie_dma1_buffering_reader_fifo_syncfifo_writable) & (~pcie_dma1_buffering_reader_fifo_replace))) begin + pcie_dma1_buffering_reader_fifo_produce <= (pcie_dma1_buffering_reader_fifo_produce + 1'd1); + end + if (pcie_dma1_buffering_reader_fifo_do_read) begin + pcie_dma1_buffering_reader_fifo_consume <= (pcie_dma1_buffering_reader_fifo_consume + 1'd1); + end + if (((pcie_dma1_buffering_reader_fifo_syncfifo_we & pcie_dma1_buffering_reader_fifo_syncfifo_writable) & (~pcie_dma1_buffering_reader_fifo_replace))) begin + if ((~pcie_dma1_buffering_reader_fifo_do_read)) begin + pcie_dma1_buffering_reader_fifo_level0 <= (pcie_dma1_buffering_reader_fifo_level0 + 1'd1); + end + end else begin + if (pcie_dma1_buffering_reader_fifo_do_read) begin + pcie_dma1_buffering_reader_fifo_level0 <= (pcie_dma1_buffering_reader_fifo_level0 - 1'd1); + end + end + if (pcie_dma1_buffering_writer_fifo_syncfifo_re) begin + pcie_dma1_buffering_writer_fifo_readable <= 1'd1; + end else begin + if (pcie_dma1_buffering_writer_fifo_re) begin + pcie_dma1_buffering_writer_fifo_readable <= 1'd0; + end + end + if (((pcie_dma1_buffering_writer_fifo_syncfifo_we & pcie_dma1_buffering_writer_fifo_syncfifo_writable) & (~pcie_dma1_buffering_writer_fifo_replace))) begin + pcie_dma1_buffering_writer_fifo_produce <= (pcie_dma1_buffering_writer_fifo_produce + 1'd1); + end + if (pcie_dma1_buffering_writer_fifo_do_read) begin + pcie_dma1_buffering_writer_fifo_consume <= (pcie_dma1_buffering_writer_fifo_consume + 1'd1); + end + if (((pcie_dma1_buffering_writer_fifo_syncfifo_we & pcie_dma1_buffering_writer_fifo_syncfifo_writable) & (~pcie_dma1_buffering_writer_fifo_replace))) begin + if ((~pcie_dma1_buffering_writer_fifo_do_read)) begin + pcie_dma1_buffering_writer_fifo_level0 <= (pcie_dma1_buffering_writer_fifo_level0 + 1'd1); + end + end else begin + if (pcie_dma1_buffering_writer_fifo_do_read) begin + pcie_dma1_buffering_writer_fifo_level0 <= (pcie_dma1_buffering_writer_fifo_level0 - 1'd1); + end + end + pcie_msi_vector <= (pcie_msi_enable & ((pcie_msi_vector & (~pcie_msi_clear)) | pcie_msi_irqs)); + pcie_msi_msi <= (pcie_msi_msi | (pcie_msi_irqs & pcie_msi_enable)); + if (pcie_msi_source_ready) begin + pcie_msi_msi <= (pcie_msi_irqs & pcie_msi_enable); + end + if (freqmeter_period_done) begin + freqmeter_period_counter <= 1'd0; + end else begin + freqmeter_period_counter <= (freqmeter_period_counter + 1'd1); + end + freqmeter_gray_decoder_o <= freqmeter_gray_decoder_o_comb; + freqmeter_sampler_i_d <= freqmeter_sampler_i; + if (freqmeter_sampler_latch) begin + freqmeter_sampler_counter <= 1'd0; + freqmeter_sampler_o <= freqmeter_sampler_counter; + end else begin + freqmeter_sampler_counter <= (freqmeter_sampler_counter + freqmeter_sampler_inc); + end + hdmi_in0_sda_drv_reg <= hdmi_in0_sda_drv; + {hdmi_in0_samp_carry, hdmi_in0_samp_count} <= (hdmi_in0_samp_count + 1'd1); + if (hdmi_in0_samp_carry) begin + hdmi_in0_scl_i <= hdmi_in0_scl_raw; + hdmi_in0_sda_i <= hdmi_in0_sda_raw; + end + hdmi_in0_scl_r <= hdmi_in0_scl_i; + hdmi_in0_sda_r <= hdmi_in0_sda_i; + if (hdmi_in0_start) begin + hdmi_in0_counter <= 1'd0; + end + if (hdmi_in0_scl_rising) begin + if ((hdmi_in0_counter == 4'd8)) begin + hdmi_in0_counter <= 1'd0; + end else begin + hdmi_in0_counter <= (hdmi_in0_counter + 1'd1); + hdmi_in0_din <= {hdmi_in0_din[6:0], hdmi_in0_sda_i}; + end + end + if (hdmi_in0_update_is_read) begin + hdmi_in0_is_read <= hdmi_in0_din[0]; + end + if (hdmi_in0_oc_load) begin + hdmi_in0_offset_counter <= hdmi_in0_din; + end else begin + if (hdmi_in0_oc_inc) begin + hdmi_in0_offset_counter <= (hdmi_in0_offset_counter + 1'd1); + end + end + if (hdmi_in0_data_drv_en) begin + hdmi_in0_data_drv <= 1'd1; + end else begin + if (hdmi_in0_data_drv_stop) begin + hdmi_in0_data_drv <= 1'd0; + end + end + if (hdmi_in0_data_drv_en) begin + case (hdmi_in0_counter) + 1'd0: begin + hdmi_in0_data_bit <= hdmi_in0_dat_r[7]; + end + 1'd1: begin + hdmi_in0_data_bit <= hdmi_in0_dat_r[6]; + end + 2'd2: begin + hdmi_in0_data_bit <= hdmi_in0_dat_r[5]; + end + 2'd3: begin + hdmi_in0_data_bit <= hdmi_in0_dat_r[4]; + end + 3'd4: begin + hdmi_in0_data_bit <= hdmi_in0_dat_r[3]; + end + 3'd5: begin + hdmi_in0_data_bit <= hdmi_in0_dat_r[2]; + end + 3'd6: begin + hdmi_in0_data_bit <= hdmi_in0_dat_r[1]; + end + default: begin + hdmi_in0_data_bit <= hdmi_in0_dat_r[0]; + end + endcase + end + edid_state <= edid_next_state; + if ((hdmi_in0_mmcm_read_re | hdmi_in0_mmcm_write_re)) begin + hdmi_in0_mmcm_drdy_status <= 1'd0; + end else begin + if (hdmi_in0_mmcm_drdy) begin + hdmi_in0_mmcm_drdy_status <= 1'd1; + end + end + if ((hdmi_in0_mmcm_read_o_re | hdmi_in0_mmcm_write_o_re)) begin + hdmi_in0_mmcm_drdy_o_status <= 1'd0; + end else begin + if (hdmi_in0_mmcm_drdy_o) begin + hdmi_in0_mmcm_drdy_o_status <= 1'd1; + end + end + hdmi_in0_s7datacapture0_sync_mcntvalue_ping_o1 <= hdmi_in0_s7datacapture0_sync_mcntvalue_ping_o0; + if (hdmi_in0_s7datacapture0_sync_mcntvalue_ping_o1) begin + hdmi_in0_s7datacapture0_sync_mcntvalue_o <= hdmi_in0_s7datacapture0_sync_mcntvalue_obuffer; + end + hdmi_in0_s7datacapture0_sync_mcntvalue_ping_toggle_o_r <= hdmi_in0_s7datacapture0_sync_mcntvalue_ping_toggle_o; + if (hdmi_in0_s7datacapture0_sync_mcntvalue_pong_i) begin + hdmi_in0_s7datacapture0_sync_mcntvalue_pong_toggle_i <= (~hdmi_in0_s7datacapture0_sync_mcntvalue_pong_toggle_i); + end + hdmi_in0_s7datacapture0_sync_scntvalue_ping_o1 <= hdmi_in0_s7datacapture0_sync_scntvalue_ping_o0; + if (hdmi_in0_s7datacapture0_sync_scntvalue_ping_o1) begin + hdmi_in0_s7datacapture0_sync_scntvalue_o <= hdmi_in0_s7datacapture0_sync_scntvalue_obuffer; + end + hdmi_in0_s7datacapture0_sync_scntvalue_ping_toggle_o_r <= hdmi_in0_s7datacapture0_sync_scntvalue_ping_toggle_o; + if (hdmi_in0_s7datacapture0_sync_scntvalue_pong_i) begin + hdmi_in0_s7datacapture0_sync_scntvalue_pong_toggle_i <= (~hdmi_in0_s7datacapture0_sync_scntvalue_pong_toggle_i); + end + if (hdmi_in0_s7datacapture0_do_delay_rst_i) begin + hdmi_in0_s7datacapture0_do_delay_rst_toggle_i <= (~hdmi_in0_s7datacapture0_do_delay_rst_toggle_i); + end + if (hdmi_in0_s7datacapture0_do_delay_master_inc_i) begin + hdmi_in0_s7datacapture0_do_delay_master_inc_toggle_i <= (~hdmi_in0_s7datacapture0_do_delay_master_inc_toggle_i); + end + if (hdmi_in0_s7datacapture0_do_delay_master_dec_i) begin + hdmi_in0_s7datacapture0_do_delay_master_dec_toggle_i <= (~hdmi_in0_s7datacapture0_do_delay_master_dec_toggle_i); + end + if (hdmi_in0_s7datacapture0_do_delay_slave_inc_i) begin + hdmi_in0_s7datacapture0_do_delay_slave_inc_toggle_i <= (~hdmi_in0_s7datacapture0_do_delay_slave_inc_toggle_i); + end + if (hdmi_in0_s7datacapture0_do_delay_slave_dec_i) begin + hdmi_in0_s7datacapture0_do_delay_slave_dec_toggle_i <= (~hdmi_in0_s7datacapture0_do_delay_slave_dec_toggle_i); + end + if (hdmi_in0_s7datacapture0_do_reset_lateness_i) begin + hdmi_in0_s7datacapture0_do_reset_lateness_toggle_i <= (~hdmi_in0_s7datacapture0_do_reset_lateness_toggle_i); + end + if (hdmi_in0_wer0_o) begin + hdmi_in0_wer0_wer_counter_sys <= hdmi_in0_wer0_wer_counter_r; + end + if (hdmi_in0_wer0_update_re) begin + hdmi_in0_wer0_status <= hdmi_in0_wer0_wer_counter_sys; + end + hdmi_in0_wer0_toggle_o_r <= hdmi_in0_wer0_toggle_o; + hdmi_in0_s7datacapture1_sync_mcntvalue_ping_o1 <= hdmi_in0_s7datacapture1_sync_mcntvalue_ping_o0; + if (hdmi_in0_s7datacapture1_sync_mcntvalue_ping_o1) begin + hdmi_in0_s7datacapture1_sync_mcntvalue_o <= hdmi_in0_s7datacapture1_sync_mcntvalue_obuffer; + end + hdmi_in0_s7datacapture1_sync_mcntvalue_ping_toggle_o_r <= hdmi_in0_s7datacapture1_sync_mcntvalue_ping_toggle_o; + if (hdmi_in0_s7datacapture1_sync_mcntvalue_pong_i) begin + hdmi_in0_s7datacapture1_sync_mcntvalue_pong_toggle_i <= (~hdmi_in0_s7datacapture1_sync_mcntvalue_pong_toggle_i); + end + hdmi_in0_s7datacapture1_sync_scntvalue_ping_o1 <= hdmi_in0_s7datacapture1_sync_scntvalue_ping_o0; + if (hdmi_in0_s7datacapture1_sync_scntvalue_ping_o1) begin + hdmi_in0_s7datacapture1_sync_scntvalue_o <= hdmi_in0_s7datacapture1_sync_scntvalue_obuffer; + end + hdmi_in0_s7datacapture1_sync_scntvalue_ping_toggle_o_r <= hdmi_in0_s7datacapture1_sync_scntvalue_ping_toggle_o; + if (hdmi_in0_s7datacapture1_sync_scntvalue_pong_i) begin + hdmi_in0_s7datacapture1_sync_scntvalue_pong_toggle_i <= (~hdmi_in0_s7datacapture1_sync_scntvalue_pong_toggle_i); + end + if (hdmi_in0_s7datacapture1_do_delay_rst_i) begin + hdmi_in0_s7datacapture1_do_delay_rst_toggle_i <= (~hdmi_in0_s7datacapture1_do_delay_rst_toggle_i); + end + if (hdmi_in0_s7datacapture1_do_delay_master_inc_i) begin + hdmi_in0_s7datacapture1_do_delay_master_inc_toggle_i <= (~hdmi_in0_s7datacapture1_do_delay_master_inc_toggle_i); + end + if (hdmi_in0_s7datacapture1_do_delay_master_dec_i) begin + hdmi_in0_s7datacapture1_do_delay_master_dec_toggle_i <= (~hdmi_in0_s7datacapture1_do_delay_master_dec_toggle_i); + end + if (hdmi_in0_s7datacapture1_do_delay_slave_inc_i) begin + hdmi_in0_s7datacapture1_do_delay_slave_inc_toggle_i <= (~hdmi_in0_s7datacapture1_do_delay_slave_inc_toggle_i); + end + if (hdmi_in0_s7datacapture1_do_delay_slave_dec_i) begin + hdmi_in0_s7datacapture1_do_delay_slave_dec_toggle_i <= (~hdmi_in0_s7datacapture1_do_delay_slave_dec_toggle_i); + end + if (hdmi_in0_s7datacapture1_do_reset_lateness_i) begin + hdmi_in0_s7datacapture1_do_reset_lateness_toggle_i <= (~hdmi_in0_s7datacapture1_do_reset_lateness_toggle_i); + end + if (hdmi_in0_wer1_o) begin + hdmi_in0_wer1_wer_counter_sys <= hdmi_in0_wer1_wer_counter_r; + end + if (hdmi_in0_wer1_update_re) begin + hdmi_in0_wer1_status <= hdmi_in0_wer1_wer_counter_sys; + end + hdmi_in0_wer1_toggle_o_r <= hdmi_in0_wer1_toggle_o; + hdmi_in0_s7datacapture2_sync_mcntvalue_ping_o1 <= hdmi_in0_s7datacapture2_sync_mcntvalue_ping_o0; + if (hdmi_in0_s7datacapture2_sync_mcntvalue_ping_o1) begin + hdmi_in0_s7datacapture2_sync_mcntvalue_o <= hdmi_in0_s7datacapture2_sync_mcntvalue_obuffer; + end + hdmi_in0_s7datacapture2_sync_mcntvalue_ping_toggle_o_r <= hdmi_in0_s7datacapture2_sync_mcntvalue_ping_toggle_o; + if (hdmi_in0_s7datacapture2_sync_mcntvalue_pong_i) begin + hdmi_in0_s7datacapture2_sync_mcntvalue_pong_toggle_i <= (~hdmi_in0_s7datacapture2_sync_mcntvalue_pong_toggle_i); + end + hdmi_in0_s7datacapture2_sync_scntvalue_ping_o1 <= hdmi_in0_s7datacapture2_sync_scntvalue_ping_o0; + if (hdmi_in0_s7datacapture2_sync_scntvalue_ping_o1) begin + hdmi_in0_s7datacapture2_sync_scntvalue_o <= hdmi_in0_s7datacapture2_sync_scntvalue_obuffer; + end + hdmi_in0_s7datacapture2_sync_scntvalue_ping_toggle_o_r <= hdmi_in0_s7datacapture2_sync_scntvalue_ping_toggle_o; + if (hdmi_in0_s7datacapture2_sync_scntvalue_pong_i) begin + hdmi_in0_s7datacapture2_sync_scntvalue_pong_toggle_i <= (~hdmi_in0_s7datacapture2_sync_scntvalue_pong_toggle_i); + end + if (hdmi_in0_s7datacapture2_do_delay_rst_i) begin + hdmi_in0_s7datacapture2_do_delay_rst_toggle_i <= (~hdmi_in0_s7datacapture2_do_delay_rst_toggle_i); + end + if (hdmi_in0_s7datacapture2_do_delay_master_inc_i) begin + hdmi_in0_s7datacapture2_do_delay_master_inc_toggle_i <= (~hdmi_in0_s7datacapture2_do_delay_master_inc_toggle_i); + end + if (hdmi_in0_s7datacapture2_do_delay_master_dec_i) begin + hdmi_in0_s7datacapture2_do_delay_master_dec_toggle_i <= (~hdmi_in0_s7datacapture2_do_delay_master_dec_toggle_i); + end + if (hdmi_in0_s7datacapture2_do_delay_slave_inc_i) begin + hdmi_in0_s7datacapture2_do_delay_slave_inc_toggle_i <= (~hdmi_in0_s7datacapture2_do_delay_slave_inc_toggle_i); + end + if (hdmi_in0_s7datacapture2_do_delay_slave_dec_i) begin + hdmi_in0_s7datacapture2_do_delay_slave_dec_toggle_i <= (~hdmi_in0_s7datacapture2_do_delay_slave_dec_toggle_i); + end + if (hdmi_in0_s7datacapture2_do_reset_lateness_i) begin + hdmi_in0_s7datacapture2_do_reset_lateness_toggle_i <= (~hdmi_in0_s7datacapture2_do_reset_lateness_toggle_i); + end + if (hdmi_in0_wer2_o) begin + hdmi_in0_wer2_wer_counter_sys <= hdmi_in0_wer2_wer_counter_r; + end + if (hdmi_in0_wer2_update_re) begin + hdmi_in0_wer2_status <= hdmi_in0_wer2_wer_counter_sys; + end + hdmi_in0_wer2_toggle_o_r <= hdmi_in0_wer2_toggle_o; + if (hdmi_in0_frame_overflow_re) begin + hdmi_in0_frame_overflow_mask <= 1'd1; + end else begin + if (hdmi_in0_frame_overflow_reset_ack_o) begin + hdmi_in0_frame_overflow_mask <= 1'd0; + end + end + hdmi_in0_frame_fifo_graycounter1_q_binary <= hdmi_in0_frame_fifo_graycounter1_q_next_binary; + hdmi_in0_frame_fifo_graycounter1_q <= hdmi_in0_frame_fifo_graycounter1_q_next; + if (hdmi_in0_frame_overflow_reset_i) begin + hdmi_in0_frame_overflow_reset_toggle_i <= (~hdmi_in0_frame_overflow_reset_toggle_i); + end + hdmi_in0_frame_overflow_reset_ack_toggle_o_r <= hdmi_in0_frame_overflow_reset_ack_toggle_o; + if (hdmi_in0_dma_reset_words) begin + hdmi_in0_dma_current_address <= hdmi_in0_dma_slot_array_address; + hdmi_in0_dma_mwords_remaining <= hdmi_in0_dma_frame_size_storage[28:5]; + end else begin + if (hdmi_in0_dma_count_word) begin + hdmi_in0_dma_current_address <= (hdmi_in0_dma_current_address + 1'd1); + hdmi_in0_dma_mwords_remaining <= (hdmi_in0_dma_mwords_remaining - 1'd1); + end + end + if (hdmi_in0_dma_slot_array_change_slot) begin + if (hdmi_in0_dma_slot_array_slot1_address_valid) begin + hdmi_in0_dma_slot_array_current_slot <= 1'd1; + end + if (hdmi_in0_dma_slot_array_slot0_address_valid) begin + hdmi_in0_dma_slot_array_current_slot <= 1'd0; + end + end + if (((hdmi_in0_dma_fifo_syncfifo_we & hdmi_in0_dma_fifo_syncfifo_writable) & (~hdmi_in0_dma_fifo_replace))) begin + hdmi_in0_dma_fifo_produce <= (hdmi_in0_dma_fifo_produce + 1'd1); + end + if (hdmi_in0_dma_fifo_do_read) begin + hdmi_in0_dma_fifo_consume <= (hdmi_in0_dma_fifo_consume + 1'd1); + end + if (((hdmi_in0_dma_fifo_syncfifo_we & hdmi_in0_dma_fifo_syncfifo_writable) & (~hdmi_in0_dma_fifo_replace))) begin + if ((~hdmi_in0_dma_fifo_do_read)) begin + hdmi_in0_dma_fifo_level <= (hdmi_in0_dma_fifo_level + 1'd1); + end + end else begin + if (hdmi_in0_dma_fifo_do_read) begin + hdmi_in0_dma_fifo_level <= (hdmi_in0_dma_fifo_level - 1'd1); + end + end + dma_state <= dma_next_state; + hdmi_out0_core_initiator_cdc_graycounter0_q_binary <= hdmi_out0_core_initiator_cdc_graycounter0_q_next_binary; + hdmi_out0_core_initiator_cdc_graycounter0_q <= hdmi_out0_core_initiator_cdc_graycounter0_q_next; + if (hdmi_out0_core_i) begin + hdmi_out0_core_toggle_i <= (~hdmi_out0_core_toggle_i); + end + if ((hdmi_out0_driver_s7hdmioutclocking_mmcm_read_re | hdmi_out0_driver_s7hdmioutclocking_mmcm_write_re)) begin + hdmi_out0_driver_s7hdmioutclocking_mmcm_drdy_status <= 1'd0; + end else begin + if (hdmi_out0_driver_s7hdmioutclocking_mmcm_drdy) begin + hdmi_out0_driver_s7hdmioutclocking_mmcm_drdy_status <= 1'd1; + end + end + state <= next_state; + if (netv2_dat_w_next_value_ce0) begin + netv2_dat_w <= netv2_dat_w_next_value0; + end + if (netv2_adr_next_value_ce1) begin + netv2_adr <= netv2_adr_next_value1; + end + if (netv2_we_next_value_ce2) begin + netv2_we <= netv2_we_next_value2; + end + case (grant) + 1'd0: begin + if ((~request[0])) begin + if (request[1]) begin + grant <= 1'd1; + end else begin + if (request[2]) begin + grant <= 2'd2; + end else begin + if (request[3]) begin + grant <= 2'd3; + end + end + end + end + end + 1'd1: begin + if ((~request[1])) begin + if (request[2]) begin + grant <= 2'd2; + end else begin + if (request[3]) begin + grant <= 2'd3; + end else begin + if (request[0]) begin + grant <= 1'd0; + end + end + end + end + end + 2'd2: begin + if ((~request[2])) begin + if (request[3]) begin + grant <= 2'd3; + end else begin + if (request[0]) begin + grant <= 1'd0; + end else begin + if (request[1]) begin + grant <= 1'd1; + end + end + end + end + end + 2'd3: begin + if ((~request[3])) begin + if (request[0]) begin + grant <= 1'd0; + end else begin + if (request[1]) begin + grant <= 1'd1; + end else begin + if (request[2]) begin + grant <= 2'd2; + end + end + end + end + end + endcase + slave_sel_r <= slave_sel; + if (wait_1) begin + if ((~done)) begin + count <= (count - 1'd1); + end + end else begin + count <= 20'd1000000; + end + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[0]) + 1'd0: begin + interface0_bank_bus_dat_r <= crg_reset_w; + end + endcase + end + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[1:0]) + 1'd0: begin + interface1_bank_bus_dat_r <= csrbank1_reset0_w; + end + 1'd1: begin + interface1_bank_bus_dat_r <= csrbank1_scratch0_w; + end + 2'd2: begin + interface1_bank_bus_dat_r <= csrbank1_bus_errors_w; + end + endcase + end + if (csrbank1_reset0_re) begin + netv2_soccontroller_reset_storage <= csrbank1_reset0_r; + end + netv2_soccontroller_reset_re <= csrbank1_reset0_re; + if (csrbank1_scratch0_re) begin + netv2_soccontroller_scratch_storage[31:0] <= csrbank1_scratch0_r; + end + netv2_soccontroller_scratch_re <= csrbank1_scratch0_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[3:0]) + 1'd0: begin + interface2_bank_bus_dat_r <= csrbank2_rst0_w; + end + 1'd1: begin + interface2_bank_bus_dat_r <= csrbank2_half_sys8x_taps0_w; + end + 2'd2: begin + interface2_bank_bus_dat_r <= csrbank2_wlevel_en0_w; + end + 2'd3: begin + interface2_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w; + end + 3'd4: begin + interface2_bank_bus_dat_r <= csrbank2_dly_sel0_w; + end + 3'd5: begin + interface2_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w; + end + 3'd6: begin + interface2_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w; + end + 3'd7: begin + interface2_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w; + end + 4'd8: begin + interface2_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w; + end + 4'd9: begin + interface2_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w; + end + 4'd10: begin + interface2_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w; + end + 4'd11: begin + interface2_bank_bus_dat_r <= csrbank2_rdphase0_w; + end + 4'd12: begin + interface2_bank_bus_dat_r <= csrbank2_wrphase0_w; + end + endcase + end + if (csrbank2_rst0_re) begin + a7ddrphy_rst_storage <= csrbank2_rst0_r; + end + a7ddrphy_rst_re <= csrbank2_rst0_re; + if (csrbank2_half_sys8x_taps0_re) begin + a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank2_half_sys8x_taps0_r; + end + a7ddrphy_half_sys8x_taps_re <= csrbank2_half_sys8x_taps0_re; + if (csrbank2_wlevel_en0_re) begin + a7ddrphy_wlevel_en_storage <= csrbank2_wlevel_en0_r; + end + a7ddrphy_wlevel_en_re <= csrbank2_wlevel_en0_re; + if (csrbank2_dly_sel0_re) begin + a7ddrphy_dly_sel_storage[3:0] <= csrbank2_dly_sel0_r; + end + a7ddrphy_dly_sel_re <= csrbank2_dly_sel0_re; + if (csrbank2_rdphase0_re) begin + a7ddrphy_rdphase_storage[1:0] <= csrbank2_rdphase0_r; + end + a7ddrphy_rdphase_re <= csrbank2_rdphase0_re; + if (csrbank2_wrphase0_re) begin + a7ddrphy_wrphase_storage[1:0] <= csrbank2_wrphase0_r; + end + a7ddrphy_wrphase_re <= csrbank2_wrphase0_re; + interface3_bank_bus_dat_r <= 1'd0; + if (csrbank3_sel) begin + case (interface3_bank_bus_adr[0]) + 1'd0: begin + interface3_bank_bus_dat_r <= csrbank3_id1_w; + end + 1'd1: begin + interface3_bank_bus_dat_r <= csrbank3_id0_w; + end + endcase + end + interface4_bank_bus_dat_r <= 1'd0; + if (csrbank4_sel) begin + case (interface4_bank_bus_adr[1:0]) + 1'd0: begin + interface4_bank_bus_dat_r <= csrbank4_crg_reset0_w; + end + 1'd1: begin + interface4_bank_bus_dat_r <= csrbank4_mdio_w0_w; + end + 2'd2: begin + interface4_bank_bus_dat_r <= csrbank4_mdio_r_w; + end + endcase + end + if (csrbank4_crg_reset0_re) begin + ethphy_reset_storage <= csrbank4_crg_reset0_r; + end + ethphy_reset_re <= csrbank4_crg_reset0_re; + if (csrbank4_mdio_w0_re) begin + ethphy__w_storage[2:0] <= csrbank4_mdio_w0_r; + end + ethphy__w_re <= csrbank4_mdio_w0_re; + interface5_bank_bus_dat_r <= 1'd0; + if (csrbank5_sel) begin + case (interface5_bank_bus_adr[2:0]) + 1'd0: begin + interface5_bank_bus_dat_r <= csrbank5_spi_control0_w; + end + 1'd1: begin + interface5_bank_bus_dat_r <= csrbank5_spi_status_w; + end + 2'd2: begin + interface5_bank_bus_dat_r <= csrbank5_spi_mosi1_w; + end + 2'd3: begin + interface5_bank_bus_dat_r <= csrbank5_spi_mosi0_w; + end + 3'd4: begin + interface5_bank_bus_dat_r <= csrbank5_spi_miso1_w; + end + 3'd5: begin + interface5_bank_bus_dat_r <= csrbank5_spi_miso0_w; + end + 3'd6: begin + interface5_bank_bus_dat_r <= csrbank5_spi_cs0_w; + end + 3'd7: begin + interface5_bank_bus_dat_r <= csrbank5_spi_loopback0_w; + end + endcase + end + if (csrbank5_spi_control0_re) begin + flash_control_storage[15:0] <= csrbank5_spi_control0_r; + end + flash_control_re <= csrbank5_spi_control0_re; + if (csrbank5_spi_mosi1_re) begin + flash_mosi_storage[39:32] <= csrbank5_spi_mosi1_r; + end + if (csrbank5_spi_mosi0_re) begin + flash_mosi_storage[31:0] <= csrbank5_spi_mosi0_r; + end + flash_mosi_re <= csrbank5_spi_mosi0_re; + if (csrbank5_spi_cs0_re) begin + flash_cs_storage <= csrbank5_spi_cs0_r; + end + flash_cs_re <= csrbank5_spi_cs0_re; + if (csrbank5_spi_loopback0_re) begin + flash_loopback_storage <= csrbank5_spi_loopback0_r; + end + flash_loopback_re <= csrbank5_spi_loopback0_re; + sram0_sel_r <= sram0_sel; + interface6_bank_bus_dat_r <= 1'd0; + if (csrbank6_sel) begin + case (interface6_bank_bus_adr[5:0]) + 1'd0: begin + interface6_bank_bus_dat_r <= csrbank6_edid_hpd_notif_w; + end + 1'd1: begin + interface6_bank_bus_dat_r <= csrbank6_edid_hpd_en0_w; + end + 2'd2: begin + interface6_bank_bus_dat_r <= csrbank6_clocking_mmcm_reset0_w; + end + 2'd3: begin + interface6_bank_bus_dat_r <= csrbank6_clocking_locked_w; + end + 3'd4: begin + interface6_bank_bus_dat_r <= hdmi_in0_mmcm_read_w; + end + 3'd5: begin + interface6_bank_bus_dat_r <= hdmi_in0_mmcm_write_w; + end + 3'd6: begin + interface6_bank_bus_dat_r <= csrbank6_clocking_mmcm_drdy_w; + end + 3'd7: begin + interface6_bank_bus_dat_r <= csrbank6_clocking_mmcm_adr0_w; + end + 4'd8: begin + interface6_bank_bus_dat_r <= csrbank6_clocking_mmcm_dat_w0_w; + end + 4'd9: begin + interface6_bank_bus_dat_r <= csrbank6_clocking_mmcm_dat_r_w; + end + 4'd10: begin + interface6_bank_bus_dat_r <= hdmi_in0_mmcm_write_o_w; + end + 4'd11: begin + interface6_bank_bus_dat_r <= hdmi_in0_mmcm_read_o_w; + end + 4'd12: begin + interface6_bank_bus_dat_r <= csrbank6_clocking_mmcm_dat_o_r_w; + end + 4'd13: begin + interface6_bank_bus_dat_r <= csrbank6_clocking_mmcm_drdy_o_w; + end + 4'd14: begin + interface6_bank_bus_dat_r <= hdmi_in0_s7datacapture0_dly_ctl_w; + end + 4'd15: begin + interface6_bank_bus_dat_r <= csrbank6_data0_cap_phase_w; + end + 5'd16: begin + interface6_bank_bus_dat_r <= hdmi_in0_s7datacapture0_phase_reset_w; + end + 5'd17: begin + interface6_bank_bus_dat_r <= csrbank6_data0_cap_cntvalueout_m_w; + end + 5'd18: begin + interface6_bank_bus_dat_r <= csrbank6_data0_cap_cntvalueout_s_w; + end + 5'd19: begin + interface6_bank_bus_dat_r <= csrbank6_data0_charsync_char_synced_w; + end + 5'd20: begin + interface6_bank_bus_dat_r <= csrbank6_data0_charsync_ctl_pos_w; + end + 5'd21: begin + interface6_bank_bus_dat_r <= hdmi_in0_wer0_update_w; + end + 5'd22: begin + interface6_bank_bus_dat_r <= csrbank6_data0_wer_value_w; + end + 5'd23: begin + interface6_bank_bus_dat_r <= hdmi_in0_s7datacapture1_dly_ctl_w; + end + 5'd24: begin + interface6_bank_bus_dat_r <= csrbank6_data1_cap_phase_w; + end + 5'd25: begin + interface6_bank_bus_dat_r <= hdmi_in0_s7datacapture1_phase_reset_w; + end + 5'd26: begin + interface6_bank_bus_dat_r <= csrbank6_data1_cap_cntvalueout_m_w; + end + 5'd27: begin + interface6_bank_bus_dat_r <= csrbank6_data1_cap_cntvalueout_s_w; + end + 5'd28: begin + interface6_bank_bus_dat_r <= csrbank6_data1_charsync_char_synced_w; + end + 5'd29: begin + interface6_bank_bus_dat_r <= csrbank6_data1_charsync_ctl_pos_w; + end + 5'd30: begin + interface6_bank_bus_dat_r <= hdmi_in0_wer1_update_w; + end + 5'd31: begin + interface6_bank_bus_dat_r <= csrbank6_data1_wer_value_w; + end + 6'd32: begin + interface6_bank_bus_dat_r <= hdmi_in0_s7datacapture2_dly_ctl_w; + end + 6'd33: begin + interface6_bank_bus_dat_r <= csrbank6_data2_cap_phase_w; + end + 6'd34: begin + interface6_bank_bus_dat_r <= hdmi_in0_s7datacapture2_phase_reset_w; + end + 6'd35: begin + interface6_bank_bus_dat_r <= csrbank6_data2_cap_cntvalueout_m_w; + end + 6'd36: begin + interface6_bank_bus_dat_r <= csrbank6_data2_cap_cntvalueout_s_w; + end + 6'd37: begin + interface6_bank_bus_dat_r <= csrbank6_data2_charsync_char_synced_w; + end + 6'd38: begin + interface6_bank_bus_dat_r <= csrbank6_data2_charsync_ctl_pos_w; + end + 6'd39: begin + interface6_bank_bus_dat_r <= hdmi_in0_wer2_update_w; + end + 6'd40: begin + interface6_bank_bus_dat_r <= csrbank6_data2_wer_value_w; + end + 6'd41: begin + interface6_bank_bus_dat_r <= csrbank6_chansync_channels_synced_w; + end + 6'd42: begin + interface6_bank_bus_dat_r <= csrbank6_resdetection_hres_w; + end + 6'd43: begin + interface6_bank_bus_dat_r <= csrbank6_resdetection_vres_w; + end + 6'd44: begin + interface6_bank_bus_dat_r <= hdmi_in0_frame_overflow_w; + end + 6'd45: begin + interface6_bank_bus_dat_r <= csrbank6_dma_frame_size0_w; + end + 6'd46: begin + interface6_bank_bus_dat_r <= csrbank6_dma_slot0_status0_w; + end + 6'd47: begin + interface6_bank_bus_dat_r <= csrbank6_dma_slot0_address0_w; + end + 6'd48: begin + interface6_bank_bus_dat_r <= csrbank6_dma_slot1_status0_w; + end + 6'd49: begin + interface6_bank_bus_dat_r <= csrbank6_dma_slot1_address0_w; + end + 6'd50: begin + interface6_bank_bus_dat_r <= hdmi_in0_dma_slot_array_status_w; + end + 6'd51: begin + interface6_bank_bus_dat_r <= hdmi_in0_dma_slot_array_pending_w; + end + 6'd52: begin + interface6_bank_bus_dat_r <= csrbank6_dma_ev_enable0_w; + end + endcase + end + if (csrbank6_edid_hpd_en0_re) begin + hdmi_in0_hpd_en_storage <= csrbank6_edid_hpd_en0_r; + end + hdmi_in0_hpd_en_re <= csrbank6_edid_hpd_en0_re; + if (csrbank6_clocking_mmcm_reset0_re) begin + hdmi_in0_mmcm_reset_storage <= csrbank6_clocking_mmcm_reset0_r; + end + hdmi_in0_mmcm_reset_re <= csrbank6_clocking_mmcm_reset0_re; + if (csrbank6_clocking_mmcm_adr0_re) begin + hdmi_in0_mmcm_adr_storage[6:0] <= csrbank6_clocking_mmcm_adr0_r; + end + hdmi_in0_mmcm_adr_re <= csrbank6_clocking_mmcm_adr0_re; + if (csrbank6_clocking_mmcm_dat_w0_re) begin + hdmi_in0_mmcm_dat_w_storage[15:0] <= csrbank6_clocking_mmcm_dat_w0_r; + end + hdmi_in0_mmcm_dat_w_re <= csrbank6_clocking_mmcm_dat_w0_re; + if (csrbank6_dma_frame_size0_re) begin + hdmi_in0_dma_frame_size_storage[28:0] <= csrbank6_dma_frame_size0_r; + end + hdmi_in0_dma_frame_size_re <= csrbank6_dma_frame_size0_re; + if (hdmi_in0_dma_slot_array_slot0_status_we) begin + hdmi_in0_dma_slot_array_slot0_status_storage <= hdmi_in0_dma_slot_array_slot0_status_dat_w; + end + if (csrbank6_dma_slot0_status0_re) begin + hdmi_in0_dma_slot_array_slot0_status_storage[1:0] <= csrbank6_dma_slot0_status0_r; + end + hdmi_in0_dma_slot_array_slot0_status_re <= csrbank6_dma_slot0_status0_re; + if (hdmi_in0_dma_slot_array_slot0_address_we) begin + hdmi_in0_dma_slot_array_slot0_address_storage <= hdmi_in0_dma_slot_array_slot0_address_dat_w; + end + if (csrbank6_dma_slot0_address0_re) begin + hdmi_in0_dma_slot_array_slot0_address_storage[28:0] <= csrbank6_dma_slot0_address0_r; + end + hdmi_in0_dma_slot_array_slot0_address_re <= csrbank6_dma_slot0_address0_re; + if (hdmi_in0_dma_slot_array_slot1_status_we) begin + hdmi_in0_dma_slot_array_slot1_status_storage <= hdmi_in0_dma_slot_array_slot1_status_dat_w; + end + if (csrbank6_dma_slot1_status0_re) begin + hdmi_in0_dma_slot_array_slot1_status_storage[1:0] <= csrbank6_dma_slot1_status0_r; + end + hdmi_in0_dma_slot_array_slot1_status_re <= csrbank6_dma_slot1_status0_re; + if (hdmi_in0_dma_slot_array_slot1_address_we) begin + hdmi_in0_dma_slot_array_slot1_address_storage <= hdmi_in0_dma_slot_array_slot1_address_dat_w; + end + if (csrbank6_dma_slot1_address0_re) begin + hdmi_in0_dma_slot_array_slot1_address_storage[28:0] <= csrbank6_dma_slot1_address0_r; + end + hdmi_in0_dma_slot_array_slot1_address_re <= csrbank6_dma_slot1_address0_re; + if (csrbank6_dma_ev_enable0_re) begin + hdmi_in0_dma_slot_array_storage[1:0] <= csrbank6_dma_ev_enable0_r; + end + hdmi_in0_dma_slot_array_re <= csrbank6_dma_ev_enable0_re; + interface7_bank_bus_dat_r <= 1'd0; + if (csrbank7_sel) begin + case (interface7_bank_bus_adr[0]) + 1'd0: begin + interface7_bank_bus_dat_r <= csrbank7_value_w; + end + endcase + end + interface8_bank_bus_dat_r <= 1'd0; + if (csrbank8_sel) begin + case (interface8_bank_bus_adr[4:0]) + 1'd0: begin + interface8_bank_bus_dat_r <= csrbank8_core_underflow_enable0_w; + end + 1'd1: begin + interface8_bank_bus_dat_r <= hdmi_out0_core_underflow_update_underflow_update_w; + end + 2'd2: begin + interface8_bank_bus_dat_r <= csrbank8_core_underflow_counter_w; + end + 2'd3: begin + interface8_bank_bus_dat_r <= csrbank8_core_initiator_enable0_w; + end + 3'd4: begin + interface8_bank_bus_dat_r <= csrbank8_core_initiator_hres0_w; + end + 3'd5: begin + interface8_bank_bus_dat_r <= csrbank8_core_initiator_hsync_start0_w; + end + 3'd6: begin + interface8_bank_bus_dat_r <= csrbank8_core_initiator_hsync_end0_w; + end + 3'd7: begin + interface8_bank_bus_dat_r <= csrbank8_core_initiator_hscan0_w; + end + 4'd8: begin + interface8_bank_bus_dat_r <= csrbank8_core_initiator_vres0_w; + end + 4'd9: begin + interface8_bank_bus_dat_r <= csrbank8_core_initiator_vsync_start0_w; + end + 4'd10: begin + interface8_bank_bus_dat_r <= csrbank8_core_initiator_vsync_end0_w; + end + 4'd11: begin + interface8_bank_bus_dat_r <= csrbank8_core_initiator_vscan0_w; + end + 4'd12: begin + interface8_bank_bus_dat_r <= csrbank8_core_initiator_base0_w; + end + 4'd13: begin + interface8_bank_bus_dat_r <= csrbank8_core_initiator_length0_w; + end + 4'd14: begin + interface8_bank_bus_dat_r <= csrbank8_core_dma_delay_base0_w; + end + 4'd15: begin + interface8_bank_bus_dat_r <= csrbank8_driver_clocking_mmcm_reset0_w; + end + 5'd16: begin + interface8_bank_bus_dat_r <= hdmi_out0_driver_s7hdmioutclocking_mmcm_read_w; + end + 5'd17: begin + interface8_bank_bus_dat_r <= hdmi_out0_driver_s7hdmioutclocking_mmcm_write_w; + end + 5'd18: begin + interface8_bank_bus_dat_r <= csrbank8_driver_clocking_mmcm_drdy_w; + end + 5'd19: begin + interface8_bank_bus_dat_r <= csrbank8_driver_clocking_mmcm_adr0_w; + end + 5'd20: begin + interface8_bank_bus_dat_r <= csrbank8_driver_clocking_mmcm_dat_w0_w; + end + 5'd21: begin + interface8_bank_bus_dat_r <= csrbank8_driver_clocking_mmcm_dat_r_w; + end + endcase + end + if (csrbank8_core_underflow_enable0_re) begin + hdmi_out0_core_underflow_enable_storage <= csrbank8_core_underflow_enable0_r; + end + hdmi_out0_core_underflow_enable_re <= csrbank8_core_underflow_enable0_re; + if (csrbank8_core_initiator_enable0_re) begin + hdmi_out0_core_initiator_enable_storage <= csrbank8_core_initiator_enable0_r; + end + hdmi_out0_core_initiator_enable_re <= csrbank8_core_initiator_enable0_re; + if (csrbank8_core_initiator_hres0_re) begin + hdmi_out0_core_initiator_csrstorage0_storage[11:0] <= csrbank8_core_initiator_hres0_r; + end + hdmi_out0_core_initiator_csrstorage0_re <= csrbank8_core_initiator_hres0_re; + if (csrbank8_core_initiator_hsync_start0_re) begin + hdmi_out0_core_initiator_csrstorage1_storage[11:0] <= csrbank8_core_initiator_hsync_start0_r; + end + hdmi_out0_core_initiator_csrstorage1_re <= csrbank8_core_initiator_hsync_start0_re; + if (csrbank8_core_initiator_hsync_end0_re) begin + hdmi_out0_core_initiator_csrstorage2_storage[11:0] <= csrbank8_core_initiator_hsync_end0_r; + end + hdmi_out0_core_initiator_csrstorage2_re <= csrbank8_core_initiator_hsync_end0_re; + if (csrbank8_core_initiator_hscan0_re) begin + hdmi_out0_core_initiator_csrstorage3_storage[11:0] <= csrbank8_core_initiator_hscan0_r; + end + hdmi_out0_core_initiator_csrstorage3_re <= csrbank8_core_initiator_hscan0_re; + if (csrbank8_core_initiator_vres0_re) begin + hdmi_out0_core_initiator_csrstorage4_storage[11:0] <= csrbank8_core_initiator_vres0_r; + end + hdmi_out0_core_initiator_csrstorage4_re <= csrbank8_core_initiator_vres0_re; + if (csrbank8_core_initiator_vsync_start0_re) begin + hdmi_out0_core_initiator_csrstorage5_storage[11:0] <= csrbank8_core_initiator_vsync_start0_r; + end + hdmi_out0_core_initiator_csrstorage5_re <= csrbank8_core_initiator_vsync_start0_re; + if (csrbank8_core_initiator_vsync_end0_re) begin + hdmi_out0_core_initiator_csrstorage6_storage[11:0] <= csrbank8_core_initiator_vsync_end0_r; + end + hdmi_out0_core_initiator_csrstorage6_re <= csrbank8_core_initiator_vsync_end0_re; + if (csrbank8_core_initiator_vscan0_re) begin + hdmi_out0_core_initiator_csrstorage7_storage[11:0] <= csrbank8_core_initiator_vscan0_r; + end + hdmi_out0_core_initiator_csrstorage7_re <= csrbank8_core_initiator_vscan0_re; + if (csrbank8_core_initiator_base0_re) begin + hdmi_out0_core_initiator_csrstorage8_storage[31:0] <= csrbank8_core_initiator_base0_r; + end + hdmi_out0_core_initiator_csrstorage8_re <= csrbank8_core_initiator_base0_re; + if (csrbank8_core_initiator_length0_re) begin + hdmi_out0_core_initiator_csrstorage9_storage[31:0] <= csrbank8_core_initiator_length0_r; + end + hdmi_out0_core_initiator_csrstorage9_re <= csrbank8_core_initiator_length0_re; + if (csrbank8_core_dma_delay_base0_re) begin + hdmi_out0_core_dmareader_storage[31:0] <= csrbank8_core_dma_delay_base0_r; + end + hdmi_out0_core_dmareader_re <= csrbank8_core_dma_delay_base0_re; + if (csrbank8_driver_clocking_mmcm_reset0_re) begin + hdmi_out0_driver_s7hdmioutclocking_mmcm_reset_storage <= csrbank8_driver_clocking_mmcm_reset0_r; + end + hdmi_out0_driver_s7hdmioutclocking_mmcm_reset_re <= csrbank8_driver_clocking_mmcm_reset0_re; + if (csrbank8_driver_clocking_mmcm_adr0_re) begin + hdmi_out0_driver_s7hdmioutclocking_mmcm_adr_storage[6:0] <= csrbank8_driver_clocking_mmcm_adr0_r; + end + hdmi_out0_driver_s7hdmioutclocking_mmcm_adr_re <= csrbank8_driver_clocking_mmcm_adr0_re; + if (csrbank8_driver_clocking_mmcm_dat_w0_re) begin + hdmi_out0_driver_s7hdmioutclocking_mmcm_dat_w_storage[15:0] <= csrbank8_driver_clocking_mmcm_dat_w0_r; + end + hdmi_out0_driver_s7hdmioutclocking_mmcm_dat_w_re <= csrbank8_driver_clocking_mmcm_dat_w0_re; + interface9_bank_bus_dat_r <= 1'd0; + if (csrbank9_sel) begin + case (interface9_bank_bus_adr[1:0]) + 1'd0: begin + interface9_bank_bus_dat_r <= csrbank9_addr0_w; + end + 1'd1: begin + interface9_bank_bus_dat_r <= csrbank9_data0_w; + end + 2'd2: begin + interface9_bank_bus_dat_r <= csrbank9_send0_w; + end + 2'd3: begin + interface9_bank_bus_dat_r <= csrbank9_done_w; + end + endcase + end + if (csrbank9_addr0_re) begin + icap_addr_storage[4:0] <= csrbank9_addr0_r; + end + icap_addr_re <= csrbank9_addr0_re; + if (csrbank9_data0_re) begin + icap_data_storage[31:0] <= csrbank9_data0_r; + end + icap_data_re <= csrbank9_data0_re; + if (csrbank9_send0_re) begin + icap_send_storage <= csrbank9_send0_r; + end + icap_send_re <= csrbank9_send0_re; + sram1_sel_r <= sram1_sel; + interface10_bank_bus_dat_r <= 1'd0; + if (csrbank10_sel) begin + case (interface10_bank_bus_adr[4:0]) + 1'd0: begin + interface10_bank_bus_dat_r <= csrbank10_writer_enable0_w; + end + 1'd1: begin + interface10_bank_bus_dat_r <= csrbank10_writer_table_value1_w; + end + 2'd2: begin + interface10_bank_bus_dat_r <= csrbank10_writer_table_value0_w; + end + 2'd3: begin + interface10_bank_bus_dat_r <= csrbank10_writer_table_we0_w; + end + 3'd4: begin + interface10_bank_bus_dat_r <= csrbank10_writer_table_loop_prog_n0_w; + end + 3'd5: begin + interface10_bank_bus_dat_r <= csrbank10_writer_table_loop_status_w; + end + 3'd6: begin + interface10_bank_bus_dat_r <= csrbank10_writer_table_level_w; + end + 3'd7: begin + interface10_bank_bus_dat_r <= csrbank10_writer_table_flush0_w; + end + 4'd8: begin + interface10_bank_bus_dat_r <= csrbank10_reader_enable0_w; + end + 4'd9: begin + interface10_bank_bus_dat_r <= csrbank10_reader_table_value1_w; + end + 4'd10: begin + interface10_bank_bus_dat_r <= csrbank10_reader_table_value0_w; + end + 4'd11: begin + interface10_bank_bus_dat_r <= csrbank10_reader_table_we0_w; + end + 4'd12: begin + interface10_bank_bus_dat_r <= csrbank10_reader_table_loop_prog_n0_w; + end + 4'd13: begin + interface10_bank_bus_dat_r <= csrbank10_reader_table_loop_status_w; + end + 4'd14: begin + interface10_bank_bus_dat_r <= csrbank10_reader_table_level_w; + end + 4'd15: begin + interface10_bank_bus_dat_r <= csrbank10_reader_table_flush0_w; + end + 5'd16: begin + interface10_bank_bus_dat_r <= csrbank10_loopback_enable0_w; + end + 5'd17: begin + interface10_bank_bus_dat_r <= csrbank10_buffering_reader_fifo_depth0_w; + end + 5'd18: begin + interface10_bank_bus_dat_r <= csrbank10_buffering_reader_fifo_level_w; + end + 5'd19: begin + interface10_bank_bus_dat_r <= csrbank10_buffering_writer_fifo_depth0_w; + end + 5'd20: begin + interface10_bank_bus_dat_r <= csrbank10_buffering_writer_fifo_level_w; + end + endcase + end + if (csrbank10_writer_enable0_re) begin + pcie_dma0_writer_enable_storage <= csrbank10_writer_enable0_r; + end + pcie_dma0_writer_enable_re <= csrbank10_writer_enable0_re; + if (csrbank10_writer_table_value1_re) begin + pcie_dma0_writer_value_storage[57:32] <= csrbank10_writer_table_value1_r; + end + if (csrbank10_writer_table_value0_re) begin + pcie_dma0_writer_value_storage[31:0] <= csrbank10_writer_table_value0_r; + end + pcie_dma0_writer_value_re <= csrbank10_writer_table_value0_re; + if (csrbank10_writer_table_we0_re) begin + pcie_dma0_writer_we_storage <= csrbank10_writer_table_we0_r; + end + pcie_dma0_writer_we_re <= csrbank10_writer_table_we0_re; + if (csrbank10_writer_table_loop_prog_n0_re) begin + pcie_dma0_writer_loop_prog_n_storage <= csrbank10_writer_table_loop_prog_n0_r; + end + pcie_dma0_writer_loop_prog_n_re <= csrbank10_writer_table_loop_prog_n0_re; + if (csrbank10_writer_table_flush0_re) begin + pcie_dma0_writer_flush_storage <= csrbank10_writer_table_flush0_r; + end + pcie_dma0_writer_flush_re <= csrbank10_writer_table_flush0_re; + if (csrbank10_reader_enable0_re) begin + pcie_dma0_reader_enable_storage <= csrbank10_reader_enable0_r; + end + pcie_dma0_reader_enable_re <= csrbank10_reader_enable0_re; + if (csrbank10_reader_table_value1_re) begin + pcie_dma0_reader_value_storage[57:32] <= csrbank10_reader_table_value1_r; + end + if (csrbank10_reader_table_value0_re) begin + pcie_dma0_reader_value_storage[31:0] <= csrbank10_reader_table_value0_r; + end + pcie_dma0_reader_value_re <= csrbank10_reader_table_value0_re; + if (csrbank10_reader_table_we0_re) begin + pcie_dma0_reader_we_storage <= csrbank10_reader_table_we0_r; + end + pcie_dma0_reader_we_re <= csrbank10_reader_table_we0_re; + if (csrbank10_reader_table_loop_prog_n0_re) begin + pcie_dma0_reader_loop_prog_n_storage <= csrbank10_reader_table_loop_prog_n0_r; + end + pcie_dma0_reader_loop_prog_n_re <= csrbank10_reader_table_loop_prog_n0_re; + if (csrbank10_reader_table_flush0_re) begin + pcie_dma0_reader_flush_storage <= csrbank10_reader_table_flush0_r; + end + pcie_dma0_reader_flush_re <= csrbank10_reader_table_flush0_re; + if (csrbank10_loopback_enable0_re) begin + pcie_dma0_loopback_storage <= csrbank10_loopback_enable0_r; + end + pcie_dma0_loopback_re <= csrbank10_loopback_enable0_re; + if (csrbank10_buffering_reader_fifo_depth0_re) begin + pcie_dma0_buffering_reader_fifo_depth_storage[10:0] <= csrbank10_buffering_reader_fifo_depth0_r; + end + pcie_dma0_buffering_reader_fifo_depth_re <= csrbank10_buffering_reader_fifo_depth0_re; + if (csrbank10_buffering_writer_fifo_depth0_re) begin + pcie_dma0_buffering_writer_fifo_depth_storage[10:0] <= csrbank10_buffering_writer_fifo_depth0_r; + end + pcie_dma0_buffering_writer_fifo_depth_re <= csrbank10_buffering_writer_fifo_depth0_re; + interface11_bank_bus_dat_r <= 1'd0; + if (csrbank11_sel) begin + case (interface11_bank_bus_adr[4:0]) + 1'd0: begin + interface11_bank_bus_dat_r <= csrbank11_writer_enable0_w; + end + 1'd1: begin + interface11_bank_bus_dat_r <= csrbank11_writer_table_value1_w; + end + 2'd2: begin + interface11_bank_bus_dat_r <= csrbank11_writer_table_value0_w; + end + 2'd3: begin + interface11_bank_bus_dat_r <= csrbank11_writer_table_we0_w; + end + 3'd4: begin + interface11_bank_bus_dat_r <= csrbank11_writer_table_loop_prog_n0_w; + end + 3'd5: begin + interface11_bank_bus_dat_r <= csrbank11_writer_table_loop_status_w; + end + 3'd6: begin + interface11_bank_bus_dat_r <= csrbank11_writer_table_level_w; + end + 3'd7: begin + interface11_bank_bus_dat_r <= csrbank11_writer_table_flush0_w; + end + 4'd8: begin + interface11_bank_bus_dat_r <= csrbank11_reader_enable0_w; + end + 4'd9: begin + interface11_bank_bus_dat_r <= csrbank11_reader_table_value1_w; + end + 4'd10: begin + interface11_bank_bus_dat_r <= csrbank11_reader_table_value0_w; + end + 4'd11: begin + interface11_bank_bus_dat_r <= csrbank11_reader_table_we0_w; + end + 4'd12: begin + interface11_bank_bus_dat_r <= csrbank11_reader_table_loop_prog_n0_w; + end + 4'd13: begin + interface11_bank_bus_dat_r <= csrbank11_reader_table_loop_status_w; + end + 4'd14: begin + interface11_bank_bus_dat_r <= csrbank11_reader_table_level_w; + end + 4'd15: begin + interface11_bank_bus_dat_r <= csrbank11_reader_table_flush0_w; + end + 5'd16: begin + interface11_bank_bus_dat_r <= csrbank11_loopback_enable0_w; + end + 5'd17: begin + interface11_bank_bus_dat_r <= csrbank11_buffering_reader_fifo_depth0_w; + end + 5'd18: begin + interface11_bank_bus_dat_r <= csrbank11_buffering_reader_fifo_level_w; + end + 5'd19: begin + interface11_bank_bus_dat_r <= csrbank11_buffering_writer_fifo_depth0_w; + end + 5'd20: begin + interface11_bank_bus_dat_r <= csrbank11_buffering_writer_fifo_level_w; + end + endcase + end + if (csrbank11_writer_enable0_re) begin + pcie_dma1_writer_enable_storage <= csrbank11_writer_enable0_r; + end + pcie_dma1_writer_enable_re <= csrbank11_writer_enable0_re; + if (csrbank11_writer_table_value1_re) begin + pcie_dma1_writer_value_storage[57:32] <= csrbank11_writer_table_value1_r; + end + if (csrbank11_writer_table_value0_re) begin + pcie_dma1_writer_value_storage[31:0] <= csrbank11_writer_table_value0_r; + end + pcie_dma1_writer_value_re <= csrbank11_writer_table_value0_re; + if (csrbank11_writer_table_we0_re) begin + pcie_dma1_writer_we_storage <= csrbank11_writer_table_we0_r; + end + pcie_dma1_writer_we_re <= csrbank11_writer_table_we0_re; + if (csrbank11_writer_table_loop_prog_n0_re) begin + pcie_dma1_writer_loop_prog_n_storage <= csrbank11_writer_table_loop_prog_n0_r; + end + pcie_dma1_writer_loop_prog_n_re <= csrbank11_writer_table_loop_prog_n0_re; + if (csrbank11_writer_table_flush0_re) begin + pcie_dma1_writer_flush_storage <= csrbank11_writer_table_flush0_r; + end + pcie_dma1_writer_flush_re <= csrbank11_writer_table_flush0_re; + if (csrbank11_reader_enable0_re) begin + pcie_dma1_reader_enable_storage <= csrbank11_reader_enable0_r; + end + pcie_dma1_reader_enable_re <= csrbank11_reader_enable0_re; + if (csrbank11_reader_table_value1_re) begin + pcie_dma1_reader_value_storage[57:32] <= csrbank11_reader_table_value1_r; + end + if (csrbank11_reader_table_value0_re) begin + pcie_dma1_reader_value_storage[31:0] <= csrbank11_reader_table_value0_r; + end + pcie_dma1_reader_value_re <= csrbank11_reader_table_value0_re; + if (csrbank11_reader_table_we0_re) begin + pcie_dma1_reader_we_storage <= csrbank11_reader_table_we0_r; + end + pcie_dma1_reader_we_re <= csrbank11_reader_table_we0_re; + if (csrbank11_reader_table_loop_prog_n0_re) begin + pcie_dma1_reader_loop_prog_n_storage <= csrbank11_reader_table_loop_prog_n0_r; + end + pcie_dma1_reader_loop_prog_n_re <= csrbank11_reader_table_loop_prog_n0_re; + if (csrbank11_reader_table_flush0_re) begin + pcie_dma1_reader_flush_storage <= csrbank11_reader_table_flush0_r; + end + pcie_dma1_reader_flush_re <= csrbank11_reader_table_flush0_re; + if (csrbank11_loopback_enable0_re) begin + pcie_dma1_loopback_storage <= csrbank11_loopback_enable0_r; + end + pcie_dma1_loopback_re <= csrbank11_loopback_enable0_re; + if (csrbank11_buffering_reader_fifo_depth0_re) begin + pcie_dma1_buffering_reader_fifo_depth_storage[10:0] <= csrbank11_buffering_reader_fifo_depth0_r; + end + pcie_dma1_buffering_reader_fifo_depth_re <= csrbank11_buffering_reader_fifo_depth0_re; + if (csrbank11_buffering_writer_fifo_depth0_re) begin + pcie_dma1_buffering_writer_fifo_depth_storage[10:0] <= csrbank11_buffering_writer_fifo_depth0_r; + end + pcie_dma1_buffering_writer_fifo_depth_re <= csrbank11_buffering_writer_fifo_depth0_re; + interface12_bank_bus_dat_r <= 1'd0; + if (csrbank12_sel) begin + case (interface12_bank_bus_adr[1:0]) + 1'd0: begin + interface12_bank_bus_dat_r <= csrbank12_enable0_w; + end + 1'd1: begin + interface12_bank_bus_dat_r <= csrbank12_clear0_w; + end + 2'd2: begin + interface12_bank_bus_dat_r <= csrbank12_vector_w; + end + endcase + end + if (csrbank12_enable0_re) begin + pcie_msi_enable_storage[31:0] <= csrbank12_enable0_r; + end + pcie_msi_enable_re <= csrbank12_enable0_re; + if (csrbank12_clear0_re) begin + pcie_msi_clear_storage[31:0] <= csrbank12_clear0_r; + end + pcie_msi_clear_re <= csrbank12_clear0_re; + interface13_bank_bus_dat_r <= 1'd0; + if (csrbank13_sel) begin + case (interface13_bank_bus_adr[2:0]) + 1'd0: begin + interface13_bank_bus_dat_r <= csrbank13_link_status_w; + end + 1'd1: begin + interface13_bank_bus_dat_r <= csrbank13_msi_enable_w; + end + 2'd2: begin + interface13_bank_bus_dat_r <= csrbank13_msix_enable_w; + end + 2'd3: begin + interface13_bank_bus_dat_r <= csrbank13_bus_master_enable_w; + end + 3'd4: begin + interface13_bank_bus_dat_r <= csrbank13_max_request_size_w; + end + 3'd5: begin + interface13_bank_bus_dat_r <= csrbank13_max_payload_size_w; + end + endcase + end + interface14_bank_bus_dat_r <= 1'd0; + if (csrbank14_sel) begin + case (interface14_bank_bus_adr[5:0]) + 1'd0: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_control0_w; + end + 1'd1: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi0_command0_w; + end + 2'd2: begin + interface14_bank_bus_dat_r <= netv2_sdram_phaseinjector0_command_issue_w; + end + 2'd3: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi0_address0_w; + end + 3'd4: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi0_baddress0_w; + end + 3'd5: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi0_wrdata1_w; + end + 3'd6: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi0_wrdata0_w; + end + 3'd7: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi0_rddata1_w; + end + 4'd8: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi0_rddata0_w; + end + 4'd9: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi1_command0_w; + end + 4'd10: begin + interface14_bank_bus_dat_r <= netv2_sdram_phaseinjector1_command_issue_w; + end + 4'd11: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi1_address0_w; + end + 4'd12: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi1_baddress0_w; + end + 4'd13: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi1_wrdata1_w; + end + 4'd14: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi1_wrdata0_w; + end + 4'd15: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi1_rddata1_w; + end + 5'd16: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi1_rddata0_w; + end + 5'd17: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi2_command0_w; + end + 5'd18: begin + interface14_bank_bus_dat_r <= netv2_sdram_phaseinjector2_command_issue_w; + end + 5'd19: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi2_address0_w; + end + 5'd20: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi2_baddress0_w; + end + 5'd21: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi2_wrdata1_w; + end + 5'd22: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi2_wrdata0_w; + end + 5'd23: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi2_rddata1_w; + end + 5'd24: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi2_rddata0_w; + end + 5'd25: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi3_command0_w; + end + 5'd26: begin + interface14_bank_bus_dat_r <= netv2_sdram_phaseinjector3_command_issue_w; + end + 5'd27: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi3_address0_w; + end + 5'd28: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi3_baddress0_w; + end + 5'd29: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi3_wrdata1_w; + end + 5'd30: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi3_wrdata0_w; + end + 5'd31: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi3_rddata1_w; + end + 6'd32: begin + interface14_bank_bus_dat_r <= csrbank14_dfii_pi3_rddata0_w; + end + endcase + end + if (csrbank14_dfii_control0_re) begin + netv2_sdram_storage[3:0] <= csrbank14_dfii_control0_r; + end + netv2_sdram_re <= csrbank14_dfii_control0_re; + if (csrbank14_dfii_pi0_command0_re) begin + netv2_sdram_phaseinjector0_command_storage[5:0] <= csrbank14_dfii_pi0_command0_r; + end + netv2_sdram_phaseinjector0_command_re <= csrbank14_dfii_pi0_command0_re; + if (csrbank14_dfii_pi0_address0_re) begin + netv2_sdram_phaseinjector0_address_storage[13:0] <= csrbank14_dfii_pi0_address0_r; + end + netv2_sdram_phaseinjector0_address_re <= csrbank14_dfii_pi0_address0_re; + if (csrbank14_dfii_pi0_baddress0_re) begin + netv2_sdram_phaseinjector0_baddress_storage[2:0] <= csrbank14_dfii_pi0_baddress0_r; + end + netv2_sdram_phaseinjector0_baddress_re <= csrbank14_dfii_pi0_baddress0_re; + if (csrbank14_dfii_pi0_wrdata1_re) begin + netv2_sdram_phaseinjector0_wrdata_storage[63:32] <= csrbank14_dfii_pi0_wrdata1_r; + end + if (csrbank14_dfii_pi0_wrdata0_re) begin + netv2_sdram_phaseinjector0_wrdata_storage[31:0] <= csrbank14_dfii_pi0_wrdata0_r; + end + netv2_sdram_phaseinjector0_wrdata_re <= csrbank14_dfii_pi0_wrdata0_re; + if (csrbank14_dfii_pi1_command0_re) begin + netv2_sdram_phaseinjector1_command_storage[5:0] <= csrbank14_dfii_pi1_command0_r; + end + netv2_sdram_phaseinjector1_command_re <= csrbank14_dfii_pi1_command0_re; + if (csrbank14_dfii_pi1_address0_re) begin + netv2_sdram_phaseinjector1_address_storage[13:0] <= csrbank14_dfii_pi1_address0_r; + end + netv2_sdram_phaseinjector1_address_re <= csrbank14_dfii_pi1_address0_re; + if (csrbank14_dfii_pi1_baddress0_re) begin + netv2_sdram_phaseinjector1_baddress_storage[2:0] <= csrbank14_dfii_pi1_baddress0_r; + end + netv2_sdram_phaseinjector1_baddress_re <= csrbank14_dfii_pi1_baddress0_re; + if (csrbank14_dfii_pi1_wrdata1_re) begin + netv2_sdram_phaseinjector1_wrdata_storage[63:32] <= csrbank14_dfii_pi1_wrdata1_r; + end + if (csrbank14_dfii_pi1_wrdata0_re) begin + netv2_sdram_phaseinjector1_wrdata_storage[31:0] <= csrbank14_dfii_pi1_wrdata0_r; + end + netv2_sdram_phaseinjector1_wrdata_re <= csrbank14_dfii_pi1_wrdata0_re; + if (csrbank14_dfii_pi2_command0_re) begin + netv2_sdram_phaseinjector2_command_storage[5:0] <= csrbank14_dfii_pi2_command0_r; + end + netv2_sdram_phaseinjector2_command_re <= csrbank14_dfii_pi2_command0_re; + if (csrbank14_dfii_pi2_address0_re) begin + netv2_sdram_phaseinjector2_address_storage[13:0] <= csrbank14_dfii_pi2_address0_r; + end + netv2_sdram_phaseinjector2_address_re <= csrbank14_dfii_pi2_address0_re; + if (csrbank14_dfii_pi2_baddress0_re) begin + netv2_sdram_phaseinjector2_baddress_storage[2:0] <= csrbank14_dfii_pi2_baddress0_r; + end + netv2_sdram_phaseinjector2_baddress_re <= csrbank14_dfii_pi2_baddress0_re; + if (csrbank14_dfii_pi2_wrdata1_re) begin + netv2_sdram_phaseinjector2_wrdata_storage[63:32] <= csrbank14_dfii_pi2_wrdata1_r; + end + if (csrbank14_dfii_pi2_wrdata0_re) begin + netv2_sdram_phaseinjector2_wrdata_storage[31:0] <= csrbank14_dfii_pi2_wrdata0_r; + end + netv2_sdram_phaseinjector2_wrdata_re <= csrbank14_dfii_pi2_wrdata0_re; + if (csrbank14_dfii_pi3_command0_re) begin + netv2_sdram_phaseinjector3_command_storage[5:0] <= csrbank14_dfii_pi3_command0_r; + end + netv2_sdram_phaseinjector3_command_re <= csrbank14_dfii_pi3_command0_re; + if (csrbank14_dfii_pi3_address0_re) begin + netv2_sdram_phaseinjector3_address_storage[13:0] <= csrbank14_dfii_pi3_address0_r; + end + netv2_sdram_phaseinjector3_address_re <= csrbank14_dfii_pi3_address0_re; + if (csrbank14_dfii_pi3_baddress0_re) begin + netv2_sdram_phaseinjector3_baddress_storage[2:0] <= csrbank14_dfii_pi3_baddress0_r; + end + netv2_sdram_phaseinjector3_baddress_re <= csrbank14_dfii_pi3_baddress0_re; + if (csrbank14_dfii_pi3_wrdata1_re) begin + netv2_sdram_phaseinjector3_wrdata_storage[63:32] <= csrbank14_dfii_pi3_wrdata1_r; + end + if (csrbank14_dfii_pi3_wrdata0_re) begin + netv2_sdram_phaseinjector3_wrdata_storage[31:0] <= csrbank14_dfii_pi3_wrdata0_r; + end + netv2_sdram_phaseinjector3_wrdata_re <= csrbank14_dfii_pi3_wrdata0_re; + interface15_bank_bus_dat_r <= 1'd0; + if (csrbank15_sel) begin + case (interface15_bank_bus_adr[2:0]) + 1'd0: begin + interface15_bank_bus_dat_r <= csrbank15_load0_w; + end + 1'd1: begin + interface15_bank_bus_dat_r <= csrbank15_reload0_w; + end + 2'd2: begin + interface15_bank_bus_dat_r <= csrbank15_en0_w; + end + 2'd3: begin + interface15_bank_bus_dat_r <= csrbank15_update_value0_w; + end + 3'd4: begin + interface15_bank_bus_dat_r <= csrbank15_value_w; + end + 3'd5: begin + interface15_bank_bus_dat_r <= netv2_eventmanager_status_w; + end + 3'd6: begin + interface15_bank_bus_dat_r <= netv2_eventmanager_pending_w; + end + 3'd7: begin + interface15_bank_bus_dat_r <= csrbank15_ev_enable0_w; + end + endcase + end + if (csrbank15_load0_re) begin + netv2_load_storage[31:0] <= csrbank15_load0_r; + end + netv2_load_re <= csrbank15_load0_re; + if (csrbank15_reload0_re) begin + netv2_reload_storage[31:0] <= csrbank15_reload0_r; + end + netv2_reload_re <= csrbank15_reload0_re; + if (csrbank15_en0_re) begin + netv2_en_storage <= csrbank15_en0_r; + end + netv2_en_re <= csrbank15_en0_re; + if (csrbank15_update_value0_re) begin + netv2_update_value_storage <= csrbank15_update_value0_r; + end + netv2_update_value_re <= csrbank15_update_value0_re; + if (csrbank15_ev_enable0_re) begin + netv2_eventmanager_storage <= csrbank15_ev_enable0_r; + end + netv2_eventmanager_re <= csrbank15_ev_enable0_re; + interface16_bank_bus_dat_r <= 1'd0; + if (csrbank16_sel) begin + case (interface16_bank_bus_adr[3:0]) + 1'd0: begin + interface16_bank_bus_dat_r <= netv2_uartcrossover_rxtx_w; + end + 1'd1: begin + interface16_bank_bus_dat_r <= csrbank16_txfull_w; + end + 2'd2: begin + interface16_bank_bus_dat_r <= csrbank16_rxempty_w; + end + 2'd3: begin + interface16_bank_bus_dat_r <= netv2_uartcrossover_eventmanager_status_w; + end + 3'd4: begin + interface16_bank_bus_dat_r <= netv2_uartcrossover_eventmanager_pending_w; + end + 3'd5: begin + interface16_bank_bus_dat_r <= csrbank16_ev_enable0_w; + end + 3'd6: begin + interface16_bank_bus_dat_r <= csrbank16_txempty_w; + end + 3'd7: begin + interface16_bank_bus_dat_r <= csrbank16_rxfull_w; + end + 4'd8: begin + interface16_bank_bus_dat_r <= netv2_xover_rxtx_w; + end + 4'd9: begin + interface16_bank_bus_dat_r <= csrbank16_xover_txfull_w; + end + 4'd10: begin + interface16_bank_bus_dat_r <= csrbank16_xover_rxempty_w; + end + 4'd11: begin + interface16_bank_bus_dat_r <= netv2_xover_eventmanager_status_w; + end + 4'd12: begin + interface16_bank_bus_dat_r <= netv2_xover_eventmanager_pending_w; + end + 4'd13: begin + interface16_bank_bus_dat_r <= csrbank16_xover_ev_enable0_w; + end + 4'd14: begin + interface16_bank_bus_dat_r <= csrbank16_xover_txempty_w; + end + 4'd15: begin + interface16_bank_bus_dat_r <= csrbank16_xover_rxfull_w; + end + endcase + end + if (csrbank16_ev_enable0_re) begin + netv2_uartcrossover_eventmanager_storage[1:0] <= csrbank16_ev_enable0_r; + end + netv2_uartcrossover_eventmanager_re <= csrbank16_ev_enable0_re; + if (csrbank16_xover_ev_enable0_re) begin + netv2_xover_eventmanager_storage[1:0] <= csrbank16_xover_ev_enable0_r; + end + netv2_xover_eventmanager_re <= csrbank16_xover_ev_enable0_re; + interface17_bank_bus_dat_r <= 1'd0; + if (csrbank17_sel) begin + case (interface17_bank_bus_adr[2:0]) + 1'd0: begin + interface17_bank_bus_dat_r <= csrbank17_temperature_w; + end + 1'd1: begin + interface17_bank_bus_dat_r <= csrbank17_vccint_w; + end + 2'd2: begin + interface17_bank_bus_dat_r <= csrbank17_vccaux_w; + end + 2'd3: begin + interface17_bank_bus_dat_r <= csrbank17_vccbram_w; + end + 3'd4: begin + interface17_bank_bus_dat_r <= csrbank17_eoc_w; + end + 3'd5: begin + interface17_bank_bus_dat_r <= csrbank17_eos_w; + end + endcase + end + if (sys_rst) begin + netv2_soccontroller_reset_storage <= 1'd0; + netv2_soccontroller_reset_re <= 1'd0; + netv2_soccontroller_scratch_storage <= 32'd305419896; + netv2_soccontroller_scratch_re <= 1'd0; + netv2_soccontroller_bus_errors <= 32'd0; + netv2_netv2_ram_bus_ack <= 1'd0; + netv2_ram_bus_ram_bus_ack <= 1'd0; + netv2_uartcrossover_tx_pending <= 1'd0; + netv2_uartcrossover_tx_old_trigger <= 1'd0; + netv2_uartcrossover_rx_pending <= 1'd0; + netv2_uartcrossover_rx_old_trigger <= 1'd0; + netv2_uartcrossover_eventmanager_storage <= 2'd0; + netv2_uartcrossover_eventmanager_re <= 1'd0; + netv2_uartcrossover_tx_fifo_readable <= 1'd0; + netv2_uartcrossover_tx_fifo_level0 <= 5'd0; + netv2_uartcrossover_tx_fifo_produce <= 4'd0; + netv2_uartcrossover_tx_fifo_consume <= 4'd0; + netv2_uartcrossover_rx_fifo_readable <= 1'd0; + netv2_uartcrossover_rx_fifo_level0 <= 5'd0; + netv2_uartcrossover_rx_fifo_produce <= 4'd0; + netv2_uartcrossover_rx_fifo_consume <= 4'd0; + netv2_xover_tx_pending <= 1'd0; + netv2_xover_tx_old_trigger <= 1'd0; + netv2_xover_rx_pending <= 1'd0; + netv2_xover_rx_old_trigger <= 1'd0; + netv2_xover_eventmanager_storage <= 2'd0; + netv2_xover_eventmanager_re <= 1'd0; + netv2_xover_tx_fifo_source_valid <= 1'd0; + netv2_xover_tx_fifo_source_payload_data <= 8'd0; + netv2_xover_rx_fifo_source_valid <= 1'd0; + netv2_xover_rx_fifo_source_payload_data <= 8'd0; + netv2_load_storage <= 32'd0; + netv2_load_re <= 1'd0; + netv2_reload_storage <= 32'd0; + netv2_reload_re <= 1'd0; + netv2_en_storage <= 1'd0; + netv2_en_re <= 1'd0; + netv2_update_value_storage <= 1'd0; + netv2_update_value_re <= 1'd0; + netv2_value_status <= 32'd0; + netv2_zero_pending <= 1'd0; + netv2_zero_old_trigger <= 1'd0; + netv2_eventmanager_storage <= 1'd0; + netv2_eventmanager_re <= 1'd0; + netv2_value <= 32'd0; + dna_status <= 57'd0; + dna_count <= 7'd0; + xadc_temperature_status <= 12'd0; + xadc_vccint_status <= 12'd0; + xadc_vccaux_status <= 12'd0; + xadc_vccbram_status <= 12'd0; + xadc_eoc_status <= 1'd0; + xadc_eos_status <= 1'd0; + icap_clk <= 1'd0; + icap_icap_clk_counter <= 4'd0; + icap_addr_re <= 1'd0; + icap_data_re <= 1'd0; + icap_send_storage <= 1'd0; + icap_send_re <= 1'd0; + flash_pads_clk <= 1'd0; + flash_pads_cs_n <= 1'd0; + flash_pads_mosi <= 1'd0; + flash_miso1 <= 40'd0; + flash_control_storage <= 16'd0; + flash_control_re <= 1'd0; + flash_mosi_re <= 1'd0; + flash_cs_storage <= 1'd1; + flash_cs_re <= 1'd0; + flash_loopback_storage <= 1'd0; + flash_loopback_re <= 1'd0; + flash_count <= 6'd0; + flash_clk_divider1 <= 16'd0; + flash_mosi_data <= 40'd0; + flash_mosi_sel <= 6'd0; + flash_miso_data <= 40'd0; + a7ddrphy_rst_storage <= 1'd0; + a7ddrphy_rst_re <= 1'd0; + a7ddrphy_half_sys8x_taps_storage <= 5'd8; + a7ddrphy_half_sys8x_taps_re <= 1'd0; + a7ddrphy_wlevel_en_storage <= 1'd0; + a7ddrphy_wlevel_en_re <= 1'd0; + a7ddrphy_dly_sel_storage <= 4'd0; + a7ddrphy_dly_sel_re <= 1'd0; + a7ddrphy_rdphase_storage <= 2'd2; + a7ddrphy_rdphase_re <= 1'd0; + a7ddrphy_wrphase_storage <= 2'd3; + a7ddrphy_wrphase_re <= 1'd0; + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + a7ddrphy_dqspattern_o1 <= 8'd0; + a7ddrphy_bitslip0_value0 <= 3'd7; + a7ddrphy_bitslip1_value0 <= 3'd7; + a7ddrphy_bitslip2_value0 <= 3'd7; + a7ddrphy_bitslip3_value0 <= 3'd7; + a7ddrphy_bitslip0_value1 <= 3'd7; + a7ddrphy_bitslip1_value1 <= 3'd7; + a7ddrphy_bitslip2_value1 <= 3'd7; + a7ddrphy_bitslip3_value1 <= 3'd7; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + a7ddrphy_bitslip0_value2 <= 3'd7; + a7ddrphy_bitslip0_value3 <= 3'd7; + a7ddrphy_bitslip1_value2 <= 3'd7; + a7ddrphy_bitslip1_value3 <= 3'd7; + a7ddrphy_bitslip2_value2 <= 3'd7; + a7ddrphy_bitslip2_value3 <= 3'd7; + a7ddrphy_bitslip3_value2 <= 3'd7; + a7ddrphy_bitslip3_value3 <= 3'd7; + a7ddrphy_bitslip4_value0 <= 3'd7; + a7ddrphy_bitslip4_value1 <= 3'd7; + a7ddrphy_bitslip5_value0 <= 3'd7; + a7ddrphy_bitslip5_value1 <= 3'd7; + a7ddrphy_bitslip6_value0 <= 3'd7; + a7ddrphy_bitslip6_value1 <= 3'd7; + a7ddrphy_bitslip7_value0 <= 3'd7; + a7ddrphy_bitslip7_value1 <= 3'd7; + a7ddrphy_bitslip8_value0 <= 3'd7; + a7ddrphy_bitslip8_value1 <= 3'd7; + a7ddrphy_bitslip9_value0 <= 3'd7; + a7ddrphy_bitslip9_value1 <= 3'd7; + a7ddrphy_bitslip10_value0 <= 3'd7; + a7ddrphy_bitslip10_value1 <= 3'd7; + a7ddrphy_bitslip11_value0 <= 3'd7; + a7ddrphy_bitslip11_value1 <= 3'd7; + a7ddrphy_bitslip12_value0 <= 3'd7; + a7ddrphy_bitslip12_value1 <= 3'd7; + a7ddrphy_bitslip13_value0 <= 3'd7; + a7ddrphy_bitslip13_value1 <= 3'd7; + a7ddrphy_bitslip14_value0 <= 3'd7; + a7ddrphy_bitslip14_value1 <= 3'd7; + a7ddrphy_bitslip15_value0 <= 3'd7; + a7ddrphy_bitslip15_value1 <= 3'd7; + a7ddrphy_bitslip16_value0 <= 3'd7; + a7ddrphy_bitslip16_value1 <= 3'd7; + a7ddrphy_bitslip17_value0 <= 3'd7; + a7ddrphy_bitslip17_value1 <= 3'd7; + a7ddrphy_bitslip18_value0 <= 3'd7; + a7ddrphy_bitslip18_value1 <= 3'd7; + a7ddrphy_bitslip19_value0 <= 3'd7; + a7ddrphy_bitslip19_value1 <= 3'd7; + a7ddrphy_bitslip20_value0 <= 3'd7; + a7ddrphy_bitslip20_value1 <= 3'd7; + a7ddrphy_bitslip21_value0 <= 3'd7; + a7ddrphy_bitslip21_value1 <= 3'd7; + a7ddrphy_bitslip22_value0 <= 3'd7; + a7ddrphy_bitslip22_value1 <= 3'd7; + a7ddrphy_bitslip23_value0 <= 3'd7; + a7ddrphy_bitslip23_value1 <= 3'd7; + a7ddrphy_bitslip24_value0 <= 3'd7; + a7ddrphy_bitslip24_value1 <= 3'd7; + a7ddrphy_bitslip25_value0 <= 3'd7; + a7ddrphy_bitslip25_value1 <= 3'd7; + a7ddrphy_bitslip26_value0 <= 3'd7; + a7ddrphy_bitslip26_value1 <= 3'd7; + a7ddrphy_bitslip27_value0 <= 3'd7; + a7ddrphy_bitslip27_value1 <= 3'd7; + a7ddrphy_bitslip28_value0 <= 3'd7; + a7ddrphy_bitslip28_value1 <= 3'd7; + a7ddrphy_bitslip29_value0 <= 3'd7; + a7ddrphy_bitslip29_value1 <= 3'd7; + a7ddrphy_bitslip30_value0 <= 3'd7; + a7ddrphy_bitslip30_value1 <= 3'd7; + a7ddrphy_bitslip31_value0 <= 3'd7; + a7ddrphy_bitslip31_value1 <= 3'd7; + a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + netv2_sdram_storage <= 4'd1; + netv2_sdram_re <= 1'd0; + netv2_sdram_phaseinjector0_command_storage <= 6'd0; + netv2_sdram_phaseinjector0_command_re <= 1'd0; + netv2_sdram_phaseinjector0_address_re <= 1'd0; + netv2_sdram_phaseinjector0_baddress_re <= 1'd0; + netv2_sdram_phaseinjector0_wrdata_re <= 1'd0; + netv2_sdram_phaseinjector0_rddata_status <= 64'd0; + netv2_sdram_phaseinjector1_command_storage <= 6'd0; + netv2_sdram_phaseinjector1_command_re <= 1'd0; + netv2_sdram_phaseinjector1_address_re <= 1'd0; + netv2_sdram_phaseinjector1_baddress_re <= 1'd0; + netv2_sdram_phaseinjector1_wrdata_re <= 1'd0; + netv2_sdram_phaseinjector1_rddata_status <= 64'd0; + netv2_sdram_phaseinjector2_command_storage <= 6'd0; + netv2_sdram_phaseinjector2_command_re <= 1'd0; + netv2_sdram_phaseinjector2_address_re <= 1'd0; + netv2_sdram_phaseinjector2_baddress_re <= 1'd0; + netv2_sdram_phaseinjector2_wrdata_re <= 1'd0; + netv2_sdram_phaseinjector2_rddata_status <= 64'd0; + netv2_sdram_phaseinjector3_command_storage <= 6'd0; + netv2_sdram_phaseinjector3_command_re <= 1'd0; + netv2_sdram_phaseinjector3_address_re <= 1'd0; + netv2_sdram_phaseinjector3_baddress_re <= 1'd0; + netv2_sdram_phaseinjector3_wrdata_re <= 1'd0; + netv2_sdram_phaseinjector3_rddata_status <= 64'd0; + netv2_sdram_dfi_p0_address <= 14'd0; + netv2_sdram_dfi_p0_bank <= 3'd0; + netv2_sdram_dfi_p0_cas_n <= 1'd1; + netv2_sdram_dfi_p0_cs_n <= 1'd1; + netv2_sdram_dfi_p0_ras_n <= 1'd1; + netv2_sdram_dfi_p0_we_n <= 1'd1; + netv2_sdram_dfi_p0_wrdata_en <= 1'd0; + netv2_sdram_dfi_p0_rddata_en <= 1'd0; + netv2_sdram_dfi_p1_address <= 14'd0; + netv2_sdram_dfi_p1_bank <= 3'd0; + netv2_sdram_dfi_p1_cas_n <= 1'd1; + netv2_sdram_dfi_p1_cs_n <= 1'd1; + netv2_sdram_dfi_p1_ras_n <= 1'd1; + netv2_sdram_dfi_p1_we_n <= 1'd1; + netv2_sdram_dfi_p1_wrdata_en <= 1'd0; + netv2_sdram_dfi_p1_rddata_en <= 1'd0; + netv2_sdram_dfi_p2_address <= 14'd0; + netv2_sdram_dfi_p2_bank <= 3'd0; + netv2_sdram_dfi_p2_cas_n <= 1'd1; + netv2_sdram_dfi_p2_cs_n <= 1'd1; + netv2_sdram_dfi_p2_ras_n <= 1'd1; + netv2_sdram_dfi_p2_we_n <= 1'd1; + netv2_sdram_dfi_p2_wrdata_en <= 1'd0; + netv2_sdram_dfi_p2_rddata_en <= 1'd0; + netv2_sdram_dfi_p3_address <= 14'd0; + netv2_sdram_dfi_p3_bank <= 3'd0; + netv2_sdram_dfi_p3_cas_n <= 1'd1; + netv2_sdram_dfi_p3_cs_n <= 1'd1; + netv2_sdram_dfi_p3_ras_n <= 1'd1; + netv2_sdram_dfi_p3_we_n <= 1'd1; + netv2_sdram_dfi_p3_wrdata_en <= 1'd0; + netv2_sdram_dfi_p3_rddata_en <= 1'd0; + netv2_sdram_cmd_payload_a <= 14'd0; + netv2_sdram_cmd_payload_ba <= 3'd0; + netv2_sdram_cmd_payload_cas <= 1'd0; + netv2_sdram_cmd_payload_ras <= 1'd0; + netv2_sdram_cmd_payload_we <= 1'd0; + netv2_sdram_timer_count1 <= 10'd781; + netv2_sdram_postponer_req_o <= 1'd0; + netv2_sdram_postponer_count <= 1'd0; + netv2_sdram_sequencer_done1 <= 1'd0; + netv2_sdram_sequencer_counter <= 6'd0; + netv2_sdram_sequencer_count <= 1'd0; + netv2_sdram_zqcs_timer_count1 <= 27'd99999999; + netv2_sdram_zqcs_executer_done <= 1'd0; + netv2_sdram_zqcs_executer_counter <= 5'd0; + netv2_sdram_bankmachine0_cmd_buffer_lookahead_level <= 4'd0; + netv2_sdram_bankmachine0_cmd_buffer_lookahead_produce <= 3'd0; + netv2_sdram_bankmachine0_cmd_buffer_lookahead_consume <= 3'd0; + netv2_sdram_bankmachine0_cmd_buffer_source_valid <= 1'd0; + netv2_sdram_bankmachine0_cmd_buffer_source_payload_we <= 1'd0; + netv2_sdram_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0; + netv2_sdram_bankmachine0_row <= 14'd0; + netv2_sdram_bankmachine0_row_opened <= 1'd0; + netv2_sdram_bankmachine0_twtpcon_ready <= 1'd0; + netv2_sdram_bankmachine0_twtpcon_count <= 3'd0; + netv2_sdram_bankmachine0_trccon_ready <= 1'd0; + netv2_sdram_bankmachine0_trccon_count <= 3'd0; + netv2_sdram_bankmachine0_trascon_ready <= 1'd0; + netv2_sdram_bankmachine0_trascon_count <= 3'd0; + netv2_sdram_bankmachine1_cmd_buffer_lookahead_level <= 4'd0; + netv2_sdram_bankmachine1_cmd_buffer_lookahead_produce <= 3'd0; + netv2_sdram_bankmachine1_cmd_buffer_lookahead_consume <= 3'd0; + netv2_sdram_bankmachine1_cmd_buffer_source_valid <= 1'd0; + netv2_sdram_bankmachine1_cmd_buffer_source_payload_we <= 1'd0; + netv2_sdram_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0; + netv2_sdram_bankmachine1_row <= 14'd0; + netv2_sdram_bankmachine1_row_opened <= 1'd0; + netv2_sdram_bankmachine1_twtpcon_ready <= 1'd0; + netv2_sdram_bankmachine1_twtpcon_count <= 3'd0; + netv2_sdram_bankmachine1_trccon_ready <= 1'd0; + netv2_sdram_bankmachine1_trccon_count <= 3'd0; + netv2_sdram_bankmachine1_trascon_ready <= 1'd0; + netv2_sdram_bankmachine1_trascon_count <= 3'd0; + netv2_sdram_bankmachine2_cmd_buffer_lookahead_level <= 4'd0; + netv2_sdram_bankmachine2_cmd_buffer_lookahead_produce <= 3'd0; + netv2_sdram_bankmachine2_cmd_buffer_lookahead_consume <= 3'd0; + netv2_sdram_bankmachine2_cmd_buffer_source_valid <= 1'd0; + netv2_sdram_bankmachine2_cmd_buffer_source_payload_we <= 1'd0; + netv2_sdram_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0; + netv2_sdram_bankmachine2_row <= 14'd0; + netv2_sdram_bankmachine2_row_opened <= 1'd0; + netv2_sdram_bankmachine2_twtpcon_ready <= 1'd0; + netv2_sdram_bankmachine2_twtpcon_count <= 3'd0; + netv2_sdram_bankmachine2_trccon_ready <= 1'd0; + netv2_sdram_bankmachine2_trccon_count <= 3'd0; + netv2_sdram_bankmachine2_trascon_ready <= 1'd0; + netv2_sdram_bankmachine2_trascon_count <= 3'd0; + netv2_sdram_bankmachine3_cmd_buffer_lookahead_level <= 4'd0; + netv2_sdram_bankmachine3_cmd_buffer_lookahead_produce <= 3'd0; + netv2_sdram_bankmachine3_cmd_buffer_lookahead_consume <= 3'd0; + netv2_sdram_bankmachine3_cmd_buffer_source_valid <= 1'd0; + netv2_sdram_bankmachine3_cmd_buffer_source_payload_we <= 1'd0; + netv2_sdram_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0; + netv2_sdram_bankmachine3_row <= 14'd0; + netv2_sdram_bankmachine3_row_opened <= 1'd0; + netv2_sdram_bankmachine3_twtpcon_ready <= 1'd0; + netv2_sdram_bankmachine3_twtpcon_count <= 3'd0; + netv2_sdram_bankmachine3_trccon_ready <= 1'd0; + netv2_sdram_bankmachine3_trccon_count <= 3'd0; + netv2_sdram_bankmachine3_trascon_ready <= 1'd0; + netv2_sdram_bankmachine3_trascon_count <= 3'd0; + netv2_sdram_bankmachine4_cmd_buffer_lookahead_level <= 4'd0; + netv2_sdram_bankmachine4_cmd_buffer_lookahead_produce <= 3'd0; + netv2_sdram_bankmachine4_cmd_buffer_lookahead_consume <= 3'd0; + netv2_sdram_bankmachine4_cmd_buffer_source_valid <= 1'd0; + netv2_sdram_bankmachine4_cmd_buffer_source_payload_we <= 1'd0; + netv2_sdram_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0; + netv2_sdram_bankmachine4_row <= 14'd0; + netv2_sdram_bankmachine4_row_opened <= 1'd0; + netv2_sdram_bankmachine4_twtpcon_ready <= 1'd0; + netv2_sdram_bankmachine4_twtpcon_count <= 3'd0; + netv2_sdram_bankmachine4_trccon_ready <= 1'd0; + netv2_sdram_bankmachine4_trccon_count <= 3'd0; + netv2_sdram_bankmachine4_trascon_ready <= 1'd0; + netv2_sdram_bankmachine4_trascon_count <= 3'd0; + netv2_sdram_bankmachine5_cmd_buffer_lookahead_level <= 4'd0; + netv2_sdram_bankmachine5_cmd_buffer_lookahead_produce <= 3'd0; + netv2_sdram_bankmachine5_cmd_buffer_lookahead_consume <= 3'd0; + netv2_sdram_bankmachine5_cmd_buffer_source_valid <= 1'd0; + netv2_sdram_bankmachine5_cmd_buffer_source_payload_we <= 1'd0; + netv2_sdram_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0; + netv2_sdram_bankmachine5_row <= 14'd0; + netv2_sdram_bankmachine5_row_opened <= 1'd0; + netv2_sdram_bankmachine5_twtpcon_ready <= 1'd0; + netv2_sdram_bankmachine5_twtpcon_count <= 3'd0; + netv2_sdram_bankmachine5_trccon_ready <= 1'd0; + netv2_sdram_bankmachine5_trccon_count <= 3'd0; + netv2_sdram_bankmachine5_trascon_ready <= 1'd0; + netv2_sdram_bankmachine5_trascon_count <= 3'd0; + netv2_sdram_bankmachine6_cmd_buffer_lookahead_level <= 4'd0; + netv2_sdram_bankmachine6_cmd_buffer_lookahead_produce <= 3'd0; + netv2_sdram_bankmachine6_cmd_buffer_lookahead_consume <= 3'd0; + netv2_sdram_bankmachine6_cmd_buffer_source_valid <= 1'd0; + netv2_sdram_bankmachine6_cmd_buffer_source_payload_we <= 1'd0; + netv2_sdram_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0; + netv2_sdram_bankmachine6_row <= 14'd0; + netv2_sdram_bankmachine6_row_opened <= 1'd0; + netv2_sdram_bankmachine6_twtpcon_ready <= 1'd0; + netv2_sdram_bankmachine6_twtpcon_count <= 3'd0; + netv2_sdram_bankmachine6_trccon_ready <= 1'd0; + netv2_sdram_bankmachine6_trccon_count <= 3'd0; + netv2_sdram_bankmachine6_trascon_ready <= 1'd0; + netv2_sdram_bankmachine6_trascon_count <= 3'd0; + netv2_sdram_bankmachine7_cmd_buffer_lookahead_level <= 4'd0; + netv2_sdram_bankmachine7_cmd_buffer_lookahead_produce <= 3'd0; + netv2_sdram_bankmachine7_cmd_buffer_lookahead_consume <= 3'd0; + netv2_sdram_bankmachine7_cmd_buffer_source_valid <= 1'd0; + netv2_sdram_bankmachine7_cmd_buffer_source_payload_we <= 1'd0; + netv2_sdram_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0; + netv2_sdram_bankmachine7_row <= 14'd0; + netv2_sdram_bankmachine7_row_opened <= 1'd0; + netv2_sdram_bankmachine7_twtpcon_ready <= 1'd0; + netv2_sdram_bankmachine7_twtpcon_count <= 3'd0; + netv2_sdram_bankmachine7_trccon_ready <= 1'd0; + netv2_sdram_bankmachine7_trccon_count <= 3'd0; + netv2_sdram_bankmachine7_trascon_ready <= 1'd0; + netv2_sdram_bankmachine7_trascon_count <= 3'd0; + netv2_sdram_choose_cmd_grant <= 3'd0; + netv2_sdram_choose_req_grant <= 3'd0; + netv2_sdram_trrdcon_ready <= 1'd0; + netv2_sdram_trrdcon_count <= 1'd0; + netv2_sdram_tfawcon_ready <= 1'd1; + netv2_sdram_tfawcon_window <= 5'd0; + netv2_sdram_tccdcon_ready <= 1'd0; + netv2_sdram_tccdcon_count <= 1'd0; + netv2_sdram_twtrcon_ready <= 1'd0; + netv2_sdram_twtrcon_count <= 3'd0; + netv2_sdram_time0 <= 5'd0; + netv2_sdram_time1 <= 4'd0; + netv2_cmd_consumed <= 1'd0; + netv2_wdata_consumed <= 1'd0; + ethphy_reset_storage <= 1'd0; + ethphy_reset_re <= 1'd0; + ethphy_counter <= 9'd0; + ethphy__w_storage <= 3'd0; + ethphy__w_re <= 1'd0; + ethcore_mac_preamble_errors_status <= 32'd0; + ethcore_mac_crc_errors_status <= 32'd0; + ethcore_mac_tx_cdc_graycounter0_q <= 7'd0; + ethcore_mac_tx_cdc_graycounter0_q_binary <= 7'd0; + ethcore_mac_rx_cdc_graycounter1_q <= 7'd0; + ethcore_mac_rx_cdc_graycounter1_q_binary <= 7'd0; + ethcore_mac_packetizer_count <= 4'd0; + ethcore_mac_packetizer_sink_d_valid <= 1'd0; + ethcore_mac_packetizer_sink_d_ready <= 1'd0; + ethcore_mac_packetizer_sink_d_payload_ethernet_type <= 16'd0; + ethcore_mac_packetizer_sink_d_payload_sender_mac <= 48'd0; + ethcore_mac_packetizer_sink_d_payload_target_mac <= 48'd0; + ethcore_mac_packetizer_sink_d_payload_data <= 8'd0; + ethcore_mac_packetizer_sink_d_payload_last_be <= 1'd0; + ethcore_mac_packetizer_sink_d_payload_error <= 1'd0; + ethcore_mac_packetizer_fsm_from_idle <= 1'd0; + ethcore_mac_depacketizer_count <= 4'd0; + ethcore_mac_depacketizer_sink_d_valid <= 1'd0; + ethcore_mac_depacketizer_sink_d_ready <= 1'd0; + ethcore_mac_depacketizer_sink_d_payload_data <= 8'd0; + ethcore_mac_depacketizer_sink_d_payload_last_be <= 1'd0; + ethcore_mac_depacketizer_sink_d_payload_error <= 1'd0; + ethcore_mac_depacketizer_fsm_from_idle <= 1'd0; + ethcore_arp_tx_packetizer_count <= 5'd0; + ethcore_arp_tx_packetizer_sink_d_valid <= 1'd0; + ethcore_arp_tx_packetizer_sink_d_ready <= 1'd0; + ethcore_arp_tx_packetizer_sink_d_payload_data <= 8'd0; + ethcore_arp_tx_packetizer_sink_d_payload_error <= 1'd0; + ethcore_arp_tx_packetizer_fsm_from_idle <= 1'd0; + ethcore_arp_rx_depacketizer_count <= 5'd0; + ethcore_arp_rx_depacketizer_sink_d_valid <= 1'd0; + ethcore_arp_rx_depacketizer_sink_d_ready <= 1'd0; + ethcore_arp_rx_depacketizer_sink_d_payload_ethernet_type <= 16'd0; + ethcore_arp_rx_depacketizer_sink_d_payload_sender_mac <= 48'd0; + ethcore_arp_rx_depacketizer_sink_d_payload_target_mac <= 48'd0; + ethcore_arp_rx_depacketizer_sink_d_payload_data <= 8'd0; + ethcore_arp_rx_depacketizer_sink_d_payload_last_be <= 1'd0; + ethcore_arp_rx_depacketizer_sink_d_payload_error <= 1'd0; + ethcore_arp_rx_depacketizer_fsm_from_idle <= 1'd0; + ethcore_arp_table_request_pending <= 1'd0; + ethcore_arp_table_request_timer_count <= 24'd10000000; + ethcore_arp_table_request_counter <= 3'd0; + ethcore_arp_table_cached_valid <= 1'd0; + ethcore_arp_table_cached_timer_count <= 30'd1000000000; + ethcore_ip_tx_liteethipv4checksum_counter <= 4'd0; + ethcore_ip_tx_packetizer_count <= 5'd0; + ethcore_ip_tx_packetizer_sink_d_valid <= 1'd0; + ethcore_ip_tx_packetizer_sink_d_ready <= 1'd0; + ethcore_ip_tx_packetizer_sink_d_payload_data <= 8'd0; + ethcore_ip_tx_packetizer_sink_d_payload_error <= 1'd0; + ethcore_ip_tx_packetizer_fsm_from_idle <= 1'd0; + ethcore_ip_rx_depacketizer_count <= 5'd0; + ethcore_ip_rx_depacketizer_sink_d_valid <= 1'd0; + ethcore_ip_rx_depacketizer_sink_d_ready <= 1'd0; + ethcore_ip_rx_depacketizer_sink_d_payload_ethernet_type <= 16'd0; + ethcore_ip_rx_depacketizer_sink_d_payload_sender_mac <= 48'd0; + ethcore_ip_rx_depacketizer_sink_d_payload_target_mac <= 48'd0; + ethcore_ip_rx_depacketizer_sink_d_payload_data <= 8'd0; + ethcore_ip_rx_depacketizer_sink_d_payload_last_be <= 1'd0; + ethcore_ip_rx_depacketizer_sink_d_payload_error <= 1'd0; + ethcore_ip_rx_depacketizer_fsm_from_idle <= 1'd0; + ethcore_ip_rx_liteethipv4checksum_counter <= 4'd0; + ethcore_icmp_tx_packetizer_count <= 3'd0; + ethcore_icmp_tx_packetizer_sink_d_valid <= 1'd0; + ethcore_icmp_tx_packetizer_sink_d_ready <= 1'd0; + ethcore_icmp_tx_packetizer_sink_d_payload_data <= 8'd0; + ethcore_icmp_tx_packetizer_sink_d_payload_error <= 1'd0; + ethcore_icmp_tx_packetizer_fsm_from_idle <= 1'd0; + ethcore_icmp_rx_depacketizer_count <= 3'd0; + ethcore_icmp_rx_depacketizer_sink_d_valid <= 1'd0; + ethcore_icmp_rx_depacketizer_sink_d_ready <= 1'd0; + ethcore_icmp_rx_depacketizer_sink_d_payload_data <= 8'd0; + ethcore_icmp_rx_depacketizer_sink_d_payload_error <= 1'd0; + ethcore_icmp_rx_depacketizer_fsm_from_idle <= 1'd0; + ethcore_icmp_echo_buffer_readable <= 1'd0; + ethcore_icmp_echo_buffer_level0 <= 8'd0; + ethcore_icmp_echo_buffer_produce <= 7'd0; + ethcore_icmp_echo_buffer_consume <= 7'd0; + ethcore_tx_packetizer_count <= 3'd0; + ethcore_tx_packetizer_sink_d_valid <= 1'd0; + ethcore_tx_packetizer_sink_d_ready <= 1'd0; + ethcore_tx_packetizer_sink_d_payload_data <= 8'd0; + ethcore_tx_packetizer_sink_d_payload_error <= 1'd0; + ethcore_tx_packetizer_fsm_from_idle <= 1'd0; + ethcore_rx_depacketizer_count <= 3'd0; + ethcore_rx_depacketizer_sink_d_valid <= 1'd0; + ethcore_rx_depacketizer_sink_d_ready <= 1'd0; + ethcore_rx_depacketizer_sink_d_payload_data <= 8'd0; + ethcore_rx_depacketizer_sink_d_payload_error <= 1'd0; + ethcore_rx_depacketizer_fsm_from_idle <= 1'd0; + etherbone_tx_packetizer_count <= 1'd0; + etherbone_tx_packetizer_sink_d_valid <= 1'd0; + etherbone_tx_packetizer_sink_d_ready <= 1'd0; + etherbone_tx_packetizer_sink_d_payload_data <= 32'd0; + etherbone_tx_packetizer_sink_d_payload_error <= 4'd0; + etherbone_tx_packetizer_fsm_from_idle <= 1'd0; + etherbone_rx_depacketizer_count <= 1'd0; + etherbone_rx_depacketizer_sink_d_valid <= 1'd0; + etherbone_rx_depacketizer_sink_d_ready <= 1'd0; + etherbone_rx_depacketizer_sink_d_payload_data <= 32'd0; + etherbone_rx_depacketizer_sink_d_payload_error <= 4'd0; + etherbone_rx_depacketizer_fsm_from_idle <= 1'd0; + etherbone_tx_converter_converter_mux <= 2'd0; + etherbone_rx_converter_converter_source_payload_data <= 36'd0; + etherbone_rx_converter_converter_source_payload_valid_token_count <= 3'd0; + etherbone_rx_converter_converter_demux <= 2'd0; + etherbone_rx_converter_converter_strobe_all <= 1'd0; + etherbone_record_depacketizer_count <= 1'd0; + etherbone_record_depacketizer_sink_d_valid <= 1'd0; + etherbone_record_depacketizer_sink_d_ready <= 1'd0; + etherbone_record_depacketizer_sink_d_payload_data <= 32'd0; + etherbone_record_depacketizer_sink_d_payload_error <= 4'd0; + etherbone_record_depacketizer_fsm_from_idle <= 1'd0; + etherbone_record_receiver_fifo_readable <= 1'd0; + etherbone_record_receiver_fifo_level0 <= 3'd0; + etherbone_record_receiver_fifo_produce <= 2'd0; + etherbone_record_receiver_fifo_consume <= 2'd0; + etherbone_record_first <= 1'd1; + etherbone_record_sender_source_source_payload_data <= 32'd0; + etherbone_record_sender_fifo_readable <= 1'd0; + etherbone_record_sender_fifo_level0 <= 3'd0; + etherbone_record_sender_fifo_produce <= 2'd0; + etherbone_record_sender_fifo_consume <= 2'd0; + etherbone_record_packetizer_count <= 1'd0; + etherbone_record_packetizer_sink_d_valid <= 1'd0; + etherbone_record_packetizer_sink_d_ready <= 1'd0; + etherbone_record_packetizer_sink_d_payload_data <= 32'd0; + etherbone_record_packetizer_sink_d_payload_error <= 4'd0; + etherbone_record_packetizer_fsm_from_idle <= 1'd0; + etherbone_dispatcher_first <= 1'd1; + etherbone_dispatcher_ongoing1 <= 1'd0; + etherbone_dispatcher_sel_ongoing <= 1'd0; + etherbone_grant <= 1'd0; + etherbone_status0_first <= 1'd1; + etherbone_status0_ongoing1 <= 1'd0; + etherbone_status1_first <= 1'd1; + etherbone_status1_ongoing1 <= 1'd0; + etherbone_liteethetherbonewishbonemaster_source_payload_addr <= 32'd0; + etherbone_liteethetherbonewishbonemaster_source_payload_data <= 32'd0; + s7pciephy_tx_datapath_pipe_valid_source_valid <= 1'd0; + s7pciephy_tx_datapath_pipe_valid_source_payload_dat <= 64'd0; + s7pciephy_tx_datapath_pipe_valid_source_payload_be <= 8'd0; + s7pciephy_tx_datapath_cdc_graycounter0_q <= 3'd0; + s7pciephy_tx_datapath_cdc_graycounter0_q_binary <= 3'd0; + s7pciephy_rx_datapath_cdc_graycounter1_q <= 3'd0; + s7pciephy_rx_datapath_cdc_graycounter1_q_binary <= 3'd0; + s7pciephy_rx_datapath_pipe_valid_source_valid <= 1'd0; + s7pciephy_rx_datapath_pipe_valid_source_payload_dat <= 64'd0; + s7pciephy_rx_datapath_pipe_valid_source_payload_be <= 8'd0; + s7pciephy_msi_cdc_graycounter0_q <= 3'd0; + s7pciephy_msi_cdc_graycounter0_q_binary <= 3'd0; + depacketizer_header_extracter_source_payload_header <= 128'd0; + depacketizer_header_extracter_first <= 1'd0; + depacketizer_header_extracter_last <= 1'd0; + depacketizer_header_extracter_count <= 1'd0; + depacketizer_dispatcher_first <= 1'd1; + depacketizer_dispatcher_ongoing1 <= 1'd0; + depacketizer_dispatcher_sel_ongoing <= 1'd0; + packetizer_grant <= 1'd0; + packetizer_status0_first <= 1'd1; + packetizer_status0_ongoing1 <= 1'd0; + packetizer_status1_first <= 1'd1; + packetizer_status1_ongoing1 <= 1'd0; + pcie_bridge_sink_payload_adr <= 32'd0; + pcie_bridge_sink_payload_len <= 10'd0; + pcie_bridge_sink_payload_req_id <= 16'd0; + pcie_bridge_sink_payload_cmp_id <= 16'd0; + pcie_bridge_sink_payload_err <= 1'd0; + pcie_bridge_sink_payload_tag <= 8'd0; + pcie_bridge_sink_payload_dat <= 64'd0; + pcie_dma0_writer_enable_storage <= 1'd0; + pcie_dma0_writer_enable_re <= 1'd0; + pcie_dma0_writer_counter <= 13'd0; + pcie_dma0_writer_value_re <= 1'd0; + pcie_dma0_writer_we_storage <= 1'd0; + pcie_dma0_writer_we_re <= 1'd0; + pcie_dma0_writer_loop_prog_n_storage <= 1'd0; + pcie_dma0_writer_loop_prog_n_re <= 1'd0; + pcie_dma0_writer_index <= 16'd0; + pcie_dma0_writer_count <= 16'd0; + pcie_dma0_writer_flush_storage <= 1'd0; + pcie_dma0_writer_flush_re <= 1'd0; + pcie_dma0_writer_fifo_sink_valid <= 1'd0; + pcie_dma0_writer_fifo_sink_payload_address <= 32'd0; + pcie_dma0_writer_fifo_sink_payload_length <= 24'd0; + pcie_dma0_writer_fifo_sink_payload_control <= 8'd0; + pcie_dma0_writer_fifo_level0 <= 9'd0; + pcie_dma0_writer_fifo_produce0 <= 8'd0; + pcie_dma0_writer_fifo_consume0 <= 8'd0; + pcie_dma0_writer_loop_first <= 1'd1; + pcie_dma0_writer_loop_index <= 8'd0; + pcie_dma0_writer_loop_count <= 16'd0; + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_offset <= 32'd0; + pcie_dma0_writer_splitter_litepciedmadescriptorsplitter_user_id <= 32'd0; + pcie_dma0_writer_splitter_bufferizeendpoints_source_valid <= 1'd0; + pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_address <= 32'd0; + pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_length <= 24'd0; + pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_control <= 8'd0; + pcie_dma0_writer_splitter_bufferizeendpoints_source_payload_user_id <= 8'd0; + pcie_dma0_writer_fifo_readable <= 1'd0; + pcie_dma0_writer_fifo_level1 <= 9'd0; + pcie_dma0_writer_fifo_produce1 <= 8'd0; + pcie_dma0_writer_fifo_consume1 <= 8'd0; + pcie_dma0_reader_enable_storage <= 1'd0; + pcie_dma0_reader_enable_re <= 1'd0; + pcie_dma0_reader_pending_words <= 11'd0; + pcie_dma0_reader_value_re <= 1'd0; + pcie_dma0_reader_we_storage <= 1'd0; + pcie_dma0_reader_we_re <= 1'd0; + pcie_dma0_reader_loop_prog_n_storage <= 1'd0; + pcie_dma0_reader_loop_prog_n_re <= 1'd0; + pcie_dma0_reader_index <= 16'd0; + pcie_dma0_reader_count <= 16'd0; + pcie_dma0_reader_flush_storage <= 1'd0; + pcie_dma0_reader_flush_re <= 1'd0; + pcie_dma0_reader_fifo_sink_valid0 <= 1'd0; + pcie_dma0_reader_fifo_sink_payload_address <= 32'd0; + pcie_dma0_reader_fifo_sink_payload_length <= 24'd0; + pcie_dma0_reader_fifo_sink_payload_control <= 8'd0; + pcie_dma0_reader_fifo_level0 <= 9'd0; + pcie_dma0_reader_fifo_produce0 <= 8'd0; + pcie_dma0_reader_fifo_consume0 <= 8'd0; + pcie_dma0_reader_loop_first <= 1'd1; + pcie_dma0_reader_loop_index <= 8'd0; + pcie_dma0_reader_loop_count <= 16'd0; + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_offset <= 32'd0; + pcie_dma0_reader_splitter_litepciedmadescriptorsplitter_user_id <= 32'd0; + pcie_dma0_reader_splitter_bufferizeendpoints_source_valid <= 1'd0; + pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_address <= 32'd0; + pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_length <= 24'd0; + pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_control <= 8'd0; + pcie_dma0_reader_splitter_bufferizeendpoints_source_payload_user_id <= 8'd0; + pcie_dma0_reader_fifo_readable <= 1'd0; + pcie_dma0_reader_fifo_level1 <= 11'd0; + pcie_dma0_reader_fifo_produce1 <= 10'd0; + pcie_dma0_reader_fifo_consume1 <= 10'd0; + pcie_dma0_reader_last_user_id <= 8'd255; + pcie_dma0_loopback_storage <= 1'd0; + pcie_dma0_loopback_re <= 1'd0; + pcie_dma0_buffering_next_sink_valid <= 1'd0; + pcie_dma0_buffering_next_sink_payload_data <= 64'd0; + pcie_dma0_buffering_reader_fifo_depth_storage <= 11'd1024; + pcie_dma0_buffering_reader_fifo_depth_re <= 1'd0; + pcie_dma0_buffering_writer_fifo_depth_storage <= 11'd1024; + pcie_dma0_buffering_writer_fifo_depth_re <= 1'd0; + pcie_dma0_buffering_reader_fifo_readable <= 1'd0; + pcie_dma0_buffering_reader_fifo_level0 <= 8'd0; + pcie_dma0_buffering_reader_fifo_produce <= 7'd0; + pcie_dma0_buffering_reader_fifo_consume <= 7'd0; + pcie_dma0_buffering_writer_fifo_readable <= 1'd0; + pcie_dma0_buffering_writer_fifo_level0 <= 8'd0; + pcie_dma0_buffering_writer_fifo_produce <= 7'd0; + pcie_dma0_buffering_writer_fifo_consume <= 7'd0; + pcie_dma1_writer_enable_storage <= 1'd0; + pcie_dma1_writer_enable_re <= 1'd0; + pcie_dma1_writer_counter <= 13'd0; + pcie_dma1_writer_value_re <= 1'd0; + pcie_dma1_writer_we_storage <= 1'd0; + pcie_dma1_writer_we_re <= 1'd0; + pcie_dma1_writer_loop_prog_n_storage <= 1'd0; + pcie_dma1_writer_loop_prog_n_re <= 1'd0; + pcie_dma1_writer_index <= 16'd0; + pcie_dma1_writer_count <= 16'd0; + pcie_dma1_writer_flush_storage <= 1'd0; + pcie_dma1_writer_flush_re <= 1'd0; + pcie_dma1_writer_fifo_sink_valid <= 1'd0; + pcie_dma1_writer_fifo_sink_payload_address <= 32'd0; + pcie_dma1_writer_fifo_sink_payload_length <= 24'd0; + pcie_dma1_writer_fifo_sink_payload_control <= 8'd0; + pcie_dma1_writer_fifo_level0 <= 9'd0; + pcie_dma1_writer_fifo_produce0 <= 8'd0; + pcie_dma1_writer_fifo_consume0 <= 8'd0; + pcie_dma1_writer_loop_first <= 1'd1; + pcie_dma1_writer_loop_index <= 8'd0; + pcie_dma1_writer_loop_count <= 16'd0; + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_offset <= 32'd0; + pcie_dma1_writer_splitter_litepciedmadescriptorsplitter_user_id <= 32'd0; + pcie_dma1_writer_splitter_bufferizeendpoints_source_valid <= 1'd0; + pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_address <= 32'd0; + pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_length <= 24'd0; + pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_control <= 8'd0; + pcie_dma1_writer_splitter_bufferizeendpoints_source_payload_user_id <= 8'd0; + pcie_dma1_writer_fifo_readable <= 1'd0; + pcie_dma1_writer_fifo_level1 <= 9'd0; + pcie_dma1_writer_fifo_produce1 <= 8'd0; + pcie_dma1_writer_fifo_consume1 <= 8'd0; + pcie_dma1_reader_enable_storage <= 1'd0; + pcie_dma1_reader_enable_re <= 1'd0; + pcie_dma1_reader_pending_words <= 11'd0; + pcie_dma1_reader_value_re <= 1'd0; + pcie_dma1_reader_we_storage <= 1'd0; + pcie_dma1_reader_we_re <= 1'd0; + pcie_dma1_reader_loop_prog_n_storage <= 1'd0; + pcie_dma1_reader_loop_prog_n_re <= 1'd0; + pcie_dma1_reader_index <= 16'd0; + pcie_dma1_reader_count <= 16'd0; + pcie_dma1_reader_flush_storage <= 1'd0; + pcie_dma1_reader_flush_re <= 1'd0; + pcie_dma1_reader_fifo_sink_valid0 <= 1'd0; + pcie_dma1_reader_fifo_sink_payload_address <= 32'd0; + pcie_dma1_reader_fifo_sink_payload_length <= 24'd0; + pcie_dma1_reader_fifo_sink_payload_control <= 8'd0; + pcie_dma1_reader_fifo_level0 <= 9'd0; + pcie_dma1_reader_fifo_produce0 <= 8'd0; + pcie_dma1_reader_fifo_consume0 <= 8'd0; + pcie_dma1_reader_loop_first <= 1'd1; + pcie_dma1_reader_loop_index <= 8'd0; + pcie_dma1_reader_loop_count <= 16'd0; + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_offset <= 32'd0; + pcie_dma1_reader_splitter_litepciedmadescriptorsplitter_user_id <= 32'd0; + pcie_dma1_reader_splitter_bufferizeendpoints_source_valid <= 1'd0; + pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_address <= 32'd0; + pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_length <= 24'd0; + pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_control <= 8'd0; + pcie_dma1_reader_splitter_bufferizeendpoints_source_payload_user_id <= 8'd0; + pcie_dma1_reader_fifo_readable <= 1'd0; + pcie_dma1_reader_fifo_level1 <= 11'd0; + pcie_dma1_reader_fifo_produce1 <= 10'd0; + pcie_dma1_reader_fifo_consume1 <= 10'd0; + pcie_dma1_reader_last_user_id <= 8'd255; + pcie_dma1_loopback_storage <= 1'd0; + pcie_dma1_loopback_re <= 1'd0; + pcie_dma1_buffering_next_sink_valid <= 1'd0; + pcie_dma1_buffering_next_sink_payload_data <= 64'd0; + pcie_dma1_buffering_reader_fifo_depth_storage <= 11'd1024; + pcie_dma1_buffering_reader_fifo_depth_re <= 1'd0; + pcie_dma1_buffering_writer_fifo_depth_storage <= 11'd1024; + pcie_dma1_buffering_writer_fifo_depth_re <= 1'd0; + pcie_dma1_buffering_reader_fifo_readable <= 1'd0; + pcie_dma1_buffering_reader_fifo_level0 <= 8'd0; + pcie_dma1_buffering_reader_fifo_produce <= 7'd0; + pcie_dma1_buffering_reader_fifo_consume <= 7'd0; + pcie_dma1_buffering_writer_fifo_readable <= 1'd0; + pcie_dma1_buffering_writer_fifo_level0 <= 8'd0; + pcie_dma1_buffering_writer_fifo_produce <= 7'd0; + pcie_dma1_buffering_writer_fifo_consume <= 7'd0; + pcie_msi_enable_storage <= 32'd0; + pcie_msi_enable_re <= 1'd0; + pcie_msi_clear_storage <= 32'd0; + pcie_msi_clear_re <= 1'd0; + pcie_msi_vector <= 32'd0; + pcie_msi_msi <= 32'd0; + pcie_dma0_counter <= 32'd0; + pcie_dma1_counter <= 32'd0; + freqmeter_period_counter <= 32'd0; + freqmeter_sampler_o <= 32'd0; + freqmeter_sampler_counter <= 32'd0; + freqmeter_sampler_i_d <= 6'd0; + hdmi_in0_hpd_en_storage <= 1'd0; + hdmi_in0_hpd_en_re <= 1'd0; + hdmi_in0_sda_i <= 1'd0; + hdmi_in0_sda_drv_reg <= 1'd0; + hdmi_in0_scl_i <= 1'd0; + hdmi_in0_samp_count <= 6'd0; + hdmi_in0_samp_carry <= 1'd0; + hdmi_in0_scl_r <= 1'd0; + hdmi_in0_sda_r <= 1'd0; + hdmi_in0_din <= 8'd0; + hdmi_in0_counter <= 4'd0; + hdmi_in0_is_read <= 1'd0; + hdmi_in0_offset_counter <= 8'd0; + hdmi_in0_data_bit <= 1'd0; + hdmi_in0_data_drv <= 1'd0; + hdmi_in0_mmcm_reset_storage <= 1'd1; + hdmi_in0_mmcm_reset_re <= 1'd0; + hdmi_in0_mmcm_drdy_status <= 1'd0; + hdmi_in0_mmcm_adr_storage <= 7'd0; + hdmi_in0_mmcm_adr_re <= 1'd0; + hdmi_in0_mmcm_dat_w_storage <= 16'd0; + hdmi_in0_mmcm_dat_w_re <= 1'd0; + hdmi_in0_mmcm_drdy_o_status <= 1'd0; + hdmi_in0_s7datacapture0_sync_mcntvalue_ping_o1 <= 1'd0; + hdmi_in0_s7datacapture0_sync_scntvalue_ping_o1 <= 1'd0; + hdmi_in0_wer0_status <= 24'd0; + hdmi_in0_wer0_wer_counter_sys <= 24'd0; + hdmi_in0_s7datacapture1_sync_mcntvalue_ping_o1 <= 1'd0; + hdmi_in0_s7datacapture1_sync_scntvalue_ping_o1 <= 1'd0; + hdmi_in0_wer1_status <= 24'd0; + hdmi_in0_wer1_wer_counter_sys <= 24'd0; + hdmi_in0_s7datacapture2_sync_mcntvalue_ping_o1 <= 1'd0; + hdmi_in0_s7datacapture2_sync_scntvalue_ping_o1 <= 1'd0; + hdmi_in0_wer2_status <= 24'd0; + hdmi_in0_wer2_wer_counter_sys <= 24'd0; + hdmi_in0_frame_fifo_graycounter1_q <= 10'd0; + hdmi_in0_frame_fifo_graycounter1_q_binary <= 10'd0; + hdmi_in0_frame_overflow_mask <= 1'd0; + hdmi_in0_dma_frame_size_storage <= 29'd0; + hdmi_in0_dma_frame_size_re <= 1'd0; + hdmi_in0_dma_slot_array_slot0_status_storage <= 2'd0; + hdmi_in0_dma_slot_array_slot0_status_re <= 1'd0; + hdmi_in0_dma_slot_array_slot0_address_storage <= 29'd0; + hdmi_in0_dma_slot_array_slot0_address_re <= 1'd0; + hdmi_in0_dma_slot_array_slot1_status_storage <= 2'd0; + hdmi_in0_dma_slot_array_slot1_status_re <= 1'd0; + hdmi_in0_dma_slot_array_slot1_address_storage <= 29'd0; + hdmi_in0_dma_slot_array_slot1_address_re <= 1'd0; + hdmi_in0_dma_slot_array_storage <= 2'd0; + hdmi_in0_dma_slot_array_re <= 1'd0; + hdmi_in0_dma_slot_array_current_slot <= 1'd0; + hdmi_in0_dma_current_address <= 24'd0; + hdmi_in0_dma_mwords_remaining <= 24'd0; + hdmi_in0_dma_fifo_level <= 5'd0; + hdmi_in0_dma_fifo_produce <= 4'd0; + hdmi_in0_dma_fifo_consume <= 4'd0; + litedramcrossbar_cmd_cdc_cdc_graycounter1_q <= 3'd0; + litedramcrossbar_cmd_cdc_cdc_graycounter1_q_binary <= 3'd0; + litedramcrossbar_rdata_cdc_cdc_graycounter0_q <= 5'd0; + litedramcrossbar_rdata_cdc_cdc_graycounter0_q_binary <= 5'd0; + hdmi_out0_core_underflow_enable_storage <= 1'd0; + hdmi_out0_core_underflow_enable_re <= 1'd0; + hdmi_out0_core_initiator_cdc_graycounter0_q <= 3'd0; + hdmi_out0_core_initiator_cdc_graycounter0_q_binary <= 3'd0; + hdmi_out0_core_initiator_enable_storage <= 1'd0; + hdmi_out0_core_initiator_enable_re <= 1'd0; + hdmi_out0_core_initiator_csrstorage0_storage <= 12'd0; + hdmi_out0_core_initiator_csrstorage0_re <= 1'd0; + hdmi_out0_core_initiator_csrstorage1_storage <= 12'd0; + hdmi_out0_core_initiator_csrstorage1_re <= 1'd0; + hdmi_out0_core_initiator_csrstorage2_storage <= 12'd0; + hdmi_out0_core_initiator_csrstorage2_re <= 1'd0; + hdmi_out0_core_initiator_csrstorage3_storage <= 12'd0; + hdmi_out0_core_initiator_csrstorage3_re <= 1'd0; + hdmi_out0_core_initiator_csrstorage4_storage <= 12'd0; + hdmi_out0_core_initiator_csrstorage4_re <= 1'd0; + hdmi_out0_core_initiator_csrstorage5_storage <= 12'd0; + hdmi_out0_core_initiator_csrstorage5_re <= 1'd0; + hdmi_out0_core_initiator_csrstorage6_storage <= 12'd0; + hdmi_out0_core_initiator_csrstorage6_re <= 1'd0; + hdmi_out0_core_initiator_csrstorage7_storage <= 12'd0; + hdmi_out0_core_initiator_csrstorage7_re <= 1'd0; + hdmi_out0_core_initiator_csrstorage8_storage <= 32'd0; + hdmi_out0_core_initiator_csrstorage8_re <= 1'd0; + hdmi_out0_core_initiator_csrstorage9_storage <= 32'd0; + hdmi_out0_core_initiator_csrstorage9_re <= 1'd0; + hdmi_out0_core_dmareader_storage <= 32'd0; + hdmi_out0_core_dmareader_re <= 1'd0; + hdmi_out0_driver_s7hdmioutclocking_mmcm_reset_storage <= 1'd0; + hdmi_out0_driver_s7hdmioutclocking_mmcm_reset_re <= 1'd0; + hdmi_out0_driver_s7hdmioutclocking_mmcm_drdy_status <= 1'd0; + hdmi_out0_driver_s7hdmioutclocking_mmcm_adr_storage <= 7'd0; + hdmi_out0_driver_s7hdmioutclocking_mmcm_adr_re <= 1'd0; + hdmi_out0_driver_s7hdmioutclocking_mmcm_dat_w_storage <= 16'd0; + hdmi_out0_driver_s7hdmioutclocking_mmcm_dat_w_re <= 1'd0; + s7spiflash_state <= 2'd0; + litedramcore_refresher_state <= 2'd0; + litedramcore_bankmachine0_state <= 4'd0; + litedramcore_bankmachine1_state <= 4'd0; + litedramcore_bankmachine2_state <= 4'd0; + litedramcore_bankmachine3_state <= 4'd0; + litedramcore_bankmachine4_state <= 4'd0; + litedramcore_bankmachine5_state <= 4'd0; + litedramcore_bankmachine6_state <= 4'd0; + litedramcore_bankmachine7_state <= 4'd0; + litedramcore_multiplexer_state <= 4'd0; + litedramcore_roundrobin0_grant <= 2'd0; + litedramcore_roundrobin1_grant <= 2'd0; + litedramcore_roundrobin2_grant <= 2'd0; + litedramcore_roundrobin3_grant <= 2'd0; + litedramcore_roundrobin4_grant <= 2'd0; + litedramcore_roundrobin5_grant <= 2'd0; + litedramcore_roundrobin6_grant <= 2'd0; + litedramcore_roundrobin7_grant <= 2'd0; + litedramcore_new_master_wdata_ready0 <= 1'd0; + litedramcore_new_master_wdata_ready1 <= 1'd0; + litedramcore_new_master_wdata_ready2 <= 1'd0; + litedramcore_new_master_wdata_ready3 <= 1'd0; + litedramcore_new_master_wdata_ready4 <= 1'd0; + litedramcore_new_master_wdata_ready5 <= 1'd0; + litedramcore_new_master_rdata_valid0 <= 1'd0; + litedramcore_new_master_rdata_valid1 <= 1'd0; + litedramcore_new_master_rdata_valid2 <= 1'd0; + litedramcore_new_master_rdata_valid3 <= 1'd0; + litedramcore_new_master_rdata_valid4 <= 1'd0; + litedramcore_new_master_rdata_valid5 <= 1'd0; + litedramcore_new_master_rdata_valid6 <= 1'd0; + litedramcore_new_master_rdata_valid7 <= 1'd0; + litedramcore_new_master_rdata_valid8 <= 1'd0; + litedramcore_new_master_rdata_valid9 <= 1'd0; + litedramcore_new_master_rdata_valid10 <= 1'd0; + litedramcore_new_master_rdata_valid11 <= 1'd0; + litedramcore_new_master_rdata_valid12 <= 1'd0; + litedramcore_new_master_rdata_valid13 <= 1'd0; + litedramcore_new_master_rdata_valid14 <= 1'd0; + litedramcore_new_master_rdata_valid15 <= 1'd0; + litedramcore_new_master_rdata_valid16 <= 1'd0; + litedramcore_new_master_rdata_valid17 <= 1'd0; + litedramcore_new_master_rdata_valid18 <= 1'd0; + litedramcore_new_master_rdata_valid19 <= 1'd0; + litedramcore_new_master_rdata_valid20 <= 1'd0; + litedramcore_new_master_rdata_valid21 <= 1'd0; + litedramcore_new_master_rdata_valid22 <= 1'd0; + litedramcore_new_master_rdata_valid23 <= 1'd0; + litedramcore_new_master_rdata_valid24 <= 1'd0; + litedramcore_new_master_rdata_valid25 <= 1'd0; + litedramcore_new_master_rdata_valid26 <= 1'd0; + fullmemorywe_state <= 2'd0; + liteethudpipcore_liteethmac_grant <= 1'd0; + liteethudpipcore_liteethmac_status0_first <= 1'd1; + liteethudpipcore_liteethmac_status0_ongoing1 <= 1'd0; + liteethudpipcore_liteethmac_status1_first <= 1'd1; + liteethudpipcore_liteethmac_status1_ongoing1 <= 1'd0; + liteethudpipcore_liteethmac_first <= 1'd1; + liteethudpipcore_liteethmac_ongoing1 <= 1'd0; + liteethudpipcore_liteethmac_sel_ongoing <= 2'd0; + liteethudpipcore_liteethmac_liteethmacpacketizer_state <= 2'd0; + liteethudpipcore_liteethmac_liteethmacdepacketizer_state <= 2'd0; + liteethudpipcore_liteetharptx_liteetharppacketizer_state <= 2'd0; + liteethudpipcore_liteetharptx_fsm_state <= 1'd0; + liteethudpipcore_liteetharprx_liteetharpdepacketizer_state <= 2'd0; + liteethudpipcore_liteetharprx_fsm_state <= 2'd0; + liteethudpipcore_state <= 3'd0; + liteethudpipcore_liteethip_liteethiptx_liteethipv4packetizer_state <= 2'd0; + liteethudpipcore_liteethip_liteethiptx_fsm_state <= 3'd0; + liteethudpipcore_liteethip_liteethiprx_liteethipv4depacketizer_state <= 2'd0; + liteethudpipcore_liteethip_liteethiprx_fsm_state <= 2'd0; + liteethudpipcore_liteethip_grant <= 1'd0; + liteethudpipcore_liteethip_status0_first <= 1'd1; + liteethudpipcore_liteethip_status0_ongoing1 <= 1'd0; + liteethudpipcore_liteethip_status1_first <= 1'd1; + liteethudpipcore_liteethip_status1_ongoing1 <= 1'd0; + liteethudpipcore_liteethip_first <= 1'd1; + liteethudpipcore_liteethip_ongoing1 <= 1'd0; + liteethudpipcore_liteethip_sel_ongoing <= 2'd0; + liteethudpipcore_liteethicmptx_liteethicmppacketizer_state <= 2'd0; + liteethudpipcore_liteethicmptx_fsm_state <= 1'd0; + liteethudpipcore_liteethicmprx_liteethicmpdepacketizer_state <= 2'd0; + liteethudpipcore_liteethicmprx_fsm_state <= 2'd0; + liteethudpipcore_liteethudp_liteethudptx_liteethudppacketizer_state <= 2'd0; + liteethudpipcore_liteethudp_liteethudptx_fsm_state <= 1'd0; + liteethudpipcore_liteethudp_liteethudprx_liteethudpdepacketizer_state <= 2'd0; + liteethudpipcore_liteethudp_liteethudprx_fsm_state <= 2'd0; + liteethetherbonepackettx_liteethetherbonepacketpacketizer_state <= 2'd0; + liteethetherbonepackettx_fsm_state <= 1'd0; + liteethetherbonepacketrx_liteethetherbonepacketdepacketizer_state <= 2'd0; + liteethetherbonepacketrx_fsm_state <= 2'd0; + liteethetherboneprobe_state <= 1'd0; + liteethetherbonerecorddepacketizer_state <= 2'd0; + liteethetherbonerecordreceiver_state <= 2'd0; + liteethetherbonerecordsender_state <= 2'd0; + liteethetherbonerecordpacketizer_state <= 2'd0; + liteethetherbonewishbonemaster_state <= 2'd0; + litepcietlpdepacketizer_state <= 2'd0; + litepcietlppacketizer_state <= 2'd0; + tags_queue_readable <= 1'd0; + tags_queue_level0 <= 3'd0; + tags_queue_produce <= 2'd0; + tags_queue_consume <= 2'd0; + requests_queue_readable <= 1'd0; + requests_queue_level0 <= 3'd0; + requests_queue_produce <= 2'd0; + requests_queue_consume <= 2'd0; + syncfifo0_readable <= 1'd0; + syncfifo0_level0 <= 9'd0; + syncfifo0_produce <= 8'd0; + syncfifo0_consume <= 8'd0; + syncfifo1_readable <= 1'd0; + syncfifo1_level0 <= 9'd0; + syncfifo1_produce <= 8'd0; + syncfifo1_consume <= 8'd0; + syncfifo2_readable <= 1'd0; + syncfifo2_level0 <= 9'd0; + syncfifo2_produce <= 8'd0; + syncfifo2_consume <= 8'd0; + syncfifo3_readable <= 1'd0; + syncfifo3_level0 <= 9'd0; + syncfifo3_produce <= 8'd0; + syncfifo3_consume <= 8'd0; + fill_tag <= 2'd0; + arbiter0_grant <= 1'd0; + arbiter0_status0_first <= 1'd1; + arbiter0_status0_ongoing1 <= 1'd0; + arbiter0_status1_first <= 1'd1; + arbiter0_status1_ongoing1 <= 1'd0; + dispatcher0_first <= 1'd1; + dispatcher0_ongoing1 <= 1'd0; + dispatcher0_sel_ongoing <= 2'd0; + arbiter1_grant <= 1'd0; + arbiter1_status2_first <= 1'd1; + arbiter1_status2_ongoing1 <= 1'd0; + arbiter1_status3_first <= 1'd1; + arbiter1_status3_ongoing1 <= 1'd0; + dispatcher1_first <= 1'd1; + dispatcher1_ongoing1 <= 1'd0; + dispatcher1_sel_ongoing <= 2'd0; + arbiter2_grant <= 1'd0; + arbiter2_status4_first <= 1'd1; + arbiter2_status4_ongoing1 <= 1'd0; + arbiter2_status5_first <= 1'd1; + arbiter2_status5_ongoing1 <= 1'd0; + fsm0_state0 <= 2'd0; + fsm1_state0 <= 2'd0; + litepciewishbonebridge_state <= 2'd0; + bufferizeendpoints0_state0 <= 2'd0; + fsm0_state1 <= 1'd0; + bufferizeendpoints0_state1 <= 2'd0; + fsm0_state2 <= 1'd0; + bufferizeendpoints1_state0 <= 2'd0; + fsm1_state1 <= 1'd0; + bufferizeendpoints1_state1 <= 2'd0; + fsm1_state2 <= 1'd0; + edid_state <= 4'd0; + dma_state <= 2'd0; + netv2_we <= 1'd0; + grant <= 2'd0; + slave_sel_r <= 4'd0; + count <= 20'd1000000; + sram0_sel_r <= 1'd0; + sram1_sel_r <= 1'd0; + state <= 2'd0; + end + xilinxmultiregimpl3_regs0 <= ethphy_data_r; + xilinxmultiregimpl3_regs1 <= xilinxmultiregimpl3_regs0; + xilinxmultiregimpl4_regs0 <= ethcore_mac_ps_preamble_error_toggle_i; + xilinxmultiregimpl4_regs1 <= xilinxmultiregimpl4_regs0; + xilinxmultiregimpl5_regs0 <= ethcore_mac_ps_crc_error_toggle_i; + xilinxmultiregimpl5_regs1 <= xilinxmultiregimpl5_regs0; + xilinxmultiregimpl7_regs0 <= ethcore_mac_tx_cdc_graycounter1_q; + xilinxmultiregimpl7_regs1 <= xilinxmultiregimpl7_regs0; + xilinxmultiregimpl8_regs0 <= ethcore_mac_rx_cdc_graycounter0_q; + xilinxmultiregimpl8_regs1 <= xilinxmultiregimpl8_regs0; + xilinxmultiregimpl11_regs0 <= s7pciephy_tx_datapath_cdc_graycounter1_q; + xilinxmultiregimpl11_regs1 <= xilinxmultiregimpl11_regs0; + xilinxmultiregimpl12_regs0 <= s7pciephy_rx_datapath_cdc_graycounter0_q; + xilinxmultiregimpl12_regs1 <= xilinxmultiregimpl12_regs0; + xilinxmultiregimpl15_regs0 <= s7pciephy_msi_cdc_graycounter1_q; + xilinxmultiregimpl15_regs1 <= xilinxmultiregimpl15_regs0; + xilinxmultiregimpl16_regs0 <= s7pciephy_command[2]; + xilinxmultiregimpl16_regs1 <= xilinxmultiregimpl16_regs0; + xilinxmultiregimpl17_regs0 <= s7pciephy_max_request_size; + xilinxmultiregimpl17_regs1 <= xilinxmultiregimpl17_regs0; + xilinxmultiregimpl18_regs0 <= s7pciephy_max_payload_size; + xilinxmultiregimpl18_regs1 <= xilinxmultiregimpl18_regs0; + xilinxmultiregimpl19_regs0 <= freqmeter_q; + xilinxmultiregimpl19_regs1 <= xilinxmultiregimpl19_regs0; + xilinxmultiregimpl20_regs0 <= (~hdmi_in0_scl); + xilinxmultiregimpl20_regs1 <= xilinxmultiregimpl20_regs0; + xilinxmultiregimpl21_regs0 <= (~hdmi_in0_sda); + xilinxmultiregimpl21_regs1 <= xilinxmultiregimpl21_regs0; + xilinxmultiregimpl22_regs0 <= hdmi_in0_mmcm_locked; + xilinxmultiregimpl22_regs1 <= xilinxmultiregimpl22_regs0; + xilinxmultiregimpl23_regs0 <= hdmi_in0_s7datacapture0_sync_mcntvalue_ping_toggle_i; + xilinxmultiregimpl23_regs1 <= xilinxmultiregimpl23_regs0; + xilinxmultiregimpl25_regs0 <= hdmi_in0_s7datacapture0_sync_mcntvalue_ibuffer; + xilinxmultiregimpl25_regs1 <= xilinxmultiregimpl25_regs0; + xilinxmultiregimpl26_regs0 <= hdmi_in0_s7datacapture0_sync_scntvalue_ping_toggle_i; + xilinxmultiregimpl26_regs1 <= xilinxmultiregimpl26_regs0; + xilinxmultiregimpl28_regs0 <= hdmi_in0_s7datacapture0_sync_scntvalue_ibuffer; + xilinxmultiregimpl28_regs1 <= xilinxmultiregimpl28_regs0; + xilinxmultiregimpl34_regs0 <= {hdmi_in0_s7datacapture0_too_early, hdmi_in0_s7datacapture0_too_late}; + xilinxmultiregimpl34_regs1 <= xilinxmultiregimpl34_regs0; + xilinxmultiregimpl36_regs0 <= hdmi_in0_charsync0_synced; + xilinxmultiregimpl36_regs1 <= xilinxmultiregimpl36_regs0; + xilinxmultiregimpl37_regs0 <= hdmi_in0_charsync0_word_sel; + xilinxmultiregimpl37_regs1 <= xilinxmultiregimpl37_regs0; + xilinxmultiregimpl38_regs0 <= hdmi_in0_wer0_toggle_i; + xilinxmultiregimpl38_regs1 <= xilinxmultiregimpl38_regs0; + xilinxmultiregimpl39_regs0 <= hdmi_in0_s7datacapture1_sync_mcntvalue_ping_toggle_i; + xilinxmultiregimpl39_regs1 <= xilinxmultiregimpl39_regs0; + xilinxmultiregimpl41_regs0 <= hdmi_in0_s7datacapture1_sync_mcntvalue_ibuffer; + xilinxmultiregimpl41_regs1 <= xilinxmultiregimpl41_regs0; + xilinxmultiregimpl42_regs0 <= hdmi_in0_s7datacapture1_sync_scntvalue_ping_toggle_i; + xilinxmultiregimpl42_regs1 <= xilinxmultiregimpl42_regs0; + xilinxmultiregimpl44_regs0 <= hdmi_in0_s7datacapture1_sync_scntvalue_ibuffer; + xilinxmultiregimpl44_regs1 <= xilinxmultiregimpl44_regs0; + xilinxmultiregimpl50_regs0 <= {hdmi_in0_s7datacapture1_too_early, hdmi_in0_s7datacapture1_too_late}; + xilinxmultiregimpl50_regs1 <= xilinxmultiregimpl50_regs0; + xilinxmultiregimpl52_regs0 <= hdmi_in0_charsync1_synced; + xilinxmultiregimpl52_regs1 <= xilinxmultiregimpl52_regs0; + xilinxmultiregimpl53_regs0 <= hdmi_in0_charsync1_word_sel; + xilinxmultiregimpl53_regs1 <= xilinxmultiregimpl53_regs0; + xilinxmultiregimpl54_regs0 <= hdmi_in0_wer1_toggle_i; + xilinxmultiregimpl54_regs1 <= xilinxmultiregimpl54_regs0; + xilinxmultiregimpl55_regs0 <= hdmi_in0_s7datacapture2_sync_mcntvalue_ping_toggle_i; + xilinxmultiregimpl55_regs1 <= xilinxmultiregimpl55_regs0; + xilinxmultiregimpl57_regs0 <= hdmi_in0_s7datacapture2_sync_mcntvalue_ibuffer; + xilinxmultiregimpl57_regs1 <= xilinxmultiregimpl57_regs0; + xilinxmultiregimpl58_regs0 <= hdmi_in0_s7datacapture2_sync_scntvalue_ping_toggle_i; + xilinxmultiregimpl58_regs1 <= xilinxmultiregimpl58_regs0; + xilinxmultiregimpl60_regs0 <= hdmi_in0_s7datacapture2_sync_scntvalue_ibuffer; + xilinxmultiregimpl60_regs1 <= xilinxmultiregimpl60_regs0; + xilinxmultiregimpl66_regs0 <= {hdmi_in0_s7datacapture2_too_early, hdmi_in0_s7datacapture2_too_late}; + xilinxmultiregimpl66_regs1 <= xilinxmultiregimpl66_regs0; + xilinxmultiregimpl68_regs0 <= hdmi_in0_charsync2_synced; + xilinxmultiregimpl68_regs1 <= xilinxmultiregimpl68_regs0; + xilinxmultiregimpl69_regs0 <= hdmi_in0_charsync2_word_sel; + xilinxmultiregimpl69_regs1 <= xilinxmultiregimpl69_regs0; + xilinxmultiregimpl70_regs0 <= hdmi_in0_wer2_toggle_i; + xilinxmultiregimpl70_regs1 <= xilinxmultiregimpl70_regs0; + xilinxmultiregimpl71_regs0 <= hdmi_in0_chansync_chan_synced; + xilinxmultiregimpl71_regs1 <= xilinxmultiregimpl71_regs0; + xilinxmultiregimpl72_regs0 <= hdmi_in0_resdetection_hcounter_st; + xilinxmultiregimpl72_regs1 <= xilinxmultiregimpl72_regs0; + xilinxmultiregimpl73_regs0 <= hdmi_in0_resdetection_vcounter_st; + xilinxmultiregimpl73_regs1 <= xilinxmultiregimpl73_regs0; + xilinxmultiregimpl74_regs0 <= hdmi_in0_frame_fifo_graycounter0_q; + xilinxmultiregimpl74_regs1 <= xilinxmultiregimpl74_regs0; + xilinxmultiregimpl76_regs0 <= hdmi_in0_frame_pix_overflow; + xilinxmultiregimpl76_regs1 <= xilinxmultiregimpl76_regs0; + xilinxmultiregimpl78_regs0 <= hdmi_in0_frame_overflow_reset_ack_toggle_i; + xilinxmultiregimpl78_regs1 <= xilinxmultiregimpl78_regs0; + xilinxmultiregimpl79_regs0 <= litedramcrossbar_cmd_cdc_cdc_graycounter0_q; + xilinxmultiregimpl79_regs1 <= xilinxmultiregimpl79_regs0; + xilinxmultiregimpl82_regs0 <= litedramcrossbar_rdata_cdc_cdc_graycounter1_q; + xilinxmultiregimpl82_regs1 <= xilinxmultiregimpl82_regs0; + xilinxmultiregimpl84_regs0 <= hdmi_out0_core_initiator_cdc_graycounter1_q; + xilinxmultiregimpl84_regs1 <= xilinxmultiregimpl84_regs0; + xilinxmultiregimpl85_regs0 <= hdmi_out0_core_underflow_enable_storage; + xilinxmultiregimpl85_regs1 <= xilinxmultiregimpl85_regs0; +end + +reg [31:0] mem[0:8191]; +reg [31:0] memdat; +always @(posedge sys_clk) begin + memdat <= mem[netv2_netv2_adr]; +end + +assign netv2_netv2_dat_r = memdat; + +initial begin + $readmemh("mem.init", mem); +end + +reg [31:0] mem_1[0:2047]; +reg [10:0] memadr; +always @(posedge sys_clk) begin + if (netv2_ram_we[0]) + mem_1[netv2_ram_adr][7:0] <= netv2_ram_dat_w[7:0]; + if (netv2_ram_we[1]) + mem_1[netv2_ram_adr][15:8] <= netv2_ram_dat_w[15:8]; + if (netv2_ram_we[2]) + mem_1[netv2_ram_adr][23:16] <= netv2_ram_dat_w[23:16]; + if (netv2_ram_we[3]) + mem_1[netv2_ram_adr][31:24] <= netv2_ram_dat_w[31:24]; + memadr <= netv2_ram_adr; +end + +assign netv2_ram_dat_r = mem_1[memadr]; + +initial begin + $readmemh("mem_1.init", mem_1); +end + +reg [7:0] mem_2[0:35]; +reg [5:0] memadr_1; +always @(posedge sys_clk) begin + memadr_1 <= sram1_adr; +end + +assign sram1_dat_r = mem_2[memadr_1]; + +initial begin + $readmemh("mem_2.init", mem_2); +end + +reg [9:0] storage[0:15]; +reg [9:0] memdat_1; +reg [9:0] memdat_2; +always @(posedge sys_clk) begin + if (netv2_uartcrossover_tx_fifo_wrport_we) + storage[netv2_uartcrossover_tx_fifo_wrport_adr] <= netv2_uartcrossover_tx_fifo_wrport_dat_w; + memdat_1 <= storage[netv2_uartcrossover_tx_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (netv2_uartcrossover_tx_fifo_rdport_re) + memdat_2 <= storage[netv2_uartcrossover_tx_fifo_rdport_adr]; +end + +assign netv2_uartcrossover_tx_fifo_wrport_dat_r = memdat_1; +assign netv2_uartcrossover_tx_fifo_rdport_dat_r = memdat_2; + +reg [9:0] storage_1[0:15]; +reg [9:0] memdat_3; +reg [9:0] memdat_4; +always @(posedge sys_clk) begin + if (netv2_uartcrossover_rx_fifo_wrport_we) + storage_1[netv2_uartcrossover_rx_fifo_wrport_adr] <= netv2_uartcrossover_rx_fifo_wrport_dat_w; + memdat_3 <= storage_1[netv2_uartcrossover_rx_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (netv2_uartcrossover_rx_fifo_rdport_re) + memdat_4 <= storage_1[netv2_uartcrossover_rx_fifo_rdport_adr]; +end + +assign netv2_uartcrossover_rx_fifo_wrport_dat_r = memdat_3; +assign netv2_uartcrossover_rx_fifo_rdport_dat_r = memdat_4; + +BUFG BUFG( + .I(crg_clkout0), + .O(crg_clkout_buf0) +); + +BUFG BUFG_1( + .I(crg_clkout1), + .O(crg_clkout_buf1) +); + +BUFG BUFG_2( + .I(crg_clkout2), + .O(crg_clkout_buf2) +); + +BUFG BUFG_3( + .I(crg_clkout3), + .O(crg_clkout_buf3) +); + +BUFG BUFG_4( + .I(crg_clkout4), + .O(crg_clkout_buf4) +); + +BUFG BUFG_5( + .I(crg_clkout5), + .O(crg_clkout_buf5) +); + +IDELAYCTRL IDELAYCTRL( + .REFCLK(clk200_clk), + .RST(crg_ic_reset) +); + +DNA_PORT DNA_PORT( + .CLK(dna_clk), + .DIN(dna_status[56]), + .READ((dna_count < 2'd2)), + .SHIFT(1'd1), + .DOUT(dna_do) +); + +XADC #( + .INIT_40(16'd36864), + .INIT_41(14'd12016), + .INIT_42(11'd1024), + .INIT_48(15'd18177), + .INIT_49(4'd15), + .INIT_4A(15'd18176), + .INIT_4B(1'd0), + .INIT_4C(1'd0), + .INIT_4D(1'd0), + .INIT_4E(1'd0), + .INIT_4F(1'd0), + .INIT_50(16'd46573), + .INIT_51(15'd22937), + .INIT_52(16'd41287), + .INIT_53(16'd56797), + .INIT_54(16'd43322), + .INIT_55(15'd20753), + .INIT_56(16'd37355), + .INIT_57(16'd44622), + .INIT_58(15'd22937), + .INIT_5C(15'd20753) +) XADC ( + .CONVST(1'd0), + .CONVSTCLK(1'd0), + .DADDR(xadc_dadr), + .DCLK(sys_clk), + .DEN(xadc_den), + .DI(xadc_di), + .DWE(xadc_dwe), + .RESET(sys_rst), + .VAUXN(1'd0), + .VAUXP(1'd0), + .VN(1'd0), + .VP(1'd0), + .ALM(xadc_alarm), + .BUSY(xadc_busy), + .CHANNEL(xadc_channel), + .DO(xadc_do), + .DRDY(xadc_drdy), + .EOC(xadc_eoc), + .EOS(xadc_eos), + .OT(xadc_ot) +); + +ICAPE2 #( + .ICAP_WIDTH("X32") +) ICAPE2 ( + .CLK(icap_clk), + .CSIB(icap_csib), + .I({{slice_proxy31[0], slice_proxy30[1], slice_proxy29[2], slice_proxy28[3], slice_proxy27[4], slice_proxy26[5], slice_proxy25[6], slice_proxy24[7]}, {slice_proxy23[0], slice_proxy22[1], slice_proxy21[2], slice_proxy20[3], slice_proxy19[4], slice_proxy18[5], slice_proxy17[6], slice_proxy16[7]}, {slice_proxy15[0], slice_proxy14[1], slice_proxy13[2], slice_proxy12[3], slice_proxy11[4], slice_proxy10[5], slice_proxy9[6], slice_proxy8[7]}, {slice_proxy7[0], slice_proxy6[1], slice_proxy5[2], slice_proxy4[3], slice_proxy3[4], slice_proxy2[5], slice_proxy1[6], slice_proxy0[7]}}), + .RDWRB(1'd0) +); + +STARTUPE2 STARTUPE2( + .CLK(1'd0), + .GSR(1'd0), + .GTS(1'd0), + .KEYCLEARB(1'd0), + .PACK(1'd0), + .USRCCLKO(flash_pads_clk), + .USRCCLKTS(1'd0), + .USRDONEO(1'd1), + .USRDONETS(1'd1) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(1'd0), + .D2(1'd1), + .D3(1'd0), + .D4(1'd1), + .D5(1'd0), + .D6(1'd1), + .D7(1'd0), + .D8(1'd1), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(a7ddrphy_sd_clk_se_nodelay) +); + +OBUFDS OBUFDS( + .I(a7ddrphy_sd_clk_se_nodelay), + .O(ddram_clk_p), + .OB(ddram_clk_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_1 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[0]), + .D2(a7ddrphy_dfi_p0_address[0]), + .D3(a7ddrphy_dfi_p1_address[0]), + .D4(a7ddrphy_dfi_p1_address[0]), + .D5(a7ddrphy_dfi_p2_address[0]), + .D6(a7ddrphy_dfi_p2_address[0]), + .D7(a7ddrphy_dfi_p3_address[0]), + .D8(a7ddrphy_dfi_p3_address[0]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_2 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[1]), + .D2(a7ddrphy_dfi_p0_address[1]), + .D3(a7ddrphy_dfi_p1_address[1]), + .D4(a7ddrphy_dfi_p1_address[1]), + .D5(a7ddrphy_dfi_p2_address[1]), + .D6(a7ddrphy_dfi_p2_address[1]), + .D7(a7ddrphy_dfi_p3_address[1]), + .D8(a7ddrphy_dfi_p3_address[1]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_3 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[2]), + .D2(a7ddrphy_dfi_p0_address[2]), + .D3(a7ddrphy_dfi_p1_address[2]), + .D4(a7ddrphy_dfi_p1_address[2]), + .D5(a7ddrphy_dfi_p2_address[2]), + .D6(a7ddrphy_dfi_p2_address[2]), + .D7(a7ddrphy_dfi_p3_address[2]), + .D8(a7ddrphy_dfi_p3_address[2]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[2]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_4 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[3]), + .D2(a7ddrphy_dfi_p0_address[3]), + .D3(a7ddrphy_dfi_p1_address[3]), + .D4(a7ddrphy_dfi_p1_address[3]), + .D5(a7ddrphy_dfi_p2_address[3]), + .D6(a7ddrphy_dfi_p2_address[3]), + .D7(a7ddrphy_dfi_p3_address[3]), + .D8(a7ddrphy_dfi_p3_address[3]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[3]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_5 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[4]), + .D2(a7ddrphy_dfi_p0_address[4]), + .D3(a7ddrphy_dfi_p1_address[4]), + .D4(a7ddrphy_dfi_p1_address[4]), + .D5(a7ddrphy_dfi_p2_address[4]), + .D6(a7ddrphy_dfi_p2_address[4]), + .D7(a7ddrphy_dfi_p3_address[4]), + .D8(a7ddrphy_dfi_p3_address[4]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[4]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_6 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[5]), + .D2(a7ddrphy_dfi_p0_address[5]), + .D3(a7ddrphy_dfi_p1_address[5]), + .D4(a7ddrphy_dfi_p1_address[5]), + .D5(a7ddrphy_dfi_p2_address[5]), + .D6(a7ddrphy_dfi_p2_address[5]), + .D7(a7ddrphy_dfi_p3_address[5]), + .D8(a7ddrphy_dfi_p3_address[5]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[5]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_7 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[6]), + .D2(a7ddrphy_dfi_p0_address[6]), + .D3(a7ddrphy_dfi_p1_address[6]), + .D4(a7ddrphy_dfi_p1_address[6]), + .D5(a7ddrphy_dfi_p2_address[6]), + .D6(a7ddrphy_dfi_p2_address[6]), + .D7(a7ddrphy_dfi_p3_address[6]), + .D8(a7ddrphy_dfi_p3_address[6]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[6]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_8 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[7]), + .D2(a7ddrphy_dfi_p0_address[7]), + .D3(a7ddrphy_dfi_p1_address[7]), + .D4(a7ddrphy_dfi_p1_address[7]), + .D5(a7ddrphy_dfi_p2_address[7]), + .D6(a7ddrphy_dfi_p2_address[7]), + .D7(a7ddrphy_dfi_p3_address[7]), + .D8(a7ddrphy_dfi_p3_address[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[7]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_9 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[8]), + .D2(a7ddrphy_dfi_p0_address[8]), + .D3(a7ddrphy_dfi_p1_address[8]), + .D4(a7ddrphy_dfi_p1_address[8]), + .D5(a7ddrphy_dfi_p2_address[8]), + .D6(a7ddrphy_dfi_p2_address[8]), + .D7(a7ddrphy_dfi_p3_address[8]), + .D8(a7ddrphy_dfi_p3_address[8]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[8]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_10 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[9]), + .D2(a7ddrphy_dfi_p0_address[9]), + .D3(a7ddrphy_dfi_p1_address[9]), + .D4(a7ddrphy_dfi_p1_address[9]), + .D5(a7ddrphy_dfi_p2_address[9]), + .D6(a7ddrphy_dfi_p2_address[9]), + .D7(a7ddrphy_dfi_p3_address[9]), + .D8(a7ddrphy_dfi_p3_address[9]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[9]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_11 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[10]), + .D2(a7ddrphy_dfi_p0_address[10]), + .D3(a7ddrphy_dfi_p1_address[10]), + .D4(a7ddrphy_dfi_p1_address[10]), + .D5(a7ddrphy_dfi_p2_address[10]), + .D6(a7ddrphy_dfi_p2_address[10]), + .D7(a7ddrphy_dfi_p3_address[10]), + .D8(a7ddrphy_dfi_p3_address[10]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[10]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_12 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[11]), + .D2(a7ddrphy_dfi_p0_address[11]), + .D3(a7ddrphy_dfi_p1_address[11]), + .D4(a7ddrphy_dfi_p1_address[11]), + .D5(a7ddrphy_dfi_p2_address[11]), + .D6(a7ddrphy_dfi_p2_address[11]), + .D7(a7ddrphy_dfi_p3_address[11]), + .D8(a7ddrphy_dfi_p3_address[11]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[11]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_13 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[12]), + .D2(a7ddrphy_dfi_p0_address[12]), + .D3(a7ddrphy_dfi_p1_address[12]), + .D4(a7ddrphy_dfi_p1_address[12]), + .D5(a7ddrphy_dfi_p2_address[12]), + .D6(a7ddrphy_dfi_p2_address[12]), + .D7(a7ddrphy_dfi_p3_address[12]), + .D8(a7ddrphy_dfi_p3_address[12]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[12]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_14 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[13]), + .D2(a7ddrphy_dfi_p0_address[13]), + .D3(a7ddrphy_dfi_p1_address[13]), + .D4(a7ddrphy_dfi_p1_address[13]), + .D5(a7ddrphy_dfi_p2_address[13]), + .D6(a7ddrphy_dfi_p2_address[13]), + .D7(a7ddrphy_dfi_p3_address[13]), + .D8(a7ddrphy_dfi_p3_address[13]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[13]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_15 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_bank[0]), + .D2(a7ddrphy_dfi_p0_bank[0]), + .D3(a7ddrphy_dfi_p1_bank[0]), + .D4(a7ddrphy_dfi_p1_bank[0]), + .D5(a7ddrphy_dfi_p2_bank[0]), + .D6(a7ddrphy_dfi_p2_bank[0]), + .D7(a7ddrphy_dfi_p3_bank[0]), + .D8(a7ddrphy_dfi_p3_bank[0]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_ba[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_16 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_bank[1]), + .D2(a7ddrphy_dfi_p0_bank[1]), + .D3(a7ddrphy_dfi_p1_bank[1]), + .D4(a7ddrphy_dfi_p1_bank[1]), + .D5(a7ddrphy_dfi_p2_bank[1]), + .D6(a7ddrphy_dfi_p2_bank[1]), + .D7(a7ddrphy_dfi_p3_bank[1]), + .D8(a7ddrphy_dfi_p3_bank[1]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_ba[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_17 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_bank[2]), + .D2(a7ddrphy_dfi_p0_bank[2]), + .D3(a7ddrphy_dfi_p1_bank[2]), + .D4(a7ddrphy_dfi_p1_bank[2]), + .D5(a7ddrphy_dfi_p2_bank[2]), + .D6(a7ddrphy_dfi_p2_bank[2]), + .D7(a7ddrphy_dfi_p3_bank[2]), + .D8(a7ddrphy_dfi_p3_bank[2]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_ba[2]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_18 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_ras_n), + .D2(a7ddrphy_dfi_p0_ras_n), + .D3(a7ddrphy_dfi_p1_ras_n), + .D4(a7ddrphy_dfi_p1_ras_n), + .D5(a7ddrphy_dfi_p2_ras_n), + .D6(a7ddrphy_dfi_p2_ras_n), + .D7(a7ddrphy_dfi_p3_ras_n), + .D8(a7ddrphy_dfi_p3_ras_n), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_ras_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_19 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_cas_n), + .D2(a7ddrphy_dfi_p0_cas_n), + .D3(a7ddrphy_dfi_p1_cas_n), + .D4(a7ddrphy_dfi_p1_cas_n), + .D5(a7ddrphy_dfi_p2_cas_n), + .D6(a7ddrphy_dfi_p2_cas_n), + .D7(a7ddrphy_dfi_p3_cas_n), + .D8(a7ddrphy_dfi_p3_cas_n), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_cas_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_20 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_we_n), + .D2(a7ddrphy_dfi_p0_we_n), + .D3(a7ddrphy_dfi_p1_we_n), + .D4(a7ddrphy_dfi_p1_we_n), + .D5(a7ddrphy_dfi_p2_we_n), + .D6(a7ddrphy_dfi_p2_we_n), + .D7(a7ddrphy_dfi_p3_we_n), + .D8(a7ddrphy_dfi_p3_we_n), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_we_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_21 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_cke), + .D2(a7ddrphy_dfi_p0_cke), + .D3(a7ddrphy_dfi_p1_cke), + .D4(a7ddrphy_dfi_p1_cke), + .D5(a7ddrphy_dfi_p2_cke), + .D6(a7ddrphy_dfi_p2_cke), + .D7(a7ddrphy_dfi_p3_cke), + .D8(a7ddrphy_dfi_p3_cke), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_cke) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_22 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_odt), + .D2(a7ddrphy_dfi_p0_odt), + .D3(a7ddrphy_dfi_p1_odt), + .D4(a7ddrphy_dfi_p1_odt), + .D5(a7ddrphy_dfi_p2_odt), + .D6(a7ddrphy_dfi_p2_odt), + .D7(a7ddrphy_dfi_p3_odt), + .D8(a7ddrphy_dfi_p3_odt), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_odt) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_23 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_reset_n), + .D2(a7ddrphy_dfi_p0_reset_n), + .D3(a7ddrphy_dfi_p1_reset_n), + .D4(a7ddrphy_dfi_p1_reset_n), + .D5(a7ddrphy_dfi_p2_reset_n), + .D6(a7ddrphy_dfi_p2_reset_n), + .D7(a7ddrphy_dfi_p3_reset_n), + .D8(a7ddrphy_dfi_p3_reset_n), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_reset_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_24 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_cs_n), + .D2(a7ddrphy_dfi_p0_cs_n), + .D3(a7ddrphy_dfi_p1_cs_n), + .D4(a7ddrphy_dfi_p1_cs_n), + .D5(a7ddrphy_dfi_p2_cs_n), + .D6(a7ddrphy_dfi_p2_cs_n), + .D7(a7ddrphy_dfi_p3_cs_n), + .D8(a7ddrphy_dfi_p3_cs_n), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_cs_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_25 ( + .CLK(sys4x_dqs_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip00[0]), + .D2(a7ddrphy_bitslip00[1]), + .D3(a7ddrphy_bitslip00[2]), + .D4(a7ddrphy_bitslip00[3]), + .D5(a7ddrphy_bitslip00[4]), + .D6(a7ddrphy_bitslip00[5]), + .D7(a7ddrphy_bitslip00[6]), + .D8(a7ddrphy_bitslip00[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OFB(a7ddrphy0), + .OQ(a7ddrphy_dqs_o_no_delay0), + .TQ(a7ddrphy_dqs_t0) +); + +IOBUFDS IOBUFDS( + .I(a7ddrphy_dqs_o_no_delay0), + .T(a7ddrphy_dqs_t0), + .IO(ddram_dqs_p[0]), + .IOB(ddram_dqs_n[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_26 ( + .CLK(sys4x_dqs_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip10[0]), + .D2(a7ddrphy_bitslip10[1]), + .D3(a7ddrphy_bitslip10[2]), + .D4(a7ddrphy_bitslip10[3]), + .D5(a7ddrphy_bitslip10[4]), + .D6(a7ddrphy_bitslip10[5]), + .D7(a7ddrphy_bitslip10[6]), + .D8(a7ddrphy_bitslip10[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OFB(a7ddrphy1), + .OQ(a7ddrphy_dqs_o_no_delay1), + .TQ(a7ddrphy_dqs_t1) +); + +IOBUFDS IOBUFDS_1( + .I(a7ddrphy_dqs_o_no_delay1), + .T(a7ddrphy_dqs_t1), + .IO(ddram_dqs_p[1]), + .IOB(ddram_dqs_n[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_27 ( + .CLK(sys4x_dqs_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip20[0]), + .D2(a7ddrphy_bitslip20[1]), + .D3(a7ddrphy_bitslip20[2]), + .D4(a7ddrphy_bitslip20[3]), + .D5(a7ddrphy_bitslip20[4]), + .D6(a7ddrphy_bitslip20[5]), + .D7(a7ddrphy_bitslip20[6]), + .D8(a7ddrphy_bitslip20[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OFB(a7ddrphy2), + .OQ(a7ddrphy_dqs_o_no_delay2), + .TQ(a7ddrphy_dqs_t2) +); + +IOBUFDS IOBUFDS_2( + .I(a7ddrphy_dqs_o_no_delay2), + .T(a7ddrphy_dqs_t2), + .IO(ddram_dqs_p[2]), + .IOB(ddram_dqs_n[2]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_28 ( + .CLK(sys4x_dqs_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip30[0]), + .D2(a7ddrphy_bitslip30[1]), + .D3(a7ddrphy_bitslip30[2]), + .D4(a7ddrphy_bitslip30[3]), + .D5(a7ddrphy_bitslip30[4]), + .D6(a7ddrphy_bitslip30[5]), + .D7(a7ddrphy_bitslip30[6]), + .D8(a7ddrphy_bitslip30[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OFB(a7ddrphy3), + .OQ(a7ddrphy_dqs_o_no_delay3), + .TQ(a7ddrphy_dqs_t3) +); + +IOBUFDS IOBUFDS_3( + .I(a7ddrphy_dqs_o_no_delay3), + .T(a7ddrphy_dqs_t3), + .IO(ddram_dqs_p[3]), + .IOB(ddram_dqs_n[3]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_29 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip01[0]), + .D2(a7ddrphy_bitslip01[1]), + .D3(a7ddrphy_bitslip01[2]), + .D4(a7ddrphy_bitslip01[3]), + .D5(a7ddrphy_bitslip01[4]), + .D6(a7ddrphy_bitslip01[5]), + .D7(a7ddrphy_bitslip01[6]), + .D8(a7ddrphy_bitslip01[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_dm[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_30 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip11[0]), + .D2(a7ddrphy_bitslip11[1]), + .D3(a7ddrphy_bitslip11[2]), + .D4(a7ddrphy_bitslip11[3]), + .D5(a7ddrphy_bitslip11[4]), + .D6(a7ddrphy_bitslip11[5]), + .D7(a7ddrphy_bitslip11[6]), + .D8(a7ddrphy_bitslip11[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_dm[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_31 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip21[0]), + .D2(a7ddrphy_bitslip21[1]), + .D3(a7ddrphy_bitslip21[2]), + .D4(a7ddrphy_bitslip21[3]), + .D5(a7ddrphy_bitslip21[4]), + .D6(a7ddrphy_bitslip21[5]), + .D7(a7ddrphy_bitslip21[6]), + .D8(a7ddrphy_bitslip21[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_dm[2]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_32 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip31[0]), + .D2(a7ddrphy_bitslip31[1]), + .D3(a7ddrphy_bitslip31[2]), + .D4(a7ddrphy_bitslip31[3]), + .D5(a7ddrphy_bitslip31[4]), + .D6(a7ddrphy_bitslip31[5]), + .D7(a7ddrphy_bitslip31[6]), + .D8(a7ddrphy_bitslip31[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_dm[3]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_33 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip02[0]), + .D2(a7ddrphy_bitslip02[1]), + .D3(a7ddrphy_bitslip02[2]), + .D4(a7ddrphy_bitslip02[3]), + .D5(a7ddrphy_bitslip02[4]), + .D6(a7ddrphy_bitslip02[5]), + .D7(a7ddrphy_bitslip02[6]), + .D8(a7ddrphy_bitslip02[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay0), + .TQ(a7ddrphy_dq_t0) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed0), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip03[7]), + .Q2(a7ddrphy_bitslip03[6]), + .Q3(a7ddrphy_bitslip03[5]), + .Q4(a7ddrphy_bitslip03[4]), + .Q5(a7ddrphy_bitslip03[3]), + .Q6(a7ddrphy_bitslip03[2]), + .Q7(a7ddrphy_bitslip03[1]), + .Q8(a7ddrphy_bitslip03[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay0), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed0) +); + +IOBUF IOBUF( + .I(a7ddrphy_dq_o_nodelay0), + .T(a7ddrphy_dq_t0), + .IO(ddram_dq[0]), + .O(a7ddrphy_dq_i_nodelay0) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_34 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip12[0]), + .D2(a7ddrphy_bitslip12[1]), + .D3(a7ddrphy_bitslip12[2]), + .D4(a7ddrphy_bitslip12[3]), + .D5(a7ddrphy_bitslip12[4]), + .D6(a7ddrphy_bitslip12[5]), + .D7(a7ddrphy_bitslip12[6]), + .D8(a7ddrphy_bitslip12[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay1), + .TQ(a7ddrphy_dq_t1) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_1 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip13[7]), + .Q2(a7ddrphy_bitslip13[6]), + .Q3(a7ddrphy_bitslip13[5]), + .Q4(a7ddrphy_bitslip13[4]), + .Q5(a7ddrphy_bitslip13[3]), + .Q6(a7ddrphy_bitslip13[2]), + .Q7(a7ddrphy_bitslip13[1]), + .Q8(a7ddrphy_bitslip13[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_1 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay1), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed1) +); + +IOBUF IOBUF_1( + .I(a7ddrphy_dq_o_nodelay1), + .T(a7ddrphy_dq_t1), + .IO(ddram_dq[1]), + .O(a7ddrphy_dq_i_nodelay1) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_35 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip22[0]), + .D2(a7ddrphy_bitslip22[1]), + .D3(a7ddrphy_bitslip22[2]), + .D4(a7ddrphy_bitslip22[3]), + .D5(a7ddrphy_bitslip22[4]), + .D6(a7ddrphy_bitslip22[5]), + .D7(a7ddrphy_bitslip22[6]), + .D8(a7ddrphy_bitslip22[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay2), + .TQ(a7ddrphy_dq_t2) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_2 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed2), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip23[7]), + .Q2(a7ddrphy_bitslip23[6]), + .Q3(a7ddrphy_bitslip23[5]), + .Q4(a7ddrphy_bitslip23[4]), + .Q5(a7ddrphy_bitslip23[3]), + .Q6(a7ddrphy_bitslip23[2]), + .Q7(a7ddrphy_bitslip23[1]), + .Q8(a7ddrphy_bitslip23[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_2 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay2), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed2) +); + +IOBUF IOBUF_2( + .I(a7ddrphy_dq_o_nodelay2), + .T(a7ddrphy_dq_t2), + .IO(ddram_dq[2]), + .O(a7ddrphy_dq_i_nodelay2) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_36 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip32[0]), + .D2(a7ddrphy_bitslip32[1]), + .D3(a7ddrphy_bitslip32[2]), + .D4(a7ddrphy_bitslip32[3]), + .D5(a7ddrphy_bitslip32[4]), + .D6(a7ddrphy_bitslip32[5]), + .D7(a7ddrphy_bitslip32[6]), + .D8(a7ddrphy_bitslip32[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay3), + .TQ(a7ddrphy_dq_t3) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_3 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed3), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip33[7]), + .Q2(a7ddrphy_bitslip33[6]), + .Q3(a7ddrphy_bitslip33[5]), + .Q4(a7ddrphy_bitslip33[4]), + .Q5(a7ddrphy_bitslip33[3]), + .Q6(a7ddrphy_bitslip33[2]), + .Q7(a7ddrphy_bitslip33[1]), + .Q8(a7ddrphy_bitslip33[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_3 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay3), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed3) +); + +IOBUF IOBUF_3( + .I(a7ddrphy_dq_o_nodelay3), + .T(a7ddrphy_dq_t3), + .IO(ddram_dq[3]), + .O(a7ddrphy_dq_i_nodelay3) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_37 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip40[0]), + .D2(a7ddrphy_bitslip40[1]), + .D3(a7ddrphy_bitslip40[2]), + .D4(a7ddrphy_bitslip40[3]), + .D5(a7ddrphy_bitslip40[4]), + .D6(a7ddrphy_bitslip40[5]), + .D7(a7ddrphy_bitslip40[6]), + .D8(a7ddrphy_bitslip40[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay4), + .TQ(a7ddrphy_dq_t4) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_4 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed4), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip41[7]), + .Q2(a7ddrphy_bitslip41[6]), + .Q3(a7ddrphy_bitslip41[5]), + .Q4(a7ddrphy_bitslip41[4]), + .Q5(a7ddrphy_bitslip41[3]), + .Q6(a7ddrphy_bitslip41[2]), + .Q7(a7ddrphy_bitslip41[1]), + .Q8(a7ddrphy_bitslip41[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_4 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay4), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed4) +); + +IOBUF IOBUF_4( + .I(a7ddrphy_dq_o_nodelay4), + .T(a7ddrphy_dq_t4), + .IO(ddram_dq[4]), + .O(a7ddrphy_dq_i_nodelay4) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_38 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip50[0]), + .D2(a7ddrphy_bitslip50[1]), + .D3(a7ddrphy_bitslip50[2]), + .D4(a7ddrphy_bitslip50[3]), + .D5(a7ddrphy_bitslip50[4]), + .D6(a7ddrphy_bitslip50[5]), + .D7(a7ddrphy_bitslip50[6]), + .D8(a7ddrphy_bitslip50[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay5), + .TQ(a7ddrphy_dq_t5) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_5 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed5), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip51[7]), + .Q2(a7ddrphy_bitslip51[6]), + .Q3(a7ddrphy_bitslip51[5]), + .Q4(a7ddrphy_bitslip51[4]), + .Q5(a7ddrphy_bitslip51[3]), + .Q6(a7ddrphy_bitslip51[2]), + .Q7(a7ddrphy_bitslip51[1]), + .Q8(a7ddrphy_bitslip51[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_5 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay5), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed5) +); + +IOBUF IOBUF_5( + .I(a7ddrphy_dq_o_nodelay5), + .T(a7ddrphy_dq_t5), + .IO(ddram_dq[5]), + .O(a7ddrphy_dq_i_nodelay5) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_39 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip60[0]), + .D2(a7ddrphy_bitslip60[1]), + .D3(a7ddrphy_bitslip60[2]), + .D4(a7ddrphy_bitslip60[3]), + .D5(a7ddrphy_bitslip60[4]), + .D6(a7ddrphy_bitslip60[5]), + .D7(a7ddrphy_bitslip60[6]), + .D8(a7ddrphy_bitslip60[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay6), + .TQ(a7ddrphy_dq_t6) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_6 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed6), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip61[7]), + .Q2(a7ddrphy_bitslip61[6]), + .Q3(a7ddrphy_bitslip61[5]), + .Q4(a7ddrphy_bitslip61[4]), + .Q5(a7ddrphy_bitslip61[3]), + .Q6(a7ddrphy_bitslip61[2]), + .Q7(a7ddrphy_bitslip61[1]), + .Q8(a7ddrphy_bitslip61[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_6 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay6), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed6) +); + +IOBUF IOBUF_6( + .I(a7ddrphy_dq_o_nodelay6), + .T(a7ddrphy_dq_t6), + .IO(ddram_dq[6]), + .O(a7ddrphy_dq_i_nodelay6) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_40 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip70[0]), + .D2(a7ddrphy_bitslip70[1]), + .D3(a7ddrphy_bitslip70[2]), + .D4(a7ddrphy_bitslip70[3]), + .D5(a7ddrphy_bitslip70[4]), + .D6(a7ddrphy_bitslip70[5]), + .D7(a7ddrphy_bitslip70[6]), + .D8(a7ddrphy_bitslip70[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay7), + .TQ(a7ddrphy_dq_t7) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_7 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed7), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip71[7]), + .Q2(a7ddrphy_bitslip71[6]), + .Q3(a7ddrphy_bitslip71[5]), + .Q4(a7ddrphy_bitslip71[4]), + .Q5(a7ddrphy_bitslip71[3]), + .Q6(a7ddrphy_bitslip71[2]), + .Q7(a7ddrphy_bitslip71[1]), + .Q8(a7ddrphy_bitslip71[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_7 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay7), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed7) +); + +IOBUF IOBUF_7( + .I(a7ddrphy_dq_o_nodelay7), + .T(a7ddrphy_dq_t7), + .IO(ddram_dq[7]), + .O(a7ddrphy_dq_i_nodelay7) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_41 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip80[0]), + .D2(a7ddrphy_bitslip80[1]), + .D3(a7ddrphy_bitslip80[2]), + .D4(a7ddrphy_bitslip80[3]), + .D5(a7ddrphy_bitslip80[4]), + .D6(a7ddrphy_bitslip80[5]), + .D7(a7ddrphy_bitslip80[6]), + .D8(a7ddrphy_bitslip80[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay8), + .TQ(a7ddrphy_dq_t8) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_8 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed8), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip81[7]), + .Q2(a7ddrphy_bitslip81[6]), + .Q3(a7ddrphy_bitslip81[5]), + .Q4(a7ddrphy_bitslip81[4]), + .Q5(a7ddrphy_bitslip81[3]), + .Q6(a7ddrphy_bitslip81[2]), + .Q7(a7ddrphy_bitslip81[1]), + .Q8(a7ddrphy_bitslip81[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_8 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay8), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed8) +); + +IOBUF IOBUF_8( + .I(a7ddrphy_dq_o_nodelay8), + .T(a7ddrphy_dq_t8), + .IO(ddram_dq[8]), + .O(a7ddrphy_dq_i_nodelay8) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_42 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip90[0]), + .D2(a7ddrphy_bitslip90[1]), + .D3(a7ddrphy_bitslip90[2]), + .D4(a7ddrphy_bitslip90[3]), + .D5(a7ddrphy_bitslip90[4]), + .D6(a7ddrphy_bitslip90[5]), + .D7(a7ddrphy_bitslip90[6]), + .D8(a7ddrphy_bitslip90[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay9), + .TQ(a7ddrphy_dq_t9) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_9 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed9), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip91[7]), + .Q2(a7ddrphy_bitslip91[6]), + .Q3(a7ddrphy_bitslip91[5]), + .Q4(a7ddrphy_bitslip91[4]), + .Q5(a7ddrphy_bitslip91[3]), + .Q6(a7ddrphy_bitslip91[2]), + .Q7(a7ddrphy_bitslip91[1]), + .Q8(a7ddrphy_bitslip91[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_9 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay9), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed9) +); + +IOBUF IOBUF_9( + .I(a7ddrphy_dq_o_nodelay9), + .T(a7ddrphy_dq_t9), + .IO(ddram_dq[9]), + .O(a7ddrphy_dq_i_nodelay9) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_43 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip100[0]), + .D2(a7ddrphy_bitslip100[1]), + .D3(a7ddrphy_bitslip100[2]), + .D4(a7ddrphy_bitslip100[3]), + .D5(a7ddrphy_bitslip100[4]), + .D6(a7ddrphy_bitslip100[5]), + .D7(a7ddrphy_bitslip100[6]), + .D8(a7ddrphy_bitslip100[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay10), + .TQ(a7ddrphy_dq_t10) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_10 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed10), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip101[7]), + .Q2(a7ddrphy_bitslip101[6]), + .Q3(a7ddrphy_bitslip101[5]), + .Q4(a7ddrphy_bitslip101[4]), + .Q5(a7ddrphy_bitslip101[3]), + .Q6(a7ddrphy_bitslip101[2]), + .Q7(a7ddrphy_bitslip101[1]), + .Q8(a7ddrphy_bitslip101[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_10 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay10), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed10) +); + +IOBUF IOBUF_10( + .I(a7ddrphy_dq_o_nodelay10), + .T(a7ddrphy_dq_t10), + .IO(ddram_dq[10]), + .O(a7ddrphy_dq_i_nodelay10) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_44 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip110[0]), + .D2(a7ddrphy_bitslip110[1]), + .D3(a7ddrphy_bitslip110[2]), + .D4(a7ddrphy_bitslip110[3]), + .D5(a7ddrphy_bitslip110[4]), + .D6(a7ddrphy_bitslip110[5]), + .D7(a7ddrphy_bitslip110[6]), + .D8(a7ddrphy_bitslip110[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay11), + .TQ(a7ddrphy_dq_t11) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_11 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed11), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip111[7]), + .Q2(a7ddrphy_bitslip111[6]), + .Q3(a7ddrphy_bitslip111[5]), + .Q4(a7ddrphy_bitslip111[4]), + .Q5(a7ddrphy_bitslip111[3]), + .Q6(a7ddrphy_bitslip111[2]), + .Q7(a7ddrphy_bitslip111[1]), + .Q8(a7ddrphy_bitslip111[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_11 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay11), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed11) +); + +IOBUF IOBUF_11( + .I(a7ddrphy_dq_o_nodelay11), + .T(a7ddrphy_dq_t11), + .IO(ddram_dq[11]), + .O(a7ddrphy_dq_i_nodelay11) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_45 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip120[0]), + .D2(a7ddrphy_bitslip120[1]), + .D3(a7ddrphy_bitslip120[2]), + .D4(a7ddrphy_bitslip120[3]), + .D5(a7ddrphy_bitslip120[4]), + .D6(a7ddrphy_bitslip120[5]), + .D7(a7ddrphy_bitslip120[6]), + .D8(a7ddrphy_bitslip120[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay12), + .TQ(a7ddrphy_dq_t12) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_12 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed12), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip121[7]), + .Q2(a7ddrphy_bitslip121[6]), + .Q3(a7ddrphy_bitslip121[5]), + .Q4(a7ddrphy_bitslip121[4]), + .Q5(a7ddrphy_bitslip121[3]), + .Q6(a7ddrphy_bitslip121[2]), + .Q7(a7ddrphy_bitslip121[1]), + .Q8(a7ddrphy_bitslip121[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_12 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay12), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed12) +); + +IOBUF IOBUF_12( + .I(a7ddrphy_dq_o_nodelay12), + .T(a7ddrphy_dq_t12), + .IO(ddram_dq[12]), + .O(a7ddrphy_dq_i_nodelay12) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_46 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip130[0]), + .D2(a7ddrphy_bitslip130[1]), + .D3(a7ddrphy_bitslip130[2]), + .D4(a7ddrphy_bitslip130[3]), + .D5(a7ddrphy_bitslip130[4]), + .D6(a7ddrphy_bitslip130[5]), + .D7(a7ddrphy_bitslip130[6]), + .D8(a7ddrphy_bitslip130[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay13), + .TQ(a7ddrphy_dq_t13) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_13 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed13), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip131[7]), + .Q2(a7ddrphy_bitslip131[6]), + .Q3(a7ddrphy_bitslip131[5]), + .Q4(a7ddrphy_bitslip131[4]), + .Q5(a7ddrphy_bitslip131[3]), + .Q6(a7ddrphy_bitslip131[2]), + .Q7(a7ddrphy_bitslip131[1]), + .Q8(a7ddrphy_bitslip131[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_13 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay13), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed13) +); + +IOBUF IOBUF_13( + .I(a7ddrphy_dq_o_nodelay13), + .T(a7ddrphy_dq_t13), + .IO(ddram_dq[13]), + .O(a7ddrphy_dq_i_nodelay13) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_47 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip140[0]), + .D2(a7ddrphy_bitslip140[1]), + .D3(a7ddrphy_bitslip140[2]), + .D4(a7ddrphy_bitslip140[3]), + .D5(a7ddrphy_bitslip140[4]), + .D6(a7ddrphy_bitslip140[5]), + .D7(a7ddrphy_bitslip140[6]), + .D8(a7ddrphy_bitslip140[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay14), + .TQ(a7ddrphy_dq_t14) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_14 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed14), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip141[7]), + .Q2(a7ddrphy_bitslip141[6]), + .Q3(a7ddrphy_bitslip141[5]), + .Q4(a7ddrphy_bitslip141[4]), + .Q5(a7ddrphy_bitslip141[3]), + .Q6(a7ddrphy_bitslip141[2]), + .Q7(a7ddrphy_bitslip141[1]), + .Q8(a7ddrphy_bitslip141[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_14 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay14), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed14) +); + +IOBUF IOBUF_14( + .I(a7ddrphy_dq_o_nodelay14), + .T(a7ddrphy_dq_t14), + .IO(ddram_dq[14]), + .O(a7ddrphy_dq_i_nodelay14) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_48 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip150[0]), + .D2(a7ddrphy_bitslip150[1]), + .D3(a7ddrphy_bitslip150[2]), + .D4(a7ddrphy_bitslip150[3]), + .D5(a7ddrphy_bitslip150[4]), + .D6(a7ddrphy_bitslip150[5]), + .D7(a7ddrphy_bitslip150[6]), + .D8(a7ddrphy_bitslip150[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay15), + .TQ(a7ddrphy_dq_t15) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_15 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed15), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip151[7]), + .Q2(a7ddrphy_bitslip151[6]), + .Q3(a7ddrphy_bitslip151[5]), + .Q4(a7ddrphy_bitslip151[4]), + .Q5(a7ddrphy_bitslip151[3]), + .Q6(a7ddrphy_bitslip151[2]), + .Q7(a7ddrphy_bitslip151[1]), + .Q8(a7ddrphy_bitslip151[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_15 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay15), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed15) +); + +IOBUF IOBUF_15( + .I(a7ddrphy_dq_o_nodelay15), + .T(a7ddrphy_dq_t15), + .IO(ddram_dq[15]), + .O(a7ddrphy_dq_i_nodelay15) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_49 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip160[0]), + .D2(a7ddrphy_bitslip160[1]), + .D3(a7ddrphy_bitslip160[2]), + .D4(a7ddrphy_bitslip160[3]), + .D5(a7ddrphy_bitslip160[4]), + .D6(a7ddrphy_bitslip160[5]), + .D7(a7ddrphy_bitslip160[6]), + .D8(a7ddrphy_bitslip160[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay16), + .TQ(a7ddrphy_dq_t16) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_16 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed16), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip161[7]), + .Q2(a7ddrphy_bitslip161[6]), + .Q3(a7ddrphy_bitslip161[5]), + .Q4(a7ddrphy_bitslip161[4]), + .Q5(a7ddrphy_bitslip161[3]), + .Q6(a7ddrphy_bitslip161[2]), + .Q7(a7ddrphy_bitslip161[1]), + .Q8(a7ddrphy_bitslip161[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_16 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay16), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed16) +); + +IOBUF IOBUF_16( + .I(a7ddrphy_dq_o_nodelay16), + .T(a7ddrphy_dq_t16), + .IO(ddram_dq[16]), + .O(a7ddrphy_dq_i_nodelay16) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_50 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip170[0]), + .D2(a7ddrphy_bitslip170[1]), + .D3(a7ddrphy_bitslip170[2]), + .D4(a7ddrphy_bitslip170[3]), + .D5(a7ddrphy_bitslip170[4]), + .D6(a7ddrphy_bitslip170[5]), + .D7(a7ddrphy_bitslip170[6]), + .D8(a7ddrphy_bitslip170[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay17), + .TQ(a7ddrphy_dq_t17) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_17 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed17), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip171[7]), + .Q2(a7ddrphy_bitslip171[6]), + .Q3(a7ddrphy_bitslip171[5]), + .Q4(a7ddrphy_bitslip171[4]), + .Q5(a7ddrphy_bitslip171[3]), + .Q6(a7ddrphy_bitslip171[2]), + .Q7(a7ddrphy_bitslip171[1]), + .Q8(a7ddrphy_bitslip171[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_17 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay17), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed17) +); + +IOBUF IOBUF_17( + .I(a7ddrphy_dq_o_nodelay17), + .T(a7ddrphy_dq_t17), + .IO(ddram_dq[17]), + .O(a7ddrphy_dq_i_nodelay17) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_51 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip180[0]), + .D2(a7ddrphy_bitslip180[1]), + .D3(a7ddrphy_bitslip180[2]), + .D4(a7ddrphy_bitslip180[3]), + .D5(a7ddrphy_bitslip180[4]), + .D6(a7ddrphy_bitslip180[5]), + .D7(a7ddrphy_bitslip180[6]), + .D8(a7ddrphy_bitslip180[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay18), + .TQ(a7ddrphy_dq_t18) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_18 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed18), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip181[7]), + .Q2(a7ddrphy_bitslip181[6]), + .Q3(a7ddrphy_bitslip181[5]), + .Q4(a7ddrphy_bitslip181[4]), + .Q5(a7ddrphy_bitslip181[3]), + .Q6(a7ddrphy_bitslip181[2]), + .Q7(a7ddrphy_bitslip181[1]), + .Q8(a7ddrphy_bitslip181[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_18 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay18), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed18) +); + +IOBUF IOBUF_18( + .I(a7ddrphy_dq_o_nodelay18), + .T(a7ddrphy_dq_t18), + .IO(ddram_dq[18]), + .O(a7ddrphy_dq_i_nodelay18) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_52 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip190[0]), + .D2(a7ddrphy_bitslip190[1]), + .D3(a7ddrphy_bitslip190[2]), + .D4(a7ddrphy_bitslip190[3]), + .D5(a7ddrphy_bitslip190[4]), + .D6(a7ddrphy_bitslip190[5]), + .D7(a7ddrphy_bitslip190[6]), + .D8(a7ddrphy_bitslip190[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay19), + .TQ(a7ddrphy_dq_t19) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_19 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed19), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip191[7]), + .Q2(a7ddrphy_bitslip191[6]), + .Q3(a7ddrphy_bitslip191[5]), + .Q4(a7ddrphy_bitslip191[4]), + .Q5(a7ddrphy_bitslip191[3]), + .Q6(a7ddrphy_bitslip191[2]), + .Q7(a7ddrphy_bitslip191[1]), + .Q8(a7ddrphy_bitslip191[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_19 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay19), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed19) +); + +IOBUF IOBUF_19( + .I(a7ddrphy_dq_o_nodelay19), + .T(a7ddrphy_dq_t19), + .IO(ddram_dq[19]), + .O(a7ddrphy_dq_i_nodelay19) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_53 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip200[0]), + .D2(a7ddrphy_bitslip200[1]), + .D3(a7ddrphy_bitslip200[2]), + .D4(a7ddrphy_bitslip200[3]), + .D5(a7ddrphy_bitslip200[4]), + .D6(a7ddrphy_bitslip200[5]), + .D7(a7ddrphy_bitslip200[6]), + .D8(a7ddrphy_bitslip200[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay20), + .TQ(a7ddrphy_dq_t20) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_20 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed20), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip201[7]), + .Q2(a7ddrphy_bitslip201[6]), + .Q3(a7ddrphy_bitslip201[5]), + .Q4(a7ddrphy_bitslip201[4]), + .Q5(a7ddrphy_bitslip201[3]), + .Q6(a7ddrphy_bitslip201[2]), + .Q7(a7ddrphy_bitslip201[1]), + .Q8(a7ddrphy_bitslip201[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_20 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay20), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed20) +); + +IOBUF IOBUF_20( + .I(a7ddrphy_dq_o_nodelay20), + .T(a7ddrphy_dq_t20), + .IO(ddram_dq[20]), + .O(a7ddrphy_dq_i_nodelay20) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_54 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip210[0]), + .D2(a7ddrphy_bitslip210[1]), + .D3(a7ddrphy_bitslip210[2]), + .D4(a7ddrphy_bitslip210[3]), + .D5(a7ddrphy_bitslip210[4]), + .D6(a7ddrphy_bitslip210[5]), + .D7(a7ddrphy_bitslip210[6]), + .D8(a7ddrphy_bitslip210[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay21), + .TQ(a7ddrphy_dq_t21) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_21 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed21), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip211[7]), + .Q2(a7ddrphy_bitslip211[6]), + .Q3(a7ddrphy_bitslip211[5]), + .Q4(a7ddrphy_bitslip211[4]), + .Q5(a7ddrphy_bitslip211[3]), + .Q6(a7ddrphy_bitslip211[2]), + .Q7(a7ddrphy_bitslip211[1]), + .Q8(a7ddrphy_bitslip211[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_21 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay21), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed21) +); + +IOBUF IOBUF_21( + .I(a7ddrphy_dq_o_nodelay21), + .T(a7ddrphy_dq_t21), + .IO(ddram_dq[21]), + .O(a7ddrphy_dq_i_nodelay21) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_55 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip220[0]), + .D2(a7ddrphy_bitslip220[1]), + .D3(a7ddrphy_bitslip220[2]), + .D4(a7ddrphy_bitslip220[3]), + .D5(a7ddrphy_bitslip220[4]), + .D6(a7ddrphy_bitslip220[5]), + .D7(a7ddrphy_bitslip220[6]), + .D8(a7ddrphy_bitslip220[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay22), + .TQ(a7ddrphy_dq_t22) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_22 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed22), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip221[7]), + .Q2(a7ddrphy_bitslip221[6]), + .Q3(a7ddrphy_bitslip221[5]), + .Q4(a7ddrphy_bitslip221[4]), + .Q5(a7ddrphy_bitslip221[3]), + .Q6(a7ddrphy_bitslip221[2]), + .Q7(a7ddrphy_bitslip221[1]), + .Q8(a7ddrphy_bitslip221[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_22 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay22), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed22) +); + +IOBUF IOBUF_22( + .I(a7ddrphy_dq_o_nodelay22), + .T(a7ddrphy_dq_t22), + .IO(ddram_dq[22]), + .O(a7ddrphy_dq_i_nodelay22) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_56 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip230[0]), + .D2(a7ddrphy_bitslip230[1]), + .D3(a7ddrphy_bitslip230[2]), + .D4(a7ddrphy_bitslip230[3]), + .D5(a7ddrphy_bitslip230[4]), + .D6(a7ddrphy_bitslip230[5]), + .D7(a7ddrphy_bitslip230[6]), + .D8(a7ddrphy_bitslip230[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay23), + .TQ(a7ddrphy_dq_t23) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_23 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed23), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip231[7]), + .Q2(a7ddrphy_bitslip231[6]), + .Q3(a7ddrphy_bitslip231[5]), + .Q4(a7ddrphy_bitslip231[4]), + .Q5(a7ddrphy_bitslip231[3]), + .Q6(a7ddrphy_bitslip231[2]), + .Q7(a7ddrphy_bitslip231[1]), + .Q8(a7ddrphy_bitslip231[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_23 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay23), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[2] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed23) +); + +IOBUF IOBUF_23( + .I(a7ddrphy_dq_o_nodelay23), + .T(a7ddrphy_dq_t23), + .IO(ddram_dq[23]), + .O(a7ddrphy_dq_i_nodelay23) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_57 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip240[0]), + .D2(a7ddrphy_bitslip240[1]), + .D3(a7ddrphy_bitslip240[2]), + .D4(a7ddrphy_bitslip240[3]), + .D5(a7ddrphy_bitslip240[4]), + .D6(a7ddrphy_bitslip240[5]), + .D7(a7ddrphy_bitslip240[6]), + .D8(a7ddrphy_bitslip240[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay24), + .TQ(a7ddrphy_dq_t24) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_24 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed24), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip241[7]), + .Q2(a7ddrphy_bitslip241[6]), + .Q3(a7ddrphy_bitslip241[5]), + .Q4(a7ddrphy_bitslip241[4]), + .Q5(a7ddrphy_bitslip241[3]), + .Q6(a7ddrphy_bitslip241[2]), + .Q7(a7ddrphy_bitslip241[1]), + .Q8(a7ddrphy_bitslip241[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_24 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay24), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed24) +); + +IOBUF IOBUF_24( + .I(a7ddrphy_dq_o_nodelay24), + .T(a7ddrphy_dq_t24), + .IO(ddram_dq[24]), + .O(a7ddrphy_dq_i_nodelay24) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_58 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip250[0]), + .D2(a7ddrphy_bitslip250[1]), + .D3(a7ddrphy_bitslip250[2]), + .D4(a7ddrphy_bitslip250[3]), + .D5(a7ddrphy_bitslip250[4]), + .D6(a7ddrphy_bitslip250[5]), + .D7(a7ddrphy_bitslip250[6]), + .D8(a7ddrphy_bitslip250[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay25), + .TQ(a7ddrphy_dq_t25) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_25 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed25), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip251[7]), + .Q2(a7ddrphy_bitslip251[6]), + .Q3(a7ddrphy_bitslip251[5]), + .Q4(a7ddrphy_bitslip251[4]), + .Q5(a7ddrphy_bitslip251[3]), + .Q6(a7ddrphy_bitslip251[2]), + .Q7(a7ddrphy_bitslip251[1]), + .Q8(a7ddrphy_bitslip251[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_25 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay25), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed25) +); + +IOBUF IOBUF_25( + .I(a7ddrphy_dq_o_nodelay25), + .T(a7ddrphy_dq_t25), + .IO(ddram_dq[25]), + .O(a7ddrphy_dq_i_nodelay25) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_59 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip260[0]), + .D2(a7ddrphy_bitslip260[1]), + .D3(a7ddrphy_bitslip260[2]), + .D4(a7ddrphy_bitslip260[3]), + .D5(a7ddrphy_bitslip260[4]), + .D6(a7ddrphy_bitslip260[5]), + .D7(a7ddrphy_bitslip260[6]), + .D8(a7ddrphy_bitslip260[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay26), + .TQ(a7ddrphy_dq_t26) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_26 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed26), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip261[7]), + .Q2(a7ddrphy_bitslip261[6]), + .Q3(a7ddrphy_bitslip261[5]), + .Q4(a7ddrphy_bitslip261[4]), + .Q5(a7ddrphy_bitslip261[3]), + .Q6(a7ddrphy_bitslip261[2]), + .Q7(a7ddrphy_bitslip261[1]), + .Q8(a7ddrphy_bitslip261[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_26 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay26), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed26) +); + +IOBUF IOBUF_26( + .I(a7ddrphy_dq_o_nodelay26), + .T(a7ddrphy_dq_t26), + .IO(ddram_dq[26]), + .O(a7ddrphy_dq_i_nodelay26) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_60 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip270[0]), + .D2(a7ddrphy_bitslip270[1]), + .D3(a7ddrphy_bitslip270[2]), + .D4(a7ddrphy_bitslip270[3]), + .D5(a7ddrphy_bitslip270[4]), + .D6(a7ddrphy_bitslip270[5]), + .D7(a7ddrphy_bitslip270[6]), + .D8(a7ddrphy_bitslip270[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay27), + .TQ(a7ddrphy_dq_t27) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_27 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed27), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip271[7]), + .Q2(a7ddrphy_bitslip271[6]), + .Q3(a7ddrphy_bitslip271[5]), + .Q4(a7ddrphy_bitslip271[4]), + .Q5(a7ddrphy_bitslip271[3]), + .Q6(a7ddrphy_bitslip271[2]), + .Q7(a7ddrphy_bitslip271[1]), + .Q8(a7ddrphy_bitslip271[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_27 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay27), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed27) +); + +IOBUF IOBUF_27( + .I(a7ddrphy_dq_o_nodelay27), + .T(a7ddrphy_dq_t27), + .IO(ddram_dq[27]), + .O(a7ddrphy_dq_i_nodelay27) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_61 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip280[0]), + .D2(a7ddrphy_bitslip280[1]), + .D3(a7ddrphy_bitslip280[2]), + .D4(a7ddrphy_bitslip280[3]), + .D5(a7ddrphy_bitslip280[4]), + .D6(a7ddrphy_bitslip280[5]), + .D7(a7ddrphy_bitslip280[6]), + .D8(a7ddrphy_bitslip280[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay28), + .TQ(a7ddrphy_dq_t28) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_28 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed28), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip281[7]), + .Q2(a7ddrphy_bitslip281[6]), + .Q3(a7ddrphy_bitslip281[5]), + .Q4(a7ddrphy_bitslip281[4]), + .Q5(a7ddrphy_bitslip281[3]), + .Q6(a7ddrphy_bitslip281[2]), + .Q7(a7ddrphy_bitslip281[1]), + .Q8(a7ddrphy_bitslip281[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_28 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay28), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed28) +); + +IOBUF IOBUF_28( + .I(a7ddrphy_dq_o_nodelay28), + .T(a7ddrphy_dq_t28), + .IO(ddram_dq[28]), + .O(a7ddrphy_dq_i_nodelay28) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_62 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip290[0]), + .D2(a7ddrphy_bitslip290[1]), + .D3(a7ddrphy_bitslip290[2]), + .D4(a7ddrphy_bitslip290[3]), + .D5(a7ddrphy_bitslip290[4]), + .D6(a7ddrphy_bitslip290[5]), + .D7(a7ddrphy_bitslip290[6]), + .D8(a7ddrphy_bitslip290[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay29), + .TQ(a7ddrphy_dq_t29) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_29 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed29), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip291[7]), + .Q2(a7ddrphy_bitslip291[6]), + .Q3(a7ddrphy_bitslip291[5]), + .Q4(a7ddrphy_bitslip291[4]), + .Q5(a7ddrphy_bitslip291[3]), + .Q6(a7ddrphy_bitslip291[2]), + .Q7(a7ddrphy_bitslip291[1]), + .Q8(a7ddrphy_bitslip291[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_29 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay29), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed29) +); + +IOBUF IOBUF_29( + .I(a7ddrphy_dq_o_nodelay29), + .T(a7ddrphy_dq_t29), + .IO(ddram_dq[29]), + .O(a7ddrphy_dq_i_nodelay29) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_63 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip300[0]), + .D2(a7ddrphy_bitslip300[1]), + .D3(a7ddrphy_bitslip300[2]), + .D4(a7ddrphy_bitslip300[3]), + .D5(a7ddrphy_bitslip300[4]), + .D6(a7ddrphy_bitslip300[5]), + .D7(a7ddrphy_bitslip300[6]), + .D8(a7ddrphy_bitslip300[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay30), + .TQ(a7ddrphy_dq_t30) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_30 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed30), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip301[7]), + .Q2(a7ddrphy_bitslip301[6]), + .Q3(a7ddrphy_bitslip301[5]), + .Q4(a7ddrphy_bitslip301[4]), + .Q5(a7ddrphy_bitslip301[3]), + .Q6(a7ddrphy_bitslip301[2]), + .Q7(a7ddrphy_bitslip301[1]), + .Q8(a7ddrphy_bitslip301[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_30 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay30), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed30) +); + +IOBUF IOBUF_30( + .I(a7ddrphy_dq_o_nodelay30), + .T(a7ddrphy_dq_t30), + .IO(ddram_dq[30]), + .O(a7ddrphy_dq_i_nodelay30) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_64 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip310[0]), + .D2(a7ddrphy_bitslip310[1]), + .D3(a7ddrphy_bitslip310[2]), + .D4(a7ddrphy_bitslip310[3]), + .D5(a7ddrphy_bitslip310[4]), + .D6(a7ddrphy_bitslip310[5]), + .D7(a7ddrphy_bitslip310[6]), + .D8(a7ddrphy_bitslip310[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay31), + .TQ(a7ddrphy_dq_t31) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_31 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed31), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip311[7]), + .Q2(a7ddrphy_bitslip311[6]), + .Q3(a7ddrphy_bitslip311[5]), + .Q4(a7ddrphy_bitslip311[4]), + .Q5(a7ddrphy_bitslip311[3]), + .Q6(a7ddrphy_bitslip311[2]), + .Q7(a7ddrphy_bitslip311[1]), + .Q8(a7ddrphy_bitslip311[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_31 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay31), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[3] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed31) +); + +IOBUF IOBUF_31( + .I(a7ddrphy_dq_o_nodelay31), + .T(a7ddrphy_dq_t31), + .IO(ddram_dq[31]), + .O(a7ddrphy_dq_i_nodelay31) +); + +reg [23:0] storage_2[0:7]; +reg [23:0] memdat_5; +always @(posedge sys_clk) begin + if (netv2_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we) + storage_2[netv2_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= netv2_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; + memdat_5 <= storage_2[netv2_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign netv2_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage_2[netv2_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_3[0:7]; +reg [23:0] memdat_6; +always @(posedge sys_clk) begin + if (netv2_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we) + storage_3[netv2_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= netv2_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; + memdat_6 <= storage_3[netv2_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign netv2_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_3[netv2_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_4[0:7]; +reg [23:0] memdat_7; +always @(posedge sys_clk) begin + if (netv2_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we) + storage_4[netv2_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= netv2_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; + memdat_7 <= storage_4[netv2_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign netv2_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_4[netv2_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_5[0:7]; +reg [23:0] memdat_8; +always @(posedge sys_clk) begin + if (netv2_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we) + storage_5[netv2_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= netv2_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; + memdat_8 <= storage_5[netv2_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_8; +assign netv2_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_5[netv2_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_6[0:7]; +reg [23:0] memdat_9; +always @(posedge sys_clk) begin + if (netv2_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we) + storage_6[netv2_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= netv2_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; + memdat_9 <= storage_6[netv2_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_9; +assign netv2_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_6[netv2_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_7[0:7]; +reg [23:0] memdat_10; +always @(posedge sys_clk) begin + if (netv2_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we) + storage_7[netv2_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= netv2_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; + memdat_10 <= storage_7[netv2_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_10; +assign netv2_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_7[netv2_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_8[0:7]; +reg [23:0] memdat_11; +always @(posedge sys_clk) begin + if (netv2_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we) + storage_8[netv2_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= netv2_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; + memdat_11 <= storage_8[netv2_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_11; +assign netv2_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_8[netv2_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_9[0:7]; +reg [23:0] memdat_12; +always @(posedge sys_clk) begin + if (netv2_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we) + storage_9[netv2_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= netv2_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; + memdat_12 <= storage_9[netv2_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_12; +assign netv2_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_9[netv2_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr]; + +reg [31:0] tag_mem[0:3]; +reg [1:0] memadr_2; +always @(posedge sys_clk) begin + if (netv2_tag_port_we) + tag_mem[netv2_tag_port_adr] <= netv2_tag_port_dat_w; + memadr_2 <= netv2_tag_port_adr; +end + +assign netv2_tag_port_dat_r = tag_mem[memadr_2]; + +assign eth_mdio = ethphy_data_oe ? ethphy_data_w : 1'bz; +assign ethphy_data_r = eth_mdio; + +reg [11:0] storage_10[0:4]; +reg [11:0] memdat_13; +always @(posedge eth_rx_clk) begin + if (ethcore_mac_liteethmaccrc32checker_syncfifo_wrport_we) + storage_10[ethcore_mac_liteethmaccrc32checker_syncfifo_wrport_adr] <= ethcore_mac_liteethmaccrc32checker_syncfifo_wrport_dat_w; + memdat_13 <= storage_10[ethcore_mac_liteethmaccrc32checker_syncfifo_wrport_adr]; +end + +always @(posedge eth_rx_clk) begin +end + +assign ethcore_mac_liteethmaccrc32checker_syncfifo_wrport_dat_r = memdat_13; +assign ethcore_mac_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage_10[ethcore_mac_liteethmaccrc32checker_syncfifo_rdport_adr]; + +reg [11:0] storage_11[0:63]; +reg [5:0] memadr_3; +reg [5:0] memadr_4; +always @(posedge sys_clk) begin + if (ethcore_mac_tx_cdc_wrport_we) + storage_11[ethcore_mac_tx_cdc_wrport_adr] <= ethcore_mac_tx_cdc_wrport_dat_w; + memadr_3 <= ethcore_mac_tx_cdc_wrport_adr; +end + +always @(posedge eth_tx_clk) begin + memadr_4 <= ethcore_mac_tx_cdc_rdport_adr; +end + +assign ethcore_mac_tx_cdc_wrport_dat_r = storage_11[memadr_3]; +assign ethcore_mac_tx_cdc_rdport_dat_r = storage_11[memadr_4]; + +reg [11:0] storage_12[0:63]; +reg [5:0] memadr_5; +reg [5:0] memadr_6; +always @(posedge eth_rx_clk) begin + if (ethcore_mac_rx_cdc_wrport_we) + storage_12[ethcore_mac_rx_cdc_wrport_adr] <= ethcore_mac_rx_cdc_wrport_dat_w; + memadr_5 <= ethcore_mac_rx_cdc_wrport_adr; +end + +always @(posedge sys_clk) begin + memadr_6 <= ethcore_mac_rx_cdc_rdport_adr; +end + +assign ethcore_mac_rx_cdc_wrport_dat_r = storage_12[memadr_5]; +assign ethcore_mac_rx_cdc_rdport_dat_r = storage_12[memadr_6]; + +reg [122:0] storage_13[0:127]; +reg [122:0] memdat_14; +reg [122:0] memdat_15; +always @(posedge sys_clk) begin + if (ethcore_icmp_echo_buffer_wrport_we) + storage_13[ethcore_icmp_echo_buffer_wrport_adr] <= ethcore_icmp_echo_buffer_wrport_dat_w; + memdat_14 <= storage_13[ethcore_icmp_echo_buffer_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (ethcore_icmp_echo_buffer_rdport_re) + memdat_15 <= storage_13[ethcore_icmp_echo_buffer_rdport_adr]; +end + +assign ethcore_icmp_echo_buffer_wrport_dat_r = memdat_14; +assign ethcore_icmp_echo_buffer_rdport_dat_r = memdat_15; + +reg [67:0] storage_14[0:3]; +reg [67:0] memdat_16; +reg [67:0] memdat_17; +always @(posedge sys_clk) begin + if (etherbone_record_receiver_fifo_wrport_we) + storage_14[etherbone_record_receiver_fifo_wrport_adr] <= etherbone_record_receiver_fifo_wrport_dat_w; + memdat_16 <= storage_14[etherbone_record_receiver_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (etherbone_record_receiver_fifo_rdport_re) + memdat_17 <= storage_14[etherbone_record_receiver_fifo_rdport_adr]; +end + +assign etherbone_record_receiver_fifo_wrport_dat_r = memdat_16; +assign etherbone_record_receiver_fifo_rdport_dat_r = memdat_17; + +reg [110:0] storage_15[0:3]; +reg [110:0] memdat_18; +reg [110:0] memdat_19; +always @(posedge sys_clk) begin + if (etherbone_record_sender_fifo_wrport_we) + storage_15[etherbone_record_sender_fifo_wrport_adr] <= etherbone_record_sender_fifo_wrport_dat_w; + memdat_18 <= storage_15[etherbone_record_sender_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (etherbone_record_sender_fifo_rdport_re) + memdat_19 <= storage_15[etherbone_record_sender_fifo_rdport_adr]; +end + +assign etherbone_record_sender_fifo_wrport_dat_r = memdat_18; +assign etherbone_record_sender_fifo_rdport_dat_r = memdat_19; + +IBUFDS_GTE2 IBUFDS_GTE2( + .CEB((~s7pciephy_pcie_rst_n)), + .I(pcie_x1_clk_p), + .IB(pcie_x1_clk_n), + .O(s7pciephy_pcie_refclk) +); + +reg [73:0] storage_16[0:3]; +reg [1:0] memadr_7; +reg [1:0] memadr_8; +always @(posedge sys_clk) begin + if (s7pciephy_tx_datapath_cdc_wrport_we) + storage_16[s7pciephy_tx_datapath_cdc_wrport_adr] <= s7pciephy_tx_datapath_cdc_wrport_dat_w; + memadr_7 <= s7pciephy_tx_datapath_cdc_wrport_adr; +end + +always @(posedge pcie_clk) begin + memadr_8 <= s7pciephy_tx_datapath_cdc_rdport_adr; +end + +assign s7pciephy_tx_datapath_cdc_wrport_dat_r = storage_16[memadr_7]; +assign s7pciephy_tx_datapath_cdc_rdport_dat_r = storage_16[memadr_8]; + +reg [73:0] storage_17[0:3]; +reg [1:0] memadr_9; +reg [1:0] memadr_10; +always @(posedge pcie_clk) begin + if (s7pciephy_rx_datapath_cdc_wrport_we) + storage_17[s7pciephy_rx_datapath_cdc_wrport_adr] <= s7pciephy_rx_datapath_cdc_wrport_dat_w; + memadr_9 <= s7pciephy_rx_datapath_cdc_wrport_adr; +end + +always @(posedge sys_clk) begin + memadr_10 <= s7pciephy_rx_datapath_cdc_rdport_adr; +end + +assign s7pciephy_rx_datapath_cdc_wrport_dat_r = storage_17[memadr_9]; +assign s7pciephy_rx_datapath_cdc_rdport_dat_r = storage_17[memadr_10]; + +reg [9:0] storage_18[0:3]; +reg [1:0] memadr_11; +reg [1:0] memadr_12; +always @(posedge sys_clk) begin + if (s7pciephy_msi_cdc_wrport_we) + storage_18[s7pciephy_msi_cdc_wrport_adr] <= s7pciephy_msi_cdc_wrport_dat_w; + memadr_11 <= s7pciephy_msi_cdc_wrport_adr; +end + +always @(posedge pcie_clk) begin + memadr_12 <= s7pciephy_msi_cdc_rdport_adr; +end + +assign s7pciephy_msi_cdc_wrport_dat_r = storage_18[memadr_11]; +assign s7pciephy_msi_cdc_rdport_dat_r = storage_18[memadr_12]; + +reg [65:0] storage_19[0:255]; +reg [65:0] memdat_20; +always @(posedge sys_clk) begin + if (pcie_dma0_writer_fifo_wrport_we0) + storage_19[pcie_dma0_writer_fifo_wrport_adr0] <= pcie_dma0_writer_fifo_wrport_dat_w0; + memdat_20 <= storage_19[pcie_dma0_writer_fifo_wrport_adr0]; +end + +always @(posedge sys_clk) begin +end + +assign pcie_dma0_writer_fifo_wrport_dat_r0 = memdat_20; +assign pcie_dma0_writer_fifo_rdport_dat_r0 = storage_19[pcie_dma0_writer_fifo_rdport_adr0]; + +reg [64:0] storage_20[0:255]; +reg [64:0] memdat_21; +reg [64:0] memdat_22; +always @(posedge sys_clk) begin + if (pcie_dma0_writer_fifo_wrport_we1) + storage_20[pcie_dma0_writer_fifo_wrport_adr1] <= pcie_dma0_writer_fifo_wrport_dat_w1; + memdat_21 <= storage_20[pcie_dma0_writer_fifo_wrport_adr1]; +end + +always @(posedge sys_clk) begin + if (pcie_dma0_writer_fifo_rdport_re) + memdat_22 <= storage_20[pcie_dma0_writer_fifo_rdport_adr1]; +end + +assign pcie_dma0_writer_fifo_wrport_dat_r1 = memdat_21; +assign pcie_dma0_writer_fifo_rdport_dat_r1 = memdat_22; + +reg [65:0] storage_21[0:255]; +reg [65:0] memdat_23; +always @(posedge sys_clk) begin + if (pcie_dma0_reader_fifo_wrport_we0) + storage_21[pcie_dma0_reader_fifo_wrport_adr0] <= pcie_dma0_reader_fifo_wrport_dat_w0; + memdat_23 <= storage_21[pcie_dma0_reader_fifo_wrport_adr0]; +end + +always @(posedge sys_clk) begin +end + +assign pcie_dma0_reader_fifo_wrport_dat_r0 = memdat_23; +assign pcie_dma0_reader_fifo_rdport_dat_r0 = storage_21[pcie_dma0_reader_fifo_rdport_adr0]; + +reg [65:0] storage_22[0:1023]; +reg [65:0] memdat_24; +reg [65:0] memdat_25; +always @(posedge sys_clk) begin + if (pcie_dma0_reader_fifo_wrport_we1) + storage_22[pcie_dma0_reader_fifo_wrport_adr1] <= pcie_dma0_reader_fifo_wrport_dat_w1; + memdat_24 <= storage_22[pcie_dma0_reader_fifo_wrport_adr1]; +end + +always @(posedge sys_clk) begin + if (pcie_dma0_reader_fifo_rdport_re) + memdat_25 <= storage_22[pcie_dma0_reader_fifo_rdport_adr1]; +end + +assign pcie_dma0_reader_fifo_wrport_dat_r1 = memdat_24; +assign pcie_dma0_reader_fifo_rdport_dat_r1 = memdat_25; + +reg [65:0] storage_23[0:127]; +reg [65:0] memdat_26; +reg [65:0] memdat_27; +always @(posedge sys_clk) begin + if (pcie_dma0_buffering_reader_fifo_wrport_we) + storage_23[pcie_dma0_buffering_reader_fifo_wrport_adr] <= pcie_dma0_buffering_reader_fifo_wrport_dat_w; + memdat_26 <= storage_23[pcie_dma0_buffering_reader_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (pcie_dma0_buffering_reader_fifo_rdport_re) + memdat_27 <= storage_23[pcie_dma0_buffering_reader_fifo_rdport_adr]; +end + +assign pcie_dma0_buffering_reader_fifo_wrport_dat_r = memdat_26; +assign pcie_dma0_buffering_reader_fifo_rdport_dat_r = memdat_27; + +reg [65:0] storage_24[0:127]; +reg [65:0] memdat_28; +reg [65:0] memdat_29; +always @(posedge sys_clk) begin + if (pcie_dma0_buffering_writer_fifo_wrport_we) + storage_24[pcie_dma0_buffering_writer_fifo_wrport_adr] <= pcie_dma0_buffering_writer_fifo_wrport_dat_w; + memdat_28 <= storage_24[pcie_dma0_buffering_writer_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (pcie_dma0_buffering_writer_fifo_rdport_re) + memdat_29 <= storage_24[pcie_dma0_buffering_writer_fifo_rdport_adr]; +end + +assign pcie_dma0_buffering_writer_fifo_wrport_dat_r = memdat_28; +assign pcie_dma0_buffering_writer_fifo_rdport_dat_r = memdat_29; + +reg [65:0] storage_25[0:255]; +reg [65:0] memdat_30; +always @(posedge sys_clk) begin + if (pcie_dma1_writer_fifo_wrport_we0) + storage_25[pcie_dma1_writer_fifo_wrport_adr0] <= pcie_dma1_writer_fifo_wrport_dat_w0; + memdat_30 <= storage_25[pcie_dma1_writer_fifo_wrport_adr0]; +end + +always @(posedge sys_clk) begin +end + +assign pcie_dma1_writer_fifo_wrport_dat_r0 = memdat_30; +assign pcie_dma1_writer_fifo_rdport_dat_r0 = storage_25[pcie_dma1_writer_fifo_rdport_adr0]; + +reg [64:0] storage_26[0:255]; +reg [64:0] memdat_31; +reg [64:0] memdat_32; +always @(posedge sys_clk) begin + if (pcie_dma1_writer_fifo_wrport_we1) + storage_26[pcie_dma1_writer_fifo_wrport_adr1] <= pcie_dma1_writer_fifo_wrport_dat_w1; + memdat_31 <= storage_26[pcie_dma1_writer_fifo_wrport_adr1]; +end + +always @(posedge sys_clk) begin + if (pcie_dma1_writer_fifo_rdport_re) + memdat_32 <= storage_26[pcie_dma1_writer_fifo_rdport_adr1]; +end + +assign pcie_dma1_writer_fifo_wrport_dat_r1 = memdat_31; +assign pcie_dma1_writer_fifo_rdport_dat_r1 = memdat_32; + +reg [65:0] storage_27[0:255]; +reg [65:0] memdat_33; +always @(posedge sys_clk) begin + if (pcie_dma1_reader_fifo_wrport_we0) + storage_27[pcie_dma1_reader_fifo_wrport_adr0] <= pcie_dma1_reader_fifo_wrport_dat_w0; + memdat_33 <= storage_27[pcie_dma1_reader_fifo_wrport_adr0]; +end + +always @(posedge sys_clk) begin +end + +assign pcie_dma1_reader_fifo_wrport_dat_r0 = memdat_33; +assign pcie_dma1_reader_fifo_rdport_dat_r0 = storage_27[pcie_dma1_reader_fifo_rdport_adr0]; + +reg [65:0] storage_28[0:1023]; +reg [65:0] memdat_34; +reg [65:0] memdat_35; +always @(posedge sys_clk) begin + if (pcie_dma1_reader_fifo_wrport_we1) + storage_28[pcie_dma1_reader_fifo_wrport_adr1] <= pcie_dma1_reader_fifo_wrport_dat_w1; + memdat_34 <= storage_28[pcie_dma1_reader_fifo_wrport_adr1]; +end + +always @(posedge sys_clk) begin + if (pcie_dma1_reader_fifo_rdport_re) + memdat_35 <= storage_28[pcie_dma1_reader_fifo_rdport_adr1]; +end + +assign pcie_dma1_reader_fifo_wrport_dat_r1 = memdat_34; +assign pcie_dma1_reader_fifo_rdport_dat_r1 = memdat_35; + +reg [65:0] storage_29[0:127]; +reg [65:0] memdat_36; +reg [65:0] memdat_37; +always @(posedge sys_clk) begin + if (pcie_dma1_buffering_reader_fifo_wrport_we) + storage_29[pcie_dma1_buffering_reader_fifo_wrport_adr] <= pcie_dma1_buffering_reader_fifo_wrport_dat_w; + memdat_36 <= storage_29[pcie_dma1_buffering_reader_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (pcie_dma1_buffering_reader_fifo_rdport_re) + memdat_37 <= storage_29[pcie_dma1_buffering_reader_fifo_rdport_adr]; +end + +assign pcie_dma1_buffering_reader_fifo_wrport_dat_r = memdat_36; +assign pcie_dma1_buffering_reader_fifo_rdport_dat_r = memdat_37; + +reg [65:0] storage_30[0:127]; +reg [65:0] memdat_38; +reg [65:0] memdat_39; +always @(posedge sys_clk) begin + if (pcie_dma1_buffering_writer_fifo_wrport_we) + storage_30[pcie_dma1_buffering_writer_fifo_wrport_adr] <= pcie_dma1_buffering_writer_fifo_wrport_dat_w; + memdat_38 <= storage_30[pcie_dma1_buffering_writer_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (pcie_dma1_buffering_writer_fifo_rdport_re) + memdat_39 <= storage_30[pcie_dma1_buffering_writer_fifo_rdport_adr]; +end + +assign pcie_dma1_buffering_writer_fifo_wrport_dat_r = memdat_38; +assign pcie_dma1_buffering_writer_fifo_rdport_dat_r = memdat_39; + +reg [7:0] edid_mem[0:255]; +reg [7:0] memadr_13; +reg [7:0] memadr_14; +always @(posedge sys_clk) begin + memadr_13 <= hdmi_in0_adr; +end + +always @(posedge sys_clk) begin + if (sram0_we) + edid_mem[sram0_adr] <= sram0_dat_w; + memadr_14 <= sram0_adr; +end + +assign hdmi_in0_dat_r = edid_mem[memadr_13]; +assign sram0_dat_r = edid_mem[memadr_14]; + +initial begin + $readmemh("edid_mem.init", edid_mem); +end + +IBUFDS_DIFF_OUT hdmi_in_ibufds( + .I(hdmi_in0_clk_p), + .IB(hdmi_in0_clk_n), + .OB(hdmi_in0_clk_input) +); + +BUFR BUFR( + .I(hdmi_in0_clk_input), + .O(hdmi_in0_clk_input_bufr) +); + +MMCME2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT_F(5.0), + .CLKFBOUT_PHASE(0.0), + .CLKIN1_PERIOD(6.734), + .CLKOUT0_DIVIDE_F(3'd5), + .CLKOUT0_PHASE(0.0), + .CLKOUT1_DIVIDE(3'd4), + .CLKOUT1_PHASE(0.0), + .CLKOUT2_DIVIDE(1'd1), + .CLKOUT2_PHASE(0.0), + .DIVCLK_DIVIDE(1'd1), + .REF_JITTER1(0.01) +) MMCME2_ADV ( + .CLKFBIN(hdmi_in0_mmcm_fb_o), + .CLKIN1(hdmi_in0_clk_input_bufr), + .DADDR(hdmi_in0_mmcm_adr_storage), + .DCLK(sys_clk), + .DEN((hdmi_in0_mmcm_read_re | hdmi_in0_mmcm_write_re)), + .DI(hdmi_in0_mmcm_dat_w_storage), + .DWE(hdmi_in0_mmcm_write_re), + .RST(hdmi_in0_mmcm_reset_storage), + .CLKFBOUT(hdmi_in0_mmcm_fb), + .CLKOUT0(hdmi_in0_mmcm_clk0), + .CLKOUT1(hdmi_in0_mmcm_clk1), + .CLKOUT2(hdmi_in0_mmcm_clk2), + .DO(hdmi_in0_mmcm_dat_r_status), + .DRDY(hdmi_in0_mmcm_drdy), + .LOCKED(hdmi_in0_mmcm_locked) +); + +BUFG BUFG_6( + .I(hdmi_in0_mmcm_clk0), + .O(hdmi_in0_pix_clk) +); + +BUFG BUFG_7( + .I(hdmi_in0_mmcm_clk1), + .O(pix1p25x_clk) +); + +BUFG BUFG_8( + .I(hdmi_in0_mmcm_clk2), + .O(hdmi_in0_pix5x_clk) +); + +BUFG BUFG_9( + .I(hdmi_in0_mmcm_fb), + .O(hdmi_in0_mmcm_fb_o) +); + +PLLE2_ADV #( + .BANDWIDTH("LOW"), + .CLKFBOUT_MULT(4'd10), + .CLKFBOUT_PHASE(0.0), + .CLKIN1_PERIOD(6.734), + .CLKOUT0_DIVIDE(4'd10), + .CLKOUT0_PHASE(0.0), + .CLKOUT2_DIVIDE(2'd2), + .CLKOUT2_PHASE(0.0), + .DIVCLK_DIVIDE(1'd1), + .REF_JITTER1(0.01) +) PLLE2_ADV ( + .CLKFBIN(hdmi_in0_mmcm_fb2_o), + .CLKIN1(hdmi_in0_mmcm_clk0), + .DADDR(hdmi_in0_mmcm_adr_storage), + .DCLK(sys_clk), + .DEN((hdmi_in0_mmcm_read_o_re | hdmi_in0_mmcm_write_o_re)), + .DI(hdmi_in0_mmcm_dat_w_storage), + .DWE(hdmi_in0_mmcm_write_o_re), + .RST(hdmi_in0_mmcm_reset_storage), + .CLKFBOUT(hdmi_in0_mmcm_fb2_o), + .CLKOUT0(hdmi_in0_mmcm_clk0_o), + .CLKOUT2(hdmi_in0_mmcm_clk2_o), + .DO(hdmi_in0_mmcm_dat_o_r_status), + .DRDY(hdmi_in0_mmcm_drdy_o), + .LOCKED(hdmi_in0_mmcm_locked_o) +); + +BUFG BUFG_10( + .I(hdmi_in0_mmcm_clk0_o), + .O(pix_o_clk) +); + +BUFG BUFG_11( + .I(hdmi_in0_mmcm_clk2_o), + .O(pix5x_o_clk) +); + +IBUFDS_DIFF_OUT IBUFDS_DIFF_OUT( + .I(hdmi_in0_data0_p), + .IB(hdmi_in0_data0_n), + .O(hdmi_in0_s7datacapture0_serdes_m_i_nodelay), + .OB(hdmi_in0_s7datacapture0_serdes_s_i_nodelay) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_32 ( + .C(pix1p25x_clk), + .CE(hdmi_in0_s7datacapture0_delay_master_ce), + .IDATAIN(hdmi_in0_s7datacapture0_serdes_m_i_nodelay), + .INC(hdmi_in0_s7datacapture0_delay_master_inc), + .LD(hdmi_in0_s7datacapture0_delay_rst), + .LDPIPEEN(1'd0), + .CNTVALUEOUT(hdmi_in0_s7datacapture0_serdes_m_cntvalue), + .DATAOUT(hdmi_in0_s7datacapture0_serdes_m_i_delayed) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_32 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(hdmi_in0_pix5x_clk), + .CLKB((~hdmi_in0_pix5x_clk)), + .CLKDIV(pix1p25x_clk), + .DDLY(hdmi_in0_s7datacapture0_serdes_m_i_delayed), + .RST(pix1p25x_rst), + .Q1(hdmi_in0_s7datacapture0_serdes_m_q[7]), + .Q2(hdmi_in0_s7datacapture0_serdes_m_q[6]), + .Q3(hdmi_in0_s7datacapture0_serdes_m_q[5]), + .Q4(hdmi_in0_s7datacapture0_serdes_m_q[4]), + .Q5(hdmi_in0_s7datacapture0_serdes_m_q[3]), + .Q6(hdmi_in0_s7datacapture0_serdes_m_q[2]), + .Q7(hdmi_in0_s7datacapture0_serdes_m_q[1]), + .Q8(hdmi_in0_s7datacapture0_serdes_m_q[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_33 ( + .C(pix1p25x_clk), + .CE(hdmi_in0_s7datacapture0_delay_slave_ce), + .IDATAIN(hdmi_in0_s7datacapture0_serdes_s_i_nodelay), + .INC(hdmi_in0_s7datacapture0_delay_slave_inc), + .LD(hdmi_in0_s7datacapture0_delay_rst), + .LDPIPEEN(1'd0), + .CNTVALUEOUT(hdmi_in0_s7datacapture0_serdes_s_cntvalue), + .DATAOUT(hdmi_in0_s7datacapture0_serdes_s_i_delayed) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_33 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(hdmi_in0_pix5x_clk), + .CLKB((~hdmi_in0_pix5x_clk)), + .CLKDIV(pix1p25x_clk), + .DDLY(hdmi_in0_s7datacapture0_serdes_s_i_delayed), + .RST(pix1p25x_rst), + .Q1(hdmi_in0_s7datacapture0_serdes_s_q[7]), + .Q2(hdmi_in0_s7datacapture0_serdes_s_q[6]), + .Q3(hdmi_in0_s7datacapture0_serdes_s_q[5]), + .Q4(hdmi_in0_s7datacapture0_serdes_s_q[4]), + .Q5(hdmi_in0_s7datacapture0_serdes_s_q[3]), + .Q6(hdmi_in0_s7datacapture0_serdes_s_q[2]), + .Q7(hdmi_in0_s7datacapture0_serdes_s_q[1]), + .Q8(hdmi_in0_s7datacapture0_serdes_s_q[0]) +); + +IBUFDS_DIFF_OUT IBUFDS_DIFF_OUT_1( + .I(hdmi_in0_data1_p), + .IB(hdmi_in0_data1_n), + .O(hdmi_in0_s7datacapture1_serdes_m_i_nodelay), + .OB(hdmi_in0_s7datacapture1_serdes_s_i_nodelay) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_34 ( + .C(pix1p25x_clk), + .CE(hdmi_in0_s7datacapture1_delay_master_ce), + .IDATAIN(hdmi_in0_s7datacapture1_serdes_m_i_nodelay), + .INC(hdmi_in0_s7datacapture1_delay_master_inc), + .LD(hdmi_in0_s7datacapture1_delay_rst), + .LDPIPEEN(1'd0), + .CNTVALUEOUT(hdmi_in0_s7datacapture1_serdes_m_cntvalue), + .DATAOUT(hdmi_in0_s7datacapture1_serdes_m_i_delayed) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_34 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(hdmi_in0_pix5x_clk), + .CLKB((~hdmi_in0_pix5x_clk)), + .CLKDIV(pix1p25x_clk), + .DDLY(hdmi_in0_s7datacapture1_serdes_m_i_delayed), + .RST(pix1p25x_rst), + .Q1(hdmi_in0_s7datacapture1_serdes_m_q[7]), + .Q2(hdmi_in0_s7datacapture1_serdes_m_q[6]), + .Q3(hdmi_in0_s7datacapture1_serdes_m_q[5]), + .Q4(hdmi_in0_s7datacapture1_serdes_m_q[4]), + .Q5(hdmi_in0_s7datacapture1_serdes_m_q[3]), + .Q6(hdmi_in0_s7datacapture1_serdes_m_q[2]), + .Q7(hdmi_in0_s7datacapture1_serdes_m_q[1]), + .Q8(hdmi_in0_s7datacapture1_serdes_m_q[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_35 ( + .C(pix1p25x_clk), + .CE(hdmi_in0_s7datacapture1_delay_slave_ce), + .IDATAIN(hdmi_in0_s7datacapture1_serdes_s_i_nodelay), + .INC(hdmi_in0_s7datacapture1_delay_slave_inc), + .LD(hdmi_in0_s7datacapture1_delay_rst), + .LDPIPEEN(1'd0), + .CNTVALUEOUT(hdmi_in0_s7datacapture1_serdes_s_cntvalue), + .DATAOUT(hdmi_in0_s7datacapture1_serdes_s_i_delayed) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_35 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(hdmi_in0_pix5x_clk), + .CLKB((~hdmi_in0_pix5x_clk)), + .CLKDIV(pix1p25x_clk), + .DDLY(hdmi_in0_s7datacapture1_serdes_s_i_delayed), + .RST(pix1p25x_rst), + .Q1(hdmi_in0_s7datacapture1_serdes_s_q[7]), + .Q2(hdmi_in0_s7datacapture1_serdes_s_q[6]), + .Q3(hdmi_in0_s7datacapture1_serdes_s_q[5]), + .Q4(hdmi_in0_s7datacapture1_serdes_s_q[4]), + .Q5(hdmi_in0_s7datacapture1_serdes_s_q[3]), + .Q6(hdmi_in0_s7datacapture1_serdes_s_q[2]), + .Q7(hdmi_in0_s7datacapture1_serdes_s_q[1]), + .Q8(hdmi_in0_s7datacapture1_serdes_s_q[0]) +); + +IBUFDS_DIFF_OUT IBUFDS_DIFF_OUT_2( + .I(hdmi_in0_data2_p), + .IB(hdmi_in0_data2_n), + .O(hdmi_in0_s7datacapture2_serdes_m_i_nodelay), + .OB(hdmi_in0_s7datacapture2_serdes_s_i_nodelay) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_36 ( + .C(pix1p25x_clk), + .CE(hdmi_in0_s7datacapture2_delay_master_ce), + .IDATAIN(hdmi_in0_s7datacapture2_serdes_m_i_nodelay), + .INC(hdmi_in0_s7datacapture2_delay_master_inc), + .LD(hdmi_in0_s7datacapture2_delay_rst), + .LDPIPEEN(1'd0), + .CNTVALUEOUT(hdmi_in0_s7datacapture2_serdes_m_cntvalue), + .DATAOUT(hdmi_in0_s7datacapture2_serdes_m_i_delayed) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_36 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(hdmi_in0_pix5x_clk), + .CLKB((~hdmi_in0_pix5x_clk)), + .CLKDIV(pix1p25x_clk), + .DDLY(hdmi_in0_s7datacapture2_serdes_m_i_delayed), + .RST(pix1p25x_rst), + .Q1(hdmi_in0_s7datacapture2_serdes_m_q[7]), + .Q2(hdmi_in0_s7datacapture2_serdes_m_q[6]), + .Q3(hdmi_in0_s7datacapture2_serdes_m_q[5]), + .Q4(hdmi_in0_s7datacapture2_serdes_m_q[4]), + .Q5(hdmi_in0_s7datacapture2_serdes_m_q[3]), + .Q6(hdmi_in0_s7datacapture2_serdes_m_q[2]), + .Q7(hdmi_in0_s7datacapture2_serdes_m_q[1]), + .Q8(hdmi_in0_s7datacapture2_serdes_m_q[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_37 ( + .C(pix1p25x_clk), + .CE(hdmi_in0_s7datacapture2_delay_slave_ce), + .IDATAIN(hdmi_in0_s7datacapture2_serdes_s_i_nodelay), + .INC(hdmi_in0_s7datacapture2_delay_slave_inc), + .LD(hdmi_in0_s7datacapture2_delay_rst), + .LDPIPEEN(1'd0), + .CNTVALUEOUT(hdmi_in0_s7datacapture2_serdes_s_cntvalue), + .DATAOUT(hdmi_in0_s7datacapture2_serdes_s_i_delayed) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_37 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(hdmi_in0_pix5x_clk), + .CLKB((~hdmi_in0_pix5x_clk)), + .CLKDIV(pix1p25x_clk), + .DDLY(hdmi_in0_s7datacapture2_serdes_s_i_delayed), + .RST(pix1p25x_rst), + .Q1(hdmi_in0_s7datacapture2_serdes_s_q[7]), + .Q2(hdmi_in0_s7datacapture2_serdes_s_q[6]), + .Q3(hdmi_in0_s7datacapture2_serdes_s_q[5]), + .Q4(hdmi_in0_s7datacapture2_serdes_s_q[4]), + .Q5(hdmi_in0_s7datacapture2_serdes_s_q[3]), + .Q6(hdmi_in0_s7datacapture2_serdes_s_q[2]), + .Q7(hdmi_in0_s7datacapture2_serdes_s_q[1]), + .Q8(hdmi_in0_s7datacapture2_serdes_s_q[0]) +); + +reg [20:0] storage_31[0:7]; +reg [2:0] memadr_15; +always @(posedge hdmi_in0_pix_clk) begin + if (hdmi_in0_chansync_syncbuffer0_wrport_we) + storage_31[hdmi_in0_chansync_syncbuffer0_wrport_adr] <= hdmi_in0_chansync_syncbuffer0_wrport_dat_w; + memadr_15 <= hdmi_in0_chansync_syncbuffer0_wrport_adr; +end + +always @(posedge hdmi_in0_pix_clk) begin +end + +assign hdmi_in0_chansync_syncbuffer0_wrport_dat_r = storage_31[memadr_15]; +assign hdmi_in0_chansync_syncbuffer0_rdport_dat_r = storage_31[hdmi_in0_chansync_syncbuffer0_rdport_adr]; + +reg [20:0] storage_32[0:7]; +reg [2:0] memadr_16; +always @(posedge hdmi_in0_pix_clk) begin + if (hdmi_in0_chansync_syncbuffer1_wrport_we) + storage_32[hdmi_in0_chansync_syncbuffer1_wrport_adr] <= hdmi_in0_chansync_syncbuffer1_wrport_dat_w; + memadr_16 <= hdmi_in0_chansync_syncbuffer1_wrport_adr; +end + +always @(posedge hdmi_in0_pix_clk) begin +end + +assign hdmi_in0_chansync_syncbuffer1_wrport_dat_r = storage_32[memadr_16]; +assign hdmi_in0_chansync_syncbuffer1_rdport_dat_r = storage_32[hdmi_in0_chansync_syncbuffer1_rdport_adr]; + +reg [20:0] storage_33[0:7]; +reg [2:0] memadr_17; +always @(posedge hdmi_in0_pix_clk) begin + if (hdmi_in0_chansync_syncbuffer2_wrport_we) + storage_33[hdmi_in0_chansync_syncbuffer2_wrport_adr] <= hdmi_in0_chansync_syncbuffer2_wrport_dat_w; + memadr_17 <= hdmi_in0_chansync_syncbuffer2_wrport_adr; +end + +always @(posedge hdmi_in0_pix_clk) begin +end + +assign hdmi_in0_chansync_syncbuffer2_wrport_dat_r = storage_33[memadr_17]; +assign hdmi_in0_chansync_syncbuffer2_rdport_dat_r = storage_33[hdmi_in0_chansync_syncbuffer2_rdport_adr]; + +reg [258:0] storage_34[0:511]; +reg [8:0] memadr_18; +reg [8:0] memadr_19; +always @(posedge hdmi_in0_pix_clk) begin + if (hdmi_in0_frame_fifo_wrport_we) + storage_34[hdmi_in0_frame_fifo_wrport_adr] <= hdmi_in0_frame_fifo_wrport_dat_w; + memadr_18 <= hdmi_in0_frame_fifo_wrport_adr; +end + +always @(posedge sys_clk) begin + memadr_19 <= hdmi_in0_frame_fifo_rdport_adr; +end + +assign hdmi_in0_frame_fifo_wrport_dat_r = storage_34[memadr_18]; +assign hdmi_in0_frame_fifo_rdport_dat_r = storage_34[memadr_19]; + +reg [257:0] storage_35[0:15]; +reg [257:0] memdat_40; +always @(posedge sys_clk) begin + if (hdmi_in0_dma_fifo_wrport_we) + storage_35[hdmi_in0_dma_fifo_wrport_adr] <= hdmi_in0_dma_fifo_wrport_dat_w; + memdat_40 <= storage_35[hdmi_in0_dma_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign hdmi_in0_dma_fifo_wrport_dat_r = memdat_40; +assign hdmi_in0_dma_fifo_rdport_dat_r = storage_35[hdmi_in0_dma_fifo_rdport_adr]; + +reg [26:0] storage_36[0:3]; +reg [1:0] memadr_20; +reg [1:0] memadr_21; +always @(posedge hdmi_out0_pix_clk) begin + if (litedramcrossbar_cmd_cdc_cdc_wrport_we) + storage_36[litedramcrossbar_cmd_cdc_cdc_wrport_adr] <= litedramcrossbar_cmd_cdc_cdc_wrport_dat_w; + memadr_20 <= litedramcrossbar_cmd_cdc_cdc_wrport_adr; +end + +always @(posedge sys_clk) begin + memadr_21 <= litedramcrossbar_cmd_cdc_cdc_rdport_adr; +end + +assign litedramcrossbar_cmd_cdc_cdc_wrport_dat_r = storage_36[memadr_20]; +assign litedramcrossbar_cmd_cdc_cdc_rdport_dat_r = storage_36[memadr_21]; + +reg [257:0] storage_37[0:15]; +reg [3:0] memadr_22; +reg [3:0] memadr_23; +always @(posedge sys_clk) begin + if (litedramcrossbar_rdata_cdc_cdc_wrport_we) + storage_37[litedramcrossbar_rdata_cdc_cdc_wrport_adr] <= litedramcrossbar_rdata_cdc_cdc_wrport_dat_w; + memadr_22 <= litedramcrossbar_rdata_cdc_cdc_wrport_adr; +end + +always @(posedge hdmi_out0_pix_clk) begin + memadr_23 <= litedramcrossbar_rdata_cdc_cdc_rdport_adr; +end + +assign litedramcrossbar_rdata_cdc_cdc_wrport_dat_r = storage_37[memadr_22]; +assign litedramcrossbar_rdata_cdc_cdc_rdport_dat_r = storage_37[memadr_23]; + +reg [257:0] storage_38[0:14]; +reg [257:0] memdat_41; +always @(posedge hdmi_out0_pix_clk) begin + if (litedramcrossbar_rdata_fifo_wrport_we) + storage_38[litedramcrossbar_rdata_fifo_wrport_adr] <= litedramcrossbar_rdata_fifo_wrport_dat_w; + memdat_41 <= storage_38[litedramcrossbar_rdata_fifo_wrport_adr]; +end + +always @(posedge hdmi_out0_pix_clk) begin +end + +assign litedramcrossbar_rdata_fifo_wrport_dat_r = memdat_41; +assign litedramcrossbar_rdata_fifo_rdport_dat_r = storage_38[litedramcrossbar_rdata_fifo_rdport_adr]; + +reg [161:0] storage_39[0:3]; +reg [1:0] memadr_24; +reg [1:0] memadr_25; +always @(posedge sys_clk) begin + if (hdmi_out0_core_initiator_cdc_wrport_we) + storage_39[hdmi_out0_core_initiator_cdc_wrport_adr] <= hdmi_out0_core_initiator_cdc_wrport_dat_w; + memadr_24 <= hdmi_out0_core_initiator_cdc_wrport_adr; +end + +always @(posedge hdmi_out0_pix_clk) begin + memadr_25 <= hdmi_out0_core_initiator_cdc_rdport_adr; +end + +assign hdmi_out0_core_initiator_cdc_wrport_dat_r = storage_39[memadr_24]; +assign hdmi_out0_core_initiator_cdc_rdport_dat_r = storage_39[memadr_25]; + +reg [17:0] storage_40[0:511]; +reg [17:0] memdat_42; +reg [17:0] memdat_43; +always @(posedge hdmi_out0_pix_clk) begin + if (hdmi_out0_core_dmareader_fifo_wrport_we) + storage_40[hdmi_out0_core_dmareader_fifo_wrport_adr] <= hdmi_out0_core_dmareader_fifo_wrport_dat_w; + memdat_42 <= storage_40[hdmi_out0_core_dmareader_fifo_wrport_adr]; +end + +always @(posedge hdmi_out0_pix_clk) begin + if (hdmi_out0_core_dmareader_fifo_rdport_re) + memdat_43 <= storage_40[hdmi_out0_core_dmareader_fifo_rdport_adr]; +end + +assign hdmi_out0_core_dmareader_fifo_wrport_dat_r = memdat_42; +assign hdmi_out0_core_dmareader_fifo_rdport_dat_r = memdat_43; + +MMCME2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT_F(30.0), + .CLKFBOUT_PHASE(0.0), + .CLKIN1_PERIOD(10.0), + .CLKOUT0_DIVIDE_F(10.0), + .CLKOUT0_PHASE(0.0), + .CLKOUT1_DIVIDE(2'd2), + .CLKOUT1_PHASE(0.0), + .DIVCLK_DIVIDE(2'd2), + .REF_JITTER1(0.01) +) MMCME2_ADV_1 ( + .CLKFBIN(hdmi_out0_driver_s7hdmioutclocking_mmcm_fb), + .CLKIN1(clk100_clk), + .DADDR(hdmi_out0_driver_s7hdmioutclocking_mmcm_adr_storage), + .DCLK(sys_clk), + .DEN((hdmi_out0_driver_s7hdmioutclocking_mmcm_read_re | hdmi_out0_driver_s7hdmioutclocking_mmcm_write_re)), + .DI(hdmi_out0_driver_s7hdmioutclocking_mmcm_dat_w_storage), + .DWE(hdmi_out0_driver_s7hdmioutclocking_mmcm_write_re), + .RST(hdmi_out0_driver_s7hdmioutclocking_mmcm_reset_storage), + .CLKFBOUT(hdmi_out0_driver_s7hdmioutclocking_mmcm_fb), + .CLKOUT0(hdmi_out0_driver_s7hdmioutclocking_mmcm_clk0), + .CLKOUT1(hdmi_out0_driver_s7hdmioutclocking_mmcm_clk1), + .DO(hdmi_out0_driver_s7hdmioutclocking_mmcm_dat_r_status), + .DRDY(hdmi_out0_driver_s7hdmioutclocking_mmcm_drdy), + .LOCKED(hdmi_out0_driver_s7hdmioutclocking_mmcm_locked) +); + +BUFG BUFG_12( + .I(hdmi_out0_driver_s7hdmioutclocking_mmcm_clk0), + .O(hdmi_out0_pix_clk) +); + +BUFG BUFG_13( + .I(hdmi_out0_driver_s7hdmioutclocking_mmcm_clk1), + .O(hdmi_out0_pix5x_clk) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("DDR"), + .DATA_WIDTH(4'd10), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_65 ( + .CLK(hdmi_out0_pix5x_clk), + .CLKDIV(hdmi_out0_pix_clk), + .D1(hdmi_out0_driver_s7hdmioutclocking_data1[0]), + .D2(hdmi_out0_driver_s7hdmioutclocking_data1[1]), + .D3(hdmi_out0_driver_s7hdmioutclocking_data1[2]), + .D4(hdmi_out0_driver_s7hdmioutclocking_data1[3]), + .D5(hdmi_out0_driver_s7hdmioutclocking_data1[4]), + .D6(hdmi_out0_driver_s7hdmioutclocking_data1[5]), + .D7(hdmi_out0_driver_s7hdmioutclocking_data1[6]), + .D8(hdmi_out0_driver_s7hdmioutclocking_data1[7]), + .OCE(hdmi_out0_driver_s7hdmioutclocking_ce), + .RST(hdmi_out0_pix_rst), + .SHIFTIN1(hdmi_out0_driver_s7hdmioutclocking_shift[0]), + .SHIFTIN2(hdmi_out0_driver_s7hdmioutclocking_shift[1]), + .TCE(1'd0), + .OQ(hdmi_out0_driver_s7hdmioutclocking_pad_se) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("DDR"), + .DATA_WIDTH(4'd10), + .SERDES_MODE("SLAVE"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_66 ( + .CLK(hdmi_out0_pix5x_clk), + .CLKDIV(hdmi_out0_pix_clk), + .D1(1'd0), + .D2(1'd0), + .D3(hdmi_out0_driver_s7hdmioutclocking_data1[8]), + .D4(hdmi_out0_driver_s7hdmioutclocking_data1[9]), + .D5(1'd0), + .D6(1'd0), + .D7(1'd0), + .D8(1'd0), + .OCE(hdmi_out0_driver_s7hdmioutclocking_ce), + .RST(hdmi_out0_pix_rst), + .SHIFTIN1(1'd0), + .SHIFTIN2(1'd0), + .TCE(1'd0), + .SHIFTOUT1(hdmi_out0_driver_s7hdmioutclocking_shift[0]), + .SHIFTOUT2(hdmi_out0_driver_s7hdmioutclocking_shift[1]) +); + +OBUFDS OBUFDS_1( + .I(hdmi_out0_driver_s7hdmioutclocking_pad_se), + .O(hdmi_out0_clk_p), + .OB(hdmi_out0_clk_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("DDR"), + .DATA_WIDTH(4'd10), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_67 ( + .CLK(hdmi_out0_pix5x_clk), + .CLKDIV(hdmi_out0_pix_clk), + .D1(hdmi_out0_driver_hdmi_phy_es0_data[0]), + .D2(hdmi_out0_driver_hdmi_phy_es0_data[1]), + .D3(hdmi_out0_driver_hdmi_phy_es0_data[2]), + .D4(hdmi_out0_driver_hdmi_phy_es0_data[3]), + .D5(hdmi_out0_driver_hdmi_phy_es0_data[4]), + .D6(hdmi_out0_driver_hdmi_phy_es0_data[5]), + .D7(hdmi_out0_driver_hdmi_phy_es0_data[6]), + .D8(hdmi_out0_driver_hdmi_phy_es0_data[7]), + .OCE(hdmi_out0_driver_hdmi_phy_es0_ce), + .RST(hdmi_out0_pix_rst), + .SHIFTIN1(hdmi_out0_driver_hdmi_phy_es0_shift[0]), + .SHIFTIN2(hdmi_out0_driver_hdmi_phy_es0_shift[1]), + .TCE(1'd0), + .OQ(hdmi_out0_driver_hdmi_phy_es0_pad_se) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("DDR"), + .DATA_WIDTH(4'd10), + .SERDES_MODE("SLAVE"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_68 ( + .CLK(hdmi_out0_pix5x_clk), + .CLKDIV(hdmi_out0_pix_clk), + .D1(1'd0), + .D2(1'd0), + .D3(hdmi_out0_driver_hdmi_phy_es0_data[8]), + .D4(hdmi_out0_driver_hdmi_phy_es0_data[9]), + .D5(1'd0), + .D6(1'd0), + .D7(1'd0), + .D8(1'd0), + .OCE(hdmi_out0_driver_hdmi_phy_es0_ce), + .RST(hdmi_out0_pix_rst), + .SHIFTIN1(1'd0), + .SHIFTIN2(1'd0), + .TCE(1'd0), + .SHIFTOUT1(hdmi_out0_driver_hdmi_phy_es0_shift[0]), + .SHIFTOUT2(hdmi_out0_driver_hdmi_phy_es0_shift[1]) +); + +OBUFDS OBUFDS_2( + .I(hdmi_out0_driver_hdmi_phy_es0_pad_se), + .O(hdmi_out0_data0_p), + .OB(hdmi_out0_data0_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("DDR"), + .DATA_WIDTH(4'd10), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_69 ( + .CLK(hdmi_out0_pix5x_clk), + .CLKDIV(hdmi_out0_pix_clk), + .D1(hdmi_out0_driver_hdmi_phy_es1_data[0]), + .D2(hdmi_out0_driver_hdmi_phy_es1_data[1]), + .D3(hdmi_out0_driver_hdmi_phy_es1_data[2]), + .D4(hdmi_out0_driver_hdmi_phy_es1_data[3]), + .D5(hdmi_out0_driver_hdmi_phy_es1_data[4]), + .D6(hdmi_out0_driver_hdmi_phy_es1_data[5]), + .D7(hdmi_out0_driver_hdmi_phy_es1_data[6]), + .D8(hdmi_out0_driver_hdmi_phy_es1_data[7]), + .OCE(hdmi_out0_driver_hdmi_phy_es1_ce), + .RST(hdmi_out0_pix_rst), + .SHIFTIN1(hdmi_out0_driver_hdmi_phy_es1_shift[0]), + .SHIFTIN2(hdmi_out0_driver_hdmi_phy_es1_shift[1]), + .TCE(1'd0), + .OQ(hdmi_out0_driver_hdmi_phy_es1_pad_se) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("DDR"), + .DATA_WIDTH(4'd10), + .SERDES_MODE("SLAVE"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_70 ( + .CLK(hdmi_out0_pix5x_clk), + .CLKDIV(hdmi_out0_pix_clk), + .D1(1'd0), + .D2(1'd0), + .D3(hdmi_out0_driver_hdmi_phy_es1_data[8]), + .D4(hdmi_out0_driver_hdmi_phy_es1_data[9]), + .D5(1'd0), + .D6(1'd0), + .D7(1'd0), + .D8(1'd0), + .OCE(hdmi_out0_driver_hdmi_phy_es1_ce), + .RST(hdmi_out0_pix_rst), + .SHIFTIN1(1'd0), + .SHIFTIN2(1'd0), + .TCE(1'd0), + .SHIFTOUT1(hdmi_out0_driver_hdmi_phy_es1_shift[0]), + .SHIFTOUT2(hdmi_out0_driver_hdmi_phy_es1_shift[1]) +); + +OBUFDS OBUFDS_3( + .I(hdmi_out0_driver_hdmi_phy_es1_pad_se), + .O(hdmi_out0_data1_p), + .OB(hdmi_out0_data1_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("DDR"), + .DATA_WIDTH(4'd10), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_71 ( + .CLK(hdmi_out0_pix5x_clk), + .CLKDIV(hdmi_out0_pix_clk), + .D1(hdmi_out0_driver_hdmi_phy_es2_data[0]), + .D2(hdmi_out0_driver_hdmi_phy_es2_data[1]), + .D3(hdmi_out0_driver_hdmi_phy_es2_data[2]), + .D4(hdmi_out0_driver_hdmi_phy_es2_data[3]), + .D5(hdmi_out0_driver_hdmi_phy_es2_data[4]), + .D6(hdmi_out0_driver_hdmi_phy_es2_data[5]), + .D7(hdmi_out0_driver_hdmi_phy_es2_data[6]), + .D8(hdmi_out0_driver_hdmi_phy_es2_data[7]), + .OCE(hdmi_out0_driver_hdmi_phy_es2_ce), + .RST(hdmi_out0_pix_rst), + .SHIFTIN1(hdmi_out0_driver_hdmi_phy_es2_shift[0]), + .SHIFTIN2(hdmi_out0_driver_hdmi_phy_es2_shift[1]), + .TCE(1'd0), + .OQ(hdmi_out0_driver_hdmi_phy_es2_pad_se) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("DDR"), + .DATA_WIDTH(4'd10), + .SERDES_MODE("SLAVE"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_72 ( + .CLK(hdmi_out0_pix5x_clk), + .CLKDIV(hdmi_out0_pix_clk), + .D1(1'd0), + .D2(1'd0), + .D3(hdmi_out0_driver_hdmi_phy_es2_data[8]), + .D4(hdmi_out0_driver_hdmi_phy_es2_data[9]), + .D5(1'd0), + .D6(1'd0), + .D7(1'd0), + .D8(1'd0), + .OCE(hdmi_out0_driver_hdmi_phy_es2_ce), + .RST(hdmi_out0_pix_rst), + .SHIFTIN1(1'd0), + .SHIFTIN2(1'd0), + .TCE(1'd0), + .SHIFTOUT1(hdmi_out0_driver_hdmi_phy_es2_shift[0]), + .SHIFTOUT2(hdmi_out0_driver_hdmi_phy_es2_shift[1]) +); + +OBUFDS OBUFDS_4( + .I(hdmi_out0_driver_hdmi_phy_es2_pad_se), + .O(hdmi_out0_data2_p), + .OB(hdmi_out0_data2_n) +); + +reg [9:0] storage_41[0:3]; +reg [9:0] memdat_44; +always @(posedge hdmi_out0_pix_clk) begin + if (hdmi_out0_resetinserter_y_fifo_wrport_we) + storage_41[hdmi_out0_resetinserter_y_fifo_wrport_adr] <= hdmi_out0_resetinserter_y_fifo_wrport_dat_w; + memdat_44 <= storage_41[hdmi_out0_resetinserter_y_fifo_wrport_adr]; +end + +always @(posedge hdmi_out0_pix_clk) begin +end + +assign hdmi_out0_resetinserter_y_fifo_wrport_dat_r = memdat_44; +assign hdmi_out0_resetinserter_y_fifo_rdport_dat_r = storage_41[hdmi_out0_resetinserter_y_fifo_rdport_adr]; + +reg [9:0] storage_42[0:3]; +reg [9:0] memdat_45; +always @(posedge hdmi_out0_pix_clk) begin + if (hdmi_out0_resetinserter_cb_fifo_wrport_we) + storage_42[hdmi_out0_resetinserter_cb_fifo_wrport_adr] <= hdmi_out0_resetinserter_cb_fifo_wrport_dat_w; + memdat_45 <= storage_42[hdmi_out0_resetinserter_cb_fifo_wrport_adr]; +end + +always @(posedge hdmi_out0_pix_clk) begin +end + +assign hdmi_out0_resetinserter_cb_fifo_wrport_dat_r = memdat_45; +assign hdmi_out0_resetinserter_cb_fifo_rdport_dat_r = storage_42[hdmi_out0_resetinserter_cb_fifo_rdport_adr]; + +reg [9:0] storage_43[0:3]; +reg [9:0] memdat_46; +always @(posedge hdmi_out0_pix_clk) begin + if (hdmi_out0_resetinserter_cr_fifo_wrport_we) + storage_43[hdmi_out0_resetinserter_cr_fifo_wrport_adr] <= hdmi_out0_resetinserter_cr_fifo_wrport_dat_w; + memdat_46 <= storage_43[hdmi_out0_resetinserter_cr_fifo_wrport_adr]; +end + +always @(posedge hdmi_out0_pix_clk) begin +end + +assign hdmi_out0_resetinserter_cr_fifo_wrport_dat_r = memdat_46; +assign hdmi_out0_resetinserter_cr_fifo_rdport_dat_r = storage_43[hdmi_out0_resetinserter_cr_fifo_rdport_adr]; + +VexRiscv VexRiscv( + .clk(sys_clk), + .dBusWishbone_ACK(netv2_cpu_dbus_ack), + .dBusWishbone_DAT_MISO(netv2_cpu_dbus_dat_r), + .dBusWishbone_ERR(netv2_cpu_dbus_err), + .externalInterruptArray(netv2_cpu_interrupt), + .externalResetVector(netv2_vexriscv), + .iBusWishbone_ACK(netv2_cpu_ibus_ack), + .iBusWishbone_DAT_MISO(netv2_cpu_ibus_dat_r), + .iBusWishbone_ERR(netv2_cpu_ibus_err), + .reset((sys_rst | netv2_cpu_reset)), + .softwareInterrupt(1'd0), + .timerInterrupt(1'd0), + .dBusWishbone_ADR(netv2_cpu_dbus_adr), + .dBusWishbone_BTE(netv2_cpu_dbus_bte), + .dBusWishbone_CTI(netv2_cpu_dbus_cti), + .dBusWishbone_CYC(netv2_cpu_dbus_cyc), + .dBusWishbone_DAT_MOSI(netv2_cpu_dbus_dat_w), + .dBusWishbone_SEL(netv2_cpu_dbus_sel), + .dBusWishbone_STB(netv2_cpu_dbus_stb), + .dBusWishbone_WE(netv2_cpu_dbus_we), + .iBusWishbone_ADR(netv2_cpu_ibus_adr), + .iBusWishbone_BTE(netv2_cpu_ibus_bte), + .iBusWishbone_CTI(netv2_cpu_ibus_cti), + .iBusWishbone_CYC(netv2_cpu_ibus_cyc), + .iBusWishbone_DAT_MOSI(netv2_cpu_ibus_dat_w), + .iBusWishbone_SEL(netv2_cpu_ibus_sel), + .iBusWishbone_STB(netv2_cpu_ibus_stb), + .iBusWishbone_WE(netv2_cpu_ibus_we) +); + +PLLE2_ADV #( + .CLKFBOUT_MULT(6'd32), + .CLKIN1_PERIOD(20.0), + .CLKOUT0_DIVIDE(5'd16), + .CLKOUT0_PHASE(1'd0), + .CLKOUT1_DIVIDE(3'd4), + .CLKOUT1_PHASE(1'd0), + .CLKOUT2_DIVIDE(3'd4), + .CLKOUT2_PHASE(7'd90), + .CLKOUT3_DIVIDE(4'd8), + .CLKOUT3_PHASE(1'd0), + .CLKOUT4_DIVIDE(5'd16), + .CLKOUT4_PHASE(1'd0), + .CLKOUT5_DIVIDE(6'd32), + .CLKOUT5_PHASE(1'd0), + .DIVCLK_DIVIDE(1'd1), + .REF_JITTER1(0.01), + .STARTUP_WAIT("FALSE") +) PLLE2_ADV_1 ( + .CLKFBIN(pll_fb), + .CLKIN1(crg_clkin), + .RST(crg_reset), + .CLKFBOUT(pll_fb), + .CLKOUT0(crg_clkout0), + .CLKOUT1(crg_clkout1), + .CLKOUT2(crg_clkout2), + .CLKOUT3(crg_clkout3), + .CLKOUT4(crg_clkout4), + .CLKOUT5(crg_clkout5), + .LOCKED(crg_locked) +); + +reg [7:0] data_mem_grain0[0:3]; +reg [1:0] memadr_26; +always @(posedge sys_clk) begin + if (netv2_data_port_we[0]) + data_mem_grain0[netv2_data_port_adr] <= netv2_data_port_dat_w[7:0]; + memadr_26 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[7:0] = data_mem_grain0[memadr_26]; + +reg [7:0] data_mem_grain1[0:3]; +reg [1:0] memadr_27; +always @(posedge sys_clk) begin + if (netv2_data_port_we[1]) + data_mem_grain1[netv2_data_port_adr] <= netv2_data_port_dat_w[15:8]; + memadr_27 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[15:8] = data_mem_grain1[memadr_27]; + +reg [7:0] data_mem_grain2[0:3]; +reg [1:0] memadr_28; +always @(posedge sys_clk) begin + if (netv2_data_port_we[2]) + data_mem_grain2[netv2_data_port_adr] <= netv2_data_port_dat_w[23:16]; + memadr_28 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[23:16] = data_mem_grain2[memadr_28]; + +reg [7:0] data_mem_grain3[0:3]; +reg [1:0] memadr_29; +always @(posedge sys_clk) begin + if (netv2_data_port_we[3]) + data_mem_grain3[netv2_data_port_adr] <= netv2_data_port_dat_w[31:24]; + memadr_29 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[31:24] = data_mem_grain3[memadr_29]; + +reg [7:0] data_mem_grain4[0:3]; +reg [1:0] memadr_30; +always @(posedge sys_clk) begin + if (netv2_data_port_we[4]) + data_mem_grain4[netv2_data_port_adr] <= netv2_data_port_dat_w[39:32]; + memadr_30 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[39:32] = data_mem_grain4[memadr_30]; + +reg [7:0] data_mem_grain5[0:3]; +reg [1:0] memadr_31; +always @(posedge sys_clk) begin + if (netv2_data_port_we[5]) + data_mem_grain5[netv2_data_port_adr] <= netv2_data_port_dat_w[47:40]; + memadr_31 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[47:40] = data_mem_grain5[memadr_31]; + +reg [7:0] data_mem_grain6[0:3]; +reg [1:0] memadr_32; +always @(posedge sys_clk) begin + if (netv2_data_port_we[6]) + data_mem_grain6[netv2_data_port_adr] <= netv2_data_port_dat_w[55:48]; + memadr_32 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[55:48] = data_mem_grain6[memadr_32]; + +reg [7:0] data_mem_grain7[0:3]; +reg [1:0] memadr_33; +always @(posedge sys_clk) begin + if (netv2_data_port_we[7]) + data_mem_grain7[netv2_data_port_adr] <= netv2_data_port_dat_w[63:56]; + memadr_33 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[63:56] = data_mem_grain7[memadr_33]; + +reg [7:0] data_mem_grain8[0:3]; +reg [1:0] memadr_34; +always @(posedge sys_clk) begin + if (netv2_data_port_we[8]) + data_mem_grain8[netv2_data_port_adr] <= netv2_data_port_dat_w[71:64]; + memadr_34 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[71:64] = data_mem_grain8[memadr_34]; + +reg [7:0] data_mem_grain9[0:3]; +reg [1:0] memadr_35; +always @(posedge sys_clk) begin + if (netv2_data_port_we[9]) + data_mem_grain9[netv2_data_port_adr] <= netv2_data_port_dat_w[79:72]; + memadr_35 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[79:72] = data_mem_grain9[memadr_35]; + +reg [7:0] data_mem_grain10[0:3]; +reg [1:0] memadr_36; +always @(posedge sys_clk) begin + if (netv2_data_port_we[10]) + data_mem_grain10[netv2_data_port_adr] <= netv2_data_port_dat_w[87:80]; + memadr_36 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[87:80] = data_mem_grain10[memadr_36]; + +reg [7:0] data_mem_grain11[0:3]; +reg [1:0] memadr_37; +always @(posedge sys_clk) begin + if (netv2_data_port_we[11]) + data_mem_grain11[netv2_data_port_adr] <= netv2_data_port_dat_w[95:88]; + memadr_37 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[95:88] = data_mem_grain11[memadr_37]; + +reg [7:0] data_mem_grain12[0:3]; +reg [1:0] memadr_38; +always @(posedge sys_clk) begin + if (netv2_data_port_we[12]) + data_mem_grain12[netv2_data_port_adr] <= netv2_data_port_dat_w[103:96]; + memadr_38 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[103:96] = data_mem_grain12[memadr_38]; + +reg [7:0] data_mem_grain13[0:3]; +reg [1:0] memadr_39; +always @(posedge sys_clk) begin + if (netv2_data_port_we[13]) + data_mem_grain13[netv2_data_port_adr] <= netv2_data_port_dat_w[111:104]; + memadr_39 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[111:104] = data_mem_grain13[memadr_39]; + +reg [7:0] data_mem_grain14[0:3]; +reg [1:0] memadr_40; +always @(posedge sys_clk) begin + if (netv2_data_port_we[14]) + data_mem_grain14[netv2_data_port_adr] <= netv2_data_port_dat_w[119:112]; + memadr_40 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[119:112] = data_mem_grain14[memadr_40]; + +reg [7:0] data_mem_grain15[0:3]; +reg [1:0] memadr_41; +always @(posedge sys_clk) begin + if (netv2_data_port_we[15]) + data_mem_grain15[netv2_data_port_adr] <= netv2_data_port_dat_w[127:120]; + memadr_41 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[127:120] = data_mem_grain15[memadr_41]; + +reg [7:0] data_mem_grain16[0:3]; +reg [1:0] memadr_42; +always @(posedge sys_clk) begin + if (netv2_data_port_we[16]) + data_mem_grain16[netv2_data_port_adr] <= netv2_data_port_dat_w[135:128]; + memadr_42 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[135:128] = data_mem_grain16[memadr_42]; + +reg [7:0] data_mem_grain17[0:3]; +reg [1:0] memadr_43; +always @(posedge sys_clk) begin + if (netv2_data_port_we[17]) + data_mem_grain17[netv2_data_port_adr] <= netv2_data_port_dat_w[143:136]; + memadr_43 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[143:136] = data_mem_grain17[memadr_43]; + +reg [7:0] data_mem_grain18[0:3]; +reg [1:0] memadr_44; +always @(posedge sys_clk) begin + if (netv2_data_port_we[18]) + data_mem_grain18[netv2_data_port_adr] <= netv2_data_port_dat_w[151:144]; + memadr_44 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[151:144] = data_mem_grain18[memadr_44]; + +reg [7:0] data_mem_grain19[0:3]; +reg [1:0] memadr_45; +always @(posedge sys_clk) begin + if (netv2_data_port_we[19]) + data_mem_grain19[netv2_data_port_adr] <= netv2_data_port_dat_w[159:152]; + memadr_45 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[159:152] = data_mem_grain19[memadr_45]; + +reg [7:0] data_mem_grain20[0:3]; +reg [1:0] memadr_46; +always @(posedge sys_clk) begin + if (netv2_data_port_we[20]) + data_mem_grain20[netv2_data_port_adr] <= netv2_data_port_dat_w[167:160]; + memadr_46 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[167:160] = data_mem_grain20[memadr_46]; + +reg [7:0] data_mem_grain21[0:3]; +reg [1:0] memadr_47; +always @(posedge sys_clk) begin + if (netv2_data_port_we[21]) + data_mem_grain21[netv2_data_port_adr] <= netv2_data_port_dat_w[175:168]; + memadr_47 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[175:168] = data_mem_grain21[memadr_47]; + +reg [7:0] data_mem_grain22[0:3]; +reg [1:0] memadr_48; +always @(posedge sys_clk) begin + if (netv2_data_port_we[22]) + data_mem_grain22[netv2_data_port_adr] <= netv2_data_port_dat_w[183:176]; + memadr_48 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[183:176] = data_mem_grain22[memadr_48]; + +reg [7:0] data_mem_grain23[0:3]; +reg [1:0] memadr_49; +always @(posedge sys_clk) begin + if (netv2_data_port_we[23]) + data_mem_grain23[netv2_data_port_adr] <= netv2_data_port_dat_w[191:184]; + memadr_49 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[191:184] = data_mem_grain23[memadr_49]; + +reg [7:0] data_mem_grain24[0:3]; +reg [1:0] memadr_50; +always @(posedge sys_clk) begin + if (netv2_data_port_we[24]) + data_mem_grain24[netv2_data_port_adr] <= netv2_data_port_dat_w[199:192]; + memadr_50 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[199:192] = data_mem_grain24[memadr_50]; + +reg [7:0] data_mem_grain25[0:3]; +reg [1:0] memadr_51; +always @(posedge sys_clk) begin + if (netv2_data_port_we[25]) + data_mem_grain25[netv2_data_port_adr] <= netv2_data_port_dat_w[207:200]; + memadr_51 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[207:200] = data_mem_grain25[memadr_51]; + +reg [7:0] data_mem_grain26[0:3]; +reg [1:0] memadr_52; +always @(posedge sys_clk) begin + if (netv2_data_port_we[26]) + data_mem_grain26[netv2_data_port_adr] <= netv2_data_port_dat_w[215:208]; + memadr_52 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[215:208] = data_mem_grain26[memadr_52]; + +reg [7:0] data_mem_grain27[0:3]; +reg [1:0] memadr_53; +always @(posedge sys_clk) begin + if (netv2_data_port_we[27]) + data_mem_grain27[netv2_data_port_adr] <= netv2_data_port_dat_w[223:216]; + memadr_53 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[223:216] = data_mem_grain27[memadr_53]; + +reg [7:0] data_mem_grain28[0:3]; +reg [1:0] memadr_54; +always @(posedge sys_clk) begin + if (netv2_data_port_we[28]) + data_mem_grain28[netv2_data_port_adr] <= netv2_data_port_dat_w[231:224]; + memadr_54 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[231:224] = data_mem_grain28[memadr_54]; + +reg [7:0] data_mem_grain29[0:3]; +reg [1:0] memadr_55; +always @(posedge sys_clk) begin + if (netv2_data_port_we[29]) + data_mem_grain29[netv2_data_port_adr] <= netv2_data_port_dat_w[239:232]; + memadr_55 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[239:232] = data_mem_grain29[memadr_55]; + +reg [7:0] data_mem_grain30[0:3]; +reg [1:0] memadr_56; +always @(posedge sys_clk) begin + if (netv2_data_port_we[30]) + data_mem_grain30[netv2_data_port_adr] <= netv2_data_port_dat_w[247:240]; + memadr_56 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[247:240] = data_mem_grain30[memadr_56]; + +reg [7:0] data_mem_grain31[0:3]; +reg [1:0] memadr_57; +always @(posedge sys_clk) begin + if (netv2_data_port_we[31]) + data_mem_grain31[netv2_data_port_adr] <= netv2_data_port_dat_w[255:248]; + memadr_57 <= netv2_data_port_adr; +end + +assign netv2_data_port_dat_r[255:248] = data_mem_grain31[memadr_57]; + +pcie_support #( + .C_DATA_WIDTH(7'd64), + .KEEP_WIDTH(4'd8), + .LINK_CAP_MAX_LINK_WIDTH(1'd1), + .PCIE_GT_DEVICE("GTP"), + .PCIE_REFCLK_FREQ(1'd0), + .PCIE_USERCLK1_FREQ(2'd3), + .PCIE_USERCLK2_FREQ(2'd3) +) pcie_support ( + .cfg_aer_interrupt_msgnum(1'd0), + .cfg_ds_bus_number(1'd0), + .cfg_ds_device_number(1'd0), + .cfg_ds_function_number(1'd0), + .cfg_dsn(1'd0), + .cfg_err_acs(1'd0), + .cfg_err_aer_headerlog(1'd0), + .cfg_err_atomic_egress_blocked(1'd0), + .cfg_err_cor(1'd0), + .cfg_err_cpl_abort(1'd0), + .cfg_err_cpl_timeout(1'd0), + .cfg_err_cpl_unexpect(1'd0), + .cfg_err_ecrc(1'd0), + .cfg_err_internal_cor(1'd0), + .cfg_err_internal_uncor(1'd0), + .cfg_err_locked(1'd0), + .cfg_err_malformed(1'd0), + .cfg_err_mc_blocked(1'd0), + .cfg_err_norecovery(1'd0), + .cfg_err_poisoned(1'd0), + .cfg_err_posted(1'd0), + .cfg_err_tlp_cpl_header(1'd0), + .cfg_err_ur(1'd0), + .cfg_interrupt(s7pciephy_msi_cdc_source_valid), + .cfg_interrupt_assert(1'd0), + .cfg_interrupt_di(s7pciephy_msi_cdc_source_payload_dat), + .cfg_interrupt_stat(1'd0), + .cfg_mgmt_byte_en(1'd0), + .cfg_mgmt_di(1'd0), + .cfg_mgmt_dwaddr(1'd0), + .cfg_mgmt_rd_en(1'd0), + .cfg_mgmt_wr_en(1'd0), + .cfg_mgmt_wr_readonly(1'd0), + .cfg_mgmt_wr_rw1c_as_rw(1'd0), + .cfg_pciecap_interrupt_msgnum(1'd0), + .cfg_pm_force_state(1'd0), + .cfg_pm_force_state_en(1'd0), + .cfg_pm_halt_aspm_l0s(1'd0), + .cfg_pm_halt_aspm_l1(1'd0), + .cfg_pm_send_pme_to(1'd0), + .cfg_pm_wake(1'd0), + .cfg_trn_pending(1'd0), + .cfg_turnoff_ok(1'd0), + .fc_sel(1'd0), + .m_axis_rx_tready(s7pciephy_rx_datapath_sink_sink_ready), + .pci_exp_rxn(pcie_x1_rx_n), + .pci_exp_rxp(pcie_x1_rx_p), + .pcie_drp_addr(1'd0), + .pcie_drp_clk(1'd1), + .pcie_drp_di(1'd0), + .pcie_drp_en(1'd0), + .pcie_drp_we(1'd0), + .pipe_mmcm_rst_n(1'd1), + .pipe_pclk_sel_slave(1'd0), + .pl_directed_link_auton(1'd0), + .pl_directed_link_change(1'd0), + .pl_directed_link_speed(1'd0), + .pl_directed_link_width(1'd0), + .pl_downstream_deemph_source(1'd0), + .pl_transmit_hot_rst(1'd0), + .pl_upstream_prefer_deemph(1'd1), + .rx_np_ok(1'd1), + .rx_np_req(1'd1), + .s_axis_tx_tdata(s7pciephy_tx_datapath_source_source_payload_dat), + .s_axis_tx_tkeep(s7pciephy_tx_datapath_source_source_payload_be), + .s_axis_tx_tlast(s7pciephy_tx_datapath_source_source_last), + .s_axis_tx_tuser(1'd0), + .s_axis_tx_tvalid(s7pciephy_tx_datapath_source_source_valid), + .sys_clk(s7pciephy_pcie_refclk), + .sys_rst_n(s7pciephy_pcie_rst_n), + .tx_cfg_gnt(1'd1), + .cfg_aer_ecrc_check_en(s7pciephy22), + .cfg_aer_ecrc_gen_en(s7pciephy23), + .cfg_aer_rooterr_corr_err_received(s7pciephy47), + .cfg_aer_rooterr_corr_err_reporting_en(s7pciephy44), + .cfg_aer_rooterr_fatal_err_received(s7pciephy49), + .cfg_aer_rooterr_fatal_err_reporting_en(s7pciephy46), + .cfg_aer_rooterr_non_fatal_err_received(s7pciephy48), + .cfg_aer_rooterr_non_fatal_err_reporting_en(s7pciephy45), + .cfg_bridge_serr_en(s7pciephy38), + .cfg_bus_number(s7pciephy_bus_number), + .cfg_command(s7pciephy_command), + .cfg_dcommand(s7pciephy_dcommand), + .cfg_dcommand2(s7pciephy31), + .cfg_device_number(s7pciephy_device_number), + .cfg_dstatus(s7pciephy28), + .cfg_err_aer_headerlog_set(s7pciephy21), + .cfg_err_cpl_rdy(s7pciephy20), + .cfg_function_number(s7pciephy_function_number), + .cfg_interrupt_do(s7pciephy24), + .cfg_interrupt_mmenable(s7pciephy25), + .cfg_interrupt_msienable(s7pciephy_msi_enable_status), + .cfg_interrupt_msixenable(s7pciephy_msix_enable_status), + .cfg_interrupt_msixfm(s7pciephy26), + .cfg_interrupt_rdy(s7pciephy_msi_cdc_source_ready), + .cfg_lcommand(s7pciephy30), + .cfg_lstatus(s7pciephy29), + .cfg_mgmt_do(s7pciephy18), + .cfg_mgmt_rd_wr_done(s7pciephy19), + .cfg_msg_data(s7pciephy52), + .cfg_msg_received(s7pciephy51), + .cfg_msg_received_assert_int_a(s7pciephy60), + .cfg_msg_received_assert_int_b(s7pciephy61), + .cfg_msg_received_assert_int_c(s7pciephy62), + .cfg_msg_received_assert_int_d(s7pciephy63), + .cfg_msg_received_deassert_int_a(s7pciephy64), + .cfg_msg_received_deassert_int_b(s7pciephy65), + .cfg_msg_received_deassert_int_c(s7pciephy66), + .cfg_msg_received_deassert_int_d(s7pciephy67), + .cfg_msg_received_err_cor(s7pciephy55), + .cfg_msg_received_err_fatal(s7pciephy57), + .cfg_msg_received_err_non_fatal(s7pciephy56), + .cfg_msg_received_pm_as_nak(s7pciephy53), + .cfg_msg_received_pm_pme(s7pciephy58), + .cfg_msg_received_pme_to_ack(s7pciephy59), + .cfg_msg_received_setslotpowerlimit(s7pciephy54), + .cfg_pcie_link_state(s7pciephy32), + .cfg_pmcsr_pme_en(s7pciephy34), + .cfg_pmcsr_pme_status(s7pciephy36), + .cfg_pmcsr_powerstate(s7pciephy35), + .cfg_received_func_lvl_rst(s7pciephy37), + .cfg_root_control_pme_int_en(s7pciephy43), + .cfg_root_control_syserr_corr_err_en(s7pciephy40), + .cfg_root_control_syserr_fatal_err_en(s7pciephy42), + .cfg_root_control_syserr_non_fatal_err_en(s7pciephy41), + .cfg_slot_control_electromech_il_ctl_pulse(s7pciephy39), + .cfg_status(s7pciephy27), + .cfg_to_turnoff(s7pciephy33), + .cfg_vc_tcvc_map(s7pciephy50), + .fc_cpld(s7pciephy12), + .fc_cplh(s7pciephy13), + .fc_npd(s7pciephy14), + .fc_nph(s7pciephy15), + .fc_pd(s7pciephy16), + .fc_ph(s7pciephy17), + .m_axis_rx_tdata(s7pciephy_rx_datapath_sink_sink_payload_dat), + .m_axis_rx_tkeep(s7pciephy_rx_datapath_sink_sink_payload_be), + .m_axis_rx_tlast(s7pciephy_m_axis_rx_tlast), + .m_axis_rx_tuser(s7pciephy_m_axis_rx_tuser), + .m_axis_rx_tvalid(s7pciephy_rx_datapath_sink_sink_valid), + .pci_exp_txn(pcie_x1_tx_n), + .pci_exp_txp(pcie_x1_tx_p), + .pcie_drp_do(s7pciephy79), + .pcie_drp_rdy(s7pciephy78), + .pipe_dclk_out(s7pciephy3), + .pipe_mmcm_lock_out(s7pciephy7), + .pipe_oobclk_out(s7pciephy6), + .pipe_pclk_out_slave(s7pciephy0), + .pipe_rxoutclk_out(s7pciephy2), + .pipe_rxusrclk_out(s7pciephy1), + .pipe_userclk1_out(s7pciephy4), + .pipe_userclk2_out(s7pciephy5), + .pl_directed_change_done(s7pciephy76), + .pl_initial_link_width(s7pciephy75), + .pl_lane_reversal_mode(s7pciephy68), + .pl_link_gen2_cap(s7pciephy73), + .pl_link_partner_gen2_supported(s7pciephy74), + .pl_link_upcfg_cap(s7pciephy72), + .pl_ltssm_state(s7pciephy_csrfield_ltssm), + .pl_phy_lnk_up(s7pciephy69), + .pl_received_hot_rst(s7pciephy77), + .pl_rx_pm_state(s7pciephy71), + .pl_sel_lnk_rate(s7pciephy_csrfield_rate), + .pl_sel_lnk_width(s7pciephy_csrfield_width), + .pl_tx_pm_state(s7pciephy70), + .s_axis_tx_tready(s7pciephy_tx_datapath_source_source_ready), + .tx_buf_av(s7pciephy9), + .tx_cfg_req(s7pciephy11), + .tx_err_drop(s7pciephy10), + .user_app_rdy(s7pciephy8), + .user_clk_out(pcie_clk), + .user_lnk_up(s7pciephy_csrfield_status), + .user_reset_out(pcie_rst) +); + +reg [3:0] storage_44[0:3]; +reg [3:0] memdat_47; +reg [3:0] memdat_48; +always @(posedge sys_clk) begin + if (tags_queue_wrport_we) + storage_44[tags_queue_wrport_adr] <= tags_queue_wrport_dat_w; + memdat_47 <= storage_44[tags_queue_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (tags_queue_rdport_re) + memdat_48 <= storage_44[tags_queue_rdport_adr]; +end + +assign tags_queue_wrport_dat_r = memdat_47; +assign tags_queue_rdport_dat_r = memdat_48; + +reg [19:0] storage_45[0:3]; +reg [19:0] memdat_49; +reg [19:0] memdat_50; +always @(posedge sys_clk) begin + if (requests_queue_wrport_we) + storage_45[requests_queue_wrport_adr] <= requests_queue_wrport_dat_w; + memdat_49 <= storage_45[requests_queue_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (requests_queue_rdport_re) + memdat_50 <= storage_45[requests_queue_rdport_adr]; +end + +assign requests_queue_wrport_dat_r = memdat_49; +assign requests_queue_rdport_dat_r = memdat_50; + +reg [165:0] storage_46[0:255]; +reg [165:0] memdat_51; +reg [165:0] memdat_52; +always @(posedge sys_clk) begin + if (syncfifo0_wrport_we) + storage_46[syncfifo0_wrport_adr] <= syncfifo0_wrport_dat_w; + memdat_51 <= storage_46[syncfifo0_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (syncfifo0_rdport_re) + memdat_52 <= storage_46[syncfifo0_rdport_adr]; +end + +assign syncfifo0_wrport_dat_r = memdat_51; +assign syncfifo0_rdport_dat_r = memdat_52; + +reg [165:0] storage_47[0:255]; +reg [165:0] memdat_53; +reg [165:0] memdat_54; +always @(posedge sys_clk) begin + if (syncfifo1_wrport_we) + storage_47[syncfifo1_wrport_adr] <= syncfifo1_wrport_dat_w; + memdat_53 <= storage_47[syncfifo1_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (syncfifo1_rdport_re) + memdat_54 <= storage_47[syncfifo1_rdport_adr]; +end + +assign syncfifo1_wrport_dat_r = memdat_53; +assign syncfifo1_rdport_dat_r = memdat_54; + +reg [165:0] storage_48[0:255]; +reg [165:0] memdat_55; +reg [165:0] memdat_56; +always @(posedge sys_clk) begin + if (syncfifo2_wrport_we) + storage_48[syncfifo2_wrport_adr] <= syncfifo2_wrport_dat_w; + memdat_55 <= storage_48[syncfifo2_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (syncfifo2_rdport_re) + memdat_56 <= storage_48[syncfifo2_rdport_adr]; +end + +assign syncfifo2_wrport_dat_r = memdat_55; +assign syncfifo2_rdport_dat_r = memdat_56; + +reg [165:0] storage_49[0:255]; +reg [165:0] memdat_57; +reg [165:0] memdat_58; +always @(posedge sys_clk) begin + if (syncfifo3_wrport_we) + storage_49[syncfifo3_wrport_adr] <= syncfifo3_wrport_dat_w; + memdat_57 <= storage_49[syncfifo3_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (syncfifo3_rdport_re) + memdat_58 <= storage_49[syncfifo3_rdport_adr]; +end + +assign syncfifo3_wrport_dat_r = memdat_57; +assign syncfifo3_rdport_dat_r = memdat_58; + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE ( + .C(sys_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl0), + .Q(xilinxasyncresetsynchronizerimpl0_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_1 ( + .C(sys_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl0), + .Q(sys_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_2 ( + .C(sys4x_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl1), + .Q(xilinxasyncresetsynchronizerimpl1_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_3 ( + .C(sys4x_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl1), + .Q(xilinxasyncresetsynchronizerimpl1_expr) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_4 ( + .C(sys4x_dqs_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl2), + .Q(xilinxasyncresetsynchronizerimpl2_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_5 ( + .C(sys4x_dqs_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl2), + .Q(xilinxasyncresetsynchronizerimpl2_expr) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_6 ( + .C(clk200_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl3), + .Q(xilinxasyncresetsynchronizerimpl3_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_7 ( + .C(clk200_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl3_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl3), + .Q(clk200_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_8 ( + .C(clk100_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl4), + .Q(xilinxasyncresetsynchronizerimpl4_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_9 ( + .C(clk100_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl4_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl4), + .Q(clk100_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_10 ( + .C(eth_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl5), + .Q(xilinxasyncresetsynchronizerimpl5_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_11 ( + .C(eth_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl5_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl5), + .Q(eth_rst) +); + +ODDR #( + .DDR_CLK_EDGE("SAME_EDGE") +) ODDR ( + .C(eth_tx_clk), + .CE(1'd1), + .D1(1'd0), + .D2(1'd1), + .R(1'd0), + .S(1'd0), + .Q(eth_clocks_ref_clk) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_12 ( + .C(eth_tx_clk), + .CE(1'd1), + .D(1'd0), + .PRE(ethphy_reset0), + .Q(xilinxasyncresetsynchronizerimpl6_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_13 ( + .C(eth_tx_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl6_rst_meta), + .PRE(ethphy_reset0), + .Q(eth_tx_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_14 ( + .C(eth_rx_clk), + .CE(1'd1), + .D(1'd0), + .PRE(ethphy_reset0), + .Q(xilinxasyncresetsynchronizerimpl7_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_15 ( + .C(eth_rx_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl7_rst_meta), + .PRE(ethphy_reset0), + .Q(eth_rx_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_16 ( + .C(hdmi_in0_pix_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl8), + .Q(xilinxasyncresetsynchronizerimpl8_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_17 ( + .C(hdmi_in0_pix_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl8_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl8), + .Q(hdmi_in0_pix_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_18 ( + .C(pix1p25x_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl9), + .Q(xilinxasyncresetsynchronizerimpl9_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_19 ( + .C(pix1p25x_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl9_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl9), + .Q(pix1p25x_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_20 ( + .C(pix_o_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl10), + .Q(xilinxasyncresetsynchronizerimpl10_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_21 ( + .C(pix_o_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl10_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl10), + .Q(pix_o_rst) +); + +endmodule diff --git a/third_party/litepcie b/third_party/litepcie new file mode 160000 index 00000000..5e88ab62 --- /dev/null +++ b/third_party/litepcie @@ -0,0 +1 @@ +Subproject commit 5e88ab62b708ad7a14209cea4f0025f2e055a47b diff --git a/toolchains/vivado.py b/toolchains/vivado.py index 100adb76..3e5bbaeb 100644 --- a/toolchains/vivado.py +++ b/toolchains/vivado.py @@ -96,6 +96,13 @@ def run(self): 'file_type': 'verilogSource' } ) + elif f.endswith(".xci"): + self.files.append( + { + 'name': os.path.realpath(f), + 'file_type': 'xci' + } + ) self.files.append( {